Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor provided with: a laminate in which a plurality of dielectric layers are laminated; first internal electrode layers led out to both end surfaces of the laminate; second internal electrode layers led out to both side surfaces of the laminate; a first external electrode and a second external electrode connected to the first internal electrode layer and disposed on both end surfaces; and a third external electrode and a fourth external electrode connected to the second internal electrode layer and disposed on both side surfaces. The number of the first internal electrode layers is larger than the number of the second internal electrode layers, and two or more first internal electrode layers are continuously laminated. A recess is formed in the first internal electrode layer so as not to overlap with the third external electrode and the fourth external electrode disposed on a portion of the two main surfaces when the multilayer ceramic capacitor is viewed from the height direction.

Description

[0001] This application is a divisional application of the invention patent application with the application date of February 15, 2022, application number 202210139714.5, and invention name “Stacked Ceramic Capacitor”. Technical Field

[0002] The present invention relates to a laminated ceramic capacitor. Background Art

[0003] For example, as a decoupling capacitor for stabilizing a power supply voltage supplied to an integrated circuit component (IC) operating at high speed or as a noise countermeasure component for a power supply line supplied to the integrated circuit component (IC), a chip-shaped electronic component having a general structure as described in Japanese Utility Model Application Laid-Open No. 02-082022 is known.

[0004] In the sheet-like electronic component described in Japanese Utility Model Application Laid-Open No. 02-082022, a plurality of dielectric green sheets having through electrodes printed on one surface and a plurality of dielectric green sheets having capacitor electrodes printed on one surface in a direction perpendicular to the through electrodes are alternately stacked, and external electrodes are connected to the through electrodes and the capacitor electrodes.

[0005] However, in a through-type capacitor such as that described in Japanese Utility Model Publication No. 02-082022, in order to achieve further low capacitance, the following design is adopted: the capacitor electrode is arranged on the outermost surface side of the electronic component body, the width of the capacitor electrode is smaller than the width of the external electrode connected to the capacitor electrode side, and the external electrode connected to the capacitor electrode side overlaps with the through-electrode when viewed from the stacking direction. In the case of such a design, if a high electric field is applied, the electric field is concentrated on the overlapping portion of the through-electrode and the external electrode, and there is a possibility that insulation breakdown occurs between the external electrode connected to the capacitor electrode side and the through-electrode. Summary of the invention

[0006] Therefore, a main object of the present invention is to provide a multilayer ceramic capacitor that enables a capacitor with low capacitance and can suppress dielectric breakdown between internal electrode layers and external electrodes even when a high electric field is applied.

[0007] The multilayer ceramic capacitor according to the present invention is a multilayer ceramic capacitor comprising: a multilayer body having a plurality of laminated dielectric layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction and the length direction; a plurality of first internal electrode layers arranged on the plurality of dielectric layers and led out to the first end surface and the second end surface; a plurality of second internal electrode layers arranged on the plurality of dielectric layers and led out to the first side surface and the second side surface; a first external electrode arranged on the first end surface and connected to the first internal electrode layer; a second external electrode arranged on the second end surface and connected to the first internal electrode layer; a third external electrode arranged on the first side surface, and extending from the first side surface and arranged on a portion of the first main surface and a portion of the second main surface, and connected to the second internal electrode layer; and a fourth external electrode arranged on the second side surface and The first internal electrode layer extends from the second side surface and is arranged on a part of the first main surface and a part of the second main surface, and is connected to the second internal electrode layer, wherein the number of the first internal electrode layers is greater than the number of the second internal electrode layers, and two or more first internal electrode layers are continuously stacked, and the first internal electrode layer is formed with a recessed portion so that when the laminated ceramic capacitor is observed from the height direction, it does not overlap with the third external electrode arranged on a part of the first main surface and a part of the second main surface and the fourth external electrode arranged on a part of the first main surface and a part of the second main surface, and the second internal electrode layer is arranged at least between the first internal electrode layer located closest to the first main surface and the first main surface, and at least between the first internal electrode layer located closest to the second main surface and the second main surface, and the length of the second internal electrode layer in the longitudinal direction is shorter than the maximum length in the longitudinal direction of the third external electrode arranged on a part of the first main surface and a part of the second main surface and the fourth external electrode arranged on a part of the first main surface and a part of the second main surface.

[0008] In the stacked ceramic capacitor involved in the present invention, the number of first internal electrode layers is greater than the number of second internal electrode layers, and two or more first internal electrode layers are continuously stacked, thereby suppressing the increase in electrostatic capacitance of the stacked ceramic capacitor. In addition, not only the number of first internal electrode layers increases, the number of first internal electrode layers connected in parallel increases, and the conductivity between the first internal electrode layer and the external electrode is improved, thereby suppressing the increase in DC resistance.

[0009] Furthermore, in the multilayer ceramic capacitor according to the present invention, a recess is formed in the first internal electrode layer so that, when the multilayer ceramic capacitor is observed from the height direction, the first internal electrode layer does not overlap with the third external electrode arranged on a portion of the first main surface and a portion of the second main surface and the fourth external electrode arranged on a portion of the first main surface and a portion of the second main surface. Therefore, even if a high electric field is applied to the multilayer ceramic capacitor according to the present invention, insulation breakdown between the third external electrode connected to the second internal electrode layer and the fourth external electrode and the first internal electrode layer can be suppressed.

[0010] Furthermore, in the multilayer ceramic capacitor according to the present invention, the second internal electrode layer is arranged at least between the first internal electrode layer located closest to the first main surface and the first main surface, and at least between the first internal electrode layer located closest to the second main surface and the second main surface, so that the current path to the mounting substrate can be shortened, a low ESL effect can be obtained, and even when a high electric field is applied to the multilayer ceramic capacitor according to the present invention, the insulation breakdown between the third external electrode connected to the second internal electrode layer and the fourth external electrode and the first internal electrode layer can be suppressed. As a result, the insulation breakdown voltage (BDV) of the multilayer ceramic capacitor can be improved.

[0011] Furthermore, in the multilayer ceramic capacitor involved in the present invention, the length of the second internal electrode layer in the longitudinal direction is smaller than the maximum length of the third external electrode arranged on a portion of the first main surface and a portion of the second main surface and the fourth external electrode arranged on a portion of the first main surface and a portion of the second main surface, so that a lower capacitance can be set while reducing the DC resistance.

[0012] The above-mentioned object, other objects, features and advantages of the present invention will become more apparent from the following description of the embodiment of the present invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is an external perspective view showing an example of a multilayer ceramic capacitor (three-terminal multilayer ceramic capacitor) according to an embodiment of the present invention.

[0014] Figure 2A 1 is a plan view showing an example of a multilayer ceramic capacitor (three-terminal multilayer ceramic capacitor) according to an embodiment of the present invention.

[0015] Figure 2B is from Figure 2A The illustrated diagram is a perspective view of the individual internal electrode layers from a top view.

[0016] Figure 3This is a side view showing an example of a multilayer ceramic capacitor (three-terminal multilayer ceramic capacitor) according to an embodiment of the present invention.

[0017] Figure 4 yes Figure 1 Cross-sectional view at line IV-IV.

[0018] Figure 5 yes Figure 1 Cross-sectional view at line V-V.

[0019] Figure 6 yes Figure 4 Cross-sectional view at line VI-VI.

[0020] Figure 7 yes Figure 4 Cross-sectional view taken along line VII-VII.

[0021] Figure 8 It is shown Figure 1 The modified example of the multilayer ceramic capacitor shown in FIG. Figure 4 The corresponding cross-sectional view.

[0022] Fig. 9 It is shown Figure 1 The modified example of the multilayer ceramic capacitor shown in FIG. Figure 5 The corresponding cross-sectional view.

[0023] Fig. 10A LT is a cross-sectional view showing an example of the multilayer ceramic capacitor according to Comparative Examples 1 and 2.

[0024] Fig. 10B WT is a cross-sectional view showing an example of the multilayer ceramic capacitor according to Comparative Examples 1 and 2.

[0025] Fig.11A yes Fig. 10A Line XIA-XIA cross-sectional view.

[0026] Fig. 11B yes Fig. 10A Line XIB-XIB sectional view.

[0027] Fig. 12A An example of a laminated ceramic capacitor according to Comparative Examples 3 and 4 is shown. Figure 4 The corresponding cross-sectional view.

[0028] Fig. 12B An example of a laminated ceramic capacitor according to Comparative Examples 3 and 4 is shown. Figure 5 The corresponding cross-sectional view.

[0029] Fig.13This is a schematic cross-sectional view showing an example of a method for measuring the thickness of a dielectric layer.

[0030] Fig.14 It is a graph showing the relationship between the element thickness and the breakdown voltage in each sample of the example and the comparative example. DETAILED DESCRIPTION

[0031] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. In the embodiments shown below, the same or common parts are denoted by the same reference numerals in the drawings, and their description will not be repeated.

[0032] 1. Multilayer ceramic capacitors

[0033] A multilayer ceramic capacitor according to an embodiment of the present invention will be described. The multilayer ceramic capacitor according to this embodiment is a three-terminal multilayer ceramic capacitor.

[0034] Figure 1 This is an external perspective view showing an example of a multilayer ceramic capacitor (three-terminal multilayer ceramic capacitor) according to an embodiment of the present invention. Figure 2A is a plan view showing an example of a multilayer ceramic capacitor (three-terminal multilayer ceramic capacitor) according to an embodiment of the present invention, Figure 2B is from Figure 2A The illustrated diagram is a perspective view of the individual internal electrode layers from a top view. Figure 3 This is a side view showing an example of a multilayer ceramic capacitor (three-terminal multilayer ceramic capacitor) according to an embodiment of the present invention. Figure 4 yes Figure 1 Cross-sectional view at line IV-IV. Figure 5 yes Figure 1 Cross-sectional view at line V-V. Figure 6 yes Figure 4 Cross-sectional view at line VI-VI. Figure 7 yes Figure 4 Cross-sectional view taken along line VII-VII.

[0035] like Figures 1 to 3 As shown, the multilayer ceramic capacitor 10 includes, for example, a substantially rectangular parallelepiped multilayer body 12 and external electrodes 30 .

[0036] The laminate 12 has a plurality of laminated dielectric layers 14 and a plurality of internal electrode layers 16 laminated on the dielectric layers 14. Furthermore, the laminate 12 has a first main surface 12a and a second main surface 12b opposite to each other in the height direction x, a first side surface 12c and a second side surface 12d opposite to each other in the width direction y orthogonal to the height direction x, and a first end surface 12e and a second end surface 12f opposite to each other in the length direction z orthogonal to the height direction x and the width direction y.

[0037] In addition, the dimension L of the laminate 12 in the longitudinal direction z is not necessarily longer than the dimension W in the width direction y.

[0038] The external electrodes 30 are arranged on the first end face 12e side and the second end face 12f side and the first side face 12c side and the second side face 12d side of the stacked body 12. The external electrodes 30 include a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d. The details of the first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d will be described later.

[0039] In the laminate 12, the corners and ridges are rounded. The corners are the portions where three adjacent faces of the laminate intersect, and the ridges are the portions where two adjacent faces of the laminate intersect. In addition, concavities and convexities may be formed partially or entirely on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0040] The size of the laminate 12 is not particularly limited.

[0041] The laminated body 12 includes an inner layer portion 18 , and a first main surface side outer layer portion 20 a and a second main surface side outer layer portion 20 b which are arranged to sandwich the inner layer portion 18 in the height direction x.

[0042] The inner layer portion 18 includes a plurality of dielectric layers 14 and a plurality of internal electrode layers 16. The inner layer portion 18 includes the internal electrode layer 16 located closest to the first main surface 12a to the internal electrode layer 16 located closest to the second main surface 12b in the height direction x.

[0043] The first principal surface side outer layer portion 20a is located on the first principal surface 12a side. The first principal surface side outer layer portion 20a is an aggregate of a plurality of dielectric layers 14 located between the first principal surface 12a and the internal electrode layer 16 closest to the first principal surface 12a.

[0044] The second principal surface side outer layer portion 20b is located on the second principal surface 12b side. The second principal surface side outer layer portion 20b is an aggregate of a plurality of dielectric layers 14 located between the second principal surface 12b and the internal electrode layer 16 closest to the second principal surface 12b.

[0045] The dielectric layer 14 used in the first main surface side outer layer portion 20 a and the second main surface side outer layer portion 20 b may be the same as the dielectric layer 14 used in the inner layer portion 18 .

[0046] The laminate 12 has a first side surface side outer layer portion 22a located on the first side surface 12c side and formed of a plurality of dielectric layers 14 located between the first side surface 12c and the outermost surface of the inner layer portion 18 on the first side surface 12c side.

[0047] Similarly, the laminate 12 has a second side outer layer portion 22b located on the second side 12d side and formed of a plurality of dielectric layers 14 located between the second side 12d and the outermost surface of the inner layer portion 18 on the second side 12d side.

[0048] exist Figure 5 The range of the first side outer layer portion 22a and the second side outer layer portion 22b in the width direction y is shown. The width of the first side outer layer portion 22a and the second side outer layer portion 22b in the width direction y is also called W interval or lateral interval.

[0049] The dielectric layer 14 can be formed of a dielectric material such as a ceramic material. As such a dielectric material, for example, a dielectric ceramic containing a component such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 can be used. In the case where the above-mentioned dielectric material is included as the main component, a material to which a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound whose content is less than that of the main component may be added, for example, according to the desired characteristics of the laminate 12.

[0050] The thickness of dielectric layer 14 after firing is preferably 30 μm or more and 80 μm or less.

[0051] The number of laminated dielectric layers 14 is preferably 15 or more and 300 or less. The number of dielectric layers 14 is the sum of the number of dielectric layers 14 in the inner layer portion 18 and the number of dielectric layers 14 in the first main surface side outer layer portion 20a and the second main surface side outer layer portion 20b.

[0052] The internal electrode portion 16 includes a plurality of first internal electrode layers 16 a and a plurality of second internal electrode layers 16 b as the plurality of internal electrode layers 16 .

[0053] The first internal electrode layer 16 a is arranged on the dielectric layer 14 .

[0054] like Figure 6As shown in FIG. 1 , the first internal electrode layer 16a extends between the first end face 12e and the second end face 12f of the laminate 12, and includes a first region 26a corresponding to the center portion thereof, a second region 26b extending from the first region 26a and leading to the first end face 12e of the laminate 12, and a third region 26c extending from the first region 26a and leading to the second end face 12f of the laminate 12. The first region 26a is located in the center portion on the dielectric layer 14. The second region 26b is exposed at the first end face 12e of the laminate 12, and the third region 26c is exposed at the second end face 12f of the laminate 12. Therefore, the first internal electrode layer 16a is not exposed at the first side face 12c and the second side face 12d of the laminate 12.

[0055] The shape of the first internal electrode layer 16a is not particularly limited, but is preferably a rectangular shape. However, the corners may be rounded.

[0056] When the multilayer ceramic capacitor 10 is viewed from the height direction x, Figure 2B As shown, the first internal electrode layer 16a is formed with a recess 29a so as not to overlap with the third external electrode 30c arranged on a portion of the first main surface 12a and a portion of the second main surface 12b, and is formed with a recess 29b so as not to overlap with the fourth external electrode 30d arranged on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0057] More specifically, in the first region 26a of the first internal electrode layer 16a, there is a recess 29a on the first side surface 12c where the internal electrode layer 16 is not formed, and there is a recess 29b on the second side surface 12d where the internal electrode layer 16 is not formed.

[0058] Thus, even when a high electric field is applied to the multilayer ceramic capacitor 10 , insulation breakdown between the third external electrode 30 c and the fourth external electrode 30 d connected to the second internal electrode layer 16 b and the first internal electrode layer 16 a can be suppressed.

[0059] The shape of the recessed portion 29 a is not particularly limited as long as it does not overlap with the third external electrode 30 c disposed on a portion of the first main surface 12 a and the second main surface 12 b when the multilayer ceramic capacitor 10 is viewed in the height direction x.

[0060] Likewise, the shape of the recess 29 b is not particularly limited as long as it does not overlap with the fourth external electrode 30 d disposed on a portion of the first main surface 12 a and the second main surface 12 b when the multilayer ceramic capacitor 10 is viewed in the height direction x.

[0061] In the present embodiment, the shapes of the recessed portion 29a and the recessed portion 29b are semicircular.

[0062] The second internal electrode layer 16b is arranged on a dielectric layer 14 different from the dielectric layer 14 on which the first internal electrode layer 16a is arranged.

[0063] like Figure 7 As shown in FIG. 1 , the second internal electrode layer 16b extends across the first side surface 12c and the second side surface 12d of the laminate 12, and includes a fourth region portion 28a corresponding to the center portion thereof, a fifth region portion 28b extending from the fourth region portion 28a and leading to the first side surface 12c, and a sixth region portion 28c extending from the fourth region portion 28a and leading to the second side surface 12d. The fourth region portion 28a is located in the center portion on the dielectric layer 14. The fifth region portion 28b is exposed at the first side surface 12c of the laminate 12, and the sixth region portion 28c is exposed at the second side surface 12d of the laminate 12. Therefore, the second internal electrode layer 16b is not exposed at the first end surface 12e and the second end surface 12f of the laminate 12.

[0064] The shapes of the fourth region 28a, the fifth region 28b, and the sixth region 28c of the second internal electrode layer 16b are not particularly limited, but are preferably rectangular. However, the corners of each region may be rounded.

[0065] The second internal electrode layer 16b is arranged at least between the first internal electrode layer 16a located closest to the first main surface 12a and the first main surface 12a, and at least between the first internal electrode layer 16a located closest to the second main surface 12b and the second main surface 12b.

[0066] As a result, the current path to the mounting substrate can be shortened, a low ESL (equivalent series resistance) effect can be obtained, and even when a high electric field is applied to the multilayer ceramic capacitor 10, insulation breakdown between the third external electrode 30c and the fourth external electrode 30d connected to the second internal electrode layer 16b and the first internal electrode layer 16a can be suppressed. As a result, the insulation breakdown voltage (BDV) of the multilayer ceramic capacitor 10 can be improved.

[0067] The length of the second internal electrode layer 16b in the longitudinal direction z is smaller than the maximum length of the third external electrode 30c arranged on a portion of the first main surface 12a and a portion of the second main surface 12b and the fourth external electrode 30d arranged on a portion of the first main surface 12a and a portion of the second main surface 12b in the longitudinal direction z.

[0068] This allows the capacitance to be lowered while reducing the DC resistance.

[0069] The second internal electrode layer 16b preferably has the following structure: the fourth region 28a of the second internal electrode layer 16b does not extend in the direction of the first end face 12e and the second end face 12f, and the width of the fourth region 28a of the second internal electrode layer 16b in the length direction z connecting the first end face 12e and the second end face 12f is the same length as the width of the fifth region 28b and the sixth region 28c of the second internal electrode layer 16b in the length direction z connecting the first end face 12e and the second end face 12f.

[0070] Thus, by adjusting only the area of ​​the second internal electrode layer 16 b without changing the area of ​​the first internal electrode layer 16 a , the capacitance of the multilayer ceramic capacitor 10 can be reduced while reducing the DC resistance.

[0071] The first region 26a of the first internal electrode layer 16a and the fourth region 28a of the second internal electrode layer 16b face each other.

[0072] The number of the first internal electrode layers 16a is greater than the number of the second internal electrode layers 16b, and two or more first internal electrode layers 16a are continuously stacked. Figure 1 The multilayer ceramic capacitor 10 shown can suppress the increase of electrostatic capacitance, and not only the number of first internal electrode layers 16a is increased and the number of first internal electrode layers 16a connected in parallel is increased, but also the conductivity between the first internal electrode layer 16a and the external electrode 30 is improved, thereby suppressing the increase of DC resistance.

[0073] The inner layer 18 of the laminate 12 includes a capacitance forming portion 19 in which the first internal electrode layer 16a and the second internal electrode layer 16b are opposed to each other via the dielectric layer 14 to form an electrostatic capacitor, and an internal electrode laminate portion 24 which is a region in which two or more first internal electrode layers 16a are continuously laminated. The laminated ceramic capacitor 10 exhibits capacitor characteristics through the capacitance forming portion 19.

[0074] In addition, Figure 1 In the multilayer ceramic capacitor 10 shown in FIG. Figure 8 as well as Fig. 9 As shown, the second internal electrode layer 16b is arranged so as to divide the internal electrode laminated portion 24, which is a region where two or more first internal electrode layers 16a are continuously laminated. At this time, the internal electrode laminated portion 24 is divided into the first internal electrode laminated portion 24a and the second internal electrode laminated portion 24b by one second internal electrode layer 16b.

[0075] As a result, the aggregates of the first internal electrode layers 16 a are dispersed, so that the heat dissipation effect is improved and the temperature rise suppression effect can be obtained.

[0076] Furthermore, a single second internal electrode layer 16b may be provided, which is configured to divide the internal electrode laminated portion 24, which is a region where two or more first internal electrode layers 16a are continuously laminated, into a plurality of parts. This allows more first internal electrode layers 16a to be laminated, and the DC resistance can be reduced.

[0077] On the other hand, the second internal electrode layer 16b configured to divide the internal electrode laminated portion 24, which is a region where two or more first internal electrode layers 16a are continuously laminated, into a plurality of layers may be configured to be continuously laminated in two or more layers. Thus, even if the number of second internal electrode layers 16b is reduced, connectivity with the third external electrode 30c formed on the first side surface 12c and the fourth external electrode 30d formed on the second side surface 12d can be made more sufficient.

[0078] The thickness of the dielectric layer 14 located between the first internal electrode layer 16a and the second internal electrode layer 16b is preferably 30 μm or more. This allows the effect of the present invention to be more pronounced in a region where the effect is more pronounced.

[0079] The thickness of the dielectric layer 14 between the first internal electrode layer 16a and the second internal electrode layer 16b is preferably greater than the thickness of the dielectric layer 14 located between the first internal electrode layers 16a. This allows more first internal electrode layers 16a to be stacked, further increasing the effect of reducing the DC resistance.

[0080] When observing the multilayer ceramic capacitor 10 from the height direction x, the distances on the same plane from the edges of the end portions of the third external electrode 30c arranged on a portion of the first main surface 12a and a portion of the second main surface 12b and the fourth external electrode 30d arranged on a portion of the first main surface 12a and a portion of the second main surface 12b to the edges of the end portions of the recessed portion 29a of the first internal electrode layer 16a, and the distances on the same plane from the edges of the end portions of the third external electrode 30c arranged on a portion of the first main surface 12a and a portion of the second main surface 12b and the fourth external electrode 30d arranged on a portion of the first main surface 12a and a portion of the second main surface 12b to the edges of the end portions of the recessed portion 29b of the first internal electrode layer 16a are preferably at least 100 μm in short.

[0081] Thus, even when a high electric field is applied, insulation breakdown between the third external electrode 30c and the fourth external electrode 30d connected to the second internal electrode layer 16b and the first internal electrode layer 16a can be more significantly suppressed.

[0082] In the first internal electrode layer 16a, the shortest distance between the recesses 29a and 29b in the width direction y is shorter than the shortest distance in the width direction y of the first internal electrode layer 16a in a portion where the recesses 29a and 29b are not formed.

[0083] Thus, even when a high electric field is applied, insulation breakdown between the third external electrode 30c and the fourth external electrode 30d connected to the second internal electrode layer 16b and the first internal electrode layer 16a can be more significantly suppressed.

[0084] The total number of the first internal electrode layers 16 a and the second internal electrode layers 16 b is preferably 15 or more and 200 or less.

[0085] The number of first internal electrode layers 16 a is not particularly limited, but is preferably, for example, 50 or more and 100 or less.

[0086] Furthermore, the number of the second internal electrode layers 16b is at least smaller than the number of the first internal electrode layers 16a. Specifically, the number of the second internal electrode layers 16b is not particularly limited, but is preferably, for example, 1 or more and 20 or less.

[0087] The thickness of the first internal electrode layer 16 a and the second internal electrode layer 16 b is not particularly limited, but is preferably about 0.5 μm or more and 2.0 μm or less, for example.

[0088] The thickness of the fourth region 28a of the second internal electrode layer 16b is not particularly limited, but is preferably about 30 μm or more and 80 μm or less, for example.

[0089] The first internal electrode layer 16 a and the second internal electrode layer 16 b can be formed of an appropriate conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals such as an Ag—Pd alloy.

[0090] External electrodes 30 are arranged on the first end face 12e and second end face 12f and the first side face 12c and second side face 12d of the stacked body 12. The external electrodes 30 include a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0091] The first external electrode 30a is arranged on the first end surface 12e of the stacked body 12. The first external electrode 30a is arranged to extend from the first end surface 12e of the stacked body 12 and cover a portion of each of the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d. In addition, the first external electrode 30a is electrically connected to the second region 26b of the first internal electrode layer 16a exposed on the first end surface 12e of the stacked body 12. In addition, the first external electrode 30a may be arranged only on the first end surface 12e of the stacked body 12.

[0092] The second external electrode 30b is arranged on the second end surface 12f of the stacked body 12. The second external electrode 30b is arranged to extend from the second end surface 12f of the stacked body 12 and cover a portion of each of the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d. In addition, the second external electrode 30b is electrically connected to the third region 26c of the first internal electrode layer 16a exposed on the second end surface 12f of the stacked body 12. In addition, the second external electrode 30b may be arranged only on the second end surface 12f of the stacked body 12.

[0093] The third external electrode 30 is disposed on the first side surface 12c of the stacked body 12. The third external electrode 30c is disposed so as to extend from the first side surface 12c and cover a portion of the first main surface 12a and the second main surface 12b. The third external electrode 30c is electrically connected to the fifth region 28b of the second internal electrode layer 16b exposed on the first side surface 12c of the stacked body 12.

[0094] The fourth external electrode 30d is arranged on the second side surface 12d of the stacked body 12. The fourth external electrode 30d is arranged to extend from the second side surface 12d and cover a portion of the first main surface 12a and the second main surface 12b. The fourth external electrode 30d is electrically connected to the sixth region 28c of the second internal electrode layer 16b exposed on the second side surface 12d of the stacked body 12.

[0095] The external electrode 30 includes a base electrode layer 32 disposed on the surface of the laminate 12 and a plating layer 34 disposed to cover the base electrode layer 32 .

[0096] The foundation electrode layer 32 includes a first foundation electrode layer 32 a , a second foundation electrode layer 32 b , a third foundation electrode layer 32 c , and a fourth foundation electrode layer 32 d .

[0097] The first foundation electrode layer 32a is disposed on the surface of the first end surface 12e of the laminate 12, and is formed so as to extend from the first end surface 12e to cover a portion of each of the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d.

[0098] The second foundation electrode layer 32b is disposed on the surface of the second end surface 12f of the laminate 12, and is formed so as to extend from the second end surface 12f to cover a portion of each of the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d.

[0099] Alternatively, the first foundation electrode layer 32 a may be disposed only on the surface of the first end face 12 e of the stacked body 12 , and the second foundation electrode layer 32 b may be disposed only on the surface of the second end face 12 f of the stacked body 12 .

[0100] The third foundation electrode layer 32 c is disposed on the surface of the first side surface 12 c of the laminate 12 , and is formed so as to extend from the first side surface 12 c and cover a portion of each of the first main surface 12 a and the second main surface 12 b .

[0101] The fourth foundation electrode layer 32 d is disposed on the surface of the second side surface 12 d of the laminate 12 , and is formed so as to extend from the second side surface 12 d to cover a portion of each of the first main surface 12 a and the second main surface 12 b .

[0102] The base electrode layer 32 includes at least one selected from a sintered layer, a conductive resin layer, a thin film layer, and the like.

[0103] Hereinafter, each structure in the case where the base electrode layer 32 is set as the above-mentioned sintered layer, conductive resin layer, and thin film layer will be described.

[0104] (Situation of burnt layer)

[0105] The sintered layer contains a glass component and a metal component. The glass component of the sintered layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. As the metal component of the sintered layer, for example, it contains at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The sintered layer can also be a plurality of layers. The sintered layer is formed by applying a conductive paste containing a glass component and a metal component to the stack 12 and sintering it. The sintered layer can be a sintered layer in which a stack having an internal electrode layer 16 and a dielectric layer 14 and a conductive paste applied to the stack are sintered at the same time, or it can be a sintered layer in which a conductive paste is applied to the stack 12 and sintered after the stack 12 is obtained by sintering the stack having an internal electrode layer 16 and a dielectric layer 14. In addition, in the case where the sintered layer is a sintered layer formed by simultaneously sintering a laminate sheet having an internal electrode layer 16 and a dielectric layer 14 and a conductive paste applied to the laminate sheet, it is preferred that the sintered layer be formed by sintering a material to which a dielectric material is added instead of a glass component.

[0106] The thickness of the first foundation electrode layer 32a located at the center of the first end surface 12e in the height direction x in the direction connecting the first end surface 12e and the second end surface 12f is preferably about 3 μm or more and 70 μm or less.

[0107] Furthermore, the thickness of the second foundation electrode layer 32b located at the second end surface 12f in the center portion in the height direction x in the direction connecting the first end surface 12e and the second end surface 12f is preferably about 3 μm or more and 70 μm or less.

[0108] When the first base electrode layer 32a is provided on a portion of the first principal surface 12a, a portion of the second principal surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d, the thickness in the height direction connecting the first principal surface 12a and the second principal surface 12b located at the center in the longitudinal direction z of the first base electrode layer 32a on the first principal surface 12a, the second principal surface 12b, the first side surface 12c, and the second side surface 12d is preferably, for example, greater than 3 μm and less than 40 μm.

[0109] In addition, when the second base electrode layer 32b is provided on a portion of the first principal surface 12a and a portion of the second principal surface 12b and a portion of the first side surface 12c and a portion of the second side surface 12d, the thickness in the height direction connecting the first principal surface 12a and the second principal surface 12b located at the center portion in the longitudinal direction z of the second base electrode layer 32b on the first principal surface 12a and the second principal surface 12b, the first side surface 12c and the second side surface 12d is preferably, for example, greater than 3 μm and less than 40 μm.

[0110] The thickness of the third underlying electrode layer 32 c located on the first side surface 12 c in the center portion in the height direction x in the direction connecting the first side surface 12 c and the second side surface 12 d is preferably about 3 μm or more and 70 μm or less.

[0111] Furthermore, the thickness of the fourth foundation electrode layer 32d located on the second side surface 12d in the center portion in the height direction x in the direction connecting the first side surface 12c and the second side surface 12d is preferably about 3 μm or more and 70 μm or less.

[0112] (Conductive resin layer)

[0113] The conductive resin layer may be a plurality of layers.

[0114] The conductive resin layer may be disposed on the sintered layer so as to cover the sintered layer, or may be directly disposed on the laminate 12 .

[0115] The conductive resin layer contains a thermosetting resin and a metal.

[0116] The conductive resin layer may completely cover the base electrode layer 32 or may cover a portion of the base electrode layer 32 .

[0117] The conductive resin layer contains a thermosetting resin and is therefore more flexible than a conductive layer composed of, for example, a plated film or a sintered product of a conductive paste. Therefore, even when a physical shock or a shock caused by a thermal cycle is applied to the multilayer ceramic capacitor 10, the conductive resin layer can function as a buffer layer to prevent cracks from occurring in the multilayer ceramic capacitor 10.

[0118] As the metal contained in the conductive resin layer, Ag, Cu, Ni, Sn, Bi, or an alloy containing these can be used.

[0119] In addition, metal powder coated with Ag on the surface of the metal powder can also be used. When using metal powder coated with Ag on the surface of the metal powder, it is preferred to use Cu, Ni, Sn, Bi or their alloy powder as the metal powder. The reason for using Ag as a conductive metal powder is that Ag has the lowest resistivity among metals and is suitable for electrode materials. Ag is a precious metal, so it is not oxidized and has high weather resistance. In addition, it is also because the metal of the base material can be set to a cheap metal while maintaining the above-mentioned characteristics of Ag.

[0120] Furthermore, as the metal contained in the conductive resin layer, Cu and Ni subjected to an oxidation-proof treatment can be used.

[0121] In addition, as the metal contained in the conductive resin layer, a metal powder obtained by coating the surface of Sn, Ni, or Cu can be used. When a metal powder obtained by coating the surface of Sn, Ni, or Cu is used, it is preferred to use Ag, Cu, Ni, Sn, Bi, or alloy powders thereof as the metal powder.

[0122] The conductive fillers are in contact with each other, thereby forming an electric conduction path inside the conductive resin layer.

[0123] The metal contained in the conductive resin layer may be a spherical metal, a flat metal, or the like. However, it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0124] As the resin of the conductive resin layer, various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, polyimide resin, etc. can be used. Among them, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, adhesion, etc.

[0125] In addition, it is preferred that a curing agent is included in the conductive resin layer together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenolic compounds, amines, acid anhydrides, imidazoles, active esters, and amide-imides can be used as the curing agent for the epoxy resin.

[0126] The thickness of the conductive resin layer located at the center of the stacked body 12 located at the first end surface 12 e and the second end surface 12 f in the height direction x is preferably about 10 μm or more and 150 μm or less, for example.

[0127] (Thin film layer)

[0128] When a thin film layer is provided as the base electrode layer 32 , the thin film layer is formed by a thin film forming method such as sputtering or vapor deposition and is a layer having a thickness of 1 μm or less in which metal particles are deposited.

[0129] The plating layer 34 includes a first plating layer 34 a , a second plating layer 34 b , a third plating layer 34 c , and a fourth plating layer 34 d .

[0130] The first plating layer 34 a , the second plating layer 34 b , the third plating layer 34 c , and the fourth plating layer 34 d include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0131] The first plating layer 34a is arranged to cover the first foundation electrode layer 32a.

[0132] The second plating layer 34b is arranged to cover the second foundation electrode layer 32b.

[0133] The third plating layer 34c is arranged to cover the third base electrode layer 32c.

[0134] The fourth plating layer 34d is arranged to cover the fourth base electrode layer 32d.

[0135] The plating layer 34 may be formed of a plurality of layers. In this case, the plating layer 34 preferably has a two-layer structure of a lower plating layer formed of Ni plating formed on the base electrode layer 32 and an upper plating layer formed of Sn plating formed on the lower plating layer.

[0136] That is, the first plating layer 34 a includes a first lower plating layer and a first upper plating layer located on the surface of the first lower plating layer.

[0137] The second plating layer 34 b includes a second lower plating layer and a second upper plating layer located on the surface of the second lower plating layer.

[0138] The third plating layer 34c includes a third lower plating layer and a second upper plating layer located on the surface of the third lower plating layer.

[0139] The fourth plating layer 34d includes a fourth lower plating layer and a second upper plating layer located on the surface of the fourth lower plating layer.

[0140] The lower plating layer composed of Ni plating is used to prevent the base electrode layer 32 from being corroded by the solder when mounting the multilayer ceramic capacitor 10, and the upper plating layer composed of Sn plating is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, so that it can be mounted easily.

[0141] The thickness of each plating layer is preferably 2.0 μm or more and 15.0 μm or less.

[0142] Alternatively, the external electrode 30 may be formed only of a plating layer without providing the base electrode layer 32 .

[0143] Although not shown in the drawings, a structure in which the base electrode layer 32 is not provided but a plating layer is provided will be described below.

[0144] Any one or each of the first to fourth external electrodes 30a to 30d may be provided with a plated layer directly on the surface of the laminate 12 without providing the base electrode layer 32. That is, the laminated ceramic capacitor 10 may also have a structure including a plated layer electrically connected to the first internal electrode layer 16a and the second internal electrode layer 16b. In such a case, a catalyst may be provided on the surface of the laminate 12 as a pretreatment, and then the plated layer may be formed.

[0145] In addition, when a plating layer is formed directly on the laminate 12 without providing a base electrode layer 32, the height can be reduced, that is, thinned, corresponding to the amount by which the thickness of the base electrode layer 32 is reduced, or it can be converted into the thickness of the laminate 12, that is, the thickness of the inner layer 18, thereby improving the design freedom of the thin sheet.

[0146] The plating layer preferably includes a lower plating electrode formed on the surface of the laminate 12 and an upper plating electrode formed on the surface of the lower plating electrode. The lower plating electrode and the upper plating electrode each preferably include at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing the metal.

[0147] Furthermore, the lower-layer plated electrode is preferably formed using Ni having a solder barrier property, and the upper-layer plated electrode is preferably formed using Sn or Au having good solder wettability.

[0148] In addition, for example, when Ni is used to form the first internal electrode layer 16a and the second internal electrode layer 16b, the lower plated electrode is preferably formed using Cu having good bonding properties with Ni. In addition, the upper plated electrode can be formed as needed, and the first external electrode 30a to the fourth external electrode 30d can each be composed of only the lower plated electrode. The plated layer can be the upper plated electrode as the outermost layer, or other plated electrodes can be further formed on the surface of the upper plated electrode.

[0149] Here, when the external electrode 30 is formed only by the plating layer without providing the base electrode layer 32 , the thickness of each plating layer arranged without providing the base electrode layer 32 is preferably 1 μm to 15 μm.

[0150] Furthermore, the plating layer preferably does not contain glass. The metal ratio per unit volume of the plating layer is preferably 99 volume % or more.

[0151] The dimension in the length direction z of the multilayer ceramic capacitor 10 including the multilayer body 12 and the first to fourth external electrodes 30a to 30d is set as the L dimension, the dimension in the height direction x of the multilayer ceramic capacitor 10 including the multilayer body 12 and the first to fourth external electrodes 30a to 30d is set as the T dimension, and the dimension in the width direction y of the multilayer ceramic capacitor 10 including the multilayer body 12 and the first to fourth external electrodes 30a to 30d is set as the W dimension.

[0152] The dimensions of the multilayer ceramic capacitor 10 are not particularly limited, but the L dimension in the length direction z is 1.0 mm or more and 3.2 mm or less, the W dimension in the width direction y is 0.5 mm or more and 2.5 mm or less, and the T dimension in the height direction x is 0.3 mm or more and 2.5 mm or less. The dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0153] according to Figure 1 The illustrated multilayer ceramic capacitor 10 has the above-described structure, and thus can suppress dielectric breakdown between the third external electrode 30c and the fourth external electrode 30d connected to the second internal electrode layer 16b and the first internal electrode layer 16a, even when a high electric field is applied to the multilayer ceramic capacitor 10. As a result, the dielectric breakdown voltage (BDV) of the multilayer ceramic capacitor 10 can be increased.

[0154] 2. Manufacturing method of multilayer ceramic capacitor

[0155] Next, a method for manufacturing a multilayer ceramic capacitor according to the present invention will be described.

[0156] First, a dielectric sheet for a dielectric layer and a conductive paste for an internal electrode are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and the solvent may be known binders and solvents.

[0157] Conductive paste for the internal electrode layer is printed on the dielectric sheet in a predetermined pattern by, for example, screen printing or gravure printing, etc. Thus, a dielectric sheet having a pattern of the first internal electrode layer and a dielectric sheet having a pattern of the second internal electrode layer are prepared.

[0158] More specifically, a screen printing plate for printing the first internal electrode layer and a screen printing plate for printing the second internal electrode layer can be prepared separately, and the patterns of the respective internal electrode layers can be printed using a printer capable of printing the two screen printing plates separately.

[0159] Here, the sheets printed with the first internal electrode layer and the second internal electrode layer are stacked so as to obtain a desired structure, thereby forming a portion to be the inner layer portion 18. At this time, the sheets printed with the first internal electrode layer are more than the sheets printed with the second internal electrode layer, and two or more sheets printed with the first internal electrode layer are continuously stacked.

[0160] Next, a predetermined number of dielectric sheets without the pattern of the internal electrode layer printed thereon are stacked to form a portion that will become the second main surface side outer layer portion 20b on the second main surface side. Then, the portion that will become the inner layer portion 18 formed by the above-mentioned process is stacked on the portion that will become the second main surface side outer layer portion 20b, and a predetermined number of dielectric sheets without the pattern of the internal electrode layer printed thereon are stacked to form a portion that will become the first main surface side outer layer portion 20a on the first main surface side. In this way, a laminated sheet is produced.

[0161] Next, the laminated sheets are pressed in the laminating direction by isostatic pressing or the like to produce a laminated block.

[0162] Next, the laminated block is cut into a predetermined size to form laminated sheets. At this time, the corners and ridges of the laminated sheets may be rounded by barrel grinding or the like.

[0163] Then, the cut laminated sheets are fired to produce the laminated body 12. The firing temperature depends on the materials of the dielectric layer 14 and the internal electrode layer 16, but is preferably 900°C or higher and 1400°C or lower.

[0164] (Base electrode layer)

[0165] Next, the third foundation electrode layer 32c of the third external electrode 30c is formed on the first side surface 12c of the fired laminate 12, and the fourth foundation electrode layer 32d of the fourth external electrode 30d is formed on the second side surface 12d of the laminate 12.

[0166] When forming a sintered layer as the base electrode layer 32, a conductive paste containing a glass component and a metal component is applied and then sintered to form the sintered layer as the base electrode layer 32. The sintering temperature is preferably 700°C or more and 900°C or less.

[0167] Here, various methods can be used as a method for forming the sintered layer. For example, a method of extruding and applying a conductive paste from a slit can be used. In the case of this method, by increasing the amount of conductive paste extruded, the base electrode layer 32 can be formed not only on the first side surface 12c and the second side surface 12d, but also on a part of the first main surface 12a and a part of the second main surface 12b.

[0168] In addition, the base electrode layer 32 can also be formed by using a roller transfer method. In the case of the roller transfer method, the base electrode layer 32 can be formed not only on the first side surface 12c and the second side surface 12d, but also on a part of the first main surface 12a and a part of the second main surface 12b. By increasing the pressure during roller transfer, the base electrode layer 32 can also be formed on a part of the first main surface 12a and a part of the second main surface 12b.

[0169] Next, the first foundation electrode layer 32a of the first external electrode 30a is formed on the first end surface 12e of the fired laminate 12, and the second foundation electrode layer 32b of the second external electrode 30b is formed on the second end surface 12f of the laminate 12.

[0170] When forming a sintered layer as the base electrode layer 32, similarly to the case of forming each base electrode layer 32 of the third external electrode 30c and the fourth external electrode 30d, a conductive paste containing a glass component and a metal component is applied and then sintered to form a sintered layer as the base electrode layer 32. The temperature of the sintering treatment at this time is preferably 700° C. or higher and 900° C. or lower.

[0171] The baked layer of the base electrode layer 32 as the first external electrode 30 a and the second external electrode 30 b can be formed by applying a conductive paste by squeezing it out from a slit or by a roll transfer method.

[0172] In addition, regarding the sintering process, the third base electrode layer 32c of the third external electrode 30c, the fourth base electrode layer 32d of the fourth external electrode 30d, the first base electrode layer 32a of the first external electrode 30a, and the second base electrode layer 32b of the second external electrode 30b can be sintered simultaneously, or the third base electrode layer 32c of the third external electrode 30c, the fourth base electrode layer 32d of the fourth external electrode 30d, the first base electrode layer 32a of the first external electrode 30a, and the second base electrode layer 32b of the second external electrode 30b can be sintered separately and independently.

[0173] (Conductive resin layer)

[0174] When the base electrode layer 32 is formed by a conductive resin layer, the conductive resin layer can be formed by the following method: The conductive resin layer can be formed on the surface of the sintered layer, or the conductive resin layer can be formed directly on the laminate 12 as a single body without forming a sintered layer.

[0175] As a method for forming the conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied on the sintered layer or the laminate 12, and heat-treated at a temperature of 250° C. to 550° C. to thermally cure the resin, thereby forming the conductive resin layer. The atmosphere during the heat treatment is preferably an N2 atmosphere. In addition, in order to prevent the scattering of the resin and the oxidation of various metal components, the oxygen concentration is preferably suppressed to 100 ppm or less.

[0176] As a method for applying the conductive resin paste, similar to the method of forming the base electrode layer 32 from a sintered layer, for example, a method of applying the conductive resin paste by squeezing it out from a slit or a roll transfer method can be used.

[0177] (Thin film layer)

[0178] When the base electrode layer 32 is formed of a thin film layer, a mask or the like is provided, and the base electrode layer is formed by a thin film forming method such as sputtering or evaporation at a location where the external electrode 30 is to be formed. The base electrode layer formed of a thin film layer is a layer of 1 μm or less in which metal particles are deposited.

[0179] (Plating electrode)

[0180] Furthermore, instead of providing the base electrode layer 32, plated electrodes may be provided in the second region 26a, the third region 26b, the fifth region 28b, and the sixth region 28c of the laminate 12 where the internal electrode layer 16 is exposed. In this case, the following method can be used for formation.

[0181] The first end face 12e and the second end face 12f of the stack 12 are plated to form lower-layer plated electrodes on the second region 26b and the third region 26c, which are exposed portions of the first internal electrode layer 16a. Similarly, the first side face 12c and the second side face 12d of the stack 12 are plated to form lower-layer plated electrodes on the fifth region 28b and the sixth region 28c, which are exposed portions of the second internal electrode layer 16b. When performing the plating process, either electrolytic plating or electroless plating may be used, but electroless plating requires pretreatment with a catalyst or the like in order to increase the plating deposition rate, which has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferably used. As a plating method, drum plating is preferably used. In addition, an upper-layer plated electrode formed on the surface of the lower-layer plated electrode may also be formed as required.

[0182] Next, the plating layer 34 is formed on the surface of the base electrode layer 32 , the surface of the conductive resin layer, or the surface of the lower plating electrode or the surface of the upper plating electrode as necessary.

[0183] In more detail, in the present embodiment, a Ni plating layer is formed as a lower plating layer on the base electrode layer 32 as a sintered layer, and a Sn plating layer is formed as an upper plating layer. The Ni plating layer and the Sn plating layer are formed in sequence, for example, by a drum plating method. When performing the plating process, any one of electrolytic plating and electroless plating can also be adopted. However, electroless plating needs to be pre-treated with a catalyst etc. in order to improve the plating precipitation speed, and there is a disadvantage that the process is complicated. Therefore, it is usually preferred to adopt electrolytic plating.

[0184] As described above, the multilayer ceramic capacitor 10 according to the present embodiment is manufactured.

[0185] 3. Experimental Examples

[0186] Next, in order to confirm the effects of the laminated ceramic capacitor according to the present invention described above, a laminated ceramic capacitor was manufactured as an experimental sample, and an experiment was conducted to measure the dielectric breakdown voltage (BDV) of the laminated ceramic capacitor.

[0187] As an example, a device having an internal structure such as Figures 4 to 9 As a comparative example, a multilayer ceramic capacitor having no recessed portion in the first internal electrode layer was prepared. FIG. 10A to FIG. 12B The examples and comparative examples were produced so that the capacitance, rated voltage, and thickness of the dielectric layer were the same.

[0188] (1) Specifications of samples in the examples

[0189] First, according to the above-mentioned method for manufacturing a multilayer ceramic capacitor, multilayer ceramic capacitors according to Examples 1 to 4 having the following specifications were produced.

[0190] (Example 1)

[0191] · Structure of multilayer ceramic capacitor: 3 terminals (refer to Figure 1 )

[0192] ・Dimensions of multilayer ceramic capacitors L×W×T (including design values): 1.6mm×0.8mm×0.6mm

[0193] Material of dielectric layer: BaTiO3

[0194] Electrostatic capacitance: 0.47nF

[0195] Rated voltage: 100V

[0196] ·Thickness of dielectric layer: 23.3μm

[0197] LT section structure: refer to Figure 8

[0198] WT section structure: refer to Fig. 9

[0199] ·Structure of internal electrode layer

[0200] ·1st internal electrode layer

[0201] Material: Ni

[0202] Shape: Reference Figure 6

[0203] Number of pieces: 65 pieces

[0204] Thickness: 1.0μm

[0205] · Second internal electrode layer

[0206] Material: Ni

[0207] Shape: Reference Figure 7

[0208] Number of pieces: 3 pieces

[0209] Thickness: 1.0μm

[0210] ·External electrode structure

[0211] ·First external electrode and second external electrode

[0212] Base electrode layer: a sintered layer containing conductive metal (Cu) and glass components

[0213] Thickness of the center of the end surface: 45 μm

[0214] Plating layer: Two-layer structure of Ni plating layer and Sn plating layer

[0215] Ni plating layer thickness: 4 μm

[0216] Thickness of Sn plating layer: 4μm

[0217] · The third external electrode and the fourth external electrode

[0218] Base electrode layer: a sintered layer containing conductive metal (Cu) and glass components

[0219] Thickness of the center of the end surface: 30 μm

[0220] Plating layer: Two-layer structure of Ni plating layer and Sn plating layer

[0221] Ni plating layer thickness: 4 μm

[0222] Thickness of Sn plating layer: 4μm

[0223] (Example 2)

[0224] · Structure of multilayer ceramic capacitor: 3 terminals (refer to Figure 1 )

[0225] ・Dimensions of multilayer ceramic capacitors L×W×T (including design values): 1.6mm×0.8mm×0.6mm

[0226] Material of dielectric layer: BaTiO3

[0227] Electrostatic capacitance: 0.33nF

[0228] Rated voltage: 100V

[0229] ·Thickness of dielectric layer: 30.0μm

[0230] LT section structure: refer to Figure 8

[0231] WT section structure: refer to Fig. 9

[0232] ·Structure of internal electrode layer

[0233] ·1st internal electrode layer

[0234] Material: Ni

[0235] Shape: Reference Figure 6

[0236] Number of pieces: 57 pieces

[0237] Thickness: 1.0μm

[0238] · Second internal electrode layer

[0239] Material: Ni

[0240] Shape: Reference Figure 7

[0241] Number of pieces: 3 pieces

[0242] Thickness: 1.0μm

[0243] ·External electrode structure

[0244] ·First external electrode and second external electrode

[0245] Base electrode layer: a sintered layer containing conductive metal (Cu) and glass components

[0246] Thickness of the center of the end surface: 45 μm

[0247] Plating layer: Two-layer structure of Ni plating layer and Sn plating layer

[0248] Ni plating layer thickness: 4 μm

[0249] Thickness of Sn plating layer: 4μm

[0250] · The third external electrode and the fourth external electrode

[0251] Base electrode layer: a sintered layer containing conductive metal (Cu) and glass components

[0252] Thickness of the center of the end surface: 30 μm

[0253] Plating layer: Two-layer structure of Ni plating layer and Sn plating layer

[0254] Ni plating layer thickness: 4 μm

[0255] Thickness of Sn plating layer: 4μm

[0256] (Example 3)

[0257] · Structure of multilayer ceramic capacitor: 3 terminals (refer to Figure 1 )

[0258] ・Dimensions of multilayer ceramic capacitors L×W×T (including design values): 1.6mm×0.8mm×0.6mm

[0259] Material of dielectric layer: BaTiO3

[0260] Electrostatic capacitance: 0.22nF

[0261] Rated voltage: 100V

[0262] ·Thickness of dielectric layer: 37.7μm

[0263] LT section structure: refer to Figure 4

[0264] WT section structure: refer to Figure 5

[0265] ·Structure of internal electrode layer

[0266] ·1st internal electrode layer

[0267] Material: Ni

[0268] Shape: Reference Figure 6

[0269] Number of pieces: 70 pieces

[0270] Thickness: 1.0μm

[0271] · Second internal electrode layer

[0272] Material: Ni

[0273] Shape: Reference Figure 7

[0274] Number of pieces: Two pieces

[0275] Thickness: 1.0μm

[0276] ·External electrode structure

[0277] ·First external electrode and second external electrode

[0278] Base electrode layer: a sintered layer containing conductive metal (Cu) and glass components

[0279] Thickness of the center of the end surface: 45 μm

[0280] Plating layer: Two-layer structure of Ni plating layer and Sn plating layer

[0281] Ni plating layer thickness: 4 μm

[0282] Thickness of Sn plating layer: 4μm

[0283] · The third external electrode and the fourth external electrode

[0284] Base electrode layer: a sintered layer containing conductive metal (Cu) and glass components

[0285] Thickness of the center of the end surface: 30 μm

[0286] Plating layer: Two-layer structure of Ni plating layer and Sn plating layer

[0287] Ni plating layer thickness: 4 μm

[0288] Thickness of Sn plating layer: 4μm

[0289] (Example 4)

[0290] · Structure of multilayer ceramic capacitor: 3 terminals (refer to Figure 1 )

[0291] ・Dimensions of multilayer ceramic capacitors L×W×T (including design values): 1.6mm×0.8mm×0.6mm

[0292] Material of dielectric layer: BaTiO3

[0293] Electrostatic capacitance: 0.10nF

[0294] Rated voltage: 100V

[0295] ·Thickness of dielectric layer: 75.7μm

[0296] LT section structure: refer to Figure 4

[0297] WT section structure: refer to Figure 5

[0298] ·Structure of internal electrode layer

[0299] ·1st internal electrode layer

[0300] Material: Ni

[0301] Shape: Reference Figure 6

[0302] Number of pieces: 70 pieces

[0303] Thickness: 1.0μm

[0304] · Second internal electrode layer

[0305] Material: Ni

[0306] Shape: Reference Figure 7

[0307] Number of pieces: Two pieces

[0308] Thickness: 1.0μm

[0309] ·External electrode structure

[0310] ·First external electrode and second external electrode

[0311] Base electrode layer: a sintered layer containing conductive metal (Cu) and glass components

[0312] Thickness of the center of the end surface: 45 μm

[0313] Plating layer: Two-layer structure of Ni plating layer and Sn plating layer

[0314] Ni plating layer thickness: 4 μm

[0315] Thickness of Sn plating layer: 4μm

[0316] · The third external electrode and the fourth external electrode

[0317] Base electrode layer: a sintered layer containing conductive metal (Cu) and glass components

[0318] Thickness of the center of the end surface: 30 μm

[0319] Plating layer: Two-layer structure of Ni plating layer and Sn plating layer

[0320] Ni plating layer thickness: 4 μm

[0321] Thickness of Sn plating layer: 4μm

[0322] (2) Specifications of samples in comparative examples

[0323] Next, multilayer ceramic capacitors according to Comparative Examples 1 to 4 having the following specifications were produced.

[0324] The multilayer ceramic capacitors involved in Comparative Examples 1 and 2 are three-terminal multilayer ceramic capacitors that are the same as the multilayer ceramic capacitors involved in Examples 1 and 2, except that no recess is formed in the first internal electrode layer.

[0325] Fig. 10A LT is a cross-sectional view showing an example of a multilayer ceramic capacitor according to Comparative Examples 1 and 2. Fig. 10B WT cross-sectional view thereof. The multilayer ceramic capacitor 1A according to Comparative Examples 1 and 2 has a rectangular parallelepiped multilayer body 2, external electrodes 3 arranged on both end faces thereof, and external electrodes 4 arranged on both side faces thereof. The multilayer body 2 has a plurality of stacked dielectric layers 5 and a plurality of first internal electrode layers 6a and second internal electrode layers 6b stacked on the dielectric layers 5. The second internal electrode layer 6b is configured to divide the internal electrode stack portion 7, which is a region where two or more first internal electrode layers 6a are continuously stacked. At this time, the internal electrode stack portion 7 is divided into the first internal electrode stack portion 7a and the second internal electrode stack portion 7b by one second internal electrode layer 6b.

[0326] The detailed specifications are shown below.

[0327] (Comparative Example 1)

[0328] · Structure of multilayer ceramic capacitor: 3 terminals (refer to Fig. 9 )

[0329] ・Dimensions of multilayer ceramic capacitors L×W×T (including design values): 1.6mm×0.8mm×0.6mm

[0330] Material of dielectric layer: BaTiO3

[0331] Electrostatic capacitance: 0.47μF

[0332] Rated voltage: 100V

[0333] ·Thickness of dielectric layer: 23.3μm

[0334] LT section structure: refer to Fig. 10A

[0335] WT section structure: refer to Fig. 10B

[0336] ·Structure of internal electrode layer

[0337] ·1st internal electrode layer

[0338] Material: Ni

[0339] Shape: Reference Fig.11A

[0340] Number of pieces: 65 pieces

[0341] Thickness: 1.0μm

[0342] · Second internal electrode layer

[0343] Material: Ni

[0344] Shape: Reference Fig. 11B

[0345] Number of pieces: 3 pieces

[0346] Thickness: 1.0μm

[0347] ·External electrode structure

[0348] ·First external electrode and second external electrode

[0349] Base electrode layer: a sintered layer containing conductive metal (Cu) and glass components

[0350] Thickness of the center of the end surface: 45 μm

[0351] Plating layer: Two-layer structure of Ni plating layer and Sn plating layer

[0352] Ni plating layer thickness: 4 μm

[0353] Thickness of Sn plating layer: 4μm

[0354] · The third external electrode and the fourth external electrode

[0355] Base electrode layer: a sintered layer containing conductive metal (Cu) and glass components

[0356] Thickness of the center of the end surface: 30 μm

[0357] Plating layer: Two-layer structure of Ni plating layer and Sn plating layer

[0358] Ni plating layer thickness: 4 μm

[0359] Thickness of Sn plating layer: 4μm

[0360] (Comparative Example 2)

[0361] · Structure of multilayer ceramic capacitor: 3 terminals (refer to Fig. 9 )

[0362] ・Dimensions of multilayer ceramic capacitors L×W×T (including design values): 1.6mm×0.8mm×0.6mm

[0363] Material of dielectric layer: BaTiO3

[0364] Electrostatic capacitance: 0.33μF

[0365] Rated voltage: 100V

[0366] ·Thickness of dielectric layer: 30.0μm

[0367] LT section structure: refer to Fig. 10A

[0368] WT section structure: refer to Fig. 10B

[0369] ·Structure of internal electrode layer

[0370] ·1st internal electrode layer

[0371] Material: Ni

[0372] Shape: Reference Fig.11A

[0373] Number of pieces: 57 pieces

[0374] Thickness: 1.0μm

[0375] · Second internal electrode layer

[0376] Material: Ni

[0377] Shape: Reference Fig. 11B

[0378] Number of pieces: 3 pieces

[0379] Thickness: 1.0μm

[0380] ·External electrode structure

[0381] ·First external electrode and second external electrode

[0382] Base electrode layer: a sintered layer containing conductive metal (Cu) and glass components

[0383] Thickness of the center of the end surface: 45 μm

[0384] Plating layer: Two-layer structure of Ni plating layer and Sn plating layer

[0385] Ni plating layer thickness: 4 μm

[0386] Thickness of Sn plating layer: 4μm

[0387] · The third external electrode and the fourth external electrode

[0388] Base electrode layer: a sintered layer containing conductive metal (Cu) and glass components

[0389] Thickness of the center of the end surface: 30 μm

[0390] Plating layer: Two-layer structure of Ni plating layer and Sn plating layer

[0391] Ni plating layer thickness: 4 μm

[0392] Thickness of Sn plating layer: 4μm

[0393] The multilayer ceramic capacitors involved in Comparative Examples 3 and 4 are three-terminal multilayer ceramic capacitors that are the same as the multilayer ceramic capacitors involved in Examples 3 and 4, except that no recess is formed in the first internal electrode layer.

[0394] Fig. 12A An example of a laminated ceramic capacitor according to Comparative Examples 3 and 4 is shown. Figure 4 The corresponding cross-sectional view, Fig. 12B It is Figure 5Corresponding cross-sectional view. The multilayer ceramic capacitor 1B involved in Comparative Example 2 has a rectangular multilayer body 2, external electrodes 3 arranged on the two end faces thereof, and external electrodes 4 arranged on the two side faces thereof. The multilayer body 2 has a plurality of stacked dielectric layers 5 and a plurality of first internal electrode layers 6a and second internal electrode layers 6b stacked on the dielectric layers 5. The number of first internal electrode layers 6a is greater than the number of second internal electrode layers 6b, and two or more first internal electrode layers 6a are stacked continuously. Fig. 12A as well as Fig. 12B In the multilayer ceramic capacitor 1B shown, the second internal electrode layer 6b is arranged between the first internal electrode layer 6a located closest to the first main surface and the first main surface, and between the first internal electrode layer 6a located closest to the second main surface and the second main surface. Furthermore, the internal electrode laminated portion 7 is not divided by the first internal electrode layer 6a.

[0395] The detailed specifications are shown below.

[0396] (Comparative Example 3)

[0397] · Structure of multilayer ceramic capacitor: 3 terminals (refer to Fig. 9 )

[0398] ・Dimensions of multilayer ceramic capacitors L×W×T (including design values): 1.6mm×0.8mm×0.6mm

[0399] Material of dielectric layer: BaTiO3

[0400] Electrostatic capacitance: 0.22μF

[0401] Rated voltage: 100V

[0402] ·Thickness of dielectric layer: 37.7μm

[0403] LT section structure: refer to Fig. 12A

[0404] WT section structure: refer to Fig. 12B

[0405] ·Structure of internal electrode layer

[0406] ·1st internal electrode layer

[0407] Material: Ni

[0408] Shape: Reference Fig.11A

[0409] Number of pieces: 70 pieces

[0410] Thickness: 1.0μm

[0411] · Second internal electrode layer

[0412] Material: Ni

[0413] Shape: Reference Fig. 11B

[0414] Number of pieces: Two pieces

[0415] Thickness: 1.0μm

[0416] ·External electrode structure

[0417] ·First external electrode and second external electrode

[0418] Base electrode layer: a sintered layer containing conductive metal (Cu) and glass components

[0419] Thickness of the center of the end surface: 45 μm

[0420] Plating layer: Two-layer structure of Ni plating layer and Sn plating layer

[0421] Ni plating layer thickness: 4 μm

[0422] Thickness of Sn plating layer: 4μm

[0423] · The third external electrode and the fourth external electrode

[0424] Base electrode layer: a sintered layer containing conductive metal (Cu) and glass components

[0425] Thickness of the center of the end surface: 30 μm

[0426] Plating layer: Two-layer structure of Ni plating layer and Sn plating layer

[0427] Ni plating layer thickness: 4 μm

[0428] Thickness of Sn plating layer: 4μm

[0429] (Comparative Example 4)

[0430] · Structure of multilayer ceramic capacitor: 3 terminals (refer to Fig. 9 )

[0431] ・Dimensions of multilayer ceramic capacitors L×W×T (including design values): 1.6mm×0.8mm×0.6mm

[0432] Material of dielectric layer: BaTiO3

[0433] Electrostatic capacitance: 0.10μF

[0434] Rated voltage: 100V

[0435] ·Thickness of dielectric layer: 75.7μm

[0436] LT section structure: refer to Fig. 12A

[0437] WT section structure: refer to Fig. 12B

[0438] ·Structure of internal electrode layer

[0439] ·1st internal electrode layer

[0440] Material: Ni

[0441] Shape: Reference Fig.11A

[0442] Number of pieces: 70 pieces

[0443] Thickness: 1.0μm

[0444] · Second internal electrode layer

[0445] Material: Ni

[0446] Shape: Reference Fig. 11B

[0447] Number of pieces: Two pieces

[0448] Thickness: 1.0μm

[0449] ·External electrode structure

[0450] ·First external electrode and second external electrode

[0451] Base electrode layer: a sintered layer containing conductive metal (Cu) and glass components

[0452] Thickness of the center of the end surface: 45 μm

[0453] Plating layer: Two-layer structure of Ni plating layer and Sn plating layer

[0454] Ni plating layer thickness: 4 μm

[0455] Thickness of Sn plating layer: 4μm

[0456] · The third external electrode and the fourth external electrode

[0457] Base electrode layer: a sintered layer containing conductive metal (Cu) and glass components

[0458] Thickness of the center of the end surface: 30 μm

[0459] Plating layer: Two-layer structure of Ni plating layer and Sn plating layer

[0460] Ni plating layer thickness: 4 μm

[0461] Thickness of Sn plating layer: 4μm

[0462] (3) Method for measuring electrostatic capacitance

[0463] The electrostatic capacitance was measured using an electrostatic capacitance measuring device (LCR meter) under measurement conditions based on the standard standard (JIS C5101-1: 2010).

[0464] (4) Method for measuring the thickness of dielectric layer

[0465] The thickness of the dielectric layer of the samples according to the examples and comparative examples was measured as follows.

[0466] That is, first, the surroundings of the multilayer ceramic capacitor as a sample were reinforced with resin. At this time, the LT side of the multilayer ceramic capacitor as each sample was exposed. The so-called LT side is a length-height side, and is a side that is exposed in the internal electrode layer including the connection part to the external electrode by grinding. The LT side is ground by a grinder and ends at a depth of 1 / 2 in the width direction y of the stacked body to expose the LT cross section. The ground surface is ion-milled to remove the burrs caused by grinding, and a cross section for observation is obtained.

[0467] Next, if Fig.13 As shown, a vertical line perpendicular to the internal electrode layer is drawn at a position 1 / 2 of the length direction z of the LT section. Next, the region of the sample where the internal electrode layer is stacked (internal electrode stacking portion) is divided into three equal parts in the height direction x, thereby being divided into three regions: the upper side portion U, the middle portion M, and the lower side portion D. Then, 5 dielectric layers are selected from the center of each region in the height direction x, and the thickness of these dielectric layers on the vertical line is measured. Through the above, the thickness of the dielectric layer and the internal electrode layer is measured at a total of 15 locations of 3 regions × 5 layers for each sample, and their average value is calculated.

[0468] The thickness of the dielectric layer was measured using a scanning electron microscope.

[0469] (5) Method for determining insulation breakdown voltage

[0470] In the laminated ceramic capacitors as samples of the embodiments and comparative examples, wiring was connected to the first external electrode and the second external electrode from a DC power supply, a voltage was applied between the first internal electrode layer and the second internal electrode layer, and the voltage at which insulation breakdown occurred was measured. The voltage was increased at a boost rate of 50 V / s, and the detection current was set to 83 mA.

[0471] As experimental results, the results of the measurement of the insulation breakdown voltage are shown in Table 1 and Fig.14 .

[0472] [Table 1]

[0473]

[0474] (6) Experimental results

[0475] According to Table 1 and Fig.14 In the structures of Comparative Examples 1 to 4, when a high electric field is applied, insulation breakdown occurs between the third external electrode and the fourth external electrode arranged on a portion of the first main surface and a portion of the second main surface and the first internal electrode layer. Although the thickness of the dielectric layer increases from Comparative Examples 1 to 4, the insulation breakdown voltage (BDV) does not increase much.

[0476] On the other hand, in the structures of the present invention of Examples 1 to 4, the following result was obtained: as the thickness of the dielectric layer increased from Example 1 to Example 4, the dielectric breakdown voltage (BDV) of the multilayer ceramic capacitor increased significantly.

[0477] The above shows that the structure of the sample of the multilayer ceramic capacitor according to the embodiment can suppress the insulation breakdown between the third external electrode and the fourth external electrode connected to the second internal electrode layer and the first internal electrode layer. As a result, it is clear that the insulation breakdown voltage (BDV) of the multilayer ceramic capacitor can be improved.

[0478] In addition, as described above, although the embodiments of the present invention have been disclosed through the above description, the present invention is not limited thereto.

[0479] That is, various changes can be added to the above-described embodiments in terms of mechanism, shape, material, number, position, arrangement, etc. without departing from the scope of the technical idea and purpose of the present invention, and these are included in the present invention.

Claims

1. A multilayer ceramic capacitor comprising: A laminate having a plurality of laminated dielectric layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction and the length direction; a plurality of first internal electrode layers, arranged on the plurality of dielectric layers and led out to the first end surface and the second end surface; a plurality of second internal electrode layers, arranged on the plurality of dielectric layers and led out to the first side surface and the second side surface; a first external electrode disposed on the first end surface and connected to the first internal electrode layer; a second external electrode disposed on the second end surface and connected to the first internal electrode layer; a third external electrode disposed on the first side surface, extending from the first side surface and disposed on a portion of the first main surface and a portion of the second main surface, and connected to the second internal electrode layer; and The fourth external electrode is arranged on the second side surface, extends from the second side surface and is arranged on a part of the first main surface and a part of the second main surface, and is connected to the second internal electrode layer, wherein: The number of the first internal electrode layers is greater than the number of the second internal electrode layers, and two or more first internal electrode layers are continuously stacked. The first internal electrode layer is formed with a recessed portion so as not to overlap with the third external electrode disposed on a portion of the first main surface and a portion of the second main surface and the fourth external electrode disposed on a portion of the first main surface and a portion of the second main surface when the multilayer ceramic capacitor is viewed from the height direction. When the multilayer ceramic capacitor is viewed from the height direction, at least a portion of the recess is located between the third external electrode disposed on a portion of the first main surface and a portion of the second main surface and the fourth external electrode disposed on a portion of the first main surface and a portion of the second main surface. When the multilayer ceramic capacitor is observed from the height direction, the third external electrode disposed on a portion of the first main surface and a portion of the second main surface and the fourth external electrode disposed on a portion of the first main surface and a portion of the second main surface are substantially semicircular, and the recessed portion of the first internal electrode layer is semicircular. When the multilayer ceramic capacitor is viewed from the height direction, a distance between the substantially semicircular portion of the third external electrode disposed on a portion of the first main surface and a portion of the second main surface and the substantially semicircular portion of the fourth external electrode disposed on a portion of the first main surface and a portion of the second main surface and the semicircular arc portion of the recess of the first internal electrode layer on the same plane is 100 μm or more. The second internal electrode layer is arranged at least between the first internal electrode layer located closest to the first main surface and the first main surface, and at least between the first internal electrode layer located closest to the second main surface and the second main surface, The length of the second internal electrode layer in the longitudinal direction is smaller than the maximum length of the third external electrode arranged on a portion of the first main surface and a portion of the second main surface and the fourth external electrode arranged on a portion of the first main surface and a portion of the second main surface in the longitudinal direction.

2. The multilayer ceramic capacitor according to claim 1, wherein The second internal electrode layer extends across the first side surface and the second side surface of the stacked body and includes: a region portion located in the central portion of the dielectric layer; and a region portion extending from the region portion located in the central portion of the dielectric layer to the first side surface and the second side surface, The length of the region located in the center of the dielectric layer in the longitudinal direction connecting the first end face and the second end face is the same as the length of the extended region in the longitudinal direction connecting the first end face and the second end face.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The second internal electrode layer is arranged so as to divide a region where two or more first internal electrode layers are continuously stacked into a plurality of regions.

4. The multilayer ceramic capacitor according to claim 3, wherein: The second internal electrode layer is disposed so as to divide a region where two or more first internal electrode layers are continuously stacked into a plurality of layers.

5. The multilayer ceramic capacitor according to claim 3, wherein: The second internal electrode layer, which is arranged to divide a region where two or more first internal electrode layers are continuously stacked, into a plurality of layers, is stacked in two or more layers.

6. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The dielectric layer located between the first internal electrode layer and the second internal electrode layer has a thickness greater than that of the dielectric layer located at a position sandwiched by the first internal electrode layers.

7. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The dielectric layer located between the first internal electrode layer and the second internal electrode layer has a thickness of 30 μm or more.

8. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The shortest distance in the width direction of the first internal electrode layer at a portion where the recess is formed is shorter than the shortest distance in a portion where the recess is not formed.

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