Metal silicide manufacturing method for improving electric leakage

Abstract

The invention provides a metal silicide manufacturing method for improving electric leakage, which comprises the following steps of: providing a substrate, forming shallow trench isolation on the substrate to define an active region, forming a gate structure on the active region, forming a gate oxide layer and a gate polycrystalline silicon layer which are sequentially stacked from bottom to top on the gate structure, forming a side wall structure on the side wall of the gate structure, a source region and a drain region are formed on the active regions on the two sides of the gate structure through ion implantation; a metal barrier layer is formed, then a metal layer is formed on the metal barrier layer, and the metal barrier layer is used for slowing down the atomic diffusion speed in the metal layer; and forming metal silicide on the upper surface of the grid polycrystalline silicon layer and the source and drain regions by utilizing thermal annealing, and removing the residual metal barrier layer and metal layer. The metal barrier layer can effectively inhibit rapid diffusion of atoms of the metal layer, so that leakage current is improved.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for manufacturing metal silicide for improving leakage. Background Art

[0002] The Salicide (metal silicide) process is applied to the contact between the source, drain / gate and the metal to reduce the contact resistance and shorten the time delay associated with the gate.

[0003] The Ni-Salicide process is commonly used for technology nodes below 65nm. During high-temperature annealing, Ni atoms are the main diffusants and will diffuse rapidly into the substrate, which may cause nickel silicide to grow together with the substrate and induce leakage problems. In addition, nickel silicide is easy to agglomerate at high temperatures to form high-resistance materials, affecting the electrical properties of the device.

[0004] The existing technical method is to add 5%-10% Pt to the Ni target material, form NiPt-Salicide through doping modification, and improve the thermal stability of nickel silicide.

[0005] In order to solve the above problems, it is necessary to propose a new method for manufacturing metal silicide with improved leakage. Summary of the invention

[0006] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for manufacturing metal silicide with improved leakage, which is used to solve the problem in the prior art that during high-temperature annealing, metal atoms such as Ni atoms are the main diffusants and will diffuse rapidly into the substrate, which may cause the metal silicide to grow together with the substrate and induce leakage; the metal silicide is easy to agglomerate at high temperature to form a high-resistance material, which affects the electrical characteristics of the device.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a metal silicide with improved leakage current, comprising:

[0008] Step 1, providing a substrate, forming a shallow trench isolation on the substrate to define an active area, forming a gate structure on the active area, the gate structure consisting of a gate oxide layer and a gate polysilicon layer stacked in sequence from bottom to top, a sidewall structure formed on the sidewall of the gate structure, and forming source and drain regions on the active area on both sides of the gate structure by ion implantation;

[0009] Step 2: forming a metal barrier layer, and then forming a metal layer on the metal barrier layer, wherein the metal barrier layer is used to slow down the diffusion speed of atoms in the metal layer;

[0010] Step three: forming metal silicide on the upper surface of the gate polysilicon layer and the source and drain regions by thermal annealing, and removing the remaining metal barrier layer and the metal layer.

[0011] Preferably, the substrate in step one is a silicon substrate.

[0012] Preferably, the step of pre-amorphization ion implantation is further included before step 2.

[0013] Preferably, in step 2, the metal barrier layer and the metal layer are formed by physical vapor deposition.

[0014] Preferably, the metal barrier layer in step two does not react with the substrate and the gate polysilicon layer during the thermal annealing in step three.

[0015] Preferably, the material of the metal barrier layer in step 2 is titanium or platinum.

[0016] Preferably, the thickness of the metal barrier layer in step 2 is 1 to 5 nanometers.

[0017] Preferably, the material of the metal layer in step 2 is NiPt alloy.

[0018] Preferably, the method of forming metal silicide on the upper surface of the gate polysilicon layer and the source and drain regions by thermal annealing in step three, and removing the remaining metal barrier layer and the metal layer includes: performing a first thermal annealing to remove the remaining metal barrier layer and the metal layer; and performing a second thermal annealing.

[0019] Preferably, the first thermal annealing in step three is at 250°C-500°C, and the second thermal annealing is at 250°C-500°C.

[0020] Preferably, in step three, the remaining metal barrier layer and the metal layer are removed by wet etching.

[0021] As described above, the method for manufacturing metal silicide with improved leakage current of the present invention has the following beneficial effects:

[0022] The metal barrier layer of the present invention can effectively inhibit the rapid diffusion of metal layer atoms, thereby improving leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Shown is a schematic diagram of the process flow of the present invention;

[0024] Figure 2 It is a schematic diagram of the pre-amorphization ion implantation of the present invention;

[0025] Figure 3It is a schematic diagram of forming a metal barrier layer according to the present invention;

[0026] Figure 4 Shown is a schematic diagram of forming a metal layer according to the present invention;

[0027] Figure 5 It is a schematic diagram showing the formation of metal silicide according to the present invention;

[0028] Figure 6 It is a schematic diagram showing the improvement of SRAM IDDQ leakage of the present invention. DETAILED DESCRIPTION

[0029] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] See also Figure 1 The present invention provides a method for manufacturing a metal silicide with improved leakage current, comprising:

[0031] Step 1, providing a substrate 101, forming a shallow trench isolation 102 on the substrate 101 to define an active area, forming a gate structure on the active area, the gate structure is composed of a gate oxide layer 103 and a gate polysilicon layer 104 stacked in sequence from bottom to top, a sidewall structure 105 is formed on the sidewall of the gate structure, and ion implantation is used to form source and drain regions on the active areas on both sides of the gate structure;

[0032] In an embodiment of the present invention, the substrate 101 in step 1 is a silicon substrate.

[0033] Step 2: forming a metal barrier layer 106, the metal barrier layer 106 covers the substrate 101, the gate structure and the sidewall structure 105, forming a Figure 3 The structure shown in FIG. 1 is then formed on the metal barrier layer 106 to form a metal layer 107. Figure 4 In the structure shown, the metal barrier layer 106 is used to slow down the diffusion rate of atoms in the metal layer 107;

[0034] In the embodiments of the present invention, please refer to Figure 2 Before step 2, a pre-amorphization ion implantation step is also included, and the implanted ions may be Si / Ge ions.

[0035] In an embodiment of the present invention, in step 2, the metal barrier layer 106 and the metal layer 107 are formed by physical vapor deposition.

[0036] In the embodiment of the present invention, the metal barrier layer 106 in step two is stable and does not react with the substrate 101 and the gate polysilicon layer 104 during the thermal annealing in step three.

[0037] In an embodiment of the present invention, the material of the metal barrier layer 106 in step 2 is titanium or platinum.

[0038] In an embodiment of the present invention, the thickness of the metal barrier layer 106 in step 2 is 1 to 5 nanometers.

[0039] In an embodiment of the present invention, the material of the metal layer 107 in step 2 is NiPt alloy.

[0040] Step 3: Form metal silicide on the upper surface of the gate polysilicon layer 104 and the source and drain regions by thermal annealing, and remove the remaining metal barrier layer 106 and metal layer 107 to form Figure 5 The structure shown.

[0041] In an embodiment of the present invention, the method of forming metal silicide on the upper surface of the gate polysilicon layer 104 and the source and drain regions by thermal annealing in step three, and removing the remaining metal barrier layer 106 and the metal layer 107 includes: performing a first thermal annealing to remove the remaining metal barrier layer 106 and the metal layer 107; and performing a second thermal annealing.

[0042] In an embodiment of the present invention, the first thermal annealing in step three is at 250°C-500°C, and the second thermal annealing is at 250°C-500°C.

[0043] In the embodiment of the present invention, in step three, the remaining metal barrier layer 106 and the metal layer 107 are removed by wet etching.

[0044] See also Figure 6 ,Through experiments, the SRAM IDDQ (indicating the current drawn from the power source when the CMOS circuit is static) leakage is significantly improved by about 20%, and there is no significant difference in the metal silicide resistance.

[0045] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0046] In summary, the metal barrier layer of the present invention can effectively inhibit the rapid diffusion of metal layer atoms, thereby improving leakage current. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0047] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a metal silicide for improving leakage current, characterized in that: At least: Step 1, providing a substrate, forming a shallow trench isolation on the substrate to define an active area, forming a gate structure on the active area, the gate structure consisting of a gate oxide layer and a gate polysilicon layer stacked in sequence from bottom to top, a sidewall structure formed on the sidewall of the gate structure, and forming source and drain regions on the active area on both sides of the gate structure by ion implantation; Step 2: forming a metal barrier layer, and then forming a metal layer on the metal barrier layer, wherein the metal barrier layer is used to slow down the diffusion speed of atoms in the metal layer; Step three: forming metal silicide on the upper surface of the gate polysilicon layer and the source and drain regions by thermal annealing, and removing the remaining metal barrier layer and the metal layer.

2. The method for manufacturing a metal silicide with improved leakage current according to claim 1, characterized in that: The substrate in step one is a silicon substrate.

3. The method for manufacturing a metal silicide with improved leakage current according to claim 1, characterized in that: Before step 2, a step of pre-amorphization ion implantation is also included.

4. The method for manufacturing a metal silicide with improved leakage current according to claim 1, characterized in that: In step 2, the metal barrier layer and the metal layer are formed by physical vapor deposition.

5. The method for manufacturing metal silicide with improved leakage current according to claim 1, characterized in that: The metal barrier layer in step two does not react with the substrate and the gate polysilicon layer during the thermal annealing in step three.

6. The method for manufacturing metal silicide with improved leakage current according to claim 1, characterized in that: The material of the metal barrier layer in step 2 is titanium or platinum.

7. The method for manufacturing metal silicide with improved leakage current according to claim 1, characterized in that: The thickness of the metal barrier layer in step 2 is 1 to 5 nanometers.

8. The method for manufacturing metal silicide with improved leakage current according to claim 1, characterized in that: The material of the metal layer in step 2 is NiPt alloy.

9. The method for manufacturing metal silicide with improved leakage current according to claim 1, characterized in that: The method of using thermal annealing in step three to form metal silicide on the upper surface of the gate polysilicon layer and the source and drain regions, and removing the remaining metal barrier layer and the metal layer includes: performing a first thermal annealing to remove the remaining metal barrier layer and the metal layer; and performing a second thermal annealing.

10. The method for manufacturing metal silicide with improved leakage current according to claim 9, characterized in that: The first thermal annealing in step three is at 250°C-500°C, and the second thermal annealing is at 250°C-500°C.

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