A semiconductor structure forming method and a semiconductor structure

Abstract

The application discloses a semiconductor structure forming method and a semiconductor structure. The forming method comprises the following steps: providing a substrate, forming a plurality of photoresist mask patterns on one side of the substrate, and having an opening between two adjacent mask patterns; performing a first pretreatment process to form a polymer layer on the surface of the mask pattern on both sides of the opening; performing a first etching process to form a deep groove on the inner bottom wall of the opening; the first etching process is based on a modified Bosch process, which is a pulsed plasma etching process with helium protection; and performing a second etching process, so that the second etching acts on the sidewall surface of the deep groove. The application realizes the regulation and improvement of the etching behavior, effectively expands the etching process window, improves the sidewall defects under the high aspect ratio structure, and improves the performance and reliability of the device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor processing technology, and in particular to a semiconductor structure forming method and a semiconductor structure. Background Art

[0002] In the advanced packaging field, the Bosch process is widely used to fabricate vertical interconnect structures for through-silicon vias (TSVs) in three-dimensional integrated circuits. However, due to the periodic etching / passivation process, the Bosch process is prone to causing significant TSV sidewall roughness. This problem significantly affects the coverage of dielectric and metal steps and via filling during subsequent packaging processes. Once filled holes or voids occur, the insulation performance between the vias is affected. Therefore, it is necessary to develop a process method that can significantly reduce TSV sidewall roughness. Summary of the Invention

[0003] The purpose of this application is to overcome the above-mentioned technical problems existing in the existing Bosch process and to provide a semiconductor structure forming method and a semiconductor structure to significantly reduce the sidewall roughness of the through-silicon via.

[0004] To achieve the above objectives, the technical solutions of this application are as follows:

[0005] According to a first aspect of the present application, an embodiment of the present application provides a method for forming a semiconductor structure, comprising:

[0006] Providing a substrate, forming a plurality of photoresist mask patterns on one side of the substrate, with an opening between two adjacent mask patterns;

[0007] performing a first pretreatment process to form a polymer layer on the surface of the mask pattern on both sides of the opening;

[0008] performing a first etching process to form a deep trench on an inner bottom wall of the opening;

[0009] Performing a second etching process so that the second etching acts on the sidewall surface of the deep trench;

[0010] The first etching process is performed based on a modified Bosch process, which is a pulsed plasma etching process using helium protection.

[0011] In some embodiments, the first pretreatment process includes a pre-deposition process, which is used to: pre-protect the surface of the mask pattern by forming the polymer layer using a first process gas to reduce surface roughness; the first process gas contains a fluorine-based gas.

[0012] In some embodiments, the first process gas specifically includes C4F8, O2 and Ar.

[0013] In some embodiments, when performing the first pretreatment process, the temperature is 10° C. to 60° C., the pressure is 1 mtorr to 150 mtorr, the source power is 100 W to 1500 W, and the bias power is 10 W to 300 W.

[0014] In some embodiments, the modified Bosch process includes a plurality of periodic cycle steps sequentially formed by an etching step, a passivation layer deposition step, and an etching step; wherein the passivation layer deposition step is used to form a passivation layer, and the passivation layer is deposited on the inner wall of the deep groove and on the surface of the polymer layer.

[0015] In some embodiments, the modified Bosch process uses a second process gas containing the helium gas, and H 2 or O 2 is selectively added to the second process gas during the etching step.

[0016] In some embodiments, when performing the modified Bosch process, the temperature is 10° C. to 60° C., the pressure is 1 mtorr to 150 mtorr, the source power is 100 W to 4000 W, and the bias power is 10 W to 500 W.

[0017] In some embodiments, the second process gas includes an etching gas configured in the etching step and a passivation gas configured in the passivation layer deposition step. When H2 or O2 is selectively added to the second process gas, the flow rate of H2 is 5% to 15% of the flow rate of the etching gas, and the flow rate of O2 is 10% to 20% of the flow rate of the passivation gas.

[0018] In some embodiments, the pulsed plasma etching is used in the etching step, and the helium gas is used to accelerate the uniform distribution of plasma and the removal of reaction products to reduce the occurrence of lateral etching.

[0019] In some embodiments, the second etching process uses a third process gas including at least one of CF4, O2, Ar, and He to etch and smooth the surface layer of the sidewall of the deep trench to reduce surface roughness.

[0020] In some embodiments, when performing the second etching process, the temperature is 10° C. to 60° C., the pressure is 1 mtorr to 500 mtorr, the source power is 100 W to 1500 W, and the bias power is 10 W to 300 W.

[0021] In some embodiments, another implementation of the first pretreatment process is: the first pretreatment process is replaced by a second pretreatment process, the second pretreatment process includes a third etching process, and the third etching is applied to the surface of the mask pattern.

[0022] In some embodiments, a fourth process gas including at least one of N 2 , O 2 , and Ar is used in the third etching process to repair the surface layer of the mask pattern to reduce surface roughness.

[0023] In some embodiments, when performing the third etching process, the temperature is 10° C. to 60° C., the pressure is 1 mtorr to 150 mtorr, the source power is 100 W to 1500 W, and the bias power is 10 W to 300 W.

[0024] According to the second aspect of the present application, an embodiment of the present application further provides a semiconductor structure, which is obtained using the semiconductor structure forming method provided by any one of the embodiments of the first aspect above.

[0025] The embodiments of the present application may or at least have the following advantages:

[0026] (1) By pre-treating the surface of the photoresist mask pattern (first pre-treatment / second pre-treatment), the roughness of the sidewall of the photoresist mask pattern is significantly reduced, which can improve the density and corrosion resistance of the passivation layer formed in the subsequent modified Bosch process (main etching), improve the quality of the polymer, avoid excessive lateral etching when etching the top of the deep trench, and effectively reduce the roughness of the sidewall of the top of the deep trench, thereby laying the foundation for the subsequent main etching.

[0027] (2) By introducing helium with lower molecular weight and better thermal conductivity into the process gas (second process gas) during the main etching process instead of the argon used in the conventional Bosch process, the violent etching behavior in the top area caused by the instability of the sheath layer and the mask edge effect in the early stage of etching is reduced, and the occurrence of polymer accumulation and top roughness expansion problems is effectively prevented.

[0028] (3) By using pulsed plasma etching to etch deep trenches during the main etching, it can be combined with helium to further improve the distribution of plasma, reduce ion damage during the etching process, prevent side wall damage caused by ion scattering, and avoid the electron shielding effect, thereby improving the performance and reliability of the device.

[0029] (4) By selectively introducing H2 gas as an auxiliary gas in combination with He gas during the main etching, the extraction rate of by-products is accelerated, preventing the by-products from reacting with polymers to form complexes due to the difficulty in extracting them, thereby destroying the density of the passivation layer and improving the etching efficiency; by selectively introducing O2 gas as an auxiliary gas in combination with He gas during the main etching, a dense oxide layer can be formed, which together with the passivation layer forms a double protective film to provide protection for the etching morphology in the middle of the deep trench; therefore, while improving the quality of the passivation layer, the etching result can have better verticality and reduce the side wall roughness, thereby combining the gas characteristics of H2 gas, O2 gas and He gas with the traditional Bosch process to achieve the control and improvement of the etching behavior, effectively expand the etching process window, and lay the foundation for the subsequent smoothing of the second etching process.

[0030] (5) By introducing a second etching process as a post-processing etching step after the main etching, mild etching is performed under a high-pressure system to further smooth the sidewall roughness, thereby effectively improving or even smoothing the sidewall roughness during deep trench etching through the post-processing etching method.

[0031] In summary, through the single or coordinated regulation of the above-mentioned multiple factors, the sidewall defects of deep trenches in high aspect ratio structures are improved.

[0032] Other advantages of the present application will be described in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1-Figure 2 This is a flow chart of a method for forming a semiconductor structure according to a preferred embodiment of the present application.

[0034] Figure 3 A schematic cross-sectional view of a structure obtained after forming a photoresist mask pattern in a semiconductor structure forming method provided in a preferred embodiment of the present application.

[0035] Figure 4 A schematic cross-sectional view of a structure obtained after pre-treating the surface of a photoresist mask pattern in a method for forming a semiconductor structure provided in a preferred embodiment of the present application, wherein Figure 4 (a) is the first preprocessing, Figure 4 (b) is the second preprocessing.

[0036] Figure 5 A schematic cross-sectional view of a deep trench intermediate structure formed when a first etching process is performed in a semiconductor structure forming method provided by a preferred embodiment of the present application.

[0037] Figure 6A schematic cross-sectional view of a structure obtained after a second etching process is performed on a formed deep trench in a semiconductor structure forming method provided in a preferred embodiment of the present application.

[0038] Figure 7 A schematic diagram of the surface morphology comparison of a photoresist mask pattern before and after pretreatment in a semiconductor structure forming method provided by a preferred embodiment of the present application is shown in FIG. Figure 7 (a) before pretreatment, Figure 7 (b) After the first pretreatment, Figure 7 (c) After the second pretreatment.

[0039] Figure 8 A schematic diagram of the deep trench morphology, sidewall morphology and sidewall slice electron microscope diagram after post-processing in a semiconductor structure formation method provided by a preferred embodiment of the present application, wherein Figure 8 (a) is the deep groove morphology, Figure 8 (b) is the side wall morphology, Figure 8 (c) is a side wall slice.

[0040] Figure 9 The morphology, sidewall morphology and sidewall slice electron microscope diagram of a deep trench formed by a traditional process are provided as a comparative example, wherein Figure 9 (a) is the deep groove morphology, Figure 9 (b) is the side wall morphology, Figure 9 (c) is a side wall slice.

[0041] In the figure, 10. substrate; 20. mask pattern; 30. opening; 40. polymer layer; 50. passivation layer; 60. deep trench intermediate structure; 70. deep trench. DETAILED DESCRIPTION

[0042] In the traditional Bosch process, repeated passivation deposition can cause periodic scallop-like ripples, resulting in through-silicon via (TSV) sidewall roughness defects. These periodic ripples vary across the top, middle, and bottom of the via due to the combined effects of the physicochemical processes of the etching and passivation cycles, plasma distribution, ion bombardment energy gradient, and reaction product removal efficiency. At the top of the via, where etching is intense due to mask edge effects, high ion bombardment, and reaction product accumulation, the ripples exhibit the largest amplitude and most pronounced spacing. In the middle of the via, where etching and passivation processes are relatively stable, the ripples exhibit a relatively uniform and regular amplitude. At the bottom of the via, the ripples vary in amplitude and structure, depending on the reaction product removal and passivation layer accumulation.

[0043] Although the traditional Bosch process is mature, it is constrained by the complexity of the etching process and the narrow process window during actual adjustment, resulting in high economic and time costs for optimization. In addition, due to the edge effect of the mask, the passivation layer is insufficiently deposited in the edge area, which aggravates the etching behavior at the top. The ion bombardment is more concentrated at the top, resulting in increased lateral etching in this area during etching, forming deeper and rougher ripples. At the same time, under high aspect ratio etching structures, the ion energy decays, making it increasingly difficult for ions to enter and exit the trenches, and the extraction of etching byproducts (SiF4) is also hindered, resulting in irregular ripple structures, making regulation very difficult. For the above reasons, it is difficult to deal with the contradiction between improving the sidewall roughness and maintaining the etching morphology. It is necessary to find a new method that can both improve the sidewall roughness and maintain the etching morphology.

[0044] In response to the above problems, an embodiment of the present application provides a method for forming a semiconductor structure. By establishing a complete set of methods for pre-treatment of the mask, main etching based on the modified Bosch process, and post-processing etching, an etching process improvement scheme for deep trench (silicon via) structures with high aspect ratios is provided, and through the regulation of multiple factors, the sidewall defects under the high aspect ratio structure are improved.

[0045] The embodiment of the present application also provides a semiconductor structure obtained using the semiconductor structure formation method provided by the embodiment of the present application.

[0046] The specific implementation methods of this application are described in detail below with reference to the accompanying drawings.

[0047] refer to Figure 1 The present invention provides a method for forming a semiconductor structure, which includes the following steps:

[0048] Step S11: providing a substrate.

[0049] refer to Figure 3 In some embodiments, a silicon wafer may be used as the substrate 10 (ie, a silicon substrate), so that a desired deep trench serving as a through-silicon via (TSV) may be further formed on the substrate 10 .

[0050] In some embodiments, the silicon wafer may be doped to provide the substrate 10 with desired electrical properties.

[0051] In some embodiments, integrated circuits, such as transistor structures, may be fabricated on the substrate 10 , so that after forming through silicon vias (deep trenches), required vertical interconnections can be achieved through the through silicon vias.

[0052] Step S12: forming a plurality of photoresist mask patterns on one side of the substrate, with an opening between two adjacent mask patterns.

[0053] refer to Figure 3In some embodiments, a photoresist layer is formed on one side of the substrate 10, for example, on the upper surface of the substrate 10 shown in the figure, as a mask layer. A photolithography process is then performed on the photoresist layer to form a plurality of photoresist mask patterns 20 on the upper surface of the substrate 10. An opening 30 serving as an etching window is defined between any two adjacent mask patterns 20.

[0054] It should be noted that Figure 3 The figure schematically shows a case where two photoresist mask patterns 20 are formed on the upper surface of the substrate 10. However, it is understood that more photoresist mask patterns 20 may be formed on the upper surface of the substrate 10, such as three photoresist mask patterns, four photoresist mask patterns, ten photoresist mask patterns, etc., and the present invention is not limited thereto.

[0055] It should also be noted that a protective layer or other hard mask layer may also be formed on the upper surface of substrate 10 below the photoresist layer. The protective layer may be, for example, a silicon dioxide layer, and the hard mask layer may be, for example, a silicon dioxide layer, a silicon oxynitride layer, a silicon nitride layer, or a combination thereof. To facilitate the focus of the embodiments of the present application, the protective layer or other hard mask layers are not shown or described, but this does not mean that they do not exist.

[0056] The photoresist mask pattern 20 formed after photolithography has a relatively rough pattern surface ( Figure 3 The photoresist mask pattern 20 is drawn in a borderless manner to illustrate the rough morphology of the pattern surface), as shown in FIG. Figure 7 (a) Due to the mask edge effect, the passivation layer will be insufficiently deposited at the edge during the subsequent main etch, exacerbating the etching behavior at the top. Ion bombardment is more concentrated at the top, and lateral etching in this area is intensified during etching, resulting in deeper and rougher sidewall ripples at the top of the deep trench. Therefore, it is necessary to improve the rough surface of the photoresist mask pattern 20 through pretreatment to improve the quality of the subsequent passivation layer deposition at the edge of the mask pattern 20, reduce the degree of lateral etching at the top of the deep trench, and thus achieve the effect of reducing sidewall ripples.

[0057] Step S13: performing a first pretreatment process to form a polymer layer on the surface of the mask pattern on both sides of the opening.

[0058] refer to Figure 4 (a) The rough surface of the photoresist mask pattern 20 is pre-treated by a first pre-treatment process, with the goal of pre-forming a polymer layer 40 on the surface of the mask pattern 20 on both sides of the opening 30 .

[0059] In some embodiments, the first pretreatment process includes a pre-deposition process. By using the pre-deposition process, a polymer layer 40 ( Figure 4 (highlighted by the thick solid line in (a)), this can pre-fill and level the rough surface of the photoresist mask pattern 20. Thus, when the modified Bosch process of the embodiment of this application is subsequently used for the main etch, the passivation layer can be deposited on the relatively smooth polymer layer 40, thereby improving the density and etching resistance of the passivation layer, enhancing the quality of the passivation layer polymer, and avoiding excessive lateral etching when etching the top of the deep trench. This effectively reduces the roughness of the sidewalls at the top of the deep trench, thus laying the foundation for the subsequent main etch.

[0060] In some embodiments, a first process gas containing a fluorine-based gas is used in the pre-deposition process, so that a polymer layer 40 can be formed on the rough surface of the mask pattern 20 by using the first process gas, and the surface of the mask pattern 20 is pre-protected to reduce the surface roughness, thereby effectively suppressing excessive lateral etching when etching the top of the deep trench.

[0061] In some embodiments, the first process gas containing fluorine-based gas used in the pre-deposition process specifically includes C4F8, O2 and Ar, but is not limited thereto. In this way, (CF2) can be formed on the rough surface of the mask pattern 20. n The polymer layer 40, and the (CF2) of the polymer layer 40 n Components and polymers (CF2) that form a passivation layer in subsequent etching n The composition of the polymer is consistent with that of the polymer and can be used as a base layer during the deposition of the passivation layer, thereby improving the density and corrosion resistance of the deposited passivation layer, and ultimately improving the deposition quality of the entire polymer.

[0062] In some embodiments, when performing the first pretreatment process, i.e., the pre-deposition process, the temperature is 10° C. to 60° C. For example, the temperature may be 10° C., 14° C., 21° C., 26° C., 32° C., 37° C., 42° C., 45° C., 49° C., 58° C., or 60° C., but is not limited thereto.

[0063] In some embodiments, during the first pretreatment process, i.e., the pre-deposition process, the pressure is 1 mtorr to 150 mtorr. For example, the pressure may be 1 mtorr, 10 mtorr, 21 mtorr, 39 mtorr, 58 mtorr, 77 mtorr, 95 mtorr, 112 mtorr, 130 mtorr, or 150 mtorr, but is not limited thereto.

[0064] In some embodiments, when performing the first pretreatment process, that is, performing the pre-deposition process, the source power is 100 W to 1500 W. For example, the source power can be 100 W, 212 W, 420 W, 645 W, 864 W, 1198 W, 1300 W, 1455 W, or 1500 W, but is not limited thereto.

[0065] In some embodiments, when performing the first pretreatment process, that is, performing the pre-deposition process, the bias power is 10 W to 300 W. For example, the bias power can be 10 W, 20 W, 60 W, 95 W, 124 W, 191 W, 230 W, 256 W, 280 W, or 300 W, but is not limited thereto.

[0066] By selecting and combining the values ​​of various process parameters within the above-mentioned temperature, pressure, source power, and bias power ranges, the desired polymer layer 40 can be formed on the rough surface of the mask pattern 20, which can significantly reduce the roughness of the side walls of the photoresist mask pattern 20 and improve the density and corrosion resistance of the subsequent passivation layer, thereby laying the foundation for the subsequent main etching.

[0067] After the above pre-deposition process, the polymer layer formed on the surface of the photoresist mask pattern is as follows: Figure 7 As shown in (b) (the lateral L-shaped reflection in the figure is the surface profile of the polymer layer). It can be seen that the originally rough surface of the mask pattern is improved and becomes smoother due to the filling effect of the polymer layer, which is consistent with the Figure 7 (a) The rough surface of the photoresist mask pattern without pretreatment forms a sharp contrast, which is beneficial to the deposition of the subsequent passivation layer and can improve the density and corrosion resistance of the deposited passivation layer.

[0068] Step S14: performing a first etching process to form a deep trench on the inner bottom wall of the opening; wherein the first etching process is performed based on a modified Bosch process, which is a pulsed plasma etching process using helium protection.

[0069] refer to Figure 5 The first etching process is a modified Bosch process, resulting from an optimization of the traditional Bosch process. This modified Bosch process uses helium as the shielding gas, replacing the argon used in the traditional Bosch process, and employs pulsed plasma etching for the main etching. During the modified Bosch process, the photoresist mask pattern 20 with the polymer layer 40 formed in the previous step is used as a common mask to etch the upper surface of the substrate 10 exposed within the opening 30 (the main etching), thereby forming a deep trench (through-silicon via) on the inner bottom wall of the opening 30, with its bottom located in the substrate 10. Figure 5 The deep trench intermediate structure 60 formed when the first etching process is performed is shown. The structure of the deep trench 70 obtained after the first etching process is completed can be referred to Figure 6 .Depend on Figure 5 and Figure 6 It can be seen that the final depth of the deep trench 70 in its finished form is greater than the depth of the deep trench intermediate structure 60 .

[0070] In some embodiments, the modified Bosch process includes multiple periodic cycles of etching, passivation layer deposition, and etching. In the embodiments of the present application, a pulsed plasma etching method with helium protection is used when performing the modified Bosch process. Specifically, the pulsed plasma etching method includes multiple periodic pulse cycles of alternating on and off bias power.

[0071] Among the multiple periodic cycles of etching, passivation layer deposition, and etching, pulsed plasma etching is used in the etching step (or steps). When the bias power is on, high-energy ions bombard the surface of substrate 10, activating the etching reaction. When the bias power is off, the plasma extinguishes or the power drops sharply, allowing the deposited passivation layer 50 to effectively protect the sidewalls and remove byproducts. By varying the pulse frequency and duty cycle, plasma parameters can be controlled, resulting in a more uniform distribution of reactive particles in the plasma and ultimately improving the plasma distribution.

[0072] Compared to the continuous plasma etching method used in the traditional Bosch process, the pulsed plasma etching method used in the embodiment of the present application is to periodically turn on and off the bias power. In each pulse period, the time that the ions are in a high-energy state is relatively short, thereby reducing the cumulative damage to the surface of the substrate 10 material, and giving time for charge release, avoiding charge accumulation. The use of helium can accelerate the uniform distribution of plasma and accelerate the removal of reaction products. Therefore, by adopting a pulsed plasma etching method protected by helium, the plasma distribution can be further optimized, charge release can be helped, etching damage can be reduced, and the anisotropy of etching can be optimized. At the same time, the removal of reaction products can be further optimized, and the occurrence of lateral etching can be reduced, thereby effectively reducing the sidewall roughness.

[0073] In some embodiments, in the etching step, the passivation layer deposition step, and the multiple periodic cycle steps of the modified Bosch process, the passivation layer deposition step is used to form a protective passivation layer 50 (mainly (CF2) n The passivation layer 50 formed by the polymer is deposited not only on the inner wall of the deep trench intermediate structure 60, but also on the surface of the polymer layer 40 formed by the first pretreatment process. Figure 5 The passivation layer 50 is schematically shown ( Figure 5The deposition of photoresist (highlighted by two thick vertical solid lines) on the polymer layer on the sidewall surfaces of the mask pattern 20 on both sides of the opening 30 and on the sidewalls of the deep trench intermediate structure 60 (the bottom of the deep trench intermediate structure 60 has undergone a one-step etching process, so the passivation layer at the bottom sidewall is laterally etched away). Therefore, by performing the first pretreatment process, the roughness of the surface of the photoresist mask pattern 20 is repaired, improving the density and etching resistance of the subsequently deposited passivation layer 50. In conjunction with the helium-shielded pulsed plasma etching process, the plasma distribution is improved, ion damage during the etching process is reduced, sidewall damage caused by ion scattering is prevented, and electron shielding effects are avoided, thereby effectively preventing the impact on device performance and reliability.

[0074] In some embodiments, the modified Bosch process (first etching process) employed in the embodiments of the present application utilizes a second process gas. The second process gas includes a first sub-process gas for the etching step and a second sub-process gas for the passivation layer deposition step. The first sub-process gas includes a fluorine-based etching gas and a carrier gas, while the second sub-process gas includes a fluorine-based passivation gas and a carrier gas. A typical fluorine-based etching gas may be, for example, but not limited to, SF6; a typical fluorine-based passivation gas may be, for example, but not limited to, C4F8. In the embodiments of the present application, helium (He) is used as the carrier gas to implement a pulsed plasma etching process with helium protection.

[0075] It is worth noting that argon (Ar) gas is generally used as a carrier gas in the traditional Bosch process. However, studies have found that argon gas, due to its relatively large molecular weight and relatively poor thermal conductivity, can easily cause instability of the sheath layer in the early stage of etching, aggravate the violent etching behavior of the top area caused by the mask edge effect, and lead to the occurrence of polymer accumulation and top roughness expansion problems. Based on this, in the embodiment of the present application, when performing the main etching in the improved Bosch process as the first etching process, helium with a lower molecular weight and better thermal conductivity than argon is used as a carrier gas in the second process gas instead of argon (that is, argon is not used when the main etching is performed in the embodiment of the present application), which can reduce the instability of the sheath layer in the early stage of etching and the violent etching behavior of the top area caused by the mask edge effect, and thus can effectively prevent polymer accumulation and the expansion of the top roughness.

[0076] In addition, it is not excluded that the above step S14 may be performed by using nitrogen instead of argon in the second process gas used in the modified Bosch process.

[0077] In some embodiments, when performing the etching step in the periodic cycle step of the modified Bosch process, a small amount of H 2 or O 2 is selectively added to the second process gas (first sub-process gas) according to different needs.

[0078] Among them, when performing the main etching, by introducing H2 gas as an auxiliary gas in combination with He gas, it can help the etching by-product (SiF4) to be quickly extracted, preventing the by-product from being difficult to extract and reacting with the polymer (CF2). n The reaction generates a composite (such as Si-CF), which destroys the compactness of the passivation layer 50 and improves the etching efficiency.

[0079] If O2 gas is introduced as an auxiliary gas in combination with He gas in the main etching step, a dense oxide layer can be formed, which together with the passivation layer 50 forms a double protective film to provide protection for the middle part of the morphology when etching deep grooves. While improving the quality of the passivation layer 50, it can make the etching result more vertical and reduce the side wall roughness.

[0080] Therefore, when it is difficult to remove etching byproducts and the already formed sidewall ripples are difficult to remove due to polymer adhesion, H2 can be added to the second process gas to help remove the byproducts. When lateral etching is aggravated due to insufficient passivation layer deposition or poor deposition quality of the passivation layer 50, O2 can be introduced into the second process gas to protect the sidewalls.

[0081] Therefore, the embodiment of the present application introduces auxiliary gases including He, O2 and H2 in the main etching process, combines the characteristics of these gases themselves with the traditional Bosch process, realizes the regulation and improvement of the etching behavior, effectively expands the etching process window, and lays the foundation for the subsequent smoothing of the second etching process.

[0082] It should be noted that when performing the above-mentioned main etching, H2 and O2 as auxiliary gases cannot be added to the second process gas at the same time.

[0083] In some embodiments, the second process gas includes an etching gas (e.g., SF6) configured in the above-mentioned etching step and a passivation gas (e.g., C4F8) configured in the above-mentioned passivation layer deposition step. When H2 is selectively added to the second process gas, the flow rate of H2 is 5% to 15% of the flow rate of the etching gas configured in the second process gas, which can better accelerate the extraction of by-products. For example, the flow rate of the added H2 can be 5%, 5.1%, 5.5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 14.6% or 15% of the flow rate of the etching gas configured in the second process gas, but is not limited thereto.

[0084] In some embodiments, when O2 is selectively added to the second process gas, the O2 flow rate is 10% to 20% of the passivation gas flow rate configured in the second process gas, which can effectively protect the sidewalls. For example, the added O2 flow rate can be 10%, 10.2%, 11.5%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19.3%, or 20% of the passivation gas flow rate configured in the second process gas, but is not limited to these.

[0085] In some embodiments, when performing the modified Bosch process (first etching process), the temperature is 10° C. to 60° C. For example, the temperature may be 10° C., 10.1° C., 11° C., 22° C., 28° C., 35° C., 36° C., 44° C., 49° C., 59° C., or 60° C., but is not limited thereto.

[0086] In some embodiments, during the modified Bosch process (first etching process), the pressure is 1 mtorr to 150 mtorr. For example, the pressure may be 1 mtorr, 1.2 mtorr, 20 mtorr, 40 mtorr, 55 mtorr, 80 mtorr, 100 mtorr, 125 mtorr, 140 mtorr, or 150 mtorr, but is not limited thereto.

[0087] In some embodiments, when performing the modified Bosch process (first etching process), the source power is 100 W to 4000 W. For example, the source power can be 100 W, 200 W, 500 W, 800 W, 1000 W, 1500 W, 2000 W, 3000 W, or 4000 W, but is not limited thereto.

[0088] In some embodiments, when performing the modified Bosch process (first etching process), the bias power is 10 W to 500 W. For example, the bias power can be 10 W, 50 W, 90 W, 130 W, 180 W, 240 W, 300 W, 350 W, 400 W, or 500 W, but is not limited thereto.

[0089] By selecting and combining the values ​​of various process parameters within the above-mentioned temperature, pressure, source power, and bias power ranges, and adjusting the flow rate of selectively added O2 or H2, the etching behavior can be comprehensively controlled and improved, effectively expanding the etching process window and laying a good foundation for the subsequent smoothing of the deep trench sidewalls.

[0090] Step S15: performing a second etching process to allow the second etching to act on the sidewall surface of the deep trench.

[0091] refer to Figure 6When the first etching process is performed to the target depth, the etching of the deep trench is completed, and a deep trench 70 with the target depth is formed. Then, by performing the second etching process (post-processing process), the sidewall surface of the deep trench 70 is etched as a post-processing (second etching), and the second etching is applied to the sidewall surface of the deep trench 70 to further improve the sidewall roughness of the deep trench 70. The completed structure of the deep trench 70 after post-processing is also as shown. Figure 6 shown.

[0092] In some embodiments, a third process gas including at least one of CF 4 , O 2 , Ar, and He is used in the second etching process to perform etching and smoothing treatment on the sidewall surface of the deep trench 70 to reduce surface roughness.

[0093] In some embodiments, the second etching process is performed at a temperature of 10° C. to 60° C. For example, the temperature may be 10° C., 15° C., 20° C., 26° C., 30° C., 35° C., 40° C., 46° C., 51° C., 57° C., or 60° C., but is not limited thereto.

[0094] In some embodiments, during the second etching process, the pressure is 1 mtorr to 500 mtorr. For example, the pressure may be 1 mtorr, 2 mtorr, 10 mtorr, 30 mtorr, 61 mtorr, 85 mtorr, 104 mtorr, 150 mtorr, 200 mtorr, 254 mtorr, 300 mtorr, 347 mtorr, 420 mtorr, 488 mtorr, or 500 mtorr, but is not limited thereto.

[0095] In some embodiments, during the second etching process, the source power is 100 W to 1500 W. For example, the source power may be 100 W, 210 W, 400 W, 700 W, 900 W, 1100 W, 1250 W, 1300 W, 1400 W, or 1500 W, but is not limited thereto.

[0096] In some embodiments, during the second etching process, the bias power is 10 W to 300 W. For example, the bias power may be 10 W, 30 W, 55 W, 76 W, 100 W, 150 W, 200 W, 240 W, 290 W, or 300 W, but is not limited thereto.

[0097] When performing the second etching process, the values ​​of various process parameters are selected and combined within the above-mentioned temperature, pressure, source power, and bias power ranges, and gases such as CF4, O2, Ar, and He are used to perform mild post-etching treatment under the above-mentioned high-pressure system. This can effectively smooth the sidewall roughness of the deep trench 70, and can effectively improve or even smooth the sidewall roughness after deep trench etching.

[0098] Figure 8 The figure shows the morphology, sidewall morphology and sidewall slice examples of the deep trench after post-processing in the embodiment of the present application. It can be seen that the deep trench after post-processing not only has good sidewall verticality, but also has less residual polymer (the shadow area is small and the color is light) due to the smoother sidewalls. Figure 8 (a) , no obvious transverse ripples are observed on the sidewalls of the deep trench after post-processing ( Figure 8 (b)), and the side wall section shows that the side wall after post-processing has a smooth morphology ( Figure 8 (c)), reflecting that the roughness is very small.

[0099] and Figure 9 The deep trench formed by the traditional process without post-processing shown in the comparative example has a relatively rough sidewall and a large amount of residual polymer (the shadow area is large and the color is dark) ( Figure 9 (a) ), obvious transverse ripples can be seen on the sidewalls of the deep grooves ( Figure 9 (b)), and the side wall section shows a serrated morphology ( Figure 9 (c)), reflecting the greater roughness ( Figure 9 (c) shows a feature where the corrugation step height is measured to be as high as 82.29 nm.

[0100] Therefore, the deep trench 70 after post-processing according to the above embodiment of the present application has a better sidewall morphology than the prior art.

[0101] Another implementation of a semiconductor structure forming method of the present application is described in detail below through specific implementations and in conjunction with the accompanying drawings.

[0102] refer to Figure 2 Combined with reference Figure 3 、 Figure 4 (b) Figure 5 and Figure 6 The present invention provides another method for forming a semiconductor structure, which includes the following steps:

[0103] Step S21: Provide a substrate 10 (eg Figure 3 shown).

[0104] Step S22: forming a plurality of photoresist mask patterns 20 on one side of the substrate 10, with an opening 30 (eg, Figure 3 shown).

[0105] Step S23: performing a second pretreatment process, wherein the second pretreatment process includes a third etching process, and the third etching process acts on the surface of the mask pattern 20 (eg Figure 4(b)).

[0106] Step S24: Perform a first etching process to form a deep trench 70 on the inner bottom wall of the opening 30 (refer to Figure 5 、 Figure 6 ); wherein, the first etching process is performed based on the improved Bosch process, which is a pulsed plasma etching process using helium protection.

[0107] Step S25: Perform a second etching process to allow the second etching to act on the sidewall surface of the deep trench 70 (eg Figure 6 shown).

[0108] and Figure 1 Compared with the embodiment, steps S21, S22, S24 and S25 in this embodiment are Figure 1 Steps S11, S12, S14 and S15 in the embodiment correspond to and are identical with each other, except that step S23 is used instead of step S15 in the embodiment. Figure 1 Step S13 in the embodiment, that is, the second pretreatment process is used to replace Figure 1 In other words, the first pretreatment process in the embodiment is replaced by the third etching process in this embodiment. Figure 1 For the steps S21, S22, S24 and S25 in this embodiment, please refer to the above Figure 1 The description of step S11, step S12, step S14 and step S15 in the embodiment is combined with Figure 3 、 Figure 5 and Figure 6 It is understood that no further details will be given. The following only describes step S23 as a distinguishing step in this embodiment in detail.

[0109] refer to Figure 4 (b) After executing step S21 and step S22, a plurality of photoresist mask patterns 20 are formed on the upper surface of the substrate 10 (refer to Figure 3 ), but because the photoresist mask pattern 20 has a relatively rough pattern surface (such as Figure 7 (a)). Therefore, pretreatment is required to repair the rough surface of the photoresist mask pattern 20. This improves the density and etching resistance of the subsequent passivation layer 50 when deposited at the edge of the mask pattern 20. This improves the deposition quality of the passivation layer 50, reduces the degree of lateral etching at the top of the deep trench 70, and thus reduces sidewall ripples. Unlike the pre-deposition process used as the first pre-treatment process in the above embodiment, this embodiment uses a pre-etching (third etch, Descum) method as a second pre-treatment of the rough surface of the photoresist mask pattern 20 to repair the surface layer of the mask pattern 20 and reduce surface roughness.

[0110] In some embodiments, when the second pretreatment process is performed in step S23 , a maskless etching method is adopted so that the etching action acts on the exposed surface of the photoresist mask pattern 20 on the substrate 10 including the sidewalls.

[0111] In some embodiments, a fourth process gas is used in the third etching process to etch the surface layer of the mask pattern 20. The fourth process gas includes at least one of N2, O2, and Ar, but is not limited thereto. Thus, by etching the surface layer of the mask pattern 20 with the fourth process gas, the surface layer of the mask pattern 20 can be repaired to reduce the surface roughness, and after the repair, the mask pattern 20 has a smooth surface ( Figure 4 In (b), the smooth outline of the mask pattern 20 is represented by a thin solid line for distinction).

[0112] In some embodiments, the temperature during the third etching process is 10° C. to 60° C. For example, the temperature may be 10° C., 11° C., 24° C., 27° C., 33° C., 36° C., 43° C., 44° C., 47° C., 55° C., 59° C., or 60° C., but is not limited thereto.

[0113] In some embodiments, during the third etching process, the pressure is 1 mtorr to 150 mtorr, for example, 1 mtorr, 8 mtorr, 15 mtorr, 30 mtorr, 50 mtorr, 70 mtorr, 90 mtorr, 110 mtorr, 135 mtorr, 145 mtorr, or 150 mtorr, but is not limited thereto.

[0114] In some embodiments, during the third etching process, the source power is 100 W to 1500 W. For example, the source power may be 100 W, 150 W, 260 W, 346 W, 460 W, 551 W, 650 W, 760 W, 886 W, 950 W, 1050 W, 1105 W, 1200 W, 1300 W, 1400 W, or 1500 W, but is not limited thereto.

[0115] In some embodiments, during the third etching process, the bias power is 10 W to 300 W. For example, the bias power may be 10 W, 15 W, 30 W, 55 W, 80 W, 120 W, 180 W, 200 W, 250 W, or 300 W, but is not limited thereto.

[0116] By selecting and combining the values ​​of various process parameters within the above-mentioned temperature, pressure, source power, and bias power ranges, the rough surface of the mask pattern 20 can be well repaired during the third etching process, which can significantly reduce the roughness of the side walls of the photoresist mask pattern 20 and improve the density and corrosion resistance of the subsequently deposited passivation layer 50, thereby laying the foundation for the subsequent main etching.

[0117] like Figure 7 As shown in (c), after the third etching process, the rough surface of the mask pattern is well repaired and the roughness is significantly reduced. Figure 7 (a) There is a significant improvement, which makes the originally rough surface of the mask pattern smoother, which is beneficial to the subsequent deposition of the passivation layer and can improve the density and corrosion resistance of the deposited passivation layer.

[0118] Afterwards, referring to the aforementioned steps S14 and S15, steps S24 and S25 of this embodiment are executed, and the formation of the deep trench 70 is completed based on a semiconductor structure forming method of the second pre-processing. Figure 5 The passivation layer 50 is deposited not only on the inner wall of the deep trench intermediate structure 60 but also on the sidewall of the mask pattern 20 repaired by the third etching process (there is no polymer layer 40 on the surface of the mask pattern 20).

[0119] The embodiment of the present application also provides a semiconductor structure using the above-mentioned Figure 1 Example or Figure 2 The semiconductor structure forming method corresponding to the embodiment is obtained.

[0120] refer to Figure 6 In some embodiments, the semiconductor structure includes a substrate 10 and a deep trench 70 formed on the substrate 10 using the semiconductor structure forming method of the above embodiment.

[0121] In some embodiments, the semiconductor structure is applied to the field of three-dimensional advanced packaging, and utilizes deep trenches formed on a substrate as through-silicon via (TSV) vertical interconnect structures on a 3D integrated circuit chip.

[0122] In a third aspect, embodiments of the present application further provide a plasma processing apparatus for performing the semiconductor structure forming method corresponding to the above embodiments to produce the semiconductor structure corresponding to the above embodiments. The plasma processing apparatus may be, for example, an inductively coupled plasma (ICP) etching apparatus or a capacitively coupled plasma (CCP) etching apparatus.

[0123] In other aspects, embodiments of the present application further provide an electronic device comprising the semiconductor structure of the aforementioned embodiment or a semiconductor structure fabricated using the semiconductor structure forming method of the aforementioned embodiment. The electronic device may be a storage device, a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, or the like.

[0124] In summary, the embodiments of the present application, through the aforementioned pretreatment of the mask pattern 20 surface topography (first or second pretreatment), the main etching step based on the modified Bosch process, and the coordinated control of multiple factors in the post-process etching, form a complete set of etching process optimization solutions for deep trenches 70 (TSVs) with high aspect ratio structures. This achieves the control and improvement of etching behavior, effectively expands the etching process window, improves the sidewall defects of deep trenches 70 in high aspect ratio structures, and enhances device performance and reliability. This application effectively resolves the previously difficult dilemma of improving sidewall roughness and maintaining etched topography.

[0125] The above are only preferred embodiments of the present application, and the embodiments are not intended to limit the scope of protection of the present application. Therefore, any equivalent changes made using the description and drawings of the present application should also be included in the scope of protection of the present application.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, forming a plurality of photoresist mask patterns on one side of the substrate, with an opening between two adjacent mask patterns; performing a first pretreatment process to form a polymer layer on the surface of the mask pattern on both sides of the opening; The first pretreatment process includes a pre-deposition process, wherein the pre-deposition process is used to: pre-protect the surface of the mask pattern by forming the polymer layer using the first process gas to reduce the surface roughness; Performing a first etching process to form a deep trench on the inner bottom wall of the opening; wherein the first etching process is performed based on a modified Bosch process, the modified Bosch process is a pulsed plasma etching process using helium protection, the modified Bosch process includes a plurality of periodic cycle steps formed in sequence by an etching step, a passivation layer deposition step, and an etching step, the passivation layer deposition step is used to form a passivation layer, the passivation layer is deposited on the inner wall of the deep trench and on the surface of the polymer layer; the composition of the polymer layer (40) is consistent with the composition of the passivation layer; Performing a second etching process to allow the second etching to act on the sidewall surface of the deep trench to perform etching and smoothing processing to further improve the sidewall roughness; Among them, the first pretreatment process is used to improve the deposition quality of the passivation layer, avoid excessive lateral etching when etching the top of the deep trench, and reduce the roughness of the side wall of the top of the deep trench; the improved Bosch process uses a second process gas containing the helium, and when performing the etching step, O2 is added to the second process gas without adding H2 to form a dense oxide layer, which forms a double protective film together with the passivation layer to provide protection for the middle etching morphology, so as to improve the quality of the passivation layer while making the etching result more vertical and reducing the side wall roughness. The second process gas includes an etching gas configured in the etching step and a passivation gas configured in the passivation layer deposition step. When O2 is added, the flow rate of O2 is 10% to 20% of the flow rate of the passivation gas; the second etching process uses a third process gas including at least one of CF4, O2, Ar, and He as a post-treatment to etch and smooth the surface layer of the side wall of the deep trench to reduce the surface roughness.

2. The method for forming a semiconductor structure according to claim 1, wherein: The first process gas contains a fluorine-based gas.

3. The method for forming a semiconductor structure according to claim 2, wherein: The first process gas specifically includes C4F8, O2 and Ar; and / or, when performing the first pretreatment process, the temperature is 10℃~60℃, the pressure is 1mtorr~150mtorr, the source power is 100W~1500W, and the bias power is 10W~300W.

4. The method for forming a semiconductor structure according to claim 1, wherein: Another implementation method is: when performing the etching step, H2 is added to the second process gas instead of O2 to help extract by-products and prevent damage to the density of the passivation layer, and / or, when performing the modified Bosch process, the temperature is 10°C to 60°C, the pressure is 1mtorr to 150mtorr, the source power is 100W to 4000W, and the bias power is 10W to 500W.

5. The method for forming a semiconductor structure according to claim 4, wherein: When H2 is added to the second process gas, the flow rate of H2 is 5% to 15% of the flow rate of the etching gas.

6. The method for forming a semiconductor structure according to claim 4, wherein: The pulsed plasma etching is used in the etching step, and the helium gas is used to accelerate the uniform distribution of plasma and the removal of reaction products, so as to reduce the occurrence of lateral etching.

7. The method for forming a semiconductor structure according to claim 1, wherein: When performing the second etching process, the temperature is 10° C. to 60° C., the pressure is 1 mtorr to 500 mtorr, the source power is 100 W to 1500 W, and the bias power is 10 W to 300 W.

8. The method for forming a semiconductor structure according to claim 1, wherein: Another implementation of the first pretreatment process is: the first pretreatment process is replaced by a second pretreatment process, the second pretreatment process includes a third etching process, and the third etching is performed on the surface of the mask pattern; the third etching process uses a fourth process gas including at least one of N2, O2, and Ar to repair the surface layer of the mask pattern to reduce surface roughness; The second pretreatment process is used to improve the deposition quality of the passivation layer, avoid excessive lateral etching when etching the top of the deep trench, and reduce the roughness of the sidewalls of the top of the deep trench; in addition to being deposited on the inner wall of the deep trench, the passivation layer is also deposited on the sidewalls of the mask pattern whose surface has no polymer layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: When performing the third etching process, the temperature is 10° C. to 60° C., the pressure is 1 mtorr to 150 mtorr, the source power is 100 W to 1500 W, and the bias power is 10 W to 300 W.

10. A semiconductor structure, characterized in that The method for forming a semiconductor structure is used as claimed in any one of claims 1 to 9.

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