Preparation method and structure of packaging substrate

Abstract

The invention provides a preparation method and a structure of a packaging substrate, the method is simple in process flow and low in production cost, high-density interconnection between a chip and the packaging substrate is realized by forming an intermediate interconnection layer with a hyperfine circuit in the packaging substrate, the dependence on an intermediate layer is reduced, and the reliability of the packaging substrate is improved. Therefore, the process complexity and the production cost are obviously reduced. According to the invention, the development of a local high-density interconnection packaging technology can be promoted, and more application scenes can be developed for a product based on a packaging substrate hyperfine circuit.

Description

Technical Field

[0001] The invention belongs to the technical field of packaging, and relates to a preparation method and structure of a packaging substrate. Background Art

[0002] With the rapid development of the semiconductor industry, chip manufacturing faces increasing challenges. At extremely small sizes, physical bottlenecks become more difficult to overcome, resulting in rising R&D and production costs, declining product yields, and a gradual slowdown of Moore's Law. The semiconductor industry has gradually entered the post-Moore era. Traditional packaging can no longer meet new demands represented by artificial intelligence and high-performance computing. Leading companies in the semiconductor manufacturing field have begun to shift from focusing on improving wafer manufacturing technology nodes to exploring innovations in system-level packaging technology, and advanced packaging technology has emerged.

[0003] Advanced packaging technology has significantly improved chip performance by improving the packaging method without reducing the process node. Among them, fan-out packaging technology, including wafer-level (FOWLP) and panel-level (FOPLP), has always been an important driving force for the advancement of advanced packaging. The emerging 2.5D and 3D packaging technologies further expand the application potential of flip-chip and wafer-level packaging processes by vertically stacking multiple chips, achieving more efficient input and output. Against the backdrop of the rapid growth in computing power demand for artificial intelligence, these packaging technologies need to support higher frequencies and faster speeds of fine lines to shorten the data transmission distance between chips and improve the collaboration efficiency between chips (Die), thereby improving system performance and reducing overall power consumption.

[0004] By embedding the chip into the packaging substrate through 2.5D or 3D packaging technology, efficient connection between the chip and the substrate can be achieved. However, the implementation cost of these technologies is high, the process technology requirements are strict, and there are certain technical difficulties. At the same time, the traditional semi-additive method (SAP) widely used in existing board-level packaging faces obvious bottlenecks in the preparation of fine lines, and it is difficult to meet the requirements of line width and spacing below 5 microns. The traditional SAP process mainly relies on photolithography, chemical copper plating and etching technology, and its processing capacity is limited in many aspects. The insufficient resolution of the photolithography mask makes it impossible to further reduce the line pattern. The uniformity of metal deposition is difficult to guarantee during the chemical copper deposition process, and the etching stage is prone to over-etching or under-etching of the line. Problems. In addition, as the line accuracy increases, it has also become a challenge to balance mechanical strength and electrical performance.

[0005] In order to make up for the shortcomings of the SAP process in the preparation of ultra-fine lines, the existing technology usually introduces an interposer (such as a silicon-based interposer or a rewiring layer) as a transfer structure to achieve higher density interconnection. However, the introduction of the interposer is also accompanied by many problems. On the one hand, the material cost of the interposer is high and the manufacturing process is complex, which significantly increases the overall packaging cost; on the other hand, due to the mismatch in the thermal expansion coefficient between the interposer and the chip and substrate, thermal stress is easily generated and interface failure occurs, thereby reducing the long-term reliability of the package. At the same time, the heat dissipation performance of the interposer is relatively poor, which may cause thermal management problems in high-power chip packaging, thereby affecting system performance and stability.

[0006] Therefore, how to provide a preparation method and structure of a packaging substrate so as to reduce the introduction of intermediate layers and reduce costs while simplifying the process flow while obtaining ultra-fine circuits and meeting high-density interconnections has become an important technical problem that needs to be urgently solved by technical personnel in this field.

[0007] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0008] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method and structure for preparing a packaging substrate, which is used to solve the bottlenecks faced by the prior art in preparing ultra-fine circuits, as well as the high cost, process complexity and reliability problems caused by the introduction of an intermediate layer.

[0009] To achieve the above object and other related objects, the present invention provides a method for preparing a packaging substrate, comprising the following steps:

[0010] A core plate structure layer is provided, the core plate structure layer comprising a core plate, a metal seed layer and a metal interconnection layer, wherein the core plate comprises a plurality of first through holes, the plurality of first through holes are arranged at intervals and penetrate the core plate, the metal seed layer covers two opposite surfaces of the core plate and side walls of the first through holes, and the metal interconnection layer fills the first through holes;

[0011] Forming a first shielding layer covering the surface of the metal seed layer and the surface of the metal interconnect layer, patterning the first shielding layer to form a first opening exposing the metal seed layer, and forming an underlying metal conductive layer filling the first opening by electroplating;

[0012] Removing the first shielding layer, and etching the metal seed layer not covered by the bottom metal conductive layer by vacuum two-fluid etching or excimer laser etching to obtain a bottom metal seed layer, wherein the bottom metal seed layer and the bottom metal conductive layer constitute a bottom circuit layer;

[0013] A first ABF layer covering the bottom circuit layer is formed on the front and back sides of the core board, wherein the material of the first ABF layer includes a silica filler, and the particle size of the silica filler is ≤0.5 micrometer.

[0014] Optionally, after forming the first ABF layer on the front and back sides of the core board, the following steps are further included:

[0015] Forming an intermediate interconnection layer on the surface of the first ABF layer, the intermediate interconnection layer comprising an intermediate dielectric layer and an intermediate circuit layer at least a portion of which is embedded in the intermediate dielectric layer and electrically connected to the bottom circuit layer;

[0016] Forming a solder resist layer covering the intermediate interconnect layer, and forming a first solder resist opening in the solder resist layer on the front side of the core board, and forming a second solder resist opening in the solder resist layer on the back side of the core board, wherein the first solder resist opening and the second solder resist opening at least expose the conductive portion of the intermediate interconnect layer;

[0017] Forming a top metal seed layer by chemical copper deposition, wherein the top metal seed layer covers the surface of the solder resist layer and the inner wall of the first solder resist opening;

[0018] Forming a patterned second shielding layer on the top metal seed layer, and forming a top conductive layer covering the exposed surface of the top metal seed layer based on the patterned second shielding layer and using an electroplating method that controls different current densities in stages, wherein the top conductive layer includes electroplated copper columns that fill the solder mask openings and a top metal layer that protrudes from the surface of the solder mask layer;

[0019] removing the second shielding layer and performing a flash etching process to remove the top metal seed layer not covered by the top conductive layer;

[0020] Solder balls are formed on the top conductive layer, and the solder balls are electrically connected to the top metal layer.

[0021] Optionally, before forming the intermediate interconnect layer on the surface of the first ABF layer, a step of forming an underlying interconnect structure is further included, wherein at least a portion of the underlying interconnect structure is embedded in the first ABF layer and electrically connected to the underlying circuit layer.

[0022] Optionally, forming the intermediate interconnect layer on the surface of the first ABF layer comprises the following steps:

[0023] Forming an intermediate dielectric layer covering the first ABF layer, wherein the intermediate dielectric layer covers the bottom interconnect structure, the intermediate dielectric layer is a second ABF layer, the material of the second ABF layer includes a silicon dioxide filler, and the particle size of the silicon dioxide filler is ≤0.5 micrometer;

[0024] Laser drilling the second ABF layer using a multi-segment alignment method to obtain a second contact hole, wherein the second contact hole is aligned with the underlying interconnect structure and exposes at least a portion of the surface of the underlying interconnect structure;

[0025] Forming an intermediate metal seed layer, the intermediate metal seed layer covers the surface of the second ABF layer and the inner wall of the second contact hole, and forming a patterned fourth shielding layer on the surface of the intermediate metal seed layer to shield the area where the intermediate circuit layer is not required to be formed;

[0026] Forming an intermediate conductive layer on the exposed surface of the intermediate metal seed layer by electroplating, and removing the patterned fourth shielding layer;

[0027] The intermediate metal seed layer not covered by the intermediate conductive layer is removed by vacuum two-fluid etching or excimer laser etching to obtain an intermediate metal seed layer. The intermediate metal seed layer and the intermediate conductive layer constitute the intermediate circuit layer. The intermediate circuit layer includes an intermediate conductive plug filled in the second contact hole and an intermediate metal pad and an intermediate conductive circuit protruding from the surface of the second ABF layer.

[0028] Optionally, forming the bottom interconnect structure comprises the following steps:

[0029] Laser drilling the first ABF layer using a multi-segment alignment method to obtain a first contact hole, wherein the first contact hole is aligned with the bottom wiring layer and exposes at least a portion of the surface of the bottom wiring layer;

[0030] Forming a conductive seed layer covering the surface of the first ABF layer and the inner wall of the first contact hole, and forming a patterned third shielding layer on the surface of the conductive seed layer to shield the area where the bottom interconnect structure does not need to be formed;

[0031] Forming a bottom conductive layer on the exposed surface of the conductive seed layer by electroplating, and removing the patterned third shielding layer;

[0032] The conductive seed layer not covered by the underlying conductive layer is removed by vacuum two-fluid etching or excimer laser etching to obtain an underlying conductive seed layer. The underlying conductive seed layer and the underlying conductive layer constitute the underlying interconnect structure. The underlying interconnect structure includes an underlying conductive plug filled in the first contact hole and an underlying metal pad and an underlying conductive line protruding from the surface of the first ABF layer.

[0033] Optionally, laser drilling the first ABF layer using a multi-segment alignment method comprises the following steps:

[0034] Divide the front and back sides of the core board into a plurality of units, each of the units includes at least one two-dimensional alignment mark, determine the processing area corresponding to each of the units by reading the two-dimensional alignment mark, and realize independent alignment of each of the units based on the two-dimensional alignment mark;

[0035] A laser drill is used to laser drill the first ABF layer in each of the units. The laser drill automatically aligns by reading the two-dimensional alignment mark in each of the units to ensure that the position of the first contact hole formed by laser drilling is accurately aligned with the bottom circuit layer.

[0036] Optionally, forming the intermediate interconnect layer on the surface of the first ABF layer comprises the following steps:

[0037] Forming an intermediate dielectric layer on the surface of the first ABF layer, the intermediate dielectric layer comprising a blind hole etch stop layer, a first dielectric layer, a trench etch stop layer, a second dielectric layer and a first hard mask layer stacked in sequence;

[0038] forming a patterned first dry film on the first hard mask layer, and etching the first hard mask layer based on the patterned first dry film to form a first hard mask opening;

[0039] Removing the first dry film, and performing dry etching or laser drilling based on the first hard mask opening to form a blind hole penetrating the second dielectric layer, the trench etch stop layer, and the first dielectric layer;

[0040] forming a second dry film covering the first hard mask layer and filling the blind hole, patterning the second dry film, and etching the first hard mask layer based on the patterned second dry film to form a second hard mask opening exposing the second dielectric layer;

[0041] Removing the second dry film, and performing etching based on the second hard mask opening to form a circuit notch and a groove, wherein the etching stops at the groove etch stop layer, the minimum size of the circuit notch is ≤ 2 microns, and the bottom of the groove is connected to the top of the blind hole;

[0042] forming an intermediate metal seed layer, wherein the intermediate metal seed layer covers the surface of the first hard mask layer, the inner wall of the blind hole, the inner wall of the circuit notch and the inner wall of the groove;

[0043] Performing electroplating to form an intermediate conductive layer covering the intermediate metal seed layer, wherein the intermediate conductive layer also fills the blind hole, the line notch and the groove;

[0044] A portion of the intermediate conductive layer is removed until the top surface of the intermediate conductive layer is at the same level as the top surface of the intermediate metal seed layer, so as to obtain a portion of the intermediate circuit layer embedded in the intermediate dielectric layer and electrically connected to the bottom circuit layer, wherein the intermediate circuit layer includes a conductive interconnect structure filling the blind hole and the groove, and includes an intermediate conductive circuit filling the circuit notch.

[0045] Optionally, before forming the intermediate interconnect layer on the surface of the first ABF layer, the method further includes removing part of the first ABF layer until the surface of the remaining first ABF layer is flush with the top of the bottom wiring layer.

[0046] Optionally, before forming the intermediate metal seed layer, the following steps are also included:

[0047] Removing the blind hole etch stop layer at the bottom of the blind hole and the trench etch stop layer at the bottom of the line notch and the bottom of the trench;

[0048] A barrier layer is formed, the barrier layer covers the surface of the first hard mask layer, the inner wall of the blind hole, the inner wall of the line notch and the inner wall of the trench, and the intermediate metal seed layer covers the surface of the barrier layer.

[0049] Optionally, forming the intermediate interconnect layer on the surface of the first ABF layer comprises the following steps:

[0050] Forming an intermediate dielectric layer on the surface of the first ABF layer, the intermediate dielectric layer is a third ABF layer, the material of the third ABF layer includes a silicon dioxide filler, and the particle size of the silicon dioxide filler is ≤0.5 micrometer;

[0051] Providing a nanoimprint stamp with a concave pattern, and imprinting the nanoimprint stamp on the third ABF layer to form a pattern structure including a blind hole, a circuit notch and a groove in the third ABF layer, wherein the blind hole exposes at least a portion of the surface of the bottom circuit layer, the top of the blind hole is connected to the bottom of the groove, and the minimum size of the circuit notch is ≤2 microns;

[0052] forming an intermediate metal seed layer covering the surface of the third ABF layer, wherein the intermediate metal seed layer also covers the inner wall of the blind hole, the inner wall of the circuit notch and the inner wall of the groove;

[0053] Performing electroplating to form an intermediate conductive layer covering the intermediate metal seed layer, wherein the intermediate conductive layer also fills the blind hole, the line notch and the groove;

[0054] A portion of the intermediate conductive layer is removed until the top surface of the intermediate conductive layer is at the same level as the top surface of the intermediate metal seed layer, so as to obtain a portion of the intermediate circuit layer embedded in the intermediate dielectric layer and electrically connected to the bottom circuit layer, wherein the intermediate circuit layer includes a conductive interconnect structure filling the blind hole and the groove, and includes an intermediate conductive circuit filling the circuit notch.

[0055] Optionally, the nanoimprint stamp is imprinted on the surface of the third ABF layer by a method of simultaneous imprinting and curing.

[0056] Optionally, the forming of the nanoimprint stamp comprises the following steps:

[0057] Providing a substrate layer, and forming a bottom metal layer on the substrate layer;

[0058] A fifth patterned shielding layer is formed on the bottom metal layer, and the bottom metal layer is etched by vacuum two-fluid etching or excimer laser etching based on the patterned fifth shielding layer to form a desired recessed pattern, wherein the resolution of the fifth shielding layer is ≤1.5 microns

[0059] The fifth shielding layer is removed to form a nickel protection layer covering the surface of the bottom metal layer to protect the recessed pattern.

[0060] The present invention also provides a packaging substrate structure, which is obtained by using any of the above packaging substrate preparation methods, and comprises: a core board structure layer, a bottom circuit layer and a first ABF layer, wherein:

[0061] The core plate structure layer includes a core plate, a metal seed layer and a metal interconnection layer, the core plate includes a plurality of first through holes, the plurality of first through holes are arranged at intervals and penetrate the core plate, the metal seed layer covers two opposite sides of the core plate and side walls of the first through holes, the metal interconnection layer fills the first through holes, wherein the metal seed layer covering two opposite sides of the core plate is etched by vacuum two-fluid etching method or excimer laser etching method to form a bottom metal seed layer;

[0062] The bottom wiring layer includes the bottom metal seed layer and a bottom metal conductive layer located above the bottom metal seed layer;

[0063] The first ABF layer is located on the front and back sides of the core board, the first ABF layer covers the bottom circuit layer, and the material of the first ABF layer includes a silica filler, and the particle size of the silica filler is ≤0.5 microns.

[0064] As described above, the present invention provides a method and structure for preparing a packaging substrate, which has a simple process flow and low production cost. By forming an intermediate interconnection layer with ultra-fine lines in the packaging substrate, high-density interconnection between the chip and the packaging substrate is achieved, reducing the dependence on the intermediate layer, thereby significantly reducing the process complexity and production cost. The present invention can not only promote the development of local high-density interconnection packaging technology, but also open up more application scenarios for products based on ultra-fine lines of packaging substrates. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 Shown is a process flow chart of a method for preparing a packaging substrate of the present invention.

[0066] Figure 2 It is a schematic diagram of the cross-sectional structure of the core board provided in the first embodiment of the method for preparing the packaging substrate of the present invention.

[0067] Figure 3 It is a schematic diagram of the cross-sectional structure after forming a plurality of first through holes in the core board in the first embodiment of the method for preparing the packaging substrate of the present invention.

[0068] Figure 4 It is a schematic diagram of the cross-sectional structure after the inner wall of the first through hole is processed and the surface of the core board is roughened in the first embodiment of the method for preparing the packaging substrate of the present invention.

[0069] Figure 5 It is a schematic diagram of the cross-sectional structure presented after the metal seed layer covering the two opposite surfaces of the core board and the side wall of the first through hole is formed in the first embodiment of the method for preparing the packaging substrate of the present invention.

[0070] Figure 6 It is a schematic diagram of the cross-sectional structure after the method for preparing the packaging substrate of the present invention forms a conductive interconnect layer covering the metal seed layer in Example 1, and the conductive interconnect layer is filled into the first through hole.

[0071] Figure 7 It is a schematic diagram of the cross-sectional structure after the conductive interconnect layer is removed to expose the surface of the metal seed layer in the method for preparing the packaging substrate of the present invention in Example 1.

[0072] Figure 8It is a schematic diagram of the cross-sectional structure after forming a first shielding layer covering the surface of the metal seed layer and the surface of the metal interconnect layer in the first embodiment of the method for preparing the packaging substrate of the present invention.

[0073] Fig. 9 It is a schematic diagram of the cross-sectional structure presented after the first shielding layer is patterned in the first embodiment of the method for preparing the packaging substrate of the present invention to form a first opening exposing the metal seed layer.

[0074] Fig.10 It is a schematic diagram of the cross-sectional structure after the bottom metal conductive layer filling the first opening is formed in the first embodiment of the method for preparing the packaging substrate of the present invention.

[0075] Fig.11 It is a schematic diagram of the cross-sectional structure of the method for preparing a packaging substrate of the present invention after removing the first shielding layer in the first embodiment.

[0076] Fig.12 It is a schematic diagram of the cross-sectional structure of the method for preparing a packaging substrate of the present invention after forming a bottom metal seed layer in the first embodiment.

[0077] Fig.13 It is a schematic diagram of the cross-sectional structure after the first ABF layer covering the bottom circuit layer is formed on the front and back sides of the core board in the preparation method of the packaging substrate of the present invention in Example 1.

[0078] Fig.14 It is a schematic cross-sectional structure diagram of the method for preparing a packaging substrate of the present invention after forming a first contact hole in the first ABF layer in the first embodiment.

[0079] Fig.15 It is a schematic diagram of the cross-sectional structure after forming a bottom conductive layer on the surface of the conductive seed layer and removing the patterned third shielding layer in the first embodiment of the method for preparing the packaging substrate of the present invention.

[0080] Fig.16 It is a schematic diagram of the cross-sectional structure of the method for preparing the packaging substrate of the present invention after forming the bottom conductive seed layer in the first embodiment.

[0081] Fig.17 It is a schematic diagram of the cross-sectional structure after forming an intermediate dielectric layer covering the first ABF layer in the first embodiment of the method for preparing a packaging substrate of the present invention.

[0082] Fig.18 It is a schematic cross-sectional structure diagram of the method for preparing a packaging substrate of the present invention after forming a second contact hole in the second ABF layer in the first embodiment.

[0083] Fig.19 It is a schematic diagram of the cross-sectional structure after an intermediate conductive layer is formed on the surface of the intermediate metal seed layer in the first embodiment of the method for preparing a packaging substrate of the present invention.

[0084] Fig. 20 It is a schematic diagram of the cross-sectional structure after forming the intermediate metal seed layer in the first embodiment of the method for preparing the packaging substrate of the present invention.

[0085] Fig.21 It is a schematic diagram of the cross-sectional structure after forming two intermediate interconnection layers in the first embodiment of the method for preparing the packaging substrate of the present invention.

[0086] Fig. 22 Shown is a schematic diagram of the cross-sectional structure presented after the preparation method of the packaging substrate of the present invention forms a solder resist layer covering the intermediate interconnect layer in Example 1, forms a first solder resist opening in the solder resist layer on the front side of the core board, and forms a second solder resist opening in the solder resist layer on the back side of the core board.

[0087] Fig.23 Shown is a schematic diagram of a cross-sectional structure presented after a patterned second shielding layer is formed on the top metal seed layer in Example 1 according to the method for preparing the packaging substrate of the present invention, and a top conductive layer covering the exposed surface of the top metal seed layer is formed based on the patterned second shielding layer.

[0088] Fig.24 It is a schematic diagram of the cross-sectional structure after removing the second shielding layer and the top metal seed layer not covered by the top conductive layer in the first embodiment of the method for preparing the packaging substrate of the present invention.

[0089] Fig.25 It is a schematic diagram of the cross-sectional structure after forming solder balls on the top conductive layer in the first embodiment of the method for preparing the package substrate of the present invention.

[0090] Fig.26 It is a schematic cross-sectional structure diagram of the method for preparing the package substrate of the present invention after at least two chips are flip-chip bonded to the solder balls in the first embodiment.

[0091] Fig. 27 It is a schematic diagram of the cross-sectional structure after the first ABF layer covering the bottom circuit layer is formed on the front and back sides of the core board in the second embodiment of the method for preparing the packaging substrate of the present invention.

[0092] Fig.28 It is a schematic diagram of the cross-sectional structure of the method for preparing a packaging substrate of the present invention after a portion of the first ABF layer is removed in Example 2.

[0093] Fig.29 It is a schematic diagram of the cross-sectional structure after forming an intermediate dielectric layer on the surface of the first ABF layer in the second embodiment of the method for preparing a packaging substrate of the present invention.

[0094] Fig.30 The schematic diagram of the cross-sectional structure after the method for preparing the packaging substrate of the present invention forms a patterned first dry film in Example 2, and etches the first hard mask layer based on the patterned first dry film to form a first hard mask opening.

[0095] Fig.31 It is a schematic diagram of the cross-sectional structure after the first dry film is removed in the second embodiment of the method for preparing the packaging substrate of the present invention, and blind holes are formed by dry etching or laser drilling based on the opening of the first hard mask.

[0096] Fig.32 The schematic diagram of the cross-sectional structure shown is a method for preparing a packaging substrate of the present invention, in Example 2, in which a second dry film is formed, and the first hard mask layer is etched based on the patterned second dry film to form a second hard mask opening that exposes the second dielectric layer.

[0097] Fig.33 The schematic diagram of the cross-sectional structure of the method for preparing a packaging substrate of the present invention is shown after the second dry film is removed in the second embodiment and etching is performed based on the second hard mask opening to form circuit notches and grooves.

[0098] Fig.34 It is a schematic diagram of the cross-sectional structure presented after the blind hole etch stop layer at the bottom of the blind hole and the trench etch stop layer at the bottom of the line notch and the bottom of the trench are removed in the second embodiment of the preparation method of the packaging substrate of the present invention.

[0099] Fig.35 It is a schematic diagram of the cross-sectional structure after forming the intermediate metal seed layer in the second embodiment of the method for preparing the packaging substrate of the present invention.

[0100] Fig.36 It is a schematic diagram of the cross-sectional structure after the middle conductive layer is formed in the second embodiment of the method for preparing the packaging substrate of the present invention.

[0101] Fig.37 It is a schematic diagram of the cross-sectional structure of the packaging substrate preparation method of the present invention after removing part of the intermediate conductive layer in Example 2 to obtain a part of the intermediate circuit layer embedded in the intermediate dielectric layer and electrically connected to the bottom circuit layer.

[0102] Fig.38It is a schematic diagram of the cross-sectional structure after forming three intermediate interconnection layers in the second embodiment of the method for preparing the packaging substrate of the present invention.

[0103] Fig.39 It is a schematic diagram of the cross-sectional structure after forming a solder resist layer, a first solder resist opening, a second solder resist opening, a top metal seed layer, a top conductive layer and solder balls in the preparation method of the packaging substrate of the present invention in Example 2.

[0104] Fig.40 It is a schematic cross-sectional structure diagram of the method for preparing the package substrate of the present invention after at least two chips are flip-chip bonded to the solder balls in the second embodiment.

[0105] Fig.41 It is a schematic diagram of the cross-sectional structure after forming an intermediate dielectric layer on the surface of the first ABF layer in the third embodiment of the method for preparing a packaging substrate of the present invention.

[0106] Fig.42 The schematic diagram of the cross-sectional structure shown is a method for preparing a packaging substrate of the present invention in Example 3 in which a nanoimprint stamp is imprinted on the third ABF layer to form a graphic structure including blind holes, circuit notches and grooves in the third ABF layer.

[0107] Fig.43 It is a schematic diagram of the cross-sectional structure after forming the intermediate metal seed layer in the third embodiment of the method for preparing the packaging substrate of the present invention.

[0108] Fig.44 It is a schematic diagram of the cross-sectional structure after the middle conductive layer is formed in the third embodiment of the method for preparing the packaging substrate of the present invention.

[0109] Fig.45 It is a schematic diagram of the cross-sectional structure after removing part of the intermediate conductive layer in Example 3 of the preparation method of the packaging substrate of the present invention to obtain a part of the intermediate circuit layer embedded in the intermediate dielectric layer and electrically connected to the bottom circuit layer.

[0110] Fig.46 It is a schematic diagram of the cross-sectional structure after forming three intermediate interconnection layers in the third embodiment of the method for preparing the packaging substrate of the present invention.

[0111] Fig.47 It is a schematic diagram of the cross-sectional structure after forming a solder resist layer, a first solder resist opening, a second solder resist opening, a top metal seed layer, a top conductive layer and solder balls in the preparation method of the packaging substrate of the present invention in Example 3.

[0112] Fig.48It is a schematic cross-sectional structure diagram of the method for preparing a package substrate of the present invention after at least two chips are flip-chip bonded to the solder balls in the third embodiment.

[0113] Component number description

[0114] 1 Core board structure layer

[0115] 101 Core Board

[0116] 1011 First through hole

[0117] 102 Metal seed layer

[0118] 103 Conductive interconnect layer

[0119] 1031 Metal Interconnect Layer

[0120] 2 First shielding layer

[0121] 201 First Opening

[0122] 3 Bottom Circuit Layer

[0123] 301 Bottom metal seed layer

[0124] 302 bottom metal conductive layer

[0125] 4 First ABF layer

[0126] 5. Bottom-level interconnection structure

[0127] 501 First contact hole

[0128] 502 Conductive seed layer

[0129] 5021 Bottom conductive seed layer

[0130] 503 Bottom conductive layer

[0131] 504 Bottom conductive plug

[0132] 505 Bottom Metal Pad

[0133] 506 Bottom conductive line

[0134] 6 Intermediate interconnect layer

[0135] 601A Intermediate dielectric layer

[0136] 6011A Second ABF layer

[0137] 6012A Second contact hole

[0138] 602A Intermediate Line Layer

[0139] 6021A Intermediate metal seed layer

[0140] 60211A Intermediate metal seed layer

[0141] 6022A Intermediate conductive layer

[0142] 6023A Intermediate conductive plug

[0143] 6024A Intermediate Metal Pad

[0144] 6025A Intermediate Conductive Circuit

[0145] 601B Intermediate dielectric layer

[0146] 6011B Blind hole etch stop layer

[0147] 6012B First dielectric layer

[0148] 6013B Trench Etch Stop Layer

[0149] 6014B Second dielectric layer

[0150] 6015B First hard mask layer

[0151] 60151B First hard mask opening

[0152] 60152B Second hard mask opening

[0153] 6016B Blind Via

[0154] 6017B Line Notch

[0155] 6018B Groove

[0156] 602B Intermediate Line Layer

[0157] 6021B Intermediate metal seed layer

[0158] 6022B Intermediate conductive layer

[0159] 6023B Conductive Interconnect Structure

[0160] 6024B Intermediate conductive line

[0161] 603B First Dry Film

[0162] 604B Second dry film

[0163] 601C Intermediate dielectric layer

[0164] 6011C Third ABF layer

[0165] 6012C Blind hole

[0166] 6013C Line Notch

[0167] 6014C Groove

[0168] 602C Intermediate circuit layer

[0169] 6021C Intermediate metal seed layer

[0170] 6022C Intermediate conductive layer

[0171] 6023C Conductive Interconnect Structure

[0172] 6024C Intermediate conductive circuit

[0173] 7 Solder Mask

[0174] 701 First solder mask opening

[0175] 702 Second solder mask opening

[0176] 8 Top metal seed layer

[0177] 9 Second shielding layer

[0178] 10 Top Conductive Layer

[0179] 1001 Electroplated copper pillar

[0180] 1002 Top metal layer

[0181] 11 Solder balls

[0182] 12 Chip

[0183] 1201 Pad

[0184] 13 Plastic layer

[0185] Steps S1 to S4 DETAILED DESCRIPTION

[0186] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0187] See also Figures 1 to 48It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0188] The present invention provides a method for preparing a packaging substrate. Figure 1 , shown as a process flow chart of the method, comprising the following steps:

[0189] S1: providing a core board structure layer, the core board structure layer comprising a core board, a metal seed layer and a metal interconnection layer, wherein the core board comprises a plurality of first through holes, the plurality of first through holes are arranged at intervals and penetrate the core board, the metal seed layer covers two opposite surfaces of the core board and side walls of the first through holes, and the metal interconnection layer fills the first through holes;

[0190] S2: forming a first shielding layer covering the surface of the metal seed layer and the surface of the metal interconnect layer, patterning the first shielding layer to form a first opening exposing the metal seed layer, and forming an underlying metal conductive layer filling the first opening by electroplating;

[0191] S3: removing the first shielding layer, and etching the metal seed layer not covered by the bottom metal conductive layer by vacuum two-fluid etching or excimer laser etching to obtain a bottom metal seed layer, wherein the bottom metal seed layer and the bottom metal conductive layer constitute a bottom circuit layer;

[0192] S4: forming a first ABF layer covering the bottom circuit layer on the front and back sides of the core board, wherein the material of the first ABF layer includes a silica filler, and the particle size of the silica filler is ≤0.5 μm.

[0193] The specific implementation of each of the above steps is described in detail below with reference to the structure diagram.

[0194] First, see Figures 2 to 7 , perform the step S1: provide a core board structure layer 1, the core board structure layer 1 includes a core board 101, a metal seed layer 102 and a metal interconnection layer 1031, wherein the core board 101 includes a plurality of first through holes 1011, the plurality of first through holes 1011 are arranged at intervals and penetrate the core board 101, the metal seed layer 102 covers the two opposite sides of the core board 101 and the side walls of the first through holes 1011, and the metal interconnection layer 1031 fills the first through holes 1011.

[0195] As an example, the formation of the core plate structure layer 1 includes the following steps:

[0196] (1) Figure 2 and Figure 3 As shown, a core plate 101 is provided, and a plurality of first through holes 1011 are formed in the core plate 101. The plurality of first through holes 1011 are arranged at intervals and penetrate the core plate 101;

[0197] (2) Figure 5 As shown, a metal seed layer 102 is formed to cover two opposite surfaces of the core board 101 and the sidewalls of the first through hole 1011;

[0198] (3) Figure 6 As shown, a conductive interconnection layer 103 covering the metal seed layer 102 is formed, and the conductive interconnection layer 103 is filled into the first through hole 1011;

[0199] (4) Figure 7 As shown, the conductive interconnect layer 103 is removed until the surface of the metal seed layer 102 is exposed, wherein the conductive interconnect layer 103 filled in the first through hole 1011 serves as the metal interconnect layer 1031 .

[0200] Specifically, the core board 101 includes any one of an organic core board, a ceramic core board and a glass core board.

[0201] As an example, the Young's modulus of the core board 101 is ≥ 30 GPa. The core board 101 has high rigidity, which can ensure that the package substrate does not undergo significant warping deformation during the manufacturing process.

[0202] Specifically, the method of forming the first through hole 1011 includes but is not limited to mechanical drilling, laser induced etching, laser ablation, plasma etching, etc. In this embodiment, the first through hole 1011 is preferably formed by mechanical drilling.

[0203] As an example, Figure 4 As shown, after forming the first through hole 1011 and before forming the metal seed layer 102 , the process further includes the steps of processing the inner wall of the first through hole 1011 and roughening the surface of the core board 101 .

[0204] Specifically, the inner wall of the first through hole 1011 may be treated by a desmear process, a plasma process or other suitable processes to remove the residues generated during the formation of the first through hole 1011. When the desmear process is used to remove the residual smear on the inner wall of the first through hole 1011, an alkaline solution containing potassium permanganate may be used for chemical treatment. While removing the residues on the inner wall of the first through hole 1011, the alkaline solution may also increase the roughness of the inner wall of the first through hole 1011, thereby improving the adhesion of the material to the inner wall of the first through hole 1011. When the high energy of plasma is used to remove the drilling stains on the inner wall of the first through hole 1011, a plasma gas combination of argon (Ar) and oxygen (O2) or a plasma gas combination of nitrogen (N2) and oxygen (O2) may be used for treatment.

[0205] Specifically, after removing the drilling dirt and residual glue residue on the inner wall of the first through hole 1011, the surface of the core plate 101 is roughened. The method of roughening the surface of the core plate 101 includes chemical etching or other appropriate methods.

[0206] Specifically, Figure 5 , which is a schematic diagram of the cross-sectional structure after the metal seed layer 102 is formed in this embodiment. The material of the metal seed layer 102 includes at least one of copper, platinum, titanium, tungsten, nickel, gold, silver, and copper-nickel alloy. The method of forming the metal seed layer 102 includes chemical plating, chemical vapor deposition, physical vapor deposition or other suitable methods.

[0207] Specifically, in one example, when the metal seed layer 102 is formed by a chemical copper deposition process (a type of chemical plating), the metal seed layer 102 is a copper layer, and the thickness of the copper layer is ≤0.5 microns. In addition, the internal stress of the chemical copper deposition process is less than 50KPa, and the throwing power (TP) exceeds 80%, and the copper layer has high uniformity. In another example, when the metal seed layer 102 is formed by a magnetron sputtering (a type of chemical vapor deposition) process, the metal seed layer 102 includes a copper layer, a tungsten layer and a titanium layer stacked in sequence, the thickness of the copper layer ranges from 100 to 300 nanometers, the thickness of the titanium layer ranges from 20 to 80 nanometers, and the thickness of the tungsten layer can be selected according to actual needs, for example, 20 nanometers.

[0208] Specifically, Figure 6 As shown, the method of forming the conductive interconnection layer 103 includes electroplating, magnetron sputtering, evaporation, chemical plating or other suitable methods. In this embodiment, the conductive interconnection layer 103 is preferably formed by electroplating.

[0209] Specifically, Figure 7 As shown, the method of removing the conductive interconnection layer 103 includes mechanical grinding, chemical mechanical planarization (CMP) or other suitable methods. In this embodiment, the conductive interconnection layer 103 is preferably removed by CMP to form the metal interconnection layer 1031. The material of the metal interconnection layer 1031 includes any one of copper, platinum, titanium, tungsten, nickel, gold, silver, and copper-nickel alloy. In this embodiment, the material of the metal interconnection layer 1031 is preferably copper.

[0210] Please see again Figures 8 to 10 , perform the step S2: form a first shielding layer 2 covering the surface of the metal seed layer 102 and the surface of the metal interconnect layer 1031, pattern the first shielding layer 2 to form a first opening 201 exposing the metal seed layer 102, and use electroplating to form an underlying metal conductive layer 302 filling the first opening 201.

[0211] Specifically, Figure 8 As shown, the first shielding layer 2 is a photosensitive material layer, and the first shielding layer 2 can be patterned by exposure and development, and the first shielding layer 2 can be a dry film or a wet film. When the first shielding layer 2 is a dry film, the first shielding layer 2 is formed on the surface of the metal seed layer 102 and the metal interconnection layer 1031 by lamination or vacuum pressing; when the first shielding layer 2 is a wet film, it can be formed on the surface of the metal seed layer 102 and the metal interconnection layer 1031 by spin coating, spray coating, scraping coating, or roll-to-roll coating. In this embodiment, the first shielding layer 2 is preferably a dry film.

[0212] As an example, the resolution of the first shielding layer 2 is ≤1.5 micrometers, that is, the resolution of the dry film is ≤1.5 micrometers.

[0213] Specifically, Fig. 9 As shown, when the resolution of the first shielding layer 2 is ≤1.5 microns, the minimum size of the first opening 201 formed is less than / equal to 1.5 microns. In this embodiment, the high-resolution first shielding layer 2 can reduce errors in the exposure and other processing processes, while helping to form ultra-fine lines with a line width / line spacing ≤2 microns, and improve the uniformity and reliability of ultra-fine line pattern formation.

[0214] Specifically, Fig.10 , which is a schematic cross-sectional structure diagram of the bottom metal conductive layer 302 formed by electroplating to fill the first opening 201. In this embodiment, electroplating is performed in an electroplating tank equipped with an auxiliary cathode to deposit and form the bottom metal conductive layer 302.

[0215] Specifically, in this embodiment, the problem of uneven electroplating caused by edge effect in the traditional electroplating process can be significantly improved by introducing an auxiliary cathode. In the electroplating tank, the role of the auxiliary cathode is to optimize the spatial distribution of the electric field, regulate the uniformity of the current density, and achieve regional adjustment of the current, thereby significantly improving the overall uniformity of the electroplating. The auxiliary cathode can effectively guide the current to concentrate in a specific area, especially balance the current density in the area of ​​the first opening 201, reduce the excessive concentration of the current in the edge area, and alleviate the adverse effects of the edge effect on the quality of the electroplating layer (i.e., the underlying metal conductive layer 302) at the first opening 201. In this way, the auxiliary cathode can significantly improve the electroplating uniformity of the underlying metal conductive layer 302, making its thickness more consistent and its shape more flat, while reducing the risk of defects that may be caused in subsequent processes due to the uneven thickness of the underlying metal conductive layer 302. Compared with the conventional method of adding a shielding cover or shielding plate between the cathode and the anode of the electroplating tank, the electroplating performed by adding an auxiliary cathode can more efficiently solve the edge effect problem, avoid the uneven electroplating caused by excessive current density in isolated areas and edge areas, and significantly improve the uniformity of the thickness of the bottom metal conductive layer 302 in different areas. Compared with the electroplating performed without the auxiliary cathode, the uniformity of the bottom metal conductive layer 302 formed in this embodiment is improved by 20% to 25%.

[0216] Please see again Fig.11 and Fig.12 , perform the step S3: remove the first shielding layer 2, and use vacuum two-fluid etching or excimer laser etching to etch the metal seed layer 102 not covered by the underlying metal conductive layer 302 to obtain an underlying metal seed layer 301, and the underlying metal seed layer 301 and the underlying metal conductive layer 302 constitute a bottom wiring layer 3.

[0217] Specifically, an organic film removing liquid or an inorganic film removing liquid may be used to remove the first shielding layer 2 .

[0218] As an example, when the metal seed layer 102 is etched by vacuum two-fluid etching, the components of the selected etchant include at least one of the following ingredients: coordination compounds containing lone pair electrons, multivalent transition metal ions, compounds containing long-chain alkyl groups, and compounds containing polar groups.

[0219] Specifically, the coordination compound containing a lone pair of electrons includes a nitrogen-containing small molecule (such as triethylamine, dimethylamine) or an oxygen-containing small molecule (such as ethylene glycol, glycerol).

[0220] Specifically, the multivalent transition metal ions include trivalent iron ions (Fe 3+ ) or trivalent chromium ion (Cr 3+ ).

[0221] Specifically, the long-chain alkyl-containing compound includes polyvinyl acetal (PVA acetal) or other hydrophobic compounds.

[0222] Specifically, the compound containing polar groups includes polyvinyl pyrrolidone (PVP), polyacrylamide (PAM) or other polymer compounds containing polar groups such as hydroxyl, carbonyl or amino groups.

[0223] Specifically, the coordination compound containing lone pair electrons in the etchant can form coordination bonds with the copper atoms in the metal seed layer 102, thereby weakening the bonding between the copper atoms in the metal seed layer 102 and promoting the etching process. At the same time, the coordination effect will also change the electron cloud distribution of the copper atoms in the metal seed layer 102, making it easy to be etched by multivalent transition metal ions (such as Fe 3+ ) oxidation, while Fe 3+ When the copper atoms in the metal seed layer 102 undergo an oxidation-reduction reaction, divalent iron ions (Fe 2+ ) and converts copper into copper ions and enters the solution, while Fe 2+ Can be regenerated into Fe by oxidation 3+ , thereby maintaining the Fe 3+ While improving stability, it further promotes the etching of the metal seed layer 102. In addition, the metal seed layer 102 formed by chemical copper deposition or magnetron sputtering and the bottom metal conductive layer 302 formed by electroplating have differences in crystal structure, chemical bond strength and atomic spacing, so that the Fe in the etching solution 3+ The etching of the metal seed layer 102 will be accelerated preferentially. At the same time, the long-chain alkyl compound and the compound containing polar groups in the etching solution can form a protective film on the surface of the bottom metal conductive layer 302 to prevent corrosion, thereby further ensuring that the etching solution can efficiently and selectively etch the metal seed layer 102 without damaging the bottom metal conductive layer 302. In this embodiment, the etching agent is preferably a coordination compound containing lone pair electrons (triethylamine), Fe 3+ A mixed solution composed of a long-chain alkyl compound (such as PVA acetal) and a polar group compound (such as PVP).

[0224] In addition, the present embodiment adopts the vacuum two-fluid etching method to wet-etch the metal seed layer 102, which can also ensure that the etchant flows consistently in the center and edge areas of the packaging substrate, effectively improving the etching uniformity. Moreover, the process will atomize the etchant into tiny particles, so that the etchant can deeply contact the bottom area of ​​the metal seed layer 102, thereby significantly improving the bottom etching rate, avoiding damage caused by excessive etching, and helping to achieve ultra-fine etching with a line width / line spacing of ≤2μm. In addition, the method of etching using the vacuum two-fluid etching process in the present embodiment can effectively overcome the problem of uneven etching caused by the pool effect in traditional horizontal flash etching, as well as the problem of poor etching effect in vertical flash etching due to asynchronous spraying, excessive spray overlap, and uneven back pressure distribution.

[0225] As an example, when the metal seed layer 102 is etched by using an excimer laser etching method, the adjustable range of laser energy is 160 to 200 mJ, and the range of pulse width is 10 to 30 ns.

[0226] Specifically, when the metal seed layer 102 is etched by the excimer laser etching method, the high-density and high-energy laser photons rapidly destroy the chemical bonds in the metal seed layer 102 through instantaneous bombardment, causing a sharp rise in local pressure, resulting in the material being ejected in the form of a gas phase, thereby achieving precise removal of the metal seed layer 102. The excimer laser etching method of this embodiment utilizes the principle of instantaneous action of high-energy photons, which can effectively avoid problems such as sidewall damage and reduced processing accuracy caused by thermal diffusion in traditional laser etching methods. This method of etching the metal seed layer 102 has high processing accuracy and can achieve etching with a line width / line spacing of ≤2 microns, while significantly reducing thermal damage to the sidewalls and surrounding structures.

[0227] As an example, the minimum line width / line spacing of the bottom wiring layer 3 is ≤2 microns.

[0228] Specifically, the resolution of the first shielding layer 2 is ≤1.5 microns, that is, the minimum size of the first opening 201 formed is less than or equal to 1.5 microns. This indicates that the minimum line width / line spacing of the bottom metal conductive layer 302 filling the first opening 201 is ≤1.5 microns. In addition, the vacuum two-fluid etching method or the excimer laser etching method has a high etching accuracy, and the minimum line width / line spacing of the bottom wiring layer 3 formed can reach 2 microns or less.

[0229] Please see again Fig.13 , execute the step S4: form a first ABF layer 4 covering the bottom circuit layer 3 on the front and back sides of the core board 101, the material of the first ABF layer 4 includes a silica filler, and the particle size of the silica filler is ≤0.5 microns.

[0230] As an example, before forming the first ABF layer 4, a step of roughening the surface of the bottom wiring layer 3 is also included. Specifically, in this embodiment, the surface of the bottom wiring layer 3 is roughened using ultra-low micro-etching roughening solution CZ8401.

[0231] As an example, the arithmetic average roughness (Ra) of the surface of the bottom wiring layer 3 after roughening treatment is ≤0.1 micrometer.

[0232] Specifically, roughening the surface of the bottom wiring layer 3 using the roughening solution CZ8401 can effectively increase the specific surface area of ​​the bottom wiring layer 3. This increase in specific surface area can enhance the adhesion of the material on the bottom wiring layer 3, that is, enhance the adhesion of the first ABF layer on the bottom wiring layer 3, and enhance the bonding force between the two. This increase in bonding force is conducive to the subsequent formation of ultra-fine circuits on the first ABF layer, and improves the stability and reliability of the ultra-fine circuits.

[0233] Specifically, the first ABF layer 4 can be formed on the front and back sides of the core board 101 by lamination, coating, deposition or other appropriate methods.

[0234] As an example, the material of the first ABF layer 4 further includes epoxy resin.

[0235] Specifically, in this embodiment, the silica (SiO2) filler with a particle size of ≤0.5 microns is mixed with ABF material (Ajinomoto Build-up Film) according to a preset ratio, and epoxy resin is added, and stirred to form a uniform mixed liquid. After that, the mixed liquid is applied to the front and back of the core board 101, and hot pressing and curing treatment is performed to form the first ABF layer 4. In this embodiment, the particle size of the silica filler in the first ABF layer 4 is ≤0.5 microns, which can significantly improve the surface flatness of the first ABF layer 4. The highly flat surface can effectively avoid subsequent process problems caused by the uneven surface of the first ABF layer 4. For example, the problems of focus misalignment, blurred imaging, graphic deformation, and even inability to image in the subsequent exposure process caused by the undulation of the surface can affect the ability of fine lines to be stably formed on the first ABF surface. In addition, the first ABF layer 4 formed in this embodiment can effectively avoid the problem of filler shedding that may be caused by the large filler particle size in the subsequent drilling process. This shedding will cause gaps or delamination in the first ABF layer 4, which will affect the drilling quality and adversely affect the accuracy and quality of fine circuits subsequently formed on the surface of the first ABF layer 4. The first ABF layer 4 in this embodiment not only helps with precise alignment during the exposure process, avoids unnecessary adjustments or failures caused by surface problems, and improves the reliability and production efficiency of the overall process, but also improves the drilling quality and ensures that ultra-fine circuits are stably and accurately formed on the surface of the first ABF layer 4. It should be noted that the ultra-fine circuits described in the present invention refer to circuits with a line width / line spacing ≤ 5 microns, such as 200 nanometers, 500 nanometers, 1 micron, 2 microns, 3 microns, 4 microns, etc.

[0236] As an example, the first ABF layer 4 has a Tg≥180° C., a Young's modulus≥15 GPa, and a Df≤0.009.

[0237] Specifically, the first ABF layer 4 has excellent high temperature stability, high rigidity and high elasticity, and can effectively resist deformation caused by external forces. In addition, the low dielectric loss characteristics of the first ABF layer 4 can significantly reduce energy loss during signal transmission and improve signal integrity and transmission efficiency. At the same time, the first ABF layer 4 also has the characteristics of low thermal expansion coefficient, excellent mechanical properties and good durability, which can effectively improve the reliability of the packaging substrate in complex working environments.

[0238] As an example, after forming the first ABF layer 4 on the front and back sides of the core board 101, the following steps are also included:

[0239] (1) Please refer to Figures 17 to 21, forming an intermediate interconnection layer 6 on the surface of the first ABF layer 4, wherein the intermediate interconnection layer 6 includes an intermediate dielectric layer 601A and an intermediate circuit layer 602A at least part of which is embedded in the intermediate dielectric layer 601A and electrically connected to the bottom circuit layer 3;

[0240] (2) Please refer to Fig. 22 , forming a solder resist layer 7 covering the intermediate interconnect layer 6, and forming a first solder resist opening 701 in the solder resist layer 7 on the front side of the core board 101, and forming a second solder resist opening 702 in the solder resist layer 7 on the back side of the core board 101, wherein the first solder resist opening 701 and the second solder resist opening 702 at least expose the conductive portion of the intermediate interconnect layer 6;

[0241] (3) forming a top metal seed layer 8 by chemical copper deposition, wherein the top metal seed layer 8 covers the surface of the solder resist layer 7 and the inner wall of the first solder resist opening 701 (not shown);

[0242] (4) Please refer to Fig.23 , forming a patterned second shielding layer 9 on the top metal seed layer 8, and forming a top conductive layer 10 covering the exposed surface of the top metal seed layer 8 based on the patterned second shielding layer 9 and adopting an electroplating method of controlling different current densities in stages, wherein the top conductive layer 10 includes an electroplated copper column 1001 filling the solder resist opening 701 and a top metal layer 1002 protruding from the surface of the solder resist layer 7;

[0243] (5) Please refer to Fig.24 , removing the second shielding layer 9, and performing a flash etching process to remove the top metal seed layer 8 not covered by the top conductive layer 10;

[0244] (6) Please refer to Fig.25 , forming solder balls 11 on the top conductive layer 10 , and the solder balls 11 are electrically connected to the top metal layer 1002 .

[0245] As an example, before forming the intermediate interconnect layer 6 on the surface of the first ABF layer 4 , a step of forming an underlying interconnect structure 5 is also included, wherein at least a portion of the underlying interconnect structure 5 is embedded in the first ABF layer 4 and electrically connected to the underlying circuit layer 3 .

[0246] As an example, Figures 14 to 16 As shown, forming the bottom interconnect structure 5 includes the following steps:

[0247] (1) Fig.14As shown, the first ABF layer 4 is laser drilled by a multi-segment alignment method to obtain a first contact hole 501, and the first contact hole 501 is aligned with the bottom wiring layer 3 and exposes at least a portion of the surface of the bottom wiring layer 3;

[0248] (2) forming a conductive seed layer 502 covering the surface of the first ABF layer 4 and the inner wall of the first contact hole 501, and forming a patterned third shielding layer on the surface of the conductive seed layer 502 to shield the area where the bottom interconnect structure 5 is not required to be formed (not shown);

[0249] (3) Fig.15 As shown, an electroplating method is used to form an underlying conductive layer 503 on the exposed surface of the conductive seed layer 502, and the patterned third shielding layer is removed;

[0250] (5) Fig.16 As shown, the conductive seed layer 502 not covered by the bottom conductive layer 503 is removed by vacuum two-fluid etching or excimer laser etching to obtain a bottom conductive seed layer 5021. The bottom conductive seed layer 5021 and the bottom conductive layer 503 constitute the bottom interconnect structure 5. The bottom interconnect structure 5 includes a bottom conductive plug 504 filled in the first contact hole 501 and a bottom metal pad 505 and a bottom conductive line 506 protruding from the surface of the first ABF layer 4.

[0251] As an example, laser drilling of the first ABF layer 4 using the multi-segment alignment method includes the following steps:

[0252] (1) Dividing the front and back sides of the core board 101 into a plurality of units, each of the units including at least one two-dimensional alignment mark, determining the processing area corresponding to each of the units by reading the two-dimensional alignment mark, and realizing independent alignment of each of the units based on the two-dimensional alignment mark;

[0253] (2) A laser drill is used to laser drill the first ABF layer 4 in each of the units. The laser drill automatically aligns by reading the two-dimensional alignment mark in each of the units to ensure that the position of the first contact hole 501 formed by laser drilling is accurately aligned with the bottom circuit layer 3.

[0254] As an example, the two-dimensional alignment mark includes a cross mark, a two-dimensional ruler mark, a square mark or a mark of other suitable shapes. In this embodiment, a two-dimensional ruler mark is preferred. The two-dimensional alignment mark can provide accurate alignment information on two directional axes, so that during the laser drilling process, the actual processing position and the predetermined processing position can be consistent in the horizontal and vertical directions, thereby ensuring that the position of the first contact hole 501 formed is accurately aligned with the bottom circuit layer 3.

[0255] Specifically, when a laser drill is used to form the first contact hole 501, the laser drill used includes any one of a UV laser drill, a CO2 laser drill, a green laser drill, and an ultrafast laser drill, and these laser drills can be equipped with a picosecond laser or a femtosecond laser. In this embodiment, a laser with a wavelength in the range of 238 nanometers to 1064 nanometers is selected to form the first contact hole 501, wherein the laser energy is 13.4W and the number of pulses is 16.

[0256] Specifically, the method for forming the conductive seed layer 502 includes chemical plating, chemical vapor deposition, physical vapor deposition or other suitable methods. The material of the conductive seed layer 502 includes at least one of copper, platinum, titanium, tungsten, nickel, gold, silver, and copper-nickel alloy. Wherein, when the conductive seed layer 502 is formed by chemical copper deposition process, the internal stress of the chemical copper deposition process is less than 50KPa, the throwing power is greater than 80%, and the conductive seed layer 502 formed is a copper layer with a thickness of ≤0.5 microns. When the conductive seed layer 502 is formed by magnetron sputtering process, the conductive seed layer 502 includes a copper layer, a tungsten layer and a titanium layer stacked in sequence, wherein the thickness of the copper layer ranges from 100 to 300 nanometers, the thickness of the titanium layer ranges from 20 to 80 nanometers, and the thickness of the tungsten layer can be selected according to actual needs, for example, 20 nanometers. In a specific example, the thickness of the copper layer is 200 nanometers, the thickness of the titanium layer is 50 nanometers, and the thickness of the tungsten layer is 20 nanometers.

[0257] Specifically, the third shielding layer is a photosensitive material layer, which is patterned by exposure and development, and the third shielding layer can be a dry film or a wet film. In this embodiment, the third shielding layer is preferably a dry film, and the dry film is formed on the surface of the conductive seed layer 502 by lamination or vacuum lamination.

[0258] As an example, the resolution of the third shielding layer is ≤1.5 microns. The third shielding layer has the same function as the first shielding layer 2, which not only helps to form ultra-fine lines with a line width / line spacing of less than or equal to 2 microns, but also can effectively reduce errors in processing such as exposure and improve exposure quality.

[0259] As an example, the electroplating is performed in an electroplating bath equipped with an auxiliary cathode to form the bottom conductive layer 503 .

[0260] Specifically, the bottom conductive layer 503 is formed by the same electroplating process as the bottom metal conductive layer 302. In the process of forming the bottom conductive layer 503, the auxiliary cathode introduced into the electroplating tank significantly improves the uniformity of the bottom conductive layer 503 film, avoiding the problem of uneven electroplating caused by the difference in current density in different regions.

[0261] Specifically, the method for removing the third shielding layer is a common method for removing photosensitive materials, which will not be described in detail here.

[0262] Specifically, when the vacuum two-fluid etching method is used to form the bottom conductive seed layer 5021, the components of the selected etchant are the same as the components of the etchant used to form the bottom metal seed layer 301, and the effects of the two are also the same. The vacuum two-fluid etching method not only ensures the uniformity of the etching process and the precise control of the line width, but also significantly improves the etching efficiency.

[0263] As an example, when the conductive seed layer 502 is etched by excimer laser etching, the adjustable range of laser energy is 160-200 mJ, and the range of pulse width is 10-30 ns. The method of forming the bottom conductive seed layer 5021 by excimer laser etching in this embodiment has the characteristics of high processing accuracy and low damage.

[0264] As an example, the distance between the bottom metal pad 505 and the bottom conductive line 506 is ≥20 micrometers, and the height of the top surface of the bottom metal pad 505 is higher than the height of the bottom conductive line 506 .

[0265] Specifically, the spacing, line width and size design between the bottom metal pad 505 and the bottom conductive circuit 506 ensure that the height of the top surface of the bottom metal pad 505 is higher than the height of the bottom conductive circuit 506, thereby preventing the surface of the bottom conductive circuit 506 from being scratched or peeled off due to contact with other objects during the movement or processing of the packaging substrate, thereby effectively protecting the bottom conductive circuit 506 from damage.

[0266] As an example, the minimum line width / line spacing of the bottom conductive line 506 is ≤ 2 microns.

[0267] As an example, forming the intermediate interconnect layer 6 on the surface of the first ABF layer 4 includes the following steps:

[0268] (1) Fig.17As shown, an intermediate dielectric layer 601A covering the first ABF layer 4 is formed, and the intermediate dielectric layer 601A covers the bottom interconnect structure 5, the intermediate dielectric layer 601A is a second ABF layer 6011A, and the material of the second ABF layer 6011A includes a silicon dioxide filler, and the particle size of the silicon dioxide filler is ≤0.5 microns;

[0269] (2) Fig.18 As shown, the second ABF layer 6011A is laser drilled by a multi-segment alignment method to obtain a second contact hole 6012A, and the second contact hole 6012A is aligned with the underlying interconnection structure 5 and exposes at least a portion of the surface of the underlying interconnection structure 5;

[0270] (3) forming an intermediate metal seed layer 6021A, wherein the intermediate metal seed layer 6021A covers the surface of the second ABF layer 6011A and the inner wall of the second contact hole 6012A, and forming a patterned fourth shielding layer on the surface of the intermediate metal seed layer 6021A to shield an area where the intermediate circuit layer 602A is not required to be formed (not shown);

[0271] (4) Fig.19 As shown, an intermediate conductive layer 6022A is formed on the exposed surface of the intermediate metal seed layer 6021A by electroplating, and the patterned fourth shielding layer is removed;

[0272] (5) Fig. 20 As shown, the intermediate metal seed layer 6021A not covered by the intermediate conductive layer 6022A is removed by vacuum two-fluid etching or excimer laser etching to obtain an intermediate metal seed layer 60211A. The intermediate metal seed layer 60211A and the intermediate conductive layer 6022A constitute the intermediate circuit layer 602A. The intermediate circuit layer 602A includes an intermediate conductive plug 6023A filled in the second contact hole 6012A and an intermediate metal pad 6024A and an intermediate conductive circuit 6025A protruding from the surface of the second ABF layer 6011A.

[0273] Specifically, the second ABF layer 6011A can be formed on the surface of the first ABF layer 4 by lamination, coating, deposition or other appropriate methods.

[0274] As an example, the material of the second ABF layer 6011A further includes epoxy resin.

[0275] Specifically, in this embodiment, the SiO2 filler with a particle size of ≤0.5 μm is mixed with the ABF material in a preset ratio, and epoxy resin is added. After stirring to form a uniform mixed liquid, the mixed liquid is applied to the surface of the first ABF layer 4, and hot pressing and curing treatment is performed to form the second ABF layer 6011A.

[0276] As an example, the second ABF layer 6011A has a Tg≥180° C., a Young's modulus≥15 GPa, and a Df≤0.009.

[0277] Specifically, in this embodiment, the second ABF layer 6011A is formed in the same manner as the first ABF layer 4, and the technical effects achieved are the same. Both are formed by fillers with smaller particle sizes, and have high surface flatness, which can effectively avoid subsequent process problems caused by uneven surfaces, and ensure that fine lines (such as ultra-fine lines with line width / line spacing ≤ 2 microns) are stably and accurately formed on their surfaces. At the same time, both have excellent high-temperature stability, high rigidity, high elasticity, low dielectric loss, low thermal expansion coefficient, excellent mechanical properties and good durability, etc., can effectively resist deformation caused by external forces, reduce energy loss during signal transmission, and improve signal integrity and transmission efficiency.

[0278] Specifically, the steps of laser drilling the second ABF layer 6011A by using the multi-segment alignment method are the same as the steps of laser drilling the first ABF layer 4 by using the multi-segment alignment method, which will not be repeated here.

[0279] As an example, when the second ABF layer 6011A is laser drilled using the multi-segment alignment method, it also includes adjusting the drilling position and angle of the second contact hole 6012A according to the alignment deviation between the underlying interconnect structure 5 and the underlying circuit layer 3 to compensate for the alignment deviation between the underlying interconnect structure 5 and the underlying circuit layer 3, thereby ensuring that the second contact hole 6012A is accurately aligned with the underlying interconnect structure 5.

[0280] Specifically, if the alignment accuracy of the second contact hole 6012A is insufficient, the connectivity between the bottom metal pad 505 and the middle metal pad 6024A may be reduced, thereby causing instability or even potential failure of electrical performance, seriously affecting the overall function and reliability of the package substrate. This embodiment uses a multi-segment alignment method to laser drill the second ABF layer 6011A, which can effectively compensate for the accumulated deviations during the processing. By subdividing the processing area into multiple small areas and independently aligning each small area, this method effectively disperses the error and avoids the problem of deviation amplification caused by the accumulation of errors in a large area during overall alignment. In addition, this multi-segment alignment method can also be adjusted in real time according to the actual deviation of each small area, greatly improving the alignment accuracy, thereby ensuring accurate and reliable electrical connection between the bottom metal pad 505 and the middle metal pad 6024A.

[0281] As an example, the diameter of the second contact hole 6012A is ≤40 micrometers.

[0282] As an example, the second contact hole 6012A is formed by green laser drilling or excimer laser drilling.

[0283] Specifically, CO2 laser drilling has a good effect on removing epoxy resin in the second ABF layer 6011A, and can effectively remove this component during drilling. However, there is a thermal effect problem when removing SiO2 filler, which easily leads to a lot of glue residue on the edge of the second contact hole 6012A; while UV laser drilling is not easy to absorb SiO2 filler, which easily leads to SiO2 particles being deposited at the bottom of the second contact hole 6012A. In this embodiment, green laser drilling is preferably used to form the second contact hole 6012A. The wavelength of green light is 532nm, which is between UV laser and CO2 laser, and has the advantages of both. It can remove epoxy resin and SiO2 filler in the second ABF layer 6011A at the same time, which is conducive to the deposition of subsequent materials.

[0284] Specifically, the method of forming the intermediate metal seed layer 6021A includes chemical plating, chemical vapor deposition, physical vapor deposition or other suitable methods. The material of the intermediate metal seed layer 6021A includes at least one of copper, platinum, titanium, tungsten, nickel, gold, silver, and copper-nickel alloy. In this embodiment, the material of the intermediate metal seed layer 6021A is preferably copper.

[0285] Specifically, in one example, when the intermediate metal seed layer 6021A is formed by a chemical copper plating process, the internal stress of the chemical copper plating process is less than 50KPa, the plating capacity is greater than 80%, and the intermediate metal seed layer 6021A formed is a copper layer with a thickness of ≤0.5 microns. In another example, when the intermediate metal seed layer 6021A is formed by a magnetron sputtering process, the intermediate metal seed layer 6021A includes a copper layer / tungsten layer / titanium layer stacked in sequence, wherein the thickness of the copper layer ranges from 100 to 300 nanometers, the thickness of the titanium layer ranges from 20 to 80 nanometers, and the thickness of the tungsten layer can be selected according to actual needs, for example, 20 nanometers. In a specific example, the thickness of the copper layer is 200 nanometers, the thickness of the titanium layer is 50 nanometers, and the thickness of the tungsten layer is 20 nanometers.

[0286] As an example, the fourth shielding layer is a photosensitive material layer, which is patterned by exposure and development, and the fourth shielding layer can be a dry film or a wet film. In this embodiment, the fourth shielding layer is preferably a dry film, and the dry film is formed on the surface of the intermediate metal seed layer 6021A by lamination or vacuum lamination.

[0287] As an example, the resolution of the fourth shielding layer is ≤1.5 microns. The fourth shielding layer has the same function as the first shielding layer 2 and the third shielding layer, which not only helps to form ultra-fine lines with a line width / line spacing of ≤2 microns, but also can effectively reduce errors in processing such as exposure and improve exposure quality.

[0288] As an example, the electroplating is performed using an electroplating bath equipped with an auxiliary cathode to form the intermediate conductive layer 6022A.

[0289] Specifically, the intermediate conductive layer 6022A, the bottom conductive layer 503 and the bottom metal conductive layer 302 are all formed by the same electroplating process. That is, in the process of forming the intermediate conductive layer 6022A, an auxiliary cathode is also introduced into the electroplating tank to optimize the electric field distribution, improve the electroplating uniformity of the intermediate conductive layer 6022A, avoid the problem of uneven electroplating caused by edge effect, and thus improve the electroplating quality of the intermediate conductive layer 6022A.

[0290] Specifically, the method for removing the fourth shielding layer is a common method for removing photosensitive materials, which will not be described in detail here.

[0291] Specifically, when the intermediate metal seed layer 60211A is formed by vacuum two-fluid etching, the components of the selected etchant are the same as the components of the etchant used to form the bottom conductive seed layer 5021 and the bottom metal seed layer 301, and the effect is also the same. The vacuum two-fluid etching process can improve etching efficiency, improve etching uniformity, and accurately control etching accuracy.

[0292] As an example, when the intermediate metal seed layer 6021A is etched by excimer laser etching, the adjustable range of laser energy is 160 to 200 mJ, and the range of pulse width is 10 to 30 ns. The laser energy in this embodiment is preferably 180 mJ, the pulse width is preferably 20 ns, and high-density and high-energy excimer laser etching is achieved through a single process. The method of forming the intermediate metal seed layer 60211A by excimer laser etching in this embodiment has the characteristics of high processing accuracy and low damage.

[0293] As an example, the distance between the middle metal pad 6024A and the middle conductive line 6025A is ≥20 micrometers, and the height of the top surface of the middle metal pad 6024A is higher than the height of the middle conductive line 6025A.

[0294] Specifically, the spacing, line width and size design between the intermediate metal pad 6024A and the intermediate conductive line 6025A ensure that the top surface height of the intermediate metal pad 6024A is higher than the height of the intermediate conductive line 6025A. This design can effectively prevent the surface of the intermediate conductive line 6025A from being scratched or peeled off due to contact with other objects during the movement or certain processing of the packaging substrate, thereby effectively protecting the intermediate conductive line 6025A from damage and effectively improving the product yield.

[0295] As an example, the minimum line width / line spacing of the intermediate conductive line 6025A is ≤ 2 microns.

[0296] At this point, an intermediate interconnection layer 6 is manufactured.

[0297] It should be noted that the above steps can be repeated as needed to construct multiple layers of the intermediate interconnection layer 6, that is, different numbers of hierarchical structures can be realized according to different product specifications and performance requirements, and no specific limitation is made here. Fig.21 , which is a schematic diagram of the cross-sectional structure after two layers of intermediate interconnection layers 6 are formed.

[0298] As an example, before forming the solder resist layer 7 , the step of roughening the surface of the intermediate interconnect layer 6 is also included.

[0299] Specifically, in this embodiment, the surface of the intermediate interconnection layer 6 is roughened using super roughening solution CZ8401.

[0300] Specifically, the material of the solder resist layer 7 includes solder resist ink or other suitable solder resist materials. The method of forming the solder resist layer 7 includes mounting, coating or other suitable methods. In this embodiment, the solder resist layer 7 is made by mounting solder resist ink. Subsequently, the first solder resist opening 701 and the second solder resist opening 702 are formed in the solder resist layer 7 by a laser drilling process.

[0301] Specifically, in this embodiment, a picosecond or femtosecond laser can be used to perform the laser drilling process in Punch mode to form the first solder resist opening 701 and the second solder resist opening 702. The laser wavelength ranges from 238 to 1064 nanometers, and the laser energy and the number of shots can be selected according to actual conditions. In this embodiment, the laser energy is preferably 4.5W, and the number of shots is preferably 36.

[0302] Specifically, the second shielding layer 9 is a photosensitive material layer.

[0303] Specifically, the material of the top conductive layer 10 includes any one of copper, platinum, titanium, tungsten, nickel, gold, silver, and copper-nickel alloy. In this embodiment, the material of the top conductive layer 10 is preferably copper.

[0304] As an example, the electroplating method for controlling different current densities in stages includes three consecutive electroplating stages, and the current density of each electroplating stage increases successively, including the following steps:

[0305] (1) The first stage of electroplating is carried out with a current density ranging from 2 to 5 A / dm 2 ;

[0306] (2) The second stage of electroplating is carried out, and the current density range is 10~15A / dm 2 ;

[0307] (3) The third stage of electroplating is carried out, and the current density range is 16~20A / dm 2 .

[0308] Specifically, the lower current density in the first stage can make copper ions deposit at a uniform rate, ensuring the stable formation of the electroplated copper column 1001; the increased current density in the second stage helps to accelerate the formation of the electroplated copper column 1001 and improve production efficiency; the current density in the third stage can not only ensure the integrity and density of the electroplated copper column 1001, but also further improve production efficiency.

[0309] Specifically, the method for removing the second shielding layer 9 is a common method for removing photosensitive materials, which will not be described in detail here.

[0310] Specifically, the top metal seed layer 8 is a copper layer. In this embodiment, the flash etching process can be performed by a vacuum two-fluid etching process or an excimer laser etching process to remove the top metal seed layer 8 not covered by the top conductive layer 10 .

[0311] Specifically, the solder ball 11 may be formed by screen printing solder paste or by implanting solder balls through micro-holes.

[0312] Specifically, Fig.26 As shown, after the solder ball 11 is formed, the process further includes flip-chip bonding at least two chips 12 to the solder ball 11 , and the pads 1201 on the chips 12 are electrically connected to the solder ball 11 .

[0313] Specifically, the method further includes forming a plastic encapsulation layer 13 on the surface of the solder resist layer 7 close to the chip 12 , wherein the plastic encapsulation layer 13 covers the chip 12 and fills the gap between the chip and the solder resist layer 7 .

[0314] At this point, a packaging substrate structure with ultra-fine circuits has been manufactured.

[0315] This embodiment provides a method for preparing a packaging substrate. By optimizing the filler size, the flatness of the ABF layer is significantly improved, and the problems such as inconsistent exposure focus, pattern deformation, and even inability to image caused by the unevenness of the ABF layer are effectively avoided, thereby ensuring that fine circuits can be stably and accurately formed on its surface, including the bottom circuit layer and the middle circuit layer. At the same time, by optimizing the electroplating process method, the uniformity of electroplating is improved, the problem of uneven electroplating caused by the difference in current density in different regions is avoided, and the thickness uniformity and film quality of the circuit layer are further improved. In addition, by selecting a dry film with high resolution, the exposure quality is improved, and combined with the improved etching method, the etching of ultra-fine circuits is effectively realized, avoiding the side etching or over-etching problems that are prone to occur in traditional processes, thereby greatly improving the fineness and accuracy of the circuit. Finally, by optimizing the alignment method of laser drilling, the problem of inaccurate alignment is solved. This series of improvement measures cooperate with each other to improve the reliability and accuracy of the method for preparing ultra-fine circuits on the packaging substrate as a whole.

[0316] Embodiment 2

[0317] The present embodiment provides a method for preparing a packaging substrate. The method for preparing a packaging substrate in the present embodiment is basically the same as the method for preparing a packaging substrate in the first embodiment, except that before forming the intermediate interconnect layer 6 on the surface of the first ABF layer 4, it also includes a step of removing part of the first ABF layer 4 until the surface of the remaining first ABF layer 4 is flush with the top of the bottom wiring layer 3.

[0318] like Fig. 27 , which is a schematic diagram of the cross-sectional structure after the first ABF layer 4 covering the bottom circuit layer 3 is formed on the front and back sides of the core board 101 in this embodiment. Fig. 27 The preparation method of the structure shown is similar to that formed in Example 1. Fig.13 The structures shown are prepared in the same manner. Fig. 27 The cross-sectional structure diagram in the embodiment 1 is visually similar to that in the embodiment 1. Fig.13 There are some differences, but these differences are mainly for more intuitively demonstrating the subsequent process steps and do not change the methods used by the two embodiments in preparing the illustrated structures.

[0319] like Fig.28 As shown, it is a schematic diagram of the cross-sectional structure after a portion of the first ABF layer is removed.

[0320] Specifically, the method for removing the first ABF layer 4 includes plasma etching, chemical mechanical polishing (CMP) or other suitable methods. In this embodiment, the first ABF layer 4 is preferably removed by plasma etching.

[0321] As an example, forming the intermediate interconnect layer 6 on the surface of the first ABF layer 4 includes the following steps:

[0322] (1) Fig.29 As shown, an intermediate dielectric layer 601B is formed on the surface of the first ABF layer 4, and the intermediate dielectric layer 601B includes a blind hole etch stop layer 6011B, a first dielectric layer 6012B, a trench etch stop layer 6013B, a second dielectric layer 6014B and a first hard mask layer 6015B stacked in sequence;

[0323] (2) Fig.30 As shown, a patterned first dry film 603B is formed on the first hard mask layer 6015B, and the first hard mask layer 6015B is etched based on the patterned first dry film 603B to form a first hard mask opening 60151B;

[0324] (3) Fig.31As shown, the first dry film 603B is removed, and dry etching or laser drilling is performed based on the first hard mask opening 60151B to form a blind hole 6016B penetrating the second dielectric layer 6014B, the trench etch stop layer 6013B and the first dielectric layer 6012B;

[0325] (4) Fig.32 As shown, a second dry film 604B covering the first hard mask layer 6015B and filling the blind hole is formed, the second dry film 604B is patterned, and the first hard mask layer 6015B is etched based on the patterned second dry film 604B to form a second hard mask opening 60152B exposing the second dielectric layer 6014B;

[0326] (5) Fig.33 As shown, the second dry film 604B is removed, and etching is performed based on the second hard mask opening 60152B to form a circuit notch 6017B and a trench 6018B, the etching stops at the trench etch stop layer 6013B, the minimum size of the circuit notch 6017B is ≤ 2 microns, and the bottom of the trench 6018B is connected to the top of the blind hole 6016B;

[0327] (7) Fig.35 As shown, an intermediate metal seed layer 6021B is formed, and the intermediate metal seed layer 6021B covers the surface of the first hard mask layer 6015B, the inner wall of the blind hole 6016B, the inner wall of the line notch 6017B and the inner wall of the groove 6018B;

[0328] (8) Fig.36 As shown, electroplating is performed to form an intermediate conductive layer 6022B covering the intermediate metal seed layer 6021B, and the intermediate conductive layer 6022B also fills the blind hole 6016B, the line notch 6017B and the groove 6018B;

[0329] (9) Fig.37 As shown, part of the intermediate conductive layer 6022B is removed until the top surface of the intermediate conductive layer 6022B is at the same level as the top surface of the intermediate metal seed layer 6021B, so as to obtain a portion of the intermediate circuit layer 602B embedded in the intermediate dielectric layer 601B and electrically connected to the bottom circuit layer 3, and the intermediate circuit layer 602B includes a conductive interconnect structure 6023B filling the blind hole 6016B and the groove 6018B, and includes an intermediate conductive circuit 6024B filling the circuit notch.

[0330] Specifically, the method for forming the blind hole etch stop layer 6011B includes plasma enhanced chemical vapor deposition, remote microwave plasma chemical vapor deposition, electron cyclotron resonance chemical vapor deposition, atomic layer deposition, magnetron sputtering or other suitable methods. The material of the blind hole etch stop layer 6011B includes SiC, SiCN, SiCO or other suitable carbon-based dielectric materials. In this embodiment, the material of the blind hole etch stop layer 6011B is preferably SiCN.

[0331] Specifically, the first dielectric layer 6012B and the second dielectric layer 6014B can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition or other suitable methods. The first dielectric layer 6012B and the second dielectric layer 6014B are made of low-k (low dielectric constant) materials to reduce parasitic capacitance and reduce signal delay. In this embodiment, low-k materials suitable for the first dielectric layer 6012B and the second dielectric layer 6014B include but are not limited to SiF, SiOC, porous SiO2, etc. In this embodiment, the material of the first dielectric layer 6012B and the second dielectric layer 6014B is preferably porous SiO2.

[0332] Specifically, the method for forming the trench etch stop layer 6013B includes chemical vapor deposition, physical vapor deposition, atomic layer deposition or other suitable methods. The material for forming the trench etch stop layer 6013B includes SiN, Si3N4, SiC, SiOC, SiOF or other suitable dielectric materials. In this embodiment, the material of the trench etch stop layer 6013B is preferably SiN.

[0333] Specifically, the method of forming the first hard mask layer 6015B includes chemical vapor deposition, physical vapor deposition, atomic layer deposition or other suitable methods. The material of the first hard mask layer 6015B includes at least one of SiO2, Si3N4, SiC and TiN.

[0334] Specifically, the first dry film 603B may be formed by lamination, coating, chemical vapor deposition, physical vapor deposition, atomic layer deposition or other suitable methods. The first dry film 603B may be patterned by exposure and development to define the initial position and shape of the blind hole 6016B.

[0335] Specifically, in this embodiment, after the first hard mask layer 6015B is etched by a dry etching process, the first dry film 603B is removed by an organic solvent or an inorganic solvent.

[0336] Specifically, when the blind hole 6016B is formed by a dry etching process, the etching gas used includes but is not limited to any one or a combination of Ar, N2, O2 and CF4. The selection is made according to the actual material layer and is not overly restricted here. The blind hole etching stop layer 6011B of this embodiment can accurately control the etching depth of the blind hole 6016B to avoid damage to the underlying material (i.e., the bottom circuit layer) during etching.

[0337] Specifically, when the blind hole 6016B is formed by a laser drilling process, the selected laser includes any one of a UV laser drilling machine, a CO2 laser drilling machine, a green light laser drilling machine and an ultrafast laser drilling machine, and these laser drilling machines can be equipped with a picosecond laser or a femtosecond laser. Among them, the energy of the laser is ≥6W, and the pulse and the number of shots can be selected according to actual needs. In this embodiment, a laser with a wavelength in the range of 238 nanometers to 1064 nanometers is selected to form the blind hole 6016B, and the taper of the blind hole 6016B is adjusted by adjusting the energy, pulse and number of shots of the laser to achieve the purpose of controlling the hole shape and the depth of the blind hole. In a specific example, the energy of the laser is ≥6W, and the number of shots is ≥1 shot.

[0338] As an example, the taper between the side wall and the bottom of the blind hole 6016B is ≥85% to avoid forming a dead angle at the bottom of the blind hole 6016B that cannot be filled with material.

[0339] Specifically, the second dry film 604B may be formed by lamination, coating, chemical vapor deposition, physical vapor deposition, atomic layer deposition or other suitable methods. The second dry film 604B is a photosensitive material and may be patterned by exposure and development.

[0340] As an example, the resolution of the second dry film 604B is ≤1.5 microns, that is, the minimum size of the second hard mask opening 60152B is ≤1.5 microns.

[0341] Specifically, in this embodiment, the first hard mask layer 6015B is etched by dry etching process to form the second hard mask opening 60152B. The second hard mask opening 60152B defines the area where the line notch 6017B and the trench 6018B are formed.

[0342] In this embodiment, the second dielectric layer 6014B is etched by dry etching process to form the circuit notch 6017B and the groove 6018B. The groove etching stop layer 6013B is used to accurately control the etching depth of the circuit notch 6017B and the groove 6018B.

[0343] As an example, before forming the intermediate metal seed layer, the following steps are also included:

[0344] (1) Fig.34 As shown, the blind hole etch stop layer 6011B at the bottom of the blind hole 6016B and the trench etch stop layer 6013B at the bottom of the line notch 6017B and the bottom of the trench 6018B are removed;

[0345] (2) forming a barrier layer, wherein the barrier layer covers the surface of the first hard mask layer 6015B, the inner wall of the blind hole 6016B, the inner wall of the line notch 6017B and the inner wall of the groove 6018B, and the intermediate metal seed layer 6021B covers the surface of the barrier layer (not shown).

[0346] Specifically, the blind hole etch stop layer 6011B at the bottom of the blind hole 6016B and the trench etch stop layer 6013B at the bottom of the line notch 6017B and the bottom of the trench 6018B are removed by a dry etching process or a wet etching process.

[0347] Specifically, the method of forming the barrier layer includes chemical vapor deposition, physical vapor deposition, magnetron sputtering, atomic layer deposition or other suitable process methods. The material of the barrier layer includes TaN, TiN, TiC or other high-performance barrier materials. In this embodiment, the material of the barrier layer is preferably TaN. The barrier layer is mainly used to prevent the electroplating material (such as copper, etc.) in the subsequent electroplating process from diffusing into the dielectric layer (including the second dielectric layer 6014B and the first dielectric layer 6012B), resulting in a decrease in the performance of the dielectric layer and affecting the reliability and stability of the package substrate. In addition, the barrier layer also provides good adhesion performance, which is convenient for the subsequent formation of the intermediate metal seed layer 6021B.

[0348] Specifically, the method for forming the intermediate metal seed layer 6021B includes magnetron sputtering, chemical vapor deposition, physical vapor deposition or other suitable methods. The material of the intermediate metal seed layer 6021B includes at least one of copper, platinum, titanium, tungsten, nickel, gold, silver, and copper-nickel alloy. In this embodiment, the intermediate metal seed layer 6021B is preferably formed by magnetron sputtering and chemical copper deposition, and the material of the intermediate metal seed layer 6021B is preferably copper.

[0349] Specifically, the intermediate conductive layer 6022B is formed by electroplating, and the material of the intermediate conductive layer 6022B includes at least one of copper, platinum, titanium, tungsten, nickel, gold, silver, and copper-nickel alloy. In this embodiment, the material of the intermediate conductive layer 6022B is preferably copper.

[0350] Specifically, after the intermediate conductive layer 6022B is lowered to a certain height by using the CMP process, the remaining part of the intermediate conductive layer 6022B is removed by a dry etching process until the top surface of the intermediate conductive layer 6022B is at the same level as the top surface of the intermediate metal seed layer 6021B. In the process of removing the intermediate conductive layer 6022B by using the CMP process, the process steps of placing the plate → adding polishing liquid → mechanical grinding → thickness monitoring are repeated many times until the intermediate conductive layer 6022B is lowered to a certain height, and it is ensured that the surface of the intermediate conductive layer 6022B is level and has no pits or grooves. Among them, in the CMP process, the polishing liquid selected generally includes abrasive particles, oxidants, complexing agents, surfactants, abrasives, pH adjusters and corrosion inhibitors.

[0351] As an example, the minimum line width / line spacing of the middle conductive line 6024B is ≤ 2 microns.

[0352] At this point, an intermediate interconnection layer 6 is manufactured.

[0353] As an example, the above steps are repeated to form multiple layers of the intermediate interconnection layer 6 .

[0354] Specifically, the specific number of layers of the intermediate interconnection layer 6 can be selected according to actual needs and is not specifically limited here. Fig.38 , which is a schematic diagram of the cross-sectional structure after three intermediate interconnection layers 6 are formed in this embodiment.

[0355] Specifically, after the intermediate interconnection layer 6 is formed, the subsequent process steps are the same as those in the first embodiment, and will not be described in detail here.

[0356] The present embodiment provides a method for preparing a packaging substrate. In the process of forming an intermediate interconnection layer, the method uses a high-resolution dry film material, effectively improves the exposure accuracy, and accurately defines the size of blind holes, grooves, and line notches. At the same time, combined with a dry etching process, the process has a high anisotropic etching capability, can achieve a steep sidewall morphology, while maintaining the integrity and consistency of the line type and the groove type, thereby ensuring the high-quality formation of ultra-fine lines on the packaging substrate. In addition, in the formed intermediate interconnection layer, the intermediate conductive line is embedded in the line notch, effectively avoiding scratches or damage caused by external friction, thereby significantly enhancing the stability and reliability of the line. At the same time, the present embodiment uses a low-k dielectric layer as an intermediate dielectric layer, which effectively reduces the parasitic capacitance of the packaging substrate, improves the signal transmission performance, and also reduces the power consumption of the circuit, further improving the stability and overall performance of the circuit operation.

[0357] Embodiment 3

[0358] This embodiment provides a method for preparing a packaging substrate. The method for preparing a packaging substrate in this embodiment is basically the same as the method for preparing a packaging substrate in Embodiment 2, except that: forming the intermediate interconnection layer 6 on the surface of the first ABF layer 4 includes the following steps:

[0359] (1) Fig.41 As shown, an intermediate dielectric layer 601C is formed on the surface of the first ABF layer 4, the intermediate dielectric layer 601C is a third ABF layer 6011C, the material of the third ABF layer 6011C includes a silicon dioxide filler, and the particle size of the silicon dioxide filler is ≤0.5 microns;

[0360] (2) Fig.42 As shown, a nanoimprint stamp with a concave pattern is provided, and the nanoimprint stamp is imprinted on the third ABF layer 6011C to form a pattern structure including a blind hole 6012C, a circuit notch 6013C and a groove 6014C in the third ABF layer 6011C, wherein the blind hole 6012C exposes at least a portion of the surface of the bottom circuit layer 3, the top of the blind hole 6012C is connected to the bottom of the groove 6014C, and the minimum size of the circuit notch 6013C is ≤2 microns;

[0361] (3) Fig.43 As shown, an intermediate metal seed layer 6021C is formed to cover the surface of the third ABF layer 6011C, and the intermediate metal seed layer 6021C also covers the inner wall of the blind hole 6012C, the inner wall of the line notch 6013C and the inner wall of the groove 6014C;

[0362] (4) Fig.44 As shown, electroplating is performed to form an intermediate conductive layer 6022C covering the intermediate metal seed layer 6021C, and the intermediate conductive layer 6022C also fills the blind hole 6012C, the line notch 6013C and the groove 6014C;

[0363] (5) Fig.45 As shown, part of the intermediate conductive layer 6022C is removed until the top surface of the intermediate conductive layer 6022C is at the same level as the top surface of the intermediate metal seed layer 6021C, so as to obtain a portion of the intermediate circuit layer 602C embedded in the intermediate dielectric layer 601C and electrically connected to the bottom circuit layer 3, and the intermediate circuit layer 602C includes a conductive interconnect structure 6023C filling the blind hole 6012C and the groove 6014C, and includes an intermediate conductive circuit 6024C filling the circuit notch 6013C.

[0364] As an example, the formation of the nanoimprint stamp includes the following steps:

[0365] (1) providing a substrate layer and forming a bottom metal layer on the substrate layer (not shown);

[0366] (2) forming a patterned fifth shielding layer on the underlying metal layer, and etching the underlying metal layer based on the patterned fifth shielding layer using a vacuum two-fluid etching method or an excimer laser etching method to form a desired recessed pattern, wherein the resolution of the fifth shielding layer is ≤1.5 μm (not shown);

[0367] (3) The fifth shielding layer is removed to form a nickel protective layer covering the surface of the underlying metal layer to protect the recessed pattern (not shown).

[0368] Specifically, the third ABF layer 6011C can be formed on the surface of the first ABF layer 4 by lamination, coating, deposition or other appropriate methods.

[0369] As an example, the material of the third ABF layer 6011C further includes epoxy resin.

[0370] Specifically, in this embodiment, the SiO2 filler with a particle size of ≤0.5 microns is mixed with the ABF material according to a preset ratio, and epoxy resin is added, and after stirring to form a uniform mixed liquid, the mixed liquid is applied to the surface of the first ABF layer 4 to form the third ABF layer 6011C. The third ABF layer 6011C is formed by using fillers with a smaller particle size, has high flatness, can effectively avoid subsequent process problems caused by uneven surface, and ensure that fine circuits (such as ultra-fine circuits with a line width / line spacing of ≤2 microns) are stably and accurately formed on its surface.

[0371] As an example, the third ABF layer 6011C has a Tg≥180° C., a Young's modulus≥15 GPa, and a Df≤0.009.

[0372] As an example, the nanoimprint stamp is imprinted on the surface of the third ABF layer 6011C by a simultaneous imprinting and curing method.

[0373] Specifically, in order to ensure the alignment accuracy during the imprinting process and avoid the alignment error caused by the uneven shrinkage of the third ABF layer 6011C during the curing process, the present embodiment adopts a method of synchronizing imprinting and curing, and while imprinting the nanoimprint stamp on the surface of the third ABF layer 6011C, the third ABF layer 6011C is thermally cured. More specifically, at the beginning of imprinting, the temperature control system of the imprinting equipment is adjusted so that the third ABF layer 6011C begins to cure during the imprinting period, and at the same time, the vacuum chamber control system of the imprinting equipment is used to synchronously adjust the pressure and vacuum state to ensure that the third ABF layer 6011C is uniformly stressed and stably formed.

[0374] In a specific example, the nanoimprint stamp is imprinted on the third ABF layer 6011C under the conditions of 45 seconds of vacuum and 0.8 MPa pressure, and the temperature is maintained at 150° C. for 20 minutes to form the graphic structure in the third ABF layer 6011C. After the imprinting is completed, in order to prevent the nanoimprint stamp from adhering to the surface of the third ABF layer 6011C, the temperature condition of 200° C. is continued to be maintained for 75 minutes to ensure that the third ABF layer 6011C is completely cured before removing the nanoimprint stamp, so as to achieve a high-precision, high-quality graphic molding effect.

[0375] As an example, after the nanoimprint stamp is imprinted on the front and back of the core board structure layer 1, a step of removing the residue in the graphic structure is also included. In this embodiment, a plasma process or a desmearing process is used to remove the third ABF layer 6011C remaining at the bottom of the blind hole 6012C during the imprinting process, so that the blind hole 6012C reveals at least a portion of the surface of the bottom wiring layer 3.

[0376] Specifically, the method for forming the intermediate metal seed layer 6021C includes magnetron sputtering, chemical vapor deposition, physical vapor deposition or other suitable methods. The material of the intermediate metal seed layer 6021C includes at least one of copper, platinum, titanium, tungsten, nickel, gold, silver, and copper-nickel alloy. In this embodiment, the intermediate metal seed layer 6021C is preferably formed by magnetron sputtering and chemical copper deposition, and the material of the intermediate metal seed layer 6021C is preferably copper.

[0377] Specifically, the intermediate conductive layer 6022C is formed by electroplating, and the material of the intermediate conductive layer 6022C includes at least one of copper, platinum, titanium, tungsten, nickel, gold, silver, and copper-nickel alloy. In this embodiment, the material of the intermediate conductive layer 6022C is preferably copper.

[0378] Specifically, after the intermediate conductive layer 6022C is lowered to a certain height by a CMP process, the remaining portion of the intermediate conductive layer 6022C is removed by a dry etching process until the top surface of the intermediate conductive layer 6022C is at the same level as the top surface of the intermediate metal seed layer 6021C. The method for removing the intermediate conductive layer 6022C in this embodiment is the same as the method and function of removing the intermediate conductive layer 6022B in the second embodiment, and will not be described in detail here.

[0379] As an example, the minimum line width / line spacing of the middle conductive line 6024C is ≤ 2 microns.

[0380] At this point, an intermediate interconnection layer 6 is manufactured.

[0381] As an example, the above steps are repeated to form multiple layers of the intermediate interconnection layer 6 .

[0382] Specifically, the specific number of layers of the intermediate interconnection layer 6 can be selected according to actual needs and is not specifically limited here.

[0383] Specifically, after the intermediate interconnection layer 6 is formed, the subsequent process steps are the same as those in the first embodiment, and will not be described in detail here.

[0384] The present embodiment provides a method for preparing a packaging substrate, which forms the required graphic structure, including blind holes, grooves and circuit notches, on the packaging substrate at one time by imprinting a nanoimprint stamp in the ABF layer. Compared with the traditional stamp made of PDMS material, there is a higher thermal expansion coefficient, which is easy to cause the pattern to stretch after imprinting, making it difficult to achieve the problem of accurate imprinting of ultra-fine circuits. The nanoimprint stamp used in this embodiment is composed of an underlying metal layer and a nickel protective layer, which has a lower thermal expansion coefficient and higher mechanical strength, can effectively avoid deformation problems, and is more suitable for forming the recessed pattern required for ultra-fine circuits. At the same time, this embodiment introduces a fifth shielding layer with high resolution for exposure, and uses a vacuum two-fluid etching method or an excimer laser etching method with high etching accuracy for etching, so that a fine recessed pattern that meets the requirements can be formed in the nanoimprint stamp. The recessed pattern is efficiently transferred to the packaging substrate through the imprinting process, realizing the one-time accurate formation of the ultra-fine circuit pattern, and avoiding the problem of graphic error accumulation that may occur in the traditional multi-step process. In addition, this embodiment adopts a process of simultaneous imprinting and curing, which greatly improves the alignment accuracy during the imprinting process and ensures the high consistency and accuracy of the circuit graphics, thereby significantly improving the preparation accuracy and production efficiency of ultra-fine circuits on the packaging substrate.

[0385] Embodiment 4

[0386] This embodiment provides a packaging substrate structure, which is obtained by using any one of the packaging substrate preparation methods in Embodiment 1, Embodiment 2 and Embodiment 3, and includes: a core board structure layer 1, a bottom circuit layer 3 and a first ABF layer 4, wherein:

[0387] The core plate structure layer 1 includes a core plate 101, a metal seed layer 102 and a metal interconnection layer 1031, the core plate 101 includes a plurality of first through holes 1011, the plurality of first through holes 1011 are arranged at intervals and penetrate the core plate 101, the metal seed layer 102 covers two opposite sides of the core plate 101 and the sidewalls of the first through holes 1011, the metal interconnection layer 1031 fills the first through holes 1011, wherein the metal seed layer 102 covering two opposite sides of the core plate 101 is etched by vacuum two-fluid etching method or excimer laser etching method to form a bottom metal seed layer 301;

[0388] The bottom wiring layer 3 includes the bottom metal seed layer 301 and the bottom metal conductive layer 302 located above the bottom metal seed layer 301;

[0389] The first ABF layer 4 is located on the front and back sides of the core board 101 . The first ABF layer 4 covers the bottom circuit layer 3 . The material of the first ABF layer 4 includes a silicon dioxide filler. The particle size of the silicon dioxide filler is ≤0.5 μm.

[0390] The packaging substrate structure provided in this embodiment realizes high-density interconnection between the chip and the packaging substrate on the basis of reducing the intermediate layer, which not only achieves a thinner and higher line density packaging effect, but also significantly reduces signal loss and improves signal transmission performance and the overall reliability of the packaging substrate. In addition, in the packaging substrate structure of the present invention, the number of intermediate interconnection layers can be flexibly adjusted according to actual needs, and can be designed as 2 layers, 3 layers or more layers to meet the needs of different application scenarios, such as high-performance computing, mobile devices, artificial intelligence and other high-density packaging fields.

[0391] In summary, the present invention provides a method and structure for preparing a packaging substrate, which has a simple process flow and low production cost. By forming an intermediate interconnection layer with ultra-fine lines in the packaging substrate, high-density interconnection between the chip and the packaging substrate is achieved, reducing the dependence on the intermediate layer, thereby significantly reducing the process complexity and production cost. The present invention can not only promote the development of local high-density interconnection packaging technology, but also open up more application scenarios for products based on ultra-fine lines of packaging substrates. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0392] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a packaging substrate, characterized in that: The following steps are involved: A core plate structure layer is provided, the core plate structure layer comprising a core plate, a metal seed layer and a metal interconnection layer, wherein the core plate comprises a plurality of first through holes, the plurality of first through holes are arranged at intervals and penetrate the core plate, the metal seed layer covers two opposite surfaces of the core plate and side walls of the first through holes, and the metal interconnection layer fills the first through holes; Forming a first shielding layer covering the surface of the metal seed layer and the surface of the metal interconnect layer, patterning the first shielding layer to form a first opening exposing the metal seed layer, and forming an underlying metal conductive layer filling the first opening by electroplating; Removing the first shielding layer, and etching the metal seed layer not covered by the bottom metal conductive layer by vacuum two-fluid etching or excimer laser etching to obtain a bottom metal seed layer, wherein the bottom metal seed layer and the bottom metal conductive layer constitute a bottom circuit layer; A first ABF layer covering the bottom circuit layer is formed on the front and back sides of the core board, wherein the material of the first ABF layer includes a silica filler, and the particle size of the silica filler is ≤0.5 micrometer.

2. The method for preparing a packaging substrate according to claim 1, characterized in that: After forming the first ABF layer on the front and back sides of the core board, the following steps are also included: Forming an intermediate interconnection layer on the surface of the first ABF layer, the intermediate interconnection layer comprising an intermediate dielectric layer and an intermediate circuit layer at least a portion of which is embedded in the intermediate dielectric layer and electrically connected to the bottom circuit layer; Forming a solder resist layer covering the intermediate interconnect layer, and forming a first solder resist opening in the solder resist layer on the front side of the core board, and forming a second solder resist opening in the solder resist layer on the back side of the core board, wherein the first solder resist opening and the second solder resist opening at least expose the conductive portion of the intermediate interconnect layer; Forming a top metal seed layer by chemical copper deposition, wherein the top metal seed layer covers the surface of the solder resist layer and the inner wall of the first solder resist opening; Forming a patterned second shielding layer on the top metal seed layer, and forming a top conductive layer covering the exposed surface of the top metal seed layer based on the patterned second shielding layer and using an electroplating method that controls different current densities in stages, wherein the top conductive layer includes electroplated copper columns that fill the solder mask openings and a top metal layer that protrudes from the surface of the solder mask layer; removing the second shielding layer and performing a flash etching process to remove the top metal seed layer not covered by the top conductive layer; Solder balls are formed on the top conductive layer, and the solder balls are electrically connected to the top metal layer.

3. The method for preparing a packaging substrate according to claim 2, wherein: Before forming the intermediate interconnection layer on the surface of the first ABF layer, the method further includes forming an underlying interconnection structure, wherein at least a portion of the underlying interconnection structure is embedded in the first ABF layer and electrically connected to the underlying circuit layer.

4. The method for preparing a packaging substrate according to claim 3, characterized in that: Forming the intermediate interconnect layer on the surface of the first ABF layer comprises the following steps: Forming an intermediate dielectric layer covering the first ABF layer, wherein the intermediate dielectric layer covers the bottom interconnect structure, the intermediate dielectric layer is a second ABF layer, the material of the second ABF layer includes a silicon dioxide filler, and the particle size of the silicon dioxide filler is ≤0.5 micrometer; Laser drilling the second ABF layer using a multi-segment alignment method to obtain a second contact hole, wherein the second contact hole is aligned with the underlying interconnect structure and exposes at least a portion of the surface of the underlying interconnect structure; Forming an intermediate metal seed layer, the intermediate metal seed layer covers the surface of the second ABF layer and the inner wall of the second contact hole, and forming a patterned fourth shielding layer on the surface of the intermediate metal seed layer to shield the area where the intermediate circuit layer is not required to be formed; Forming an intermediate conductive layer on the exposed surface of the intermediate metal seed layer by electroplating, and removing the patterned fourth shielding layer; The intermediate metal seed layer not covered by the intermediate conductive layer is removed by vacuum two-fluid etching or excimer laser etching to obtain an intermediate metal seed layer. The intermediate metal seed layer and the intermediate conductive layer constitute the intermediate circuit layer. The intermediate circuit layer includes an intermediate conductive plug filled in the second contact hole and an intermediate metal pad and an intermediate conductive circuit protruding from the surface of the second ABF layer.

5. The method for preparing a packaging substrate according to claim 3, characterized in that: Forming the bottom interconnect structure comprises the following steps: Laser drilling the first ABF layer using a multi-segment alignment method to obtain a first contact hole, wherein the first contact hole is aligned with the bottom wiring layer and exposes at least a portion of the surface of the bottom wiring layer; Forming a conductive seed layer covering the surface of the first ABF layer and the inner wall of the first contact hole, and forming a patterned third shielding layer on the surface of the conductive seed layer to shield the area where the bottom interconnect structure does not need to be formed; Forming a bottom conductive layer on the exposed surface of the conductive seed layer by electroplating, and removing the patterned third shielding layer; The conductive seed layer not covered by the underlying conductive layer is removed by vacuum two-fluid etching or excimer laser etching to obtain an underlying conductive seed layer. The underlying conductive seed layer and the underlying conductive layer constitute the underlying interconnect structure. The underlying interconnect structure includes an underlying conductive plug filled in the first contact hole and an underlying metal pad and an underlying conductive line protruding from the surface of the first ABF layer.

6. The method for preparing a packaging substrate according to claim 5, characterized in that: Laser drilling the first ABF layer using a multi-segment alignment method includes the following steps: Divide the front and back sides of the core board into a plurality of units, each of the units includes at least one two-dimensional alignment mark, determine the processing area corresponding to each of the units by reading the two-dimensional alignment mark, and realize independent alignment of each of the units based on the two-dimensional alignment mark; A laser drill is used to laser drill the first ABF layer in each of the units. The laser drill automatically aligns by reading the two-dimensional alignment mark in each of the units to ensure that the position of the first contact hole formed by laser drilling is accurately aligned with the bottom circuit layer.

7. The method for preparing a packaging substrate according to claim 2, characterized in that: Forming the intermediate interconnect layer on the surface of the first ABF layer comprises the following steps: Forming an intermediate dielectric layer on the surface of the first ABF layer, the intermediate dielectric layer comprising a blind hole etch stop layer, a first dielectric layer, a trench etch stop layer, a second dielectric layer and a first hard mask layer stacked in sequence; forming a patterned first dry film on the first hard mask layer, and etching the first hard mask layer based on the patterned first dry film to form a first hard mask opening; Removing the first dry film, and performing dry etching or laser drilling based on the first hard mask opening to form a blind hole penetrating the second dielectric layer, the trench etch stop layer, and the first dielectric layer; forming a second dry film covering the first hard mask layer and filling the blind hole, patterning the second dry film, and etching the first hard mask layer based on the patterned second dry film to form a second hard mask opening exposing the second dielectric layer; Removing the second dry film, and performing etching based on the second hard mask opening to form a circuit notch and a groove, wherein the etching stops at the groove etch stop layer, the minimum size of the circuit notch is ≤ 2 microns, and the bottom of the groove is connected to the top of the blind hole; forming an intermediate metal seed layer, wherein the intermediate metal seed layer covers the surface of the first hard mask layer, the inner wall of the blind hole, the inner wall of the circuit notch and the inner wall of the groove; Performing electroplating to form an intermediate conductive layer covering the intermediate metal seed layer, wherein the intermediate conductive layer also fills the blind hole, the line notch and the groove; A portion of the intermediate conductive layer is removed until the top surface of the intermediate conductive layer is at the same level as the top surface of the intermediate metal seed layer, so as to obtain a portion of the intermediate circuit layer embedded in the intermediate dielectric layer and electrically connected to the bottom circuit layer, wherein the intermediate circuit layer includes a conductive interconnect structure filling the blind hole and the groove, and includes an intermediate conductive circuit filling the circuit notch.

8. The method for preparing a packaging substrate according to claim 7, wherein: Before forming the intermediate interconnect layer on the surface of the first ABF layer, the method further includes removing part of the first ABF layer until the surface of the remaining first ABF layer is flush with the top of the bottom wiring layer.

9. The method for preparing a packaging substrate according to claim 7, characterized in that: Before forming the intermediate metal seed layer, the following steps are also included: Removing the blind hole etch stop layer at the bottom of the blind hole and the trench etch stop layer at the bottom of the line notch and the bottom of the trench; A barrier layer is formed, the barrier layer covers the surface of the first hard mask layer, the inner wall of the blind hole, the inner wall of the line notch and the inner wall of the trench, and the intermediate metal seed layer covers the surface of the barrier layer.

10. The method for preparing a packaging substrate according to claim 2, characterized in that: Forming the intermediate interconnect layer on the surface of the first ABF layer comprises the following steps: Forming an intermediate dielectric layer on the surface of the first ABF layer, the intermediate dielectric layer is a third ABF layer, the material of the third ABF layer includes a silicon dioxide filler, and the particle size of the silicon dioxide filler is ≤0.5 micrometer; Providing a nanoimprint stamp with a concave pattern, and imprinting the nanoimprint stamp on the third ABF layer to form a pattern structure including a blind hole, a circuit notch and a groove in the third ABF layer, wherein the blind hole exposes at least a portion of the surface of the bottom circuit layer, the top of the blind hole is connected to the bottom of the groove, and the minimum size of the circuit notch is ≤2 microns; forming an intermediate metal seed layer covering the surface of the third ABF layer, wherein the intermediate metal seed layer also covers the inner wall of the blind hole, the inner wall of the circuit notch and the inner wall of the groove; Performing electroplating to form an intermediate conductive layer covering the intermediate metal seed layer, wherein the intermediate conductive layer also fills the blind hole, the line notch and the groove; A portion of the intermediate conductive layer is removed until the top surface of the intermediate conductive layer is at the same level as the top surface of the intermediate metal seed layer, so as to obtain a portion of the intermediate circuit layer embedded in the intermediate dielectric layer and electrically connected to the bottom circuit layer, wherein the intermediate circuit layer includes a conductive interconnect structure filling the blind hole and the groove, and includes an intermediate conductive circuit filling the circuit notch.

11. The method for preparing a packaging substrate according to claim 10, characterized in that: The nanoimprint stamp is imprinted on the surface of the third ABF layer by adopting a method of simultaneous imprinting and curing.

12. The method for preparing a packaging substrate according to claim 10, characterized in that: The formation of the nanoimprint stamp comprises the following steps: Providing a substrate layer, and forming a bottom metal layer on the substrate layer; A fifth patterned shielding layer is formed on the bottom metal layer, and the bottom metal layer is etched by vacuum two-fluid etching or excimer laser etching based on the patterned fifth shielding layer to form a desired recessed pattern, wherein the resolution of the fifth shielding layer is ≤1.5 microns The fifth shielding layer is removed to form a nickel protection layer covering the surface of the bottom metal layer to protect the recessed pattern.

13. A packaging substrate structure, characterized in that: The packaging substrate structure is obtained by the packaging substrate preparation method according to any one of claims 1 to 12, comprising: a core board structure layer, a bottom line layer and a first ABF layer, wherein the core board structure layer comprises a core board, a metal seed layer and a metal interconnection layer, the core board comprises a plurality of first through holes, the plurality of first through holes are arranged at intervals and penetrate the core board, the metal seed layer covers the two opposite sides of the core board and the side walls of the first through holes, the metal interconnection layer fills the first through holes, wherein the metal seed layer covering the two opposite sides of the core board is etched by vacuum two-fluid etching method or excimer laser etching method to form a bottom metal seed layer; The bottom wiring layer includes the bottom metal seed layer and a bottom metal conductive layer located above the bottom metal seed layer; The first ABF layer is located on the front and back sides of the core board, the first ABF layer covers the bottom circuit layer, and the material of the first ABF layer includes a silica filler, and the particle size of the silica filler is ≤0.5 microns.

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