Packaging device and packaging method for chip with hole

Abstract

The invention belongs to the field of chip technology, and discloses a packaging method for a chip with a hole, which is characterized by comprising the following steps: first, preparing a composite substrate with a gradient expansion coefficient; second, performing plasma etching on a metallized through hole of a DIP chip to form a micro-nano rough surface, fixing the DIP chip on the composite substrate by a gradient temperature field welding process, and injecting a liquid crystal polymer oriented by a magnetic field at the periphery of the DIP chip to form an anisotropic packaging layer; third, making a BGA pad array on the back of the packaged composite substrate, and constructing a bionic microtexture on the packaging surface by laser etching; and fourth, depositing a diamond-like carbon protective film, a gel layer and a gradient metallized outer layer on the surface of the processed packaging structure in sequence to form a packaging body; the performance of the chip packaging is improved, the thermal management, mechanical performance and protection capability of the chip are optimized, and the reliability and service life of the chip packaging are significantly improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to packaging equipment and a packaging method for a chip with a hole. Background Art

[0002] In industrial fields such as environmental exploration, electronic equipment often needs to be operated under high voltage and high corrosion (including H 2 S / Cl - The traditional chip packaging structure with holes is prone to failure due to the thermal-mechanical-chemical multi-field coupling: the high-pressure environment causes stress concentration in the package body to cause cracking, the corrosive medium penetrates through the through-hole interface to cause a short circuit, and the thermal stress generated by the temperature cycle causes fatigue fracture of the solder joint. According to statistics, the chip packaging failure rate in such an environment is 3-5 times higher than that in a conventional environment, which seriously restricts the reliability and service life of industrial sensing equipment and underwater robots.

[0003] In the existing technology, chip packaging for high-voltage environments mostly uses a single material substrate (such as FR-4 or alumina ceramic) with a conventional plastic packaging process, and interconnection is achieved by making vertical through holes on the ceramic substrate and filling them with conductive glue. However, this method has significant defects: the difference in the coefficient of thermal expansion (CTE) between the substrate and the chip material leads to the accumulation of thermal stress at the interface (such as the difference of 150% between the CTE of alumina 6.5ppm / ℃ and the CTE of silicon chip 2.6ppm / ℃), which causes the expansion of microcracks around the through hole under temperature shock, accelerates the intrusion of corrosive media along the crack path, and ultimately causes the overall failure of the packaging structure. This defect directly leads to the insufficient long-term reliability of existing packaging technology in high-voltage and high-corrosion scenarios.

[0004] In view of this, it is necessary to improve the chip packaging technology in the prior art to solve the technical problem of its poor tolerance to highly corrosive environments. Summary of the invention

[0005] The purpose of the present invention is to provide a packaging device and a packaging method for a chip with a hole to solve the above technical problems.

[0006] To achieve this object, the present invention adopts the following technical solutions:

[0007] A packaging method for a chip with a hole, comprising:

[0008] Step 1, preparing a composite substrate with a gradient expansion coefficient;

[0009] Step 2: plasma etching the metallized through-holes of the DIP chip to form a micro-nano rough surface, fixing the DIP chip on the composite substrate by a gradient temperature field welding process, and injecting a magnetic field-oriented liquid crystal polymer around the periphery of the DIP chip to form an anisotropic packaging layer;

[0010] Step 3, making a BGA pad array on the back of the packaged composite substrate, filling the BGA pads with a pressure-sensitive conductive adhesive containing carbon nanotubes, and constructing a bionic microtexture on the package surface by laser etching;

[0011] Step 4: depositing a diamond-like carbon protective film, a gel layer and a gradient metallized outer layer on the surface of the processed packaging structure in sequence to form a packaging body; wherein the gel layer contains pressure-sensitive microcapsules, and the gradient metallized layer includes a titanium layer, a gold layer and an aluminum oxide layer.

[0012] Optionally, the step 1 of preparing a composite substrate having a gradient expansion coefficient specifically includes:

[0013] Alumina ceramic is used as a core layer, and modified polyimide layers are laminated on both sides of the core layer to form a three-layer structure as a main substrate of the composite substrate;

[0014] A main through hole and an array of stress buffer holes distributed around the main through hole are simultaneously processed on the main substrate by laser micro-drilling;

[0015] A three-dimensional rewiring layer containing XY-direction copper wires and Z-direction nano silver paste channels is constructed on the surface of the core layer.

[0016] Optionally, in the gradient temperature field welding process, the main through-hole area uses Sn96.5Ag3Cu0.5 solder and the peripheral force buffer hole array uses In52Sn48 solder.

[0017] Optionally, the step 2, plasma etching the metallized through-holes of the DIP chip to form a micro-nano rough surface, fixing the DIP chip on the composite substrate using a gradient temperature field welding process, and injecting a magnetic field-oriented liquid crystal polymer around the periphery of the DIP chip to form an anisotropic packaging layer, specifically includes:

[0018] S21, performing plasma etching on the metallized through holes of the DIP chip, specifically comprising: placing the DIP chip in a vacuum reaction chamber, introducing Ar / O 2 Mix the gas and perform plasma etching under preset conditions to form a micro-nano rough structure with a depth of 5-10 μm on the inner wall of the metallized through hole, and the roughness Ra value is controlled within the range of 1.2-1.8 μm;

[0019] S22, coating flux on the surface of the composite substrate, aligning the DIP chip with the main through hole, and soldering and fixing the DIP chip on the composite substrate using a step-by-step temperature-raising soldering process;

[0020] S23, injecting a liquid crystal polymer oriented in a magnetic field around the DIP chip to form an anisotropic packaging layer, specifically comprising: setting an annular injection groove around the DIP chip, injecting the liquid crystal polymer, applying a 0.5T axial magnetic field and maintaining it for a preset time to orient the LCP molecules along the magnetic field direction, and then heating to 280°C at a rate of 5°C / min to solidify, so as to form an anisotropic packaging layer;

[0021] S24, using SiO 2 The colloidal suspension is used as a polishing liquid, and the surface of the encapsulation layer is treated by a chemical mechanical polishing process to reduce the surface roughness Ra value to below 0.1 μm, so as to perform surface planarization treatment on the anisotropic encapsulation layer.

[0022] Optionally, the process of the step-by-step temperature increase welding process is:

[0023] In the first stage, the temperature was raised to 150°C at a rate of 10°C / min and kept at this temperature for 60s to melt In52Sn48 as a low-temperature solder;

[0024] In the second stage, the temperature is raised to 220°C at a rate of 5°C / min and kept at this temperature for 30 seconds to melt Sn96.5Ag3Cu0.5 as a high melting point solder and complete the welding of the main through-hole area;

[0025] In the third stage, the temperature is lowered to room temperature at a rate of 3°C / min to form a gradient welding interface.

[0026] Optionally, the step three is to make a BGA pad array on the back of the packaged composite substrate, fill the BGA pads with a pressure-sensitive conductive adhesive containing carbon nanotubes, and construct a bionic microtexture on the package surface by laser etching, which specifically includes:

[0027] S31, using photolithography to make pad patterns on the back of the substrate, using electrochemical deposition to deposit a 5μm thick copper layer on the pattern area, and using micro-stamping to form a corrugated structure on the pad surface to form a BGA pad array with stress buffering function;

[0028] S32, mixing the silicone rubber matrix and 8 wt% of carbon nanotubes in a double planetary mixer, performing a first stage of stirring under a preset stirring condition, then adding 0.5 wt% of silane coupling agent KH-550, and continuing a second stage of stirring to obtain a pressure sensitive conductive adhesive containing carbon nanotubes;

[0029] S33, the conductive glue is filled into the corrugated structure of the pad using a dispensing process, the filling amount is controlled at 90% of the pad volume, pre-cured at 80°C for 30 minutes, and then fully cured at 120°C for 60 minutes to form an interconnect structure with pressure-resistance response characteristics.

[0030] Optionally, after S33, the step further includes:

[0031] S34, using a femtosecond laser to process a bionic micro-pit structure on the package surface, with a pit diameter of 20-50μm, a depth of 10-30μm, and a distribution density of 500-1000 / mm². During the processing, argon gas protection is introduced to prevent surface oxidation, so as to construct a bionic micro-texture on the package surface;

[0032] S35, using atomic layer deposition to deposit a 50 nm thick fluorinated silane film on the bionic micro-texture surface, so that the surface contact angle reaches 162°, forming a super-hydrophobic protective layer to perform hydrophobic modification on the bionic micro-texture surface;

[0033] S36, uses white light interferometry to measure the bionic microtexture morphology parameters, verifies the hydrophobic performance through a contact angle tester, and adjusts the laser processing parameters and atomic layer deposition process conditions according to the test results to ensure that the surface function meets the design requirements.

[0034] Optionally, the step 4, sequentially depositing a diamond-like carbon protective film, a gel layer and a gradient metallized outer layer on the surface of the treated packaging structure to form a packaging body, specifically includes:

[0035] S41, using plasma enhanced chemical vapor deposition process, with methane as precursor, a 50 μm thick diamond-like carbon protective film was deposited at a power of 300 W, a gas pressure of 50 Pa, and a temperature of 200 °C;

[0036] S42, coating the surface of the diamond-like carbon protective film with a siloxane-modified polyurethane gel, with a thickness controlled within 100 μm, wherein the gel layer contains pressure-sensitive microcapsules with a diameter of 10-50 μm, and curing at a preset temperature to form a buffer layer with pressure-responsive characteristics;

[0037] S43, using a three-step deposition process to deposit a gradient metallization outer layer, specifically comprising: firstly electrochemically depositing a titanium layer of a first thickness as a bonding layer, then using a magnetron sputtering process to deposit a gold layer of a second thickness as a conductive layer, and then using an atomic layer deposition process to deposit an aluminum oxide layer of a third thickness as an anti-corrosion layer, wherein the deposition temperatures are 25° C., 150° C., and 120° C., respectively;

[0038] S44, laser shock peening was used to treat the multi-layer interface for 3 times to enhance the interface bonding strength and activate the microcapsules in the gel layer to form a self-healing network structure.

[0039] Optionally, the step 4 further includes:

[0040] Step five, placing the package body in a high-voltage simulation system for multi-parameter coupling testing, and dynamically calibrating the package parameters through laser fine-tuning of gel layer thickness, electric field optimization of the conductive glue network, and local pulse annealing according to the test results.

[0041] The present invention further provides a packaging device for implementing the packaging method of the chip with holes as described above, the packaging device comprising:

[0042] A composite substrate preparation module, including: a laser micro-drilling unit, a wiring construction unit and a thermal pressing device;

[0043] The packaging module comprises: a plasma etching chamber for plasma etching the metallized through-holes of a DIP chip, a welding device for welding the DIP chip using a gradient temperature field welding process, and a glue injection unit for injecting glue through a directional magnetic field;

[0044] A surface treatment module, including: a pad processing unit for making a BGA pad array, a filling unit for filling a pressure-sensitive conductive adhesive containing carbon nanotubes, and a laser etching unit;

[0045] The deposition module includes: a diamond-like carbon film deposition device, a gel layer coating unit, a gradient metallization deposition unit and a laser shock strengthening device.

[0046] Compared with the prior art, the present invention has the following beneficial effects: first, a composite substrate with a gradient expansion coefficient is prepared to provide a thermal stress adaptation basis for chip packaging; then, the DIP chip through-hole is plasma etched to enhance the interface bonding force, and the differentiated thermal matching and fixation of the chip and the substrate are realized through a gradient temperature field welding process, and an anisotropic packaging layer is formed on the periphery to directionally regulate the thermal distribution; based on the encapsulated substrate structure, a BGA pad array is manufactured and filled with pressure-sensitive conductive glue, and the environmental adaptability is optimized by combining the bionic micro-textured surface; finally, a composite protective barrier is formed by the coordinated deposition of a multi-layer protective system; the method improves the performance of chip packaging by combining the composite substrate, plasma etching, gradient temperature field welding process and bionic micro-texturing technology, optimizes the thermal management, mechanical properties and protection capabilities of the chip, and significantly improves the reliability and service life of the chip packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0048] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical contents disclosed by the present invention.

[0049] Figure 1 This is a schematic diagram of a process of packaging a chip with a hole according to the first embodiment of the present invention;

[0050] Figure 2 This is the second flow chart of the packaging method of the chip with holes of the first embodiment. DETAILED DESCRIPTION

[0051] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] In the description of the present invention, it should be understood that the terms "upper", "lower", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. It should be noted that when a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0053] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific implementation methods.

[0054] Embodiment 1:

[0055] Combination Figure 1 and Figure 2As shown, an embodiment of the present invention provides a packaging method for a chip with a hole, comprising:

[0056] Step 1: Prepare a composite substrate with a gradient expansion coefficient; by preparing the composite substrate with a gradient expansion coefficient, the thermal stress mismatch problem in a high-pressure and high-corrosion environment is solved.

[0057] Step 2: Plasma etching is performed on the metallized through holes of the DIP chip to form a micro-nano rough surface, a gradient temperature field welding process is used to fix the DIP chip on the composite substrate, and a magnetic field-oriented liquid crystal polymer is injected around the periphery of the DIP chip to form an anisotropic packaging layer; the interface reliability is synergistically improved through the triple technology of plasma etching-gradient welding-directional packaging.

[0058] Step three, make a BGA pad array on the back of the packaged composite substrate, fill the BGA pad with pressure-sensitive conductive adhesive containing carbon nanotubes, and use laser etching to construct a bionic microtexture on the package surface; construct an environmentally adaptive interconnection system through corrugated BGA pad-pressure-sensitive conductive adhesive-bionic microtexture.

[0059] Step 4: depositing a diamond-like carbon protective film, a gel layer and a gradient metallized outer layer on the surface of the processed packaging structure in sequence to form a packaging body; wherein the gel layer contains pressure-sensitive microcapsules, and the gradient metallized layer includes a titanium layer, a gold layer and an aluminum oxide layer.

[0060] The working principle of the present invention is as follows: first, a composite substrate with a gradient expansion coefficient is prepared to provide a thermal stress adaptation basis for chip packaging; then, plasma etching is performed on the DIP chip through-hole to enhance the interface bonding force, and a differential thermal matching fixation of the chip and the substrate is achieved through a gradient temperature field welding process, and an anisotropic packaging layer is formed on the periphery to directionally regulate the thermal distribution; based on the encapsulated substrate structure, a BGA pad array is manufactured and filled with a pressure-sensitive conductive adhesive, and the environmental adaptability is optimized by combining a bionic micro-textured surface; finally, a composite protective barrier is formed through the coordinated deposition of a multi-layer protective system; the method improves the performance of chip packaging, optimizes the thermal management, mechanical properties and protection capabilities of the chip, and significantly improves the reliability and service life of the chip packaging by combining a composite substrate, plasma etching, a gradient temperature field welding process and bionic micro-texturing technology.

[0061] In this embodiment, it is specifically described that step 1, preparing a composite substrate with a gradient expansion coefficient, specifically includes:

[0062] S11, using alumina ceramic as a core layer, and laminating modified polyimide layers on both sides of the core layer to form a three-layer structure as a main substrate of the composite substrate;

[0063] With alumina ceramic (CTE 6.5ppm / ℃) as the core layer and modified polyimide (CTE 18ppm / ℃) coated on both sides, a three-layer structure with a CTE gradient increasing from the inside to the outside is formed, which can absorb the thermal expansion difference step by step.

[0064] S12, synchronously processing a main through hole and an array of stress buffer holes distributed around the main through hole on the main substrate by laser micro-drilling;

[0065] Laser micro-drilling simultaneously processes the main through-holes and stress buffer hole arrays, where a 30μm copper layer is deposited on the inner wall of the main through-holes to achieve electrical interconnection, and the stress buffer holes are filled with silicone rubber / carbon nanotube composites (elastic modulus 0.5GPa) to form a mechanical stress buffer network.

[0066] S13, constructing a three-dimensional rewiring layer containing XY-direction copper wires and Z-direction nano silver paste channels on the surface of the core layer.

[0067] The three-dimensional interconnection architecture breaks through the limitations of traditional planar wiring, and the XY-direction copper wire (line width / spacing 50μm, thickness 15μm) is made on the surface of alumina ceramics using photolithography-electroplating process, with a coverage rate of 95%. The Z-direction nano silver paste channel is filled with screen printing technology (silver paste particle size 20nm, solid content 85%), and a vertical conductive structure is formed through low-temperature sintering (250℃ / 30min), with a conductivity of 5×10 6 S / m, thermal conductivity 120W / mK. 3D wiring shortens the signal transmission path by 40%, while the chip junction temperature is reduced through the synergistic effect of the planar heat dissipation of the copper wire and the vertical heat conduction of the silver paste channel.

[0068] In this embodiment, it is further explained that in the gradient temperature field welding process, the main through-hole area uses Sn96.5Ag3Cu0.5 solder and the peripheral force buffer hole array uses In52Sn48 solder.

[0069] The problem of thermal stress concentration is solved by differentiated solder selection and gradient welding process. The main through-hole area uses Sn96.5Ag3Cu0.5 solder (melting point 217℃), whose high mechanical strength (tensile strength 35MPa) can withstand the high current density in the main through-hole area; the peripheral stress buffer hole array uses In52Sn48 solder (melting point 118℃), which uses its low elastic modulus to absorb the stress caused by thermal expansion differences. Through step-by-step temperature increase welding (150℃→220℃, heating rate 5℃ / min), the low-temperature solder is first melted to achieve pre-positioning, and then the high-melting point solder is melted to complete the main area welding, avoiding the overall high temperature causing the substrate to warp (deformation <0.1mm / m). This design can reduce interface thermal stress and improve the fatigue life of solder joints.

[0070] In this embodiment, it is specifically described that step 2 is to perform plasma etching on the metallized through hole of the DIP chip to form a micro-nano rough surface, fix the DIP chip on the composite substrate by using a gradient temperature field welding process, and inject a magnetic field-oriented liquid crystal polymer around the periphery of the DIP chip to form an anisotropic packaging layer, which specifically includes:

[0071] S21, performing plasma etching on the metallized through holes of the DIP chip, specifically comprising: placing the DIP chip in a vacuum reaction chamber, introducing Ar / O 2 The mixed gas is used for plasma etching under the conditions of a preset radio frequency power of 300W and a gas pressure of 50Pa, so that a micro-nano rough structure with a depth of 5-10μm is formed on the inner wall of the metallized through hole, and the roughness Ra value is controlled within the range of 1.2-1.8μm;

[0072] By Ar / O 2 Mixed gas plasma etching (volume ratio 4:1, RF power 300W, gas pressure 50Pa, time 120s) is used to modify the surface of the DIP chip through-hole. High-energy plasma bombardment forms a micro-nano rough structure on the inner wall of the through-hole (depth 5-10μm, Ra value 1.2-1.8μm). The rough surface can increase the solder wetting area (contact angle from 110° to 25°) and improve the bonding strength through the mechanical interlocking effect (shear strength from 15MPa to 28MPa). The oxygen component (20%) can simultaneously remove surface organic contamination to ensure the cleanliness of the welding interface.

[0073] S22, coating flux on the surface of the composite substrate, aligning the DIP chip with the main through hole, and soldering and fixing the DIP chip on the composite substrate using a step-by-step temperature increase soldering process.

[0074] S23, injecting a liquid crystal polymer oriented in a magnetic field at the periphery of the DIP chip to form an anisotropic packaging layer, specifically comprising: setting an annular glue injection groove at the periphery of the DIP chip, injecting the liquid crystal polymer, applying a 0.5T axial magnetic field and maintaining it for a preset time to orient the LCP molecules along the direction of the magnetic field, and then heating to 280°C at a rate of 5°C / min to solidify, so as to form an anisotropic packaging layer; wherein the formed anisotropic packaging layer has an axial thermal conductivity of 1.8W / mK and a radial thermal conductivity of 0.3W / mK.

[0075] Controlling molecular orientation through axial magnetic field: Inject LCP (melt viscosity 500Pa·s) into the annular injection groove, apply 0.5T axial magnetic field for 60s, so that the liquid crystal molecules are oriented along the magnetic field direction, forming an anisotropic structure with the long axis of the molecular chain parallel to the magnetic field direction. During the curing stage, the temperature is raised to 280℃ at 5℃ / min and kept at this temperature for 30min to make the LCP crystallinity reach 75%, and the axial thermal conductivity (1.8W / mK) is 6 times that of the radial direction (0.3W / mK), achieving efficient axial heat dissipation and radial stress isolation of the chip.

[0076] S24, using SiO 2 The colloidal suspension was used as the polishing liquid, and the surface of the encapsulation layer was treated by chemical mechanical polishing process. SiO 2 The particle size of the colloidal suspension is 50nm, the polishing pressure is 0.2MPa, the rotation speed is 60rpm, and the processing time is 120s, so that the surface roughness Ra value is reduced to below 0.1μm to perform surface flattening on the anisotropic encapsulation layer. The removal rate is improved and surface scratches are reduced through the synergistic effect of chemical corrosion and mechanical grinding.

[0077] In this embodiment, it is specifically described that the process of the step-by-step temperature increase welding process is:

[0078] In the first stage, the temperature is raised to 150°C at a rate of 10°C / min and kept at this temperature for 60 seconds to melt In52Sn48 as a low-temperature solder; the temperature is kept at 150°C for 60 seconds to completely melt the In52Sn48 solder, and its low surface tension (0.4N / m) is used to achieve self-leveling of the outer area.

[0079] In the second stage, the temperature is raised to 220°C at a rate of 5°C / min and kept at this temperature for 30 seconds to melt Sn96.5Ag3Cu0.5 as a high melting point solder and complete the welding of the main through-hole area; the temperature is raised to 220°C and kept at this temperature for 30 seconds. After the Sn96.5Ag3Cu0.5 solder melts, a high-strength connection is formed in the main through-hole area (IMC layer thickness 2-3μm).

[0080] In the third stage, the temperature is lowered to room temperature at a rate of 3℃ / min to form a gradient soldering interface. The temperature is lowered at a rate of 3℃ / min to suppress thermal shock and reduce the generation of microcracks (crack density <5 / mm²). The flux uses rosin-type activator (RA grade) to reduce the surface tension of the solder and improve the wetting coverage.

[0081] In this embodiment, it is specifically described that step three is to make a BGA pad array on the back of the packaged composite substrate, fill the BGA pad with a pressure-sensitive conductive adhesive containing carbon nanotubes, and construct a bionic micro-texture on the package surface by laser etching, which specifically includes:

[0082] S31, using photolithography to make pad patterns on the back of the substrate, using electrochemical deposition to deposit a 5μm thick copper layer on the pattern area, and using micro-stamping to form a corrugated structure on the pad surface (corrugation depth 50μm, period 200μm), the pad diameter is 0.4mm, the spacing is 0.8mm, forming a BGA pad array with stress buffering function;

[0083] High-precision stress buffer pads are achieved through a composite process of photolithography-electrodeposition-micro-stamping. The pad pattern is defined on the back of the substrate using UV lithography (wavelength 365nm, exposure dose 200mJ / cm²), and a 5μm thick copper layer is electrochemically deposited (current density 2A / dm², deposition rate 0.8μm / min) to ensure conductivity (resistivity ≤ 2μΩ·cm). The micro-stamping process (pressure 50MPa, mold temperature 150℃) forms a corrugated structure (depth 50μm, period 200μm) on the pad surface, with a corrugation radius R=25μm, which can convert external pressure into tangential stress distribution and reduce solder joint stress concentration by 40%.

[0084] S32, mixing the silicone rubber matrix and 8 wt% of carbon nanotubes in a double planetary mixer, performing a first stage of stirring under a preset stirring condition, then adding 0.5 wt% of silane coupling agent KH-550, and continuing a second stage of stirring to obtain a pressure sensitive conductive adhesive containing carbon nanotubes;

[0085] The stirring speed of the first stage was 500 rpm, the time was 30 min, 0.5 wt% of silane coupling agent KH-550 was added, and the second stage stirring was continued for 15 min to obtain a uniformly dispersed conductive adhesive precursor.

[0086] In a double planetary mixer, the silicone rubber matrix (viscosity 5000Pa·s) and 8wt% CNT were stirred at 500rpm for 30min to break up the CNT agglomerates; after adding 0.5wt% KH-550 silane coupling agent, the mixture was stirred at 200rpm for 15min to promote chemical bonding between the CNT and matrix interface (Si-O-Si bond formation rate>90%). Finally, the percolation threshold of the conductive glue was reduced to 0.5wt%, achieving a nonlinear response of pressure-conductivity.

[0087] S33, the conductive glue is filled into the corrugated structure of the pad using a dispensing process, the filling amount is controlled at 90% of the pad volume, pre-cured at 80°C for 30 minutes, and then fully cured at 120°C for 60 minutes to form an interconnect structure with pressure-resistance response characteristics.

[0088] Fill the BGA pad with pressure-sensitive conductive adhesive and cure it, specifically including: using a dispensing process to accurately fill the conductive adhesive into the corrugated pad, controlling the filling amount to 90% of the pad volume, pre-curing at 80°C for 30 minutes, and then fully curing at 120°C for 60 minutes to form an interconnect structure with pressure-resistance response characteristics (the resistance drops by 3 orders of magnitude under a pressure of 10MPa).

[0089] S34, using a femtosecond laser to process a bionic micro-pit structure on the package surface, with a pit diameter of 20-50μm, a depth of 10-30μm, and a distribution density of 500-1000 / mm². During the processing, argon gas protection is introduced to prevent surface oxidation, so as to construct a bionic micro-texture on the package surface;

[0090] Bionic surface construction is achieved through ultrafast laser cold processing technology. A femtosecond laser (wavelength 1030nm, pulse width 350fs, repetition frequency 100kHz) is used to process the shark skin-like pit structure, with a laser energy density of 5J / cm² and a scanning speed of 200mm / s. The pit morphology (diameter 20-50μm, depth 10-30μm) is precisely controlled through the multi-pulse accumulation effect (pulse number 50 / point). Argon protection (flow rate 10L / min) controls the surface oxygen content below 0.1% to avoid oxidation in the processing area (oxidation layer thickness <5nm). The design of a pit distribution density of 500-1000 / mm² reduces fluid resistance by 15%, while increasing the surface area to enhance the adhesion of the protective layer.

[0091] S35, depositing a 50 nm thick fluorinated silane film on the bionic micro-texture surface by atomic layer deposition, with a deposition temperature of 120°C and a precursor pulse time of 0.1 s, so that the surface contact angle reaches 162°, forming a super-hydrophobic protective layer to perform hydrophobic modification on the bionic micro-texture surface;

[0092] Long-term hydrophobic protection is achieved through atomic layer deposition (ALD) directional modification. Trimethylchlorosilane is used as a precursor, and 500 cycles of ALD deposition are performed at 120°C. Each cycle includes a 0.1s precursor pulse and a 10s nitrogen purge to form a 50nm thick fluorinated silane film. The surface of the film is enriched with fluorinated silicon groups, so that the contact angle reaches 162° and the rolling angle is less than 5°, achieving super hydrophobic properties. The film has excellent friction resistance and can effectively block the penetration of corrosive media.

[0093] S36, uses white light interferometry to measure the bionic microtexture morphology parameters, verifies the hydrophobic performance through a contact angle tester, and adjusts the laser processing parameters and atomic layer deposition process conditions according to the test results to ensure that the surface function meets the design requirements.

[0094] According to the test data:

[0095] Laser parameter optimization: adjust the energy density (±0.5J / cm²) to compensate for the pit depth deviation;

[0096] Atomic layer deposition process control: increase the precursor pulse time (0.1s→0.15s) to improve film coverage;

[0097] Conductive adhesive performance calibration: The CNT network is oriented by electric field assistance (1kV / cm) to reduce the resistance fluctuation to <5% under a pressure of 10MPa.

[0098] In this embodiment, it is specifically described that step 4, depositing a diamond-like carbon protective film, a gel layer and a gradient metallized outer layer on the surface of the processed packaging structure in sequence to form a packaging body, specifically includes:

[0099] S41, using plasma enhanced chemical vapor deposition process, with methane as precursor, a 50 μm thick diamond-like carbon protective film was deposited at a power of 300 W, a gas pressure of 50 Pa, and a temperature of 200 °C;

[0100] A diamond-like carbon (DLC) protective film is deposited on the surface of the packaging structure, specifically comprising: using a plasma enhanced chemical vapor deposition (PECVD) process with methane (CH 4 ) was used as the precursor, and a 50μm thick DLC film was deposited under the conditions of 300W power, 50Pa air pressure and 200℃ temperature. The film hardness reached 25GPa, the friction coefficient was reduced to 0.1, and the thermal expansion coefficient was controlled at 2.3ppm / ℃.

[0101] The active carbon ions (C+) generated by plasma dissociation combine with hydrogen radicals (H·) to form a dense structure with sp3 bonds accounting for more than 80%. The film hardness reaches 25GPa (Vickers hardness), the friction coefficient is reduced to 0.1, and the thermal expansion coefficient (2.3ppm / ℃) matches the substrate gradient. The nanoindentation modulus (300GPa) of the film can effectively resist plastic deformation under deep-sea high pressure (100MPa), and its dense structure (porosity <0.1%) can block the penetration of Cl- ions (permeability <1×10-14 cm2 / s).

[0102] S42, coating the surface of the diamond-like carbon protective film with a siloxane-modified polyurethane gel, with a thickness controlled within 100 μm, wherein the gel layer contains pressure-sensitive microcapsules with a diameter of 10-50 μm, and curing at a preset temperature to form a buffer layer with pressure-responsive characteristics;

[0103] The pressure compensation gel layer is coated and pre-cured, specifically comprising: coating the surface of the DLC film with siloxane-modified polyurethane gel, with a thickness controlled at 100 μm, the gel layer containing pressure-sensitive microcapsules with a diameter of 10-50 μm (filling amount 15 vol%), and pre-curing at 80°C for 30 minutes to form a buffer layer with pressure-responsive characteristics.

[0104] Dynamic stress compensation is achieved through a pressure-sensitive microcapsule composite gel layer. Siloxane-modified polyurethane gel (elastic modulus 0.5MPa, elongation at break 500%) was coated on the DLC surface with a thickness of 100μm, containing 15vol% pressure-sensitive microcapsules (diameter 10-50μm, shell layer of polyurethane / silicon dioxide composite, core material of epoxy resin monomer). After pre-curing at 80℃ for 30min (curing degree 60%), the microcapsules were evenly distributed in the gel layer. When the external pressure was greater than 20MPa, the microcapsules ruptured and released self-healing monomers (filling efficiency > 90%), and cracks were repaired in situ (repair rate > 85%) through ring-opening polymerization of epoxy groups (reaction activation energy 80kJ / mol).

[0105] S43, using a three-step deposition process to deposit a gradient metallization outer layer, specifically comprising: firstly electrochemically depositing a first titanium layer with a thickness of 5 μm as a bonding layer, then using a magnetron sputtering process to deposit a second gold layer with a thickness of 2 μm as a conductive layer, and then using an atomic layer deposition process to deposit a third aluminum oxide layer with a thickness of 100 nm as an anti-corrosion layer, the deposition temperatures being 25° C., 150° C., and 120° C., respectively;

[0106] Titanium bonding layer: Electrochemically deposit a 5μm thick titanium layer. The strong oxidation activity of titanium (oxidation potential -1.63V) forms a Ti-C chemical bond with the DLC surface.

[0107] Gold conductive layer: 2μm thick gold layer is deposited by magnetron sputtering, the resistivity of the gold layer is ≤2.4μΩ·cm, the thickness uniformity is ±5%, and a low-resistance electrical path is provided;

[0108] Alumina anti-corrosion layer: Atomic layer deposition of 100nm thick aluminum oxide, film density> 99.9%, corrosion resistance potential> 1.2V (vs. SCE), ion blocking efficiency> 99.99%.

[0109] S44, laser shock peening was used to treat the multi-layer interface for 3 times to enhance the interface bonding strength and activate the microcapsules in the gel layer to form a self-healing network structure.

[0110] The multi-layer structure interface is strengthened, specifically including: using laser shock strengthening (LSP) technology to treat the multi-layer interface, with a laser energy density of 5J / cm², a pulse width of 10ns, and 3 shock times, which increases the interface bonding strength by 40% and activates the microcapsules in the gel layer to form a self-healing network structure.

[0111] In this embodiment, it is further explained that step 4 further includes:

[0112] Step five, placing the package body in a high-voltage simulation system for multi-parameter coupling testing, and dynamically calibrating the package parameters through laser fine-tuning of gel layer thickness, electric field optimization of the conductive glue network, and local pulse annealing according to the test results.

[0113] Embodiment 2:

[0114] The present invention further provides a packaging device for implementing the packaging method of the chip with holes as in the first embodiment, the packaging device comprising:

[0115] A composite substrate preparation module, including: a laser micro-drilling unit, a wiring construction unit and a thermal pressing device;

[0116] Laser micro-drilling unit for processing main through-holes and stress buffer hole arrays;

[0117] A wiring construction unit, used to form XY-direction copper wires and Z-direction nano silver paste channels on the substrate surface;

[0118] A hot pressing device is used to composite the core layer of alumina ceramics with the modified polyimide layer.

[0119] The packaging module comprises: a plasma etching chamber for plasma etching the metallized through hole of a DIP chip, a welding device for welding the DIP chip by adopting a gradient temperature field welding process, and a glue injection unit for injecting glue by a directional magnetic field.

[0120] The surface treatment module includes: a pad processing unit for making a BGA pad array, a filling unit for filling a pressure-sensitive conductive adhesive containing carbon nanotubes, and a laser etching unit.

[0121] The deposition module includes: a diamond-like carbon film deposition device, a gel layer coating unit, a gradient metallization deposition unit and a laser shock strengthening device.

[0122] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A packaging method for a chip with a hole, characterized in that: include: Step 1, preparing a composite substrate with a gradient expansion coefficient; Step 2: plasma etching the metallized through-holes of the DIP chip to form a micro-nano rough surface, fixing the DIP chip on the composite substrate by a gradient temperature field welding process, and injecting a magnetic field-oriented liquid crystal polymer around the periphery of the DIP chip to form an anisotropic packaging layer; Step 3, making a BGA pad array on the back of the packaged composite substrate, filling the BGA pads with a pressure-sensitive conductive adhesive containing carbon nanotubes, and constructing a bionic microtexture on the package surface by laser etching; Step 4: depositing a diamond-like carbon protective film, a gel layer and a gradient metallized outer layer on the surface of the processed packaging structure in sequence to form a packaging body; wherein the gel layer contains pressure-sensitive microcapsules, and the gradient metallized layer includes a titanium layer, a gold layer and an aluminum oxide layer.

2. The packaging method of a chip with a hole according to claim 1, characterized in that: The step 1, preparing a composite substrate with a gradient expansion coefficient, specifically comprises: Alumina ceramic is used as a core layer, and modified polyimide layers are laminated on both sides of the core layer to form a three-layer structure as a main substrate of the composite substrate; A main through hole and an array of stress buffer holes distributed around the main through hole are simultaneously processed on the main substrate by laser micro-drilling; A three-dimensional rewiring layer containing XY-direction copper wires and Z-direction nano silver paste channels is constructed on the surface of the core layer.

3. The packaging method of a chip with a hole according to claim 2, characterized in that: In the gradient temperature field welding process, the main through hole uses Sn96.5Ag3Cu0.5 solder, and the peripheral stress buffer hole array uses In52Sn48 solder.

4. The packaging method of a chip with a hole according to claim 3, characterized in that: The second step is to perform plasma etching on the metallized through-holes of the DIP chip to form a micro-nano rough surface, fix the DIP chip on the composite substrate using a gradient temperature field welding process, and inject a magnetic field-oriented liquid crystal polymer around the DIP chip to form an anisotropic packaging layer, which specifically includes: S21, performing plasma etching on the metallized through hole of the DIP chip, specifically comprising: placing the DIP chip in a vacuum reaction chamber, introducing an Ar / O2 mixed gas with a volume ratio of 4:1, and performing plasma etching under preset conditions, so that the inner wall of the metallized through hole forms a micro-nano rough structure with a depth of 5-10 μm, and the roughness Ra value is controlled within the range of 1.2-1.8 μm; S22, coating flux on the surface of the composite substrate, aligning the DIP chip with the main through hole, and soldering and fixing the DIP chip on the composite substrate using a step-by-step temperature-raising soldering process; S23, injecting a liquid crystal polymer oriented in a magnetic field around the DIP chip to form an anisotropic packaging layer, specifically comprising: setting an annular injection groove around the DIP chip, injecting the liquid crystal polymer, applying a 0.5T axial magnetic field and maintaining it for a preset time to orient the LCP molecules along the magnetic field direction, and then heating to 280°C at a rate of 5°C / min to solidify, so as to form an anisotropic packaging layer; S24, using SiO2 colloidal suspension as polishing liquid, treating the surface of the encapsulation layer by chemical mechanical polishing process, so that the surface roughness Ra value is reduced to below 0.1 μm, so as to perform surface planarization treatment on the anisotropic encapsulation layer.

5. The packaging method of a chip with a hole according to claim 4, characterized in that: The process of the step-by-step heating welding process is as follows: In the first stage, the temperature was raised to 150°C at a rate of 10°C / min and kept at this temperature for 60s to melt In52Sn48 as a low-temperature solder; In the second stage, the temperature is raised to 220°C at a rate of 5°C / min and kept at this temperature for 30 seconds to melt Sn96.5Ag3Cu0.5 as a high melting point solder and complete the main through-hole welding; In the third stage, the temperature is lowered to room temperature at a rate of 3°C / min to form a gradient welding interface.

6. The packaging method of a chip with a hole according to claim 1, characterized in that: The step three is to make a BGA pad array on the back of the packaged composite substrate, fill the BGA pads with a pressure-sensitive conductive adhesive containing carbon nanotubes, and construct a bionic micro-texture on the package surface by laser etching, which specifically includes: S31, using photolithography to make pad patterns on the back of the substrate, using electrochemical deposition to deposit a 5μm thick copper layer on the pattern area, and using micro-stamping to form a corrugated structure on the pad surface to form a BGA pad array with stress buffering function; S32, mixing the silicone rubber matrix and 8 wt% of carbon nanotubes in a double planetary mixer, performing a first stage of stirring under a preset stirring condition, then adding 0.5 wt% of silane coupling agent KH-550, and continuing a second stage of stirring to obtain a pressure sensitive conductive adhesive containing carbon nanotubes; S33, the conductive glue is filled into the corrugated structure of the pad using a dispensing process, the filling amount is controlled at 90% of the pad volume, pre-cured at 80°C for 30 minutes, and then fully cured at 120°C for 60 minutes to form an interconnect structure with pressure-resistance response characteristics.

7. The packaging method of a chip with a hole according to claim 6, characterized in that: The S33 also includes: S34, using a femtosecond laser to process a bionic micro-pit structure on the package surface, with a pit diameter of 20-50μm, a depth of 10-30μm, and a distribution density of 500-1000 / mm². During the processing, argon gas protection is introduced to prevent surface oxidation, so as to construct a bionic micro-texture on the package surface; S35, using atomic layer deposition to deposit a 50 nm thick fluorinated silane film on the bionic micro-texture surface, so that the surface contact angle reaches 162°, forming a super-hydrophobic protective layer to perform hydrophobic modification on the bionic micro-texture surface; S36, uses white light interferometry to measure the bionic microtexture morphology parameters, verifies the hydrophobic performance through a contact angle tester, and adjusts the laser processing parameters and atomic layer deposition process conditions according to the test results to ensure that the surface function meets the design requirements.

8. The packaging method of a chip with a hole according to claim 1, characterized in that: The fourth step is to sequentially deposit a diamond-like carbon protective film, a gel layer and a gradient metallized outer layer on the surface of the treated packaging structure to form a packaging body, which specifically includes: S41, using plasma enhanced chemical vapor deposition process, with methane as precursor, a 50 μm thick diamond-like carbon protective film was deposited at a power of 300 W, a gas pressure of 50 Pa, and a temperature of 200 °C; S42, coating the surface of the diamond-like carbon protective film with a siloxane-modified polyurethane gel, with a thickness controlled within 100 μm, wherein the gel layer contains pressure-sensitive microcapsules with a diameter of 10-50 μm, and curing at a preset temperature to form a buffer layer with pressure-responsive characteristics; S43, using a three-step deposition process to deposit a gradient metallization outer layer, specifically comprising: firstly electrochemically depositing a titanium layer of a first thickness as a bonding layer, then using a magnetron sputtering process to deposit a gold layer of a second thickness as a conductive layer, and then using an atomic layer deposition process to deposit an aluminum oxide layer of a third thickness as an anti-corrosion layer, wherein the deposition temperatures are 25° C., 150° C., and 120° C., respectively; S44, laser shock peening was used to treat the multi-layer interface for 3 times to enhance the interface bonding strength and activate the microcapsules in the gel layer to form a self-healing network structure.

9. The packaging method of a chip with a hole according to claim 1, characterized in that: The step 4 further includes: Step five, placing the package body in a high-voltage simulation system for multi-parameter coupling testing, and dynamically calibrating the package parameters through laser fine-tuning of gel layer thickness, electric field optimization of the conductive glue network, and local pulse annealing according to the test results.

10. A packaging device, characterized in that: A packaging method for a chip with holes as claimed in any one of claims 1 to 9, wherein the packaging device comprises: A composite substrate preparation module, including: a laser micro-drilling unit, a wiring construction unit and a thermal pressing device; The packaging module comprises: a plasma etching chamber for plasma etching the metallized through-holes of a DIP chip, a welding device for welding the DIP chip using a gradient temperature field welding process, and a glue injection unit for injecting glue through a directional magnetic field; A surface treatment module, including: a pad processing unit for making a BGA pad array, a filling unit for filling a pressure-sensitive conductive adhesive containing carbon nanotubes, and a laser etching unit; The deposition module includes: a diamond-like carbon film deposition device, a gel layer coating unit, a gradient metallization deposition unit and a laser shock strengthening device.

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