A method, test structure, and test system for monitoring the performance of semiconductor devices

Abstract

A method, test structure and test system for monitoring the performance of semiconductor devices, relating to a method for monitoring the performance of semiconductor devices, comprising: forming at least two test units each containing a semiconductor structure on a silicon wafer, including at least one first test unit having a first structure cluster and at least one second test unit having a second structure; performing a laser annealing process on the silicon wafer and measuring the electrical parameters of the second structure; and evaluating the influence of the laser annealing process on the performance of the second structure based on the electrical parameters of the second structure measured at different first structure densities. This application evaluates the influence of the laser annealing process on the performance between semiconductor devices of different materials and different densities by measuring the electrical parameters of the second structure corresponding to different first structure densities after laser annealing; and improves the performance and yield of semiconductor devices and reduces production costs by improving the semiconductor structure design and the laser annealing process conditions.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a method, a test structure and a test system for monitoring the performance of semiconductor devices. Background Art

[0002] In the semiconductor device manufacturing process, a laser beam can be used to repair implanted lattice damage and activate impurity atoms. In the nano-CMOS manufacturing process, laser annealing is commonly used for source / drain extension region and contact region implantation annealing to obtain ultra-shallow junctions and low resistance. However, due to the different semiconductor structure materials and structures grown in different regions on the silicon wafer surface, laser annealing is prone to cause a pattern effect of different temperatures in different regions, which affects the performance between devices. Summary of the Invention

[0003] In this application, by measuring the electrical parameters of a second structure corresponding to different first structure densities after laser annealing, the influence of the laser annealing process on the performance of semiconductor devices with different materials and different densities is evaluated; it is expected to improve the performance and yield of semiconductor devices and reduce production costs by improving the semiconductor structure design and laser annealing process conditions.

[0004] Other objects and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0005] To achieve one or part or all of the above objects or other objects, the present invention provides a method, a test structure and a test system for monitoring the performance of semiconductor devices.

[0006] In a first aspect, in the present embodiment, a method for monitoring the performance of semiconductor devices is provided, including:

[0007] Form at least two test units including semiconductor structures on a silicon wafer, including at least one first test unit having a first structure cluster and at least one second test unit having a second structure; wherein, the area ratio of the first structure cluster in the first test unit is used to characterize the first structure density;

[0008] Perform a laser annealing process on the silicon wafer and test the electrical parameters of the second structure;

[0009] Based on the electrical parameters of the second structure measured under different first structure densities, evaluate the influence of the laser annealing process on the performance of the second structure.

[0010] In some of these embodiments, the first structure cluster is at least one of an active region cluster and a polysilicon cluster;

[0011] The second structure is at least one of an active region, polysilicon or a MOS transistor.

[0012] In some of these embodiments, a plurality of the first structures are centrally distributed in the first test unit to form the first structure cluster;

[0013] When there are multiple types of the first test units, the first structure clusters of each type of the first test unit are different from each other.

[0014] In some of these embodiments, when there are multiple types of the second test units, the second structures of each type of the second test unit are different from each other;

[0015] A plurality of the second structures are provided in each type of the second test unit, and the plurality of the second structures are distributed relative to the first structure cluster in different forms;

[0016] Among them, different forms at least include one of the following:

[0017] The doping type, size, setting direction, direction or distance relative to the first structure cluster of the second structure.

[0018] In some of these embodiments, testing the electrical parameters of the second structure includes:

[0019] Testing the resistance value of the second structure; and / or

[0020] Testing the saturation current, saturation threshold voltage or turn-off current of the second structure.

[0021] In some of these embodiments, evaluating the influence of the laser annealing process on the performance of the second structure based on the electrical parameters of the second structure measured under different first structure densities includes:

[0022] Drawing a relationship curve between different first structure densities and the electrical parameters of the second structure according to the measured electrical parameters, and determining the required laser annealing process window according to the relationship curve.

[0023] In some of these embodiments, evaluating the influence of the laser annealing process on the performance of the second structure based on the electrical parameters of the second structure measured under different first structure densities includes:

[0024] Obtaining the electrical parameters of a plurality of the second structures to obtain an electrical parameter set;

[0025] Based on the electrical parameter sets corresponding to different first structure densities, drawing relationship curves between a plurality of the first structure densities and the electrical parameters of the second structure, and determining the required laser annealing process window according to the plurality of relationship curves.

[0026] In some of these embodiments, determining the required laser annealing process window according to the plurality of relationship curves includes:

[0027] Determining the fluctuation range of the electrical parameters of the second structure according to the relationship curve, and determining whether the fluctuation range is within a preset threshold; if the fluctuation range is within the preset threshold, the first structure density corresponding to the relationship curve is the required laser annealing process window.

[0028] In a second aspect, a test structure for monitoring the performance of a semiconductor device is provided in this embodiment, which is used to implement the method for monitoring the performance of a semiconductor device according to any one of the above first aspects, and includes:

[0029] A silicon wafer;

[0030] At least two types of test units grown on the silicon wafer, including at least one first test unit having a first structure cluster and at least one second test unit having a second structure;

[0031] A test circuit electrically connected to the second structure for measuring the electrical parameters of the second structure.

[0032] In some of these embodiments, a plurality of the first structures are concentratedly distributed in the first test unit to form the first structure cluster;

[0033] A plurality of second structures are provided in each second test unit, and the plurality of second structures are distributed relative to the first structure cluster in different distribution forms;

[0034] Among them, different forms at least include any one of the following: the doping type, size, setting direction, direction or distance of setting relative to the first structure cluster of the second structure.

[0035] In some of these embodiments, the first structure cluster is an active region cluster or a polysilicon cluster;

[0036] The second structure is an active region, polysilicon or MOS transistor, and the test circuit is electrically connected to the second structure;

[0037] Alternatively, the second structure is a MOS transistor, and the test circuit is electrically connected to the gate, source, drain and base of the MOS transistor respectively.

[0038] In a third aspect, a test system for monitoring the influence of laser annealing on the performance of a semiconductor device is provided in this embodiment, which includes a plurality of test structures described in the second aspect. Among them, the area ratio of the first structure cluster in the first test unit is used to characterize the first structure density, and the first test units in the plurality of test structures correspond to different first structure densities.

[0039] Compared with the prior art, the beneficial effects of the present invention mainly include:

[0040] 1. The present application provides a method for monitoring the performance of semiconductor devices. By forming on a silicon wafer at least one first test unit having a first structure cluster and at least one second test unit having a second structure, after performing a laser annealing process on the silicon wafer, measuring the electrical parameters of the second structure under different first structure density conditions, which is used to evaluate the influence of the first test unit with different first structure densities on the performance of the second structure during the laser annealing process;

[0041] 2. The present application provides a test structure for monitoring the performance of semiconductor devices, which is designed to include a silicon wafer, at least one first test unit having a first structure cluster and at least one second test unit having a second structure grown on the silicon wafer, and a test circuit electrically connected to the second structure; the specific quantitative monitoring of the influence of different materials and different densities on the performance between devices can be realized through the measured electrical parameters of the second structure;

[0042] 3. The present application also designs a test system for monitoring the influence of laser annealing on the performance of semiconductor devices. By monitoring the influence of the laser annealing process on the performance between semiconductor devices with different materials and different densities, optimizing the semiconductor structure design and the laser annealing process conditions, improving the performance and yield of semiconductor devices, and reducing the production cost.

[0043] In order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the following described accompanying drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0045] Figure 1 It is a schematic flow chart of a method for monitoring the performance of semiconductor devices provided in Embodiment 1 of the present application.

[0046] Figure 2 It is a schematic diagram of a test structure for monitoring the performance of semiconductor devices provided in Embodiment 1 of the present application Figure 1 .

[0047] Figure 3 It is a schematic diagram of a test structure for monitoring the performance of semiconductor devices provided in Embodiment 1 of the present application in the polysilicon lateral setting process Figure 2 .

[0048] Figure 4 Schematic diagram of a test structure for monitoring the performance of semiconductor devices provided in Embodiment 1 of the present application in the polysilicon vertical setting process Figure 3 。

[0049] Figure 5 Relationship curve diagram of an application scenario provided in Embodiment 1 of the present application

[0050] Figure 6 Relationship curve diagram of another application scenario provided in Embodiment 1 of the present application

[0051] Figure 7 Schematic diagram of a test structure for monitoring the performance of semiconductor devices provided in Embodiment 2 of the present application Detailed implementation manners

[0052] The foregoing and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0053] The present application evaluates the influence of the laser annealing process on the performance between semiconductor devices of different materials and different densities by measuring the electrical parameters of the second structure corresponding to different first structure densities after laser annealing; and improves the performance and yield of semiconductor devices and reduces production costs by improving the semiconductor structure design and laser annealing process conditions.

[0054] The following will elaborate on each embodiment of the present application with reference to the drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present application, many technical details are proposed for the better understanding of the present application by readers. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0055] The laser annealing process of the present application is carried out in the front part of chip production. The semiconductor structures on the silicon wafer usually only include AA (active area), poly (polysilicon) and MOS devices; however, the electrical parameters of the second structure measured in the present application are carried out after all the structures on the chip are grown. For the convenience of describing the technical solution, the semiconductor substrate (silicon wafer) and each metal layer, metal connection, pad, etc. on the substrate in the embodiments of the present application are not shown.

[0056] Embodiment 1

[0057] Figure 1The following shows a method for monitoring the performance of semiconductor devices provided in Embodiment 1 of the present application.

[0058] As Figure 1 shown, a method for monitoring the performance of semiconductor devices includes:

[0059] Forming at least two test units including semiconductor structures on a silicon wafer, including at least one first test unit having a first structure cluster and at least one second test unit having a second structure;

[0060] Wherein, the area ratio of the first structure cluster in the first test unit is used to characterize the first structure density;

[0061] Performing a laser annealing process on the silicon wafer and testing the electrical parameters of the second structure;

[0062] Based on the electrical parameters of the second structure measured under different first structure densities, evaluating the influence of the laser annealing process on the performance of the second structure.

[0063] By the measured electrical parameters of the second structure, quantitatively evaluating the influence between different semiconductor structures on the silicon wafer in the laser annealing process, that is, the influence of the first test unit with the first structure density on the second structure in the second test unit; it can be used to optimize the semiconductor structure design and the laser annealing process conditions, improve the performance and yield of semiconductor devices, and reduce production costs.

[0064] In some specific embodiments, the first structure cluster is at least one of an active region cluster and a polysilicon cluster; the second structure is at least one of an active region, polysilicon, or MOS transistor; generally, the influence of MOS devices on themselves or other devices is not considered. Therefore, the first test unit does not include MOS devices. The present application does not make specific limitations on the type of semiconductor devices, and the first structure cluster in the first test unit and the second structure in the second test unit can be designed based on the requirements of specific application scenarios.

[0065] In some specific embodiments, multiple first structures are centrally distributed in the first test unit to form a first structure cluster; the first test unit has a certain semiconductor structure density, and the semiconductor structures in the first test unit are usually relatively concentratedly distributed, which can be regarded as a cluster, and the density of this cluster can be changed according to test requirements, and the density of the cluster is used as a variable for testing.

[0066] In some specific embodiments, when there are multiple types of first test units, the first structure clusters of each first test unit are different; similarly, when there are multiple types of second test units, the second structures of each second test unit are different. The "different" mentioned here can be caused by any variable difference, and the variables include the material, size, setting direction, distance, density, etc. of the semiconductor structure.

[0067] In some specific embodiments, a plurality of second structures are provided in each second test unit, and the plurality of second structures are distributed around the first structure cluster in different forms; specifically, the second structures in the second test unit are scattered around the first test unit in different distribution forms, and the distribution forms of the second structures, such as the doping type, size, setting direction, direction or distance relative to the first structure cluster, etc., can all be used as a plurality of control variables.

[0068] In a specific application, when testing the influence of the first test unit on the second test unit, it can be to test the influence of AA clusters / poly clusters with different densities on AA / poly / MOS devices in a fixed form, that is, it can be a one-to-one or one-to-many relationship, or it can be to test the influence of AA clusters / poly clusters with different densities on AA / poly / MOS devices under different morphological distributions; at the same time, it can also be the influence of AA clusters and poly clusters with different densities on AA / poly / MOS devices in a fixed form, that is, it can be a many-to-one relationship, or a many-to-many relationship, or it can be the influence of AA clusters and poly clusters with different densities on AA / poly / MOS devices under different morphological distributions. This application does not make specific limitations and can be designed based on specific application scenarios.

[0069] In some specific embodiments, a laser annealing process is performed on the silicon wafer formed with the first test unit and the second test unit, and the electrical parameters of the second structure are tested; among them, the electrical parameters of the second structure include: testing the resistance value of the second structure; and / or testing the saturation current, saturation threshold voltage or turn-off current of the second structure. This application does not make specific limitations on the electrical parameters of the second structure and can be designed according to specific application scenarios; for example, when measuring the electrical parameters of the second structure based on different first structure densities:

[0070] 1) If the first structure density is AA density (the density of the active region) and the second structure is poly (polycrystalline silicon), then the resistance can be measured for the poly.

[0071] 2) If the first structure density is Poly density (the density of polycrystalline silicon) and the second structure is AA, then the resistance can be measured for the AA.

[0072] 3) If the first structure density is AA density and the second structure is a MOS device, then the resistance can be measured for the MOS device, or other electrical parameters of the MOS can be measured (connect the four terminals G / S / D / B of the MOS transistor, saturation current, saturation threshold voltage or turn-off current).

[0073] 4) If the first structure density is Poly density and the second structure is a MOS device, then the resistance of the MOS device can be measured, or other electrical parameters of the MOS can be measured (connect the four terminals G / S / D / B of the MOS transistor, and measure the saturation current, saturation threshold voltage, or off-current).

[0074] In some specific embodiments, based on the electrical parameters of the second structure measured under different first structure densities, the influence of the laser annealing process on the performance of the second structure is evaluated, including: plotting a relationship curve between different first structure densities and the electrical parameters of the second structure according to the measured electrical parameters, and determining the required laser annealing process window according to the relationship curve. The first test unit has a certain first structure density, while the second structures in the second test unit are relatively scattered and are scattered around the first test unit. The distribution pattern of the semiconductor structure (device structure doping type, size, distance, setting direction, etc.) can be used as multiple control variables. After measuring the electrical parameters of the second structures with different control variables under a certain first structure density and plotting the relationship curve, the design adjustable range of this control variable under the current first structure density can be determined according to the relationship curve.

[0075] The first test unit is a semiconductor structure cluster, and the first structure density of this cluster can be changed according to the test requirements. The density of the cluster is used as a variable in the test. Therefore, in some specific applications, based on the electrical parameters of the second structure measured under different first structure densities, the influence of the laser annealing process on the performance of the second structure is evaluated, including:

[0076] Obtaining the electrical parameters of multiple second structures to obtain an electrical parameter set;

[0077] Based on the electrical parameter sets corresponding to different first structure densities, plotting relationship curves between multiple first structure densities and the electrical parameters of the second structure, and determining the required laser annealing process window according to the multiple relationship curves.

[0078] Specifically, determining the required laser annealing process window according to the multiple relationship curves includes: determining the fluctuation range of the electrical parameters of the second structure according to the relationship curve, and judging whether the fluctuation range is within a preset threshold; if the fluctuation range is within the preset threshold, the first structure density corresponding to this relationship curve is the required laser annealing process window.

[0079] Figure 2 The figure shows a schematic diagram of a test structure for monitoring the performance of semiconductor devices provided in Embodiment 1 of the present application Figure 1 , and this test structure can be used to implement the method for monitoring the performance of semiconductor devices described above.

[0080] Such as Figure 2As shown, a test structure for monitoring the performance of semiconductor devices includes:

[0081] A silicon wafer ( Figure 2 not shown in the figure);

[0082] At least two types of test units grown on the silicon wafer, including at least one first test unit having a first structure cluster ( Figure 2 the AA cluster in it) and at least one second test unit having a second structure ( Figure 2 the poly in it);

[0083] A test circuit ( Figure 2 not shown in the figure), electrically connected to the second structure ( Figure 2 the poly in it), for measuring the electrical parameters of the second structure.

[0084] The design of this test structure can use the measured electrical parameters to quantitatively explore the influence of the first test unit on the second test unit in the laser annealing process after the laser annealing process is performed on the silicon wafer. It is simple, convenient and effective, and variable design can be carried out based on different application scenario requirements.

[0085] In this embodiment, as Figure 2 shown, the test structure is used to monitor the influence of a large area of AA (active area) on poly (polysilicon). Figure 2 In it, the first test unit is composed of multiple active areas, which are concentrated and distributed to form a first structure cluster in the first test unit, that is, an active area cluster. The outer frame area of the entire active area cluster is 200 microns * 200 microns, and the area of the inner frame part is 25 microns * 25 microns. The first structure density is the ratio of the actual active area in the active area cluster to the outer frame area. The second structure in the second test unit refers to poly, and multiple second structures can be set, and the multiple second structures are distributed relative to the first structure cluster in different distribution forms; among them, different forms include at least any one of the following: the doping type, size, setting direction, direction or distance relative to the first structure cluster of the second structure; in Figure 2 for the convenience of illustration and display, only one poly is drawn for illustration, and the variable meanings marked by space (distance relative to the first structure cluster), width (width of the second structure), and length (length of the second structure) are marked.

[0086] Based on Figure 2 the shown test structure, the DOE for each variable (structural data, distribution form, etc.) in the test structure is shown in Table 1 below to obtain a test structure that meets the requirements of the test scenario. The data units in the width, length, and space columns in Table 1 are microns.

[0087]

[0088] Table 1

[0089] Among them, implantType is the doping type, width is the width of the polysilicon, length is the length of the polysilicon, poly Orientation represents the orientation of the polysilicon (the polysilicon is arranged horizontally h or vertically v), space is the distance between the polysilicon and the active region, location is the position of the polysilicon relative to the active region, #of DOE refers to the number of designed polysilicons, and AA density is the active region density.

[0090] Figure 3 、 Figure 4 The following figures respectively show the schematic diagrams of a test structure for monitoring the performance of semiconductor devices provided in Embodiment 1 of the present application in the polysilicon horizontal setting process Figure 2 and in the polysilicon vertical setting process Figure 3 , Figure 3 、 Figure 4 Both are based on Figure 2 the test structure, and new test structures are formed after different DOE designs in Table 1 above. Figure 3 、 Figure 4 Both are mainly used to illustrate the poly distribution designed for different test structures. The connection of the metal layer is not shown in the figure, nor is the pad and its connection situation illustrated.

[0091] Each polysilicon is tested separately, and the measurement results are plotted as a relationship curve.

[0092] For example, when testing the influence of active regions AA with different densities on a polysilicon poly with a fixed shape, the abscissa is set as the active region density, and the ordinate is set as the polysilicon resistance value, and a relationship curve is plotted;

[0093] When testing the influence of active regions AA with different densities on polysilicon polys with different shapes, the abscissa is set as space, and the ordinate is set as multiple relationship curves of resistance, and each relationship curve corresponds to an active region density.

[0094] The first structure cluster in the embodiment of the present application is an active region cluster or a polysilicon cluster; the second structure is an active region, a polysilicon, or a MOS transistor, and the test circuit is electrically connected to the second structure; during the test, the two-terminal method or the four-terminal method, that is, the KLV test, is used to test the resistance value of the polysilicon. Since the measured resistance value of the polysilicon is small, the KLV test is generally used, and the resistance value measurement is more accurate.

[0095] Figure 5 、 Figure 6 They are respectively the relationship curves obtained by the present application in different application scenarios.

[0096] As shown Figure 5 in the figure, the data of the resistance Rs varying with Space under three AA density (active region structure density) conditions are shown. The change in the resistance Rs is not significant, indicating that the current process and density conditions have little impact on the surrounding poly, and the designed adjustable range is relatively large.

[0097] As shown Figure 6 in the figure, the data of the resistance Rs varying with Space under three AA density (active region density) conditions are shown. Among them, 20% has little impact on Rs, 50% / 90% has a relatively large change in Rs, and the impact of 90% is even greater. This indicates that under the current process, high-density AA has a certain impact on the surrounding poly, while low-density AA has little impact on the surrounding poly. Therefore, when designing, it is necessary to consider the design range of AA density (active region density) and the usage limitations of poly within a certain distance. For example, some important devices need to be far away from high-density AA (active region structure density) areas to maintain stable performance. In the subsequent Example 1 of this application, different result charts such as relationship curve graphs can be used to determine whether the impact of the active region density adopted during laser annealing on the performance of polysilicon is acceptable, thereby guiding the subsequent design of the active region density and semiconductor structure.

[0098] Example 2

[0099] Example 2 of this application monitors the impact of a large area of AA (active region) on the MOS transistor structure.

[0100] As shown Figure 7 in the figure, a test structure for monitoring the performance of semiconductor devices includes:

[0101] A silicon wafer ( Figure 7 not shown in the figure);

[0102] At least two test units grown on the silicon wafer, including at least one first test unit having a first structure cluster ( Figure 7 the AA cluster in it) and at least one second test unit having a second structure ( Figure 7 the MOS transistor in it);

[0103] A test circuit ( Figure 7 not shown in the figure), electrically connected to the second structure ( Figure 7 the MOS transistor in it), for measuring the electrical parameters of the second structure.

[0104] The first structures are concentrated in the first test unit to form a first structure cluster; there are multiple second structures in each second test unit, and the multiple second structures are distributed relative to the first structure cluster in different distribution patterns.

[0105] In this embodiment, as Figure 6 shown, the test structure is for the influence of the AA (active region) cluster on MOS devices. Figure 7 In, the first test unit is composed of multiple active regions, and is concentrated in the first test unit to form a first structure cluster, that is, an active region cluster. The outer frame area of the entire active region cluster is 200 microns * 200 microns, and the area of the inner frame part is 25 microns * 25 microns. The first structure density is the ratio of the actual active region area in the active region cluster to the outer frame area. The second structure in the second test unit refers to MOS transistors, and there can be multiple of them. The multiple second structures are distributed relative to the first structure cluster in different distribution patterns; among them, different patterns at least include any one of the following: the doping type, size, setting direction, direction or distance relative to the first structure cluster of the second structure; in Figure 7 for the convenience of illustration and display, only one MOS transistor is drawn for illustration, and the variable meanings marked by space (distance relative to the first structure cluster), gl (channel length of the second structure), and gw (channel width of the second structure) are indicated.

[0106] Based on Figure 7 the shown test structure, the DOE for each variable (structure data, distribution pattern, etc.) in the test structure is as shown in Table 2 below to obtain the test structure required to meet the test scenario. The data units in the columns of gl, gw, and space in Table 1 are microns.

[0107]

[0108] Table 2

[0109] Among them, implantType is the doping type, gL is the channel length of the MOS transistor structure, gW is the channel width of the MOS transistor structure, MOS Orientation is that the polysilicon in the MOS transistor structure is arranged horizontally h or vertically v, space is the distance of the MOS transistor structure from the active region, location is the position of the MOS transistor structure relative to the active region, #of DOE refers to the number of designed MOS transistor structures, and AA density is the active region density.

[0110] In the embodiment of the present application, the first structure cluster is an active region cluster or a polysilicon cluster; the second structure is an active region, polysilicon or MOS transistor, and the test circuit is electrically connected to the second structure.

[0111] Specifically, the second structure in the embodiments of the present application is a MOS transistor. During testing, the test circuit is electrically connected to the gate, source, drain, and base of the MOS transistor respectively, and the resistance of the MOS transistor can be measured, and the electrical parameters of the MOS transistor can also be measured.

[0112] In the subsequent embodiments 2 of the present application, based on the specific data of DOE and the measured electrical parameters, a relationship curve graph in a specific application scenario can also be obtained, and whether the influence of the active region density adopted during laser annealing on the structural performance of the MOS transistor is acceptable can be determined through result charts such as different relationship curve graphs, thereby guiding the subsequent design of the active region density and semiconductor structure.

[0113] Embodiment 3

[0114] A test system for monitoring the influence of laser annealing on the performance of semiconductor devices includes multiple test structures for monitoring the performance of semiconductor devices;

[0115] Specifically, at least two types of test units are grown on a silicon wafer, including at least one first test unit having a first structure cluster and at least one second test unit having a second structure;

[0116] A test circuit is electrically connected to the second structure for measuring the electrical parameters of the second structure.

[0117] The first structures are concentratedly distributed in the first test unit to form a first structure cluster; multiple second structures are provided in each second test unit, and the multiple second structures are distributed relative to the first structure cluster in different distribution forms.

[0118] Among them, the area ratio of the first structure cluster in the first test unit is used to characterize the first structure density, and the first test units in the multiple test structures correspond to different first structure densities.

[0119] The present application evaluates the influence of the laser annealing process on the performance between semiconductor devices of different materials and different densities by measuring the electrical parameters of the second structure corresponding to different first structure densities after laser annealing; and improves the performance and yield of semiconductor devices and reduces production costs by improving the semiconductor structure design and laser annealing process conditions.

[0120] Some commonly used English nouns or letters adopted by the present invention for the convenience of clear description are only used for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.

[0121] It should also be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

Claims

1. A method for monitoring the performance of a semiconductor device, characterized in that, Comprising: Forming at least two test units including semiconductor structures on a silicon wafer, including at least one first test unit having a first structure cluster and at least one second test unit having a second structure; wherein, a plurality of the first structures are centrally distributed in the first test unit to form the first structure cluster; the area ratio of the first structure cluster in the first test unit is used to characterize the first structure density; Performing a laser annealing process on the silicon wafer and testing electrical parameters of the second structure; Evaluating the influence of the laser annealing process on the performance of the second structure based on the electrical parameters of the second structure measured under different first structure densities.

2. The method for monitoring the performance of a semiconductor device according to claim 1, characterized in that, The first structure cluster is at least one of an active region cluster, a polysilicon cluster, etc.; The second structure is at least one of an active region, polysilicon, or a MOS transistor.

3. A method for monitoring the performance of a semiconductor device according to claim 1, wherein, When there are multiple types of the first test units, the first structure clusters of each type of the first test unit are different.

4. A method for monitoring the performance of a semiconductor device according to claim 1, characterized in that, When there are multiple types of the second test units, the second structures of each type of the second test unit are different; There are multiple second structures in each type of the second test unit, and the multiple second structures are distributed relative to the first structure cluster in different forms; Among them, different forms at least include any one of the following: the doping type, size, setting direction, direction or distance relative to the first structure cluster of the second structure.

5. A method for monitoring the performance of a semiconductor device according to claim 2, characterized in that, Testing the electrical parameters of the second structure includes: Testing the resistance value of the second structure; and / or Testing the saturation current, saturation threshold voltage or off-current of the second structure.

6. A method for monitoring the performance of a semiconductor device according to claim 1, characterized in that, The evaluating the influence of the laser annealing process on the performance of the second structure based on the electrical parameters of the second structure measured under different first structure densities includes: Drawing a relationship curve between different first structure densities and the electrical parameters of the second structure according to the measured electrical parameters, and determining the required laser annealing process window according to the relationship curve.

7. A method for monitoring the performance of a semiconductor device according to claim 4, wherein, The evaluating the influence of the laser annealing process on the performance of the second structure based on the electrical parameters of the second structure measured under different first structure densities includes: Obtaining the electrical parameters of multiple second structures to obtain an electrical parameter set; Based on the electrical parameter sets corresponding to different first structure densities, drawing relationship curves between multiple first structure densities and the electrical parameters of the second structure, and determining the required laser annealing process window according to the multiple relationship curves.

8. A method for monitoring the performance of a semiconductor device according to claim 7, characterized in that, The determining the required laser annealing process window according to the multiple relationship curves includes: Determining the fluctuation range of the electrical parameters of the second structure according to the relationship curve, and determining whether the fluctuation range is within a preset threshold; if the fluctuation range is within the preset threshold, the first structure density corresponding to the relationship curve is the required laser annealing process window.

9. A test structure for monitoring the performance of a semiconductor device, which is used to implement the method for monitoring the performance of a semiconductor device according to any one of claims 1-8, characterized in that, Comprising: A silicon wafer; At least two test units are grown on the silicon wafer, including at least one first test unit having a first structural cluster and at least one second test unit having a second structure; wherein, a plurality of the first structures are centrally distributed in the first test unit to form the first structural cluster; the area ratio of the first structural cluster in the first test unit is used to characterize the first structure density; A test circuit is electrically connected to the second structure and is used to measure the electrical parameters of the second structure.

10. A test structure for monitoring the performance of a semiconductor device according to claim 9, characterized in that, A plurality of second structures are provided in each of the second test units, and the plurality of second structures are distributed relative to the first structural cluster in different distribution forms; Among them, different forms at least include any one of the following: the doping type, size, setting direction, direction or distance relative to the first structural cluster of the second structure.

11. A test structure for monitoring the performance of a semiconductor device according to claim 10, wherein, The first structural cluster is an active region cluster or a polysilicon cluster; The second structure is an active region, polysilicon or MOS transistor, and the test circuit is electrically connected to the second structure; or, the second structure is a MOS transistor, and the test circuit is electrically connected to the gate, source, drain and base of the MOS transistor respectively.

12. A test system for monitoring the influence of laser annealing on the performance of semiconductor devices, characterized in that, It includes a plurality of test structures as described in claim 9, wherein the area ratio of the first structural cluster in the first test unit is used to characterize the first structure density, and the first test units in the plurality of test structures correspond to different first structure densities.

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