Trench device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a trench device and a preparation method thereof. The preparation method comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, a first oxide layer, a hard mask layer and a dielectric layer which are stacked in sequence; forming a first photoresist layer on one side, deviating from the hard mask layer, of the dielectric layer; performing patterning etching on a key device region of the semiconductor structure based on the first photoresist layer so as to form at least one first window which penetrates through the hard mask layer and the dielectric layer and exposes the first oxide layer in the key device region; removing the first photoresist layer and cleaning residues of the first window; and forming a second photoresist layer stacked on the dielectric layer, wherein the first window is filled with the second photoresist layer. Impurities and initial defects on the key device region can be eliminated to a certain extent, so that the conical defect of the trench isolation structure in the key device region is avoided, the applicability is wide, and the cost is low.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a trench device and a method for preparing the same. Background Art

[0002] Cone defects (also known as apex defects, cone defects) are common in trench isolation structures. They are caused by impurities on the surface of the material during the etching process that partially hinder the etching process. Initially, point-shaped or smaller cone defects are formed in the impurity area. When the subsequent layers are etched, the material accumulates and expands around the initial defect to form a larger defect structure. The above-mentioned cone defects can only be detected after etching, and the current process flow cannot remove the expanded cone defects, resulting in chip short-circuit failures or a series of reliability problems. Especially when the defect is located in the high-voltage device area, it will greatly reduce the chip yield. Summary of the invention

[0003] In order to solve the above technical problems, the present application discloses, on one hand, a method for preparing a trench device, which comprises:

[0004] A semiconductor structure is provided, wherein the semiconductor structure comprises a substrate, a first oxide layer, a hard mask layer and a dielectric layer which are stacked in sequence;

[0005] forming a first photoresist layer on a side of the dielectric layer away from the hard mask layer;

[0006] Performing patterned etching on a key device region of the semiconductor structure based on the first photoresist layer to form at least one first window penetrating the hard mask layer and the dielectric layer in the key device region and exposing the first oxide layer;

[0007] removing the first photoresist layer and cleaning the first window for residues;

[0008] A second photoresist layer is formed on the dielectric layer, and the second photoresist layer fills the first window.

[0009] In an exemplary embodiment, after forming the second photoresist layer stacked on the dielectric layer, the preparation method further includes:

[0010] Performing patterned etching on a non-critical device region of the semiconductor structure based on the second photoresist layer to form at least one second window penetrating the hard mask layer and the dielectric layer and exposing the first oxide layer;

[0011] removing the second photoresist layer;

[0012] The substrate is etched based on the first window and the second window to form a first groove corresponding to the first window and a second groove corresponding to the second window.

[0013] In an exemplary embodiment, before etching the substrate based on the first window and the second window to form a first groove corresponding to the first window and a second groove corresponding to the second window, the preparation method further includes:

[0014] The second window is cleaned of residues.

[0015] In an exemplary embodiment, providing a semiconductor structure includes:

[0016] providing a substrate;

[0017] forming the first oxide layer on the substrate;

[0018] Depositing the hard mask layer on a side of the first oxide layer facing away from the substrate;

[0019] The dielectric layer is deposited on a side of the hard mask layer away from the first oxide layer.

[0020] In an exemplary embodiment, the dielectric layer includes an anti-reflection layer and a second oxide layer sequentially stacked on the hard mask layer.

[0021] In an exemplary embodiment, the anti-reflection layer is made of an inorganic material.

[0022] In an exemplary embodiment, the material of the anti-reflection layer includes one or more of silicon oxynitride, magnesium fluoride, aluminum oxide, titanium dioxide, zirconium dioxide, silicon nitride, and zinc oxide.

[0023] In an exemplary embodiment, an acid etching solution is used in the process of cleaning the residue, and the first oxide layer is chemically inert to the acid etching solution.

[0024] In an exemplary embodiment, the acid etching solution includes phosphoric acid.

[0025] On the other hand, the present application further discloses a trench device, which is prepared based on the above-mentioned preparation method.

[0026] In an exemplary embodiment, the trench device includes a substrate, a first oxide layer, a hard mask layer, and a dielectric layer, which are sequentially stacked, as well as a first window, a second window, a first trench, and a second trench;

[0027] The first window is located in the key device region of the substrate and penetrates the first oxide layer, the hard mask layer and the dielectric layer, and the second window is located in the non-key device region of the substrate and penetrates the first oxide layer, the hard mask layer and the dielectric layer;

[0028] The first groove is located in a region corresponding to the first window and extends into the substrate, and the second groove is located in a region corresponding to the second window and extends into the substrate.

[0029] The present application further discloses an integrated circuit in another aspect, wherein the integrated circuit includes the above-mentioned trench device.

[0030] The present application further discloses an electronic device in another aspect, which includes the above-mentioned trench device.

[0031] Based on the above technical solution, this application has the following beneficial effects:

[0032] The technical solution of the present application forms a first photoresist layer on the side of the dielectric layer away from the hard mask layer, and performs patterned etching on the key device area of ​​the semiconductor structure based on the first photoresist layer to form at least one first window penetrating the hard mask layer and the dielectric layer in the key device area and exposing the first oxide layer, thereby realizing mask patterning of the key device area, then removing the first photoresist layer and cleaning the residue in the first window, and then filling the first window with the second photoresist layer, thereby eliminating impurities and initial defects in the key device area to a certain extent, and realizing filling protection of the corresponding area in subsequent processes, avoiding conical defects of the trench isolation structure in the key device area, ensuring device performance and product yield, and in this method, only the first photoresist layer needs to be added as a mask, which is suitable for various device processes, has wide applicability and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 A schematic diagram of a process for preparing a trench device exemplified in the present application;

[0035] Figure 2-9 A schematic cross-sectional view of a trench device during a preparation process is provided for an embodiment of the present application;

[0036] Fig.10 A schematic cross-sectional view of a trench device during a preparation process provided as a comparative example of the present application;

[0037] The following is a supplementary description of the attached drawings:

[0038] 10-impurity particles, 20-initial defects, 30-conical defects, 40-antireflective coating, 50-photoresist layer, 100-substrate, 101-key device area, 210-first oxide layer, 220-hard mask layer, 230-dielectric layer, 231-antireflective layer, 232-second oxide layer, 310-first photoresist layer, 320-second photoresist layer, 410-first window, 420-second window, 430-first groove, 440-second groove. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0040] The term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present application. In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "top", "bottom", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may include one or more of the features explicitly or implicitly. Moreover, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here.

[0041] When a numerical range is disclosed herein, the above range is deemed to be continuous and includes the minimum and maximum values ​​of the range, as well as each value between such minimum and maximum values. Further, when a range refers to an integer, each integer between the minimum and maximum values ​​of the range is included. In addition, when multiple ranges are provided to describe features or characteristics, the ranges can be merged. In other words, unless otherwise indicated, all ranges disclosed herein should be understood to include any and all sub-ranges included therein. For example, a specified range from "1 to 10" should be deemed to include any and all sub-ranges between a minimum of 1 and a maximum of 10. Exemplary sub-ranges of ranges 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0042] The term "layer" as used in this application refers to a portion of a material including an area having a certain thickness. A layer may extend over the entire lower or upper structure, or may extend over a localized area of ​​the lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically and / or along a profiled surface. A layer may include multiple layers. For example, the dielectric layer 230 may include multiple sublayers, etc., and may have the same or different materials.

[0043] It should be understood that the definitions of “consistent”, “vertical”, etc. used in this application refer to basic consistency or basic verticality that satisfies process errors, and do not refer to absolute consistency or absolute verticality in the physical sense.

[0044] It should be understood that the “plane” used in the present application, such as the “first plane”, “second plane”, etc., refers to the XY plane of the base 100 or the substrate structure, etc., corresponding to the XY plane of the groove device, the “in-plane direction” refers to the direction parallel to the XY plane, and the “thickness direction”, “groove depth direction” or “longitudinal direction” refers to the Z direction relative to the XY plane.

[0045] In the current process, the generation of cone-shaped defects is mainly attributed to the presence of metal ions in the developer of photolithography coating, or the presence of impurities in the anti-reflective coating formed by organic solution coating. Therefore, the relevant technology reduces the cone-shaped defects by reducing the metal ion content of the developer, or uses filters with different pore sizes and different materials to filter out impurities in the organic solution to reduce impurities in the coating. However, the former method is costly and cannot be universally applied to different chip production processes and production lines. In the latter solution, even the best filter cannot completely filter out impurities, that is, it cannot completely remove the cone-shaped defects.

[0046] To solve at least one of the above problems, the following Figure 1-9The present invention introduces a method for preparing a trench device provided in an embodiment of the present invention. Figure 1 : is a flow chart of the preparation method of the trench device. This specification provides method operation steps such as the embodiments or flow charts, but based on routine or non-creative work, more or fewer operation steps may be included. The order of steps listed in the embodiments is only one way of executing the order of many steps, and does not represent the only execution order. When the preparation method is actually executed, it can be executed in the order of the methods shown in the embodiments or the drawings or in parallel. Reference Figure 1 , the preparation method may include S11-S15:

[0047] S11: Provide a semiconductor structure.

[0048] Specifically, refer to Figure 2 The semiconductor structure includes a substrate 100, a first oxide layer 210, a hard mask layer 220 and a dielectric layer 230 which are stacked in sequence.

[0049] Specifically, the substrate 100 is a semiconductor substrate capable of processing semiconductor devices. Exemplarily, the constituent material of the substrate 100 may be at least one of the following: silicon, a material containing silicon (such as III-V compound semiconductor materials of gallium arsenide (GaAs)), at least one of silicon on insulator (Silicon On Insulator, SOI), or other types of semiconductor materials capable of forming the substrate 100.

[0050] In some embodiments, the substrate 100 may include a substrate layer and an epitaxial layer, and the first oxide layer 210 is stacked on the epitaxial layer. The constituent material of the substrate layer may be at least one of the following: silicon, a material containing silicon (such as III-V compound semiconductor materials of gallium arsenide (GaAs)), at least one of silicon on insulator (SOI), or other types of semiconductor materials that can form the substrate 100. Optionally, the epitaxial layer can be formed specifically by an epitaxial growth process, and can be an epitaxial layer homogeneous with the substrate layer, such as being able to continue to grow along the lattice direction of the base layer to form an epitaxial layer, or a heterogeneous epitaxial layer. The specific process conditions such as the growth temperature can be the same as the existing process, or can be adaptively adjusted. Optionally, the epitaxial layer can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other methods. Exemplarily, the material of the epitaxial layer may include silicon, germanium, gallium arsenide, gallium phosphide (GaP), gallium nitride (GaN), etc., or may be other materials that can be epitaxially grown or deposited on a base layer and can be processed in the device region.

[0051] In a possible implementation manner, providing a semiconductor structure in S11 may include S111-S114:

[0052] S111: providing a substrate 100;

[0053] S112: forming a first oxide layer 210 on the substrate 100;

[0054] S113: depositing a hard mask layer 220 on a side of the first oxide layer 210 facing away from the substrate 100;

[0055] S114 : depositing a dielectric layer 230 on a side of the hard mask layer 220 away from the first oxide layer 210 .

[0056] Specifically, the first oxide layer 210 covers at least part of the surface of the substrate 100, can protect the substrate 100 material in the device preparation process and can serve as an insulating layer. Optionally, the first oxide layer 210 can be formed based on at least a deposition process, and the deposition process includes but is not limited to low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, high-density plasma chemical vapor deposition, atomic layer deposition, plasma enhanced atomic layer deposition, etc. Exemplarily, HDPCVD can be used to form the first oxide layer 210, and the material of the first oxide layer 210 includes but is not limited to silicon oxide. In some embodiments, the formation process of the first oxide layer 210 may include: forming a first initial oxide layer on a side surface of the substrate 100 based on a deposition process; performing chemical mechanical planarization on the first initial oxide layer until the required thickness is reached to form the first oxide layer 210. It should be noted that the first oxide layer 210 can also be formed by a thermal oxidation process or other processes, not limited to the above examples.

[0057] Specifically, the hard mask layer 220 covers at least the key device area 101 of the substrate 100 and the non-key device area 101 to be grooved, and the hard mask layer is used to form a patterned window for groove etching. Optionally, the material of the hard mask layer can specifically include at least one of silicon nitride, titanium nitride, silicon dioxide, etc., and can be deposited by chemical vapor deposition and other processes, such as plasma enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer deposition, plasma enhanced atomic layer deposition, or other types of chemical vapor deposition processes to form a hard mask. Exemplarily, the material of the hard mask layer is a SIN layer formed of silicon nitride.

[0058] Specifically, the dielectric layer 230 is stacked on the hard mask layer 220, and has an anti-reflective effect during the etching process to reduce the reflection of light during the photolithography process, thereby improving the resolution and accuracy of the photolithography. At the same time, the dielectric layer 230 can also play an isolation and protection role, further ensuring that the underlying material is protected from erosion by the etchant.

[0059] Specifically, the dielectric layer 230 is formed at least by a deposition process, such as the various vapor deposition methods exemplified above. In a possible implementation, the dielectric layer 230 includes an anti-reflection layer 231 and a second oxide layer 232 sequentially stacked on the hard mask layer 220. The second oxide layer 232 is similar to the formation method and material of the first oxide layer 210, and will not be described in detail here. The anti-reflection layer 231 is formed on the hard mask layer 220 by a deposition process, and cooperates with the second oxide layer 232 to achieve an anti-reflection effect.

[0060] In the existing process, reference Fig.10, usually only one anti-reflection coating 40 is formed on the hard mask layer 220 to achieve anti-reflection treatment during the photolithography process. The anti-reflection coating 40 is usually formed by a coating process, such as a preparation process of a bottom anti-reflection coating (BARC), and its forming materials usually include a cross-linkable resin, a thermal acid generator, a surfactant, and a solvent. However, impurities are inevitably present in the above-mentioned coating material, and filters with different pore sizes and different materials are required to filter out the impurities in the BARC. However, even if the optimal filter is used, the impurities cannot be completely filtered out, that is, a cone-shaped defect 30 is inevitably formed, and the filtering cost is high. The technical solution of this embodiment adopts a deposition method to form an anti-reflection layer 231 and a second oxide layer 232 to synergistically achieve the anti-reflection function, protection and isolation, and there is no need to use a coating solution to coat the anti-reflection coating 40, thereby avoiding impurities introduced into the overall device due to the formation of the coating, thereby avoiding the cone-shaped defect 30 caused by such impurities.

[0061] In a possible implementation manner, the anti-reflection layer is made of an inorganic material, which is beneficial to material deposition and ensures the reflection protection performance of the dielectric layer 230 .

[0062] In a possible implementation, the material of the anti-reflection layer 231 includes one or more of silicon oxynitride, magnesium fluoride, aluminum oxide, titanium dioxide, zirconium dioxide, silicon nitride, zinc oxide, or other inorganic materials that can serve as the anti-reflection layer 231. Exemplarily, the material of the anti-reflection layer 231 is silicon oxynitride (SION), and the material of the hard mask layer 220 is silicon nitride (SIN). Accordingly, the SION layer can not only serve as the anti-reflection layer 231, but also cooperate with SIN to improve the performance of the mask layer and ensure the patterning quality of the trench etching.

[0063] S12 : forming a first photoresist layer 310 on a side of the dielectric layer 230 away from the hard mask layer 220 .

[0064] Specifically, refer to Figure 3 and Figure 4The first photoresist layer 310 is used to form a patterned mask in the key device area 101. It can react chemically during the exposure process, so that the exposed area and the unexposed area show different solubility in the developer, thereby forming a desired pattern and transferring the preset pattern to the mask layer. Optionally, the first photoresist layer 310 can be formed on the dielectric layer 230 by a coating process, and pre-baked to remove the solvent in the coated photoresist solution, and the first photoresist layer 310 is formed after curing; then, the etching area of ​​the key device area 101 is exposed by exposure, and the exposed or unexposed area is dissolved by a developer to form a pattern, thereby realizing the pattern transfer of the key device area 101. In some cases, a post-baking process can also be used to further cure the photoresist layer to improve its stability and corrosion resistance. Optionally, the material of the first photoresist layer 310 may include one or more of polyimide (PI), novolac, acrylic, epoxy or silicon-based photoresist materials, or may be other materials that can be used for photolithography exposure and development.

[0065] S13 : pattern-etching the key device region 101 of the semiconductor structure based on the first photoresist layer 310 to form at least one first window 410 penetrating the hard mask layer 220 and the dielectric layer 230 in the key device region 101 and exposing the first oxide layer 210 .

[0066] Specifically, the first window 410 is used to form a first groove 430 in the key device region 101. After the first photoresist layer 310 is exposed and developed, the first photoresist layer 310 exposes the region corresponding to the first window 410, and then the dielectric layer 230 and the hard mask layer 220 are etched using the first oxide layer 210 as an etching stop layer to form the first window 410.

[0067] It is understandable that, since the metal ions or other impurities in the developer affect the etching of the dielectric layer 230 and the hard mask layer 220, after the first window 410 is formed, an initial defect 20 formed by the residue of the dielectric layer 230 or the hard mask layer 220 may exist in the exposed first oxide layer 210 region, such as Figure 4 As shown, the initial defect 20 will affect the subsequent etching of the first oxide layer 210 and the substrate. The first window 410 can be formed by dry etching or wet etching process, preferably dry etching process.

[0068] S14: removing the first photoresist layer 310 and cleaning the first window 410 for residues.

[0069] Specifically, the residue cleaning can be performed before or after the first photoresist layer 310 is removed to remove the impurities or initial defects 20 as described above, so as to prevent the initial defects 20 from expanding to form cone-shaped defects 30 during the subsequent trench etching process. The cone-shaped defects 30 are also called cone defects and are very common in the shallow trench isolation (STI) process. Figure 5 After the residue is cleaned, the initial defect 20 formed in the first window 410 is removed. In this way, the first photoresist layer 310 is added as a cone defect reduction mask (CDR mask) of the key device area 101 to facilitate the removal of impurities and defects during the patterning process of the key device area 101.

[0070] In a possible implementation, an acid etching solution is used during the cleaning of the residue, and the first oxide layer 210 is chemically inert to the acid etching solution, so as to selectively remove the initial defect 20 formed by the residue, and retain the first oxide layer 210 for subsequent trench etching. It can be understood that the main component of the initial defect 20 is the material of the hard mask layer 220, and accordingly, the initial defect 20 is chemically active to the acid etching solution and can be removed by corrosion.

[0071] In a possible implementation, the acid etching solution includes phosphoric acid, so as to remove the initial defect 20 including materials such as silicon nitride, thereby eliminating the cone-shaped defect 30 in the key device region 101, and significantly improving the yield loss caused by the defect.

[0072] S15 : forming a second photoresist layer 320 stacked on the dielectric layer 230 .

[0073] Specifically, refer to Figure 6 , the second photoresist layer 320 fills the first window 410 to avoid the introduction of impurities and structural damage in the subsequent etching process, and protect the cleanliness and structural integrity of the first window 410. More specifically, the second photoresist layer 320 also covers the key device area 101 and at least part of the non-key device area 101 for the subsequent pattern transfer of the non-key device area 101. The preparation method and the material used for the second photoresist layer 320 are similar to those of the aforementioned first photoresist layer 310, and are not described in detail here. The materials of the first photoresist layer 310 and the second photoresist layer 320 may be consistent or inconsistent, and may be set based on actual needs. Preferably, the second photoresist layer 320 may cover the active area (Active Area, AA) of the substrate 100.

[0074] Specifically, the critical device area 101 is an area where the device performance of the trench device is affected or greatly affected by the cone-shaped defect 30, such as a high-voltage device area or a high-resistance polysilicon (HR Poly) resistance area. The cone-shaped defect 30 in the critical device area 101 has a crucial impact on the product yield, which can lead to problems such as leakage and reduced breakdown voltage, resulting in yield loss.

[0075] The technical solution of the present application forms a first photoresist layer 310 on a side of the dielectric layer 230 away from the hard mask layer 220, and performs patterned etching on the key device region 101 of the semiconductor structure based on the first photoresist layer 310, so as to form at least one first window 410 penetrating the hard mask layer 220 and the dielectric layer 230 in the key device region 101 and exposing the first oxide layer 210, so as to achieve mask patterning of the key device region 101, then remove the first photoresist layer 310 and clean the residue of the first window 410, and then fill the first window 410 with the second photoresist layer 320, so as to eliminate impurities and initial defects 20 on the key device region 101 to a certain extent, and realize filling protection of the corresponding region in subsequent processes, avoid the cone-shaped defects 30 of the trench isolation structure in the key device region 101, and ensure device performance and product yield. In addition, in this method, only the first photoresist layer 310 needs to be added as a photomask, which is suitable for various device processes, has wide applicability and low cost.

[0076] Based on some or all of the above implementations, in a possible implementation, after S15, refer to Figure 7-9 , the preparation method further includes S21-S23:

[0077] S21: performing patterned etching on the non-critical device region 101 of the semiconductor structure based on the second photoresist layer 320 to form at least one second window 420 penetrating the hard mask layer 220 and the dielectric layer 230 and exposing the first oxide layer 210;

[0078] S22: removing the second photoresist layer 320;

[0079] S23 : performing substrate etching based on the first window 410 and the second window 420 to form a first groove 430 corresponding to the first window 410 and a second groove 440 corresponding to the second window 420 .

[0080] Specifically, the non-critical device area 101 refers to an area where the device performance is not affected or is less affected by the cone-shaped defect 30. For example, if the trench isolation structure is only used as an isolation area without other functions, the presence of a certain cone-shaped defect 30 will not excessively affect the performance and yield rate. The second photoresist layer 320 is used as an etching mask for the non-critical device area 101. After exposure and development, the second photoresist layer 320 exposes the area corresponding to the second window 420 in the non-critical device area 101, and then the first oxide layer 210 is used as an etching stop layer to etch the dielectric layer 230 and the hard mask layer 220 to form the second window 420, so as to realize the pattern transfer of the non-critical device area 101 for etching the second trench 440. Specifically, the etching of the second window 420 can adopt a dry etching process or a wet etching process, preferably a dry etching process. The first photoresist layer 310 and the second photoresist layer 320 are used as masks for the key device area 101 and the non-key device area 101, respectively, to decouple the pattern transfer of the two areas, remove the cone-shaped defects 30 in the key device area 101, reduce the scope of residue cleaning, reduce the complexity of the impurity removal process, and reduce film damage.

[0081] As mentioned above, the dielectric layer 230 can achieve anti-reflection performance, including an anti-reflection layer 231 and a second oxide layer 232. This structure is adopted to avoid the use of an anti-reflection coating 40 that needs to be coated, and can avoid defects caused by introducing impurities of the coating liquid into the key device area 101 and the non-key device area 101, so that the number of conical defects 30 in the non-key device area 101 is also greatly reduced, further optimizing the device performance.

[0082] Further, refer to Figure 8 and Fig. 9 In this embodiment, after forming the first window 410 and the second window 420, the second photoresist layer 320 is removed, and the trench etching based on the first window 410 and the second window 420 can be performed simultaneously without changing the original trench etching steps, thereby reducing the process modification cost. The first trench 430 and the second trench 440 are trench structures formed in the key device area 101 and the non-key device area 101, respectively, and are subsequently filled to form corresponding functional structures. In some embodiments, the first trench 430 and the second trench 440 are shallow trenches for forming shallow trench isolation (STI).

[0083] In a possible implementation, before S23, the preparation method further includes S31: cleaning the second window 420 for residues, where the residue cleaning is similar to the cleaning process in the aforementioned S14, and will not be described in detail here. By cleaning after the second window 420 is formed, the initial defects 20 in the non-critical device area 101 caused by the developer can be further removed, thereby improving the uniformity of the trench isolation structure of the entire device.

[0084] In order to better illustrate the technical effect of the technical solution of this application, the following Fig.10 The following is a preparation scheme for a comparative example. Specifically, the manufacturing method of the groove device provided in the comparative example includes the following steps: providing a semiconductor structure having a substrate 100, a first oxide layer 210, a hard mask layer and an anti-reflective coating 40 stacked in sequence; forming a photoresist layer 50 on the side of the anti-reflective coating 40 away from the hard mask layer 220; exposing and developing to expose the window area of ​​the device to be etched, cleaning to remove the anti-reflective coating 40 and etching the hard mask layer 220, and then performing groove etching to form a groove structure in the substrate 100. Fig.10 As shown, there are impurity particles 10 in the anti-reflection coating 40, and there are also impurity particles 10 remaining after the photoresist layer 50 is developed. After the anti-reflection coating 40 is removed, an initial defect 20 is formed at the impurity particles after the photoresist layer is developed. As the subsequent etching process proceeds, the defect becomes larger and larger due to material accumulation, gradually forming a larger cone-shaped defect 30, and the main components of the defect are the hard mask material and the substrate 100 material. Although the trench isolation structure formed subsequently in this comparative example can cover the cone-shaped defect 30, it will inevitably cause the performance of the key device area 101 to be reduced, resulting in yield loss.

[0085] The technical solution of the present application forms a first photoresist layer 310 on the side of the dielectric layer 230 away from the hard mask layer 220, and performs patterned etching on the key device region 101 of the semiconductor structure based on the first photoresist layer 310, so as to form at least one first window 410 penetrating the hard mask layer 220 and the dielectric layer 230 in the key device region 101 and exposing the first oxide layer 210, so as to realize mask patterning of the key device region 101, then remove the first photoresist layer 310 and clean the residue of the first window 410, and then fill the first window 410 with the second photoresist layer 320, so as to eliminate impurities and initial defects 20 on the key device region 101 to a certain extent, realize filling protection of the corresponding region in subsequent processes, avoid the conical defects 30 of the trench isolation structure in the key device region 101, ensure device performance and product yield, and in this method, only the first photoresist layer 310 needs to be added as a mask, which is suitable for various device processes, has wide applicability and low cost. Furthermore, by using the anti-reflection layer 231 and the second oxide layer 232 , it is possible to avoid impurity defects introduced by the anti-reflection coating 40 , thereby significantly reducing the cone-shaped defects 30 in the entire device area, thereby improving device performance and yield.

[0086] The embodiment of the present application also provides a trench device, which is prepared based on the above-mentioned preparation method.

[0087] In a possible implementation manner, the trench device specifically includes a substrate 100 , a first oxide layer 210 , a hard mask layer 220 , and a dielectric layer 230 , which are sequentially stacked, as well as a first window 410 , a second window 420 , a first trench 430 , and a second trench 440 .

[0088] The first window 410 is located in the key device region 101 of the substrate 100 and penetrates the first oxide layer 210 , the hard mask layer 220 and the dielectric layer 230 . The second window 420 is located in the non-key device region 101 of the substrate 100 and penetrates the first oxide layer 210 , the hard mask layer 220 and the dielectric layer 230 .

[0089] The first groove 430 is located in a region corresponding to the first window 410 and extends into the substrate 100 . The second groove 440 is located in a region corresponding to the second window 420 and extends into the substrate 100 .

[0090] The embodiment of the present application further provides an electronic device, which includes the above-mentioned trench device. Specifically, the electronic device includes the trench device and an electronic component connected to the above-mentioned trench device.

[0091] The electronic device of the embodiment of the present application can be selected from any electronic product or device such as a mobile phone, a personal digital assistant (PDA), a tablet computer (pad), a laptop computer, a game console, a television, a video compact disc (VCD), a digital video disc (DVD), a navigator, a camera, a camcorder, a voice recorder, an MP3, an MP4, a handheld game console (PlayStation Portable, PSP), etc., and can also be any intermediate product of the electronic device made of the above-mentioned groove device.

[0092] It should be noted that the above-mentioned sequence of the embodiments of the present application is for description only and does not represent the advantages and disadvantages of the embodiments. The above-mentioned specific embodiments of this specification are described. Other embodiments are within the scope of the attached claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0093] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0094] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0095] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A method for preparing a trench device, characterized in that: include: A semiconductor structure is provided, wherein the semiconductor structure comprises a substrate, a first oxide layer, a hard mask layer and a dielectric layer which are stacked in sequence; forming a first photoresist layer on a side of the dielectric layer away from the hard mask layer; Performing patterned etching on a key device region of the semiconductor structure based on the first photoresist layer to form at least one first window penetrating the hard mask layer and the dielectric layer in the key device region and exposing the first oxide layer; removing the first photoresist layer and cleaning the first window for residues; A second photoresist layer is formed on the dielectric layer, and the second photoresist layer fills the first window.

2. The preparation method according to claim 1, characterized in that: After forming the second photoresist layer stacked on the dielectric layer, the preparation method further includes: Performing patterned etching on a non-critical device region of the semiconductor structure based on the second photoresist layer to form at least one second window penetrating the hard mask layer and the dielectric layer and exposing the first oxide layer; removing the second photoresist layer; The substrate is etched based on the first window and the second window to form a first groove corresponding to the first window and a second groove corresponding to the second window.

3. The preparation method according to claim 2, characterized in that: Before etching the substrate based on the first window and the second window to form a first groove corresponding to the first window and a second groove corresponding to the second window, the preparation method further includes: The second window is cleaned of residues.

4. The preparation method according to claim 1, characterized in that: Providing a semiconductor structure includes: providing a substrate; forming the first oxide layer on the substrate; Depositing the hard mask layer on a side of the first oxide layer facing away from the substrate; The dielectric layer is deposited on a side of the hard mask layer away from the first oxide layer.

5. The preparation method according to any one of claims 1 to 4, characterized in that: The dielectric layer includes an anti-reflection layer and a second oxide layer which are sequentially stacked on the hard mask layer.

6. The preparation method according to claim 5, characterized in that: The anti-reflection layer is made of inorganic material.

7. The preparation method according to claim 5, characterized in that: The material of the anti-reflection layer includes one or more of silicon oxynitride, magnesium fluoride, aluminum oxide, titanium dioxide, zirconium dioxide, silicon nitride, and zinc oxide.

8. The preparation method according to any one of claims 1 to 4, characterized in that: An acid etching solution is used during the cleaning of the residue, and the first oxide layer is chemically inert to the acid etching solution.

9. The preparation method according to claim 8, characterized in that: The acid etching solution includes phosphoric acid.

10. A trench device, characterized in that: The trench device is manufactured by the manufacturing method according to any one of claims 1 to 9.

11. The trench device according to claim 10, characterized in that: The trench device comprises a substrate, a first oxide layer, a hard mask layer and a dielectric layer which are stacked in sequence, as well as a first window, a second window, a first trench and a second trench; The first window is located in the key device region of the substrate and penetrates the first oxide layer, the hard mask layer and the dielectric layer, and the second window is located in the non-key device region of the substrate and penetrates the first oxide layer, the hard mask layer and the dielectric layer; The first groove is located in a region corresponding to the first window and extends into the substrate, and the second groove is located in a region corresponding to the second window and extends into the substrate.

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