Manufacturing method of semiconductor device
During the manufacturing process of semiconductor devices, initial trenches are formed on the substrate and oxidized to form a sacrificial layer, and then the sacrificial layer is removed to form an isolation trench, the problem of sharp cone-shaped defects in shallow trench isolation structure is solved, and the electricality and reliability of the device are improved.
Patent Information
- Application Number
- CN202411957552.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-04-25
AI Technical Summary
Point-shaped defects may occur in shallow trench isolation structures, resulting in a decrease in electrical and reliability of semiconductor devices.
By forming a stacked liner oxide layer and hard mask layer on the substrate, the initial trench is formed, and the exposed substrate is oxidized to form a sacrificial layer, and then the sacrificial layer is continued to be etched and removed based on the initial trench to form an isolation trench.
Reduce or eliminate sharp cone-shaped defects in isolation trenches, and improve the electrical and reliability of semiconductor devices.
Smart Images
Figure CN119890135A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuit chip manufacturing process inspection, and in particular to a method for manufacturing a semiconductor device. Background Art
[0002] Shallow Trench Isolation (STI) is usually used in process technology below 0.25um. It forms a trench in the substrate after deposition, patterning, and etching the substrate using a silicon nitride mask, and fills the trench with deposited oxide. This thermally grown oxide passivates the surface of the substrate and can isolate the deposited oxide filled in the trench from the silicon material in the substrate. As an effective barrier layer, the shallow trench isolation structure can reduce or even avoid the generation of sidewall leakage current in semiconductor devices, while meeting the functional requirements of various semiconductor devices.
[0003] However, particles may be generated in other processes before the shallow trench (e.g., trenches with a depth range of 0.1μm to 0.5μm and an aspect ratio of 2:1 to 6:1) etching process and remain on the surface of the substrate, and particles may also be generated during the shallow trench etching process and fall on the substrate surface. As the etching process proceeds, the part of the substrate where particles remain will produce a cone-shaped defect, resulting in a decrease in the electrical properties and reliability of the semiconductor device finally manufactured. Summary of the invention
[0004] Based on this, it is necessary to provide a method for manufacturing a semiconductor device to reduce or even avoid the pointed cone-shaped defects in the shallow trench isolation structure, thereby improving the electrical properties and reliability of the semiconductor device.
[0005] The present application provides a method for manufacturing a semiconductor device, comprising:
[0006] Providing a substrate, on which a stacked pad oxide layer and a hard mask layer are formed;
[0007] Etching the hard mask layer, the pad oxide layer and the substrate to form an initial trench, wherein the initial trench penetrates the hard mask layer and the pad oxide layer and extends into the substrate;
[0008] Oxidizing the substrate exposed by the initial trench to form a sacrificial layer, so that the surface of the remaining substrate below the initial trench is lower than the surface of other parts of the substrate;
[0009] Removing a portion of the hard mask layer to expose a portion of the surface of the liner oxide layer close to a side of the initial trench;
[0010] The pad oxide layer and the substrate are continuously etched based on the initial trench and the sacrificial layer is removed to form an isolation trench in the substrate, wherein a surface of a portion of the substrate located below the isolation trench is lower than surfaces of other portions in the substrate.
[0011] In one embodiment, a first pointed cone portion is formed at the bottom of the initial trench, and the top of the first pointed cone portion is flush with the substrate surface on both sides of the initial trench;
[0012] In the process of oxidizing the substrate exposed by the initial groove to form a sacrificial layer, a side of the first pointed cone portion away from the substrate is also oxidized and becomes a part of the sacrificial layer;
[0013] In the process of continuing to etch the pad oxide layer and the substrate based on the initial groove and removing the sacrificial layer to form an isolation trench in the substrate, a second pointed cone portion is formed at the bottom of the isolation trench, and the orthographic projections of the first pointed cone portion and the second pointed cone portion toward the substrate surface at least partially overlap, and the top of the second pointed cone portion is lower than the substrate surface on both sides of the isolation trench.
[0014] In one embodiment, the thickness of the sacrificial layer is the same as the thickness of the pad oxide layer.
[0015] In one embodiment, the depth of the portion of the initial trench extending into the substrate ranges from 3% to 8% of the total thickness of the substrate.
[0016] In one of the embodiments, a back-etching process is used to remove part of the hard mask layer, so that a portion of the surface of the pad oxide layer close to the initial groove is exposed, and the orthographic projection of the remaining hard mask layer toward the substrate surface is spaced apart from the orthographic projection of the sacrificial layer toward the substrate surface.
[0017] In one embodiment, the process of providing a substrate on which a stacked pad oxide layer and a hard mask layer are formed further includes:
[0018] forming a patterned photoresist layer on the hard mask layer;
[0019] The process of etching the hard mask layer, the pad oxide layer and the substrate to form an initial trench includes:
[0020] Using the photoresist layer as a mask, etching the hard mask layer, the pad oxide layer and the substrate to form the initial trench;
[0021] After forming the initial trench, the method for manufacturing the semiconductor device further includes:
[0022] The photoresist layer is removed.
[0023] In one embodiment, a thermal oxidation growth process or an in-situ water vapor generation process is used to oxidize the substrate exposed by the initial trench to form a sacrificial layer.
[0024] In one embodiment, the material of the pad oxide layer and the sacrificial layer is the same, and the material of the hard mask layer is different from that of the pad oxide layer.
[0025] In one embodiment, the materials of the pad oxide layer and the sacrificial layer both include silicon oxide, and the material of the hard mask layer includes silicon nitride.
[0026] In one embodiment, after forming the isolation trench in the substrate, the method for manufacturing the semiconductor device further includes:
[0027] An insulating layer is filled in the isolation trench to form a shallow trench isolation structure including the insulating layer and the isolation trench.
[0028] In summary, the present application forms an initial groove by etching in the substrate, oxidizes the substrate exposed by the initial groove to form a sacrificial layer, and then removes the sacrificial layer based on the initial groove etching to form an isolation groove, thereby ensuring that the surface of the portion of the substrate located below the isolation groove is lower than the surface of other portions of the substrate, reducing or even eliminating the cone-shaped defects in the isolation groove, and helping to improve the electrical properties and reliability of the ultimately formed semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0030] Figure 1 It is a structural schematic diagram corresponding to a situation in which a sharp cone defect flush with the substrate surface exists in a shallow trench in a related art.
[0031] Figure 2 A flow chart of a method for manufacturing a semiconductor device provided in one of the embodiments of the present application.
[0032] Figure 3 A schematic structural diagram corresponding to the step of providing a substrate in a method for manufacturing a semiconductor device according to one embodiment of the present application, and forming a stacked liner oxide layer and a hard mask layer on the substrate.
[0033] Figure 4 A schematic structural diagram corresponding to the steps of etching a hard mask layer, a pad oxide layer and a substrate and forming an initial trench in a method for manufacturing a semiconductor device provided in one of the embodiments of the present application.
[0034] Figure 5 A schematic structural diagram corresponding to the step of oxidizing the substrate exposed by the initial trench and forming a sacrificial layer in a method for manufacturing a semiconductor device provided in one of the embodiments of the present application.
[0035] Figure 6 A schematic structural diagram corresponding to the step of removing a portion of the hard mask layer to expose one side of the pad oxide layer close to the initial trench in a method for manufacturing a semiconductor device provided in one of the embodiments of the present application.
[0036] Figure 7 A schematic structural diagram corresponding to the step of forming an isolation trench in a substrate in a method for manufacturing a semiconductor device according to one embodiment of the present application.
[0037] Figure 8 A structural schematic diagram corresponding to the step of filling an insulating layer in the isolation trench and forming a shallow trench isolation structure in a method for manufacturing a semiconductor device provided in one of the embodiments of the present application.
[0038] Among them, the description of the figure marks includes: 100-base; 101-shallow trench; 102-cone defect; 110-silicon oxide layer; 120-silicon nitride layer; 200-substrate; 201-initial trench; 201a-first cone portion; 202-isolation trench; 202a-second cone portion; 203-insulating layer; 204-shallow trench isolation structure; 210-pad oxide layer; 220-hard mask layer; 230-photoresist layer; 240-sacrificial layer. DETAILED DESCRIPTION
[0039] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0041] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0042] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0043] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0044] Figure 1 FIG. 1 is a schematic diagram of a structure corresponding to a case in which a sharp cone defect flush with the substrate surface exists in a shallow trench in a related art. Figure 1 , a silicon oxide layer 110 and a silicon nitride layer 120 are formed on the substrate 100, a shallow groove 101 is formed in the substrate 100, and the shallow groove 101 penetrates the silicon oxide layer 110 and the silicon nitride layer 120. Among them, since particles may be generated in other process steps before the shallow groove formation process and remain on the surface of the substrate 100 or other film layers, and particles may also be generated during the shallow groove etching process. Therefore, as the etching process proceeds, the etching rate of the part of the substrate 100 where particles remain is slow, and a sharp cone defect 102 is caused in the shallow groove 101, thereby causing the electrical properties and reliability of the finally manufactured semiconductor device to decrease.
[0045] Generally, the number of particles in each step of the shallow groove manufacturing process is strictly controlled to reduce the size of the cone defect or eliminate the cone defect. However, this method has strict requirements on the process equipment and shortens the cleaning and maintenance cycle of the process equipment of some process, increasing production costs and seriously affecting production efficiency.
[0046] Based on this, it is necessary to provide a method for manufacturing a semiconductor device to reduce or even avoid the pointed cone defects in the shallow trench isolation structure, thereby improving the electrical properties and reliability of the semiconductor device.
[0047] Figure 2 A flowchart of a method for manufacturing a semiconductor device provided in one embodiment of the present application. Figure 2 One embodiment of the present application provides a method for manufacturing a semiconductor device, including the following steps S01 to S05.
[0048] Step S01: providing a substrate, on which a stacked pad oxide layer and a hard mask layer are formed.
[0049] Step S02: etching the hard mask layer, the pad oxide layer and the substrate to form an initial trench, wherein the initial trench penetrates the hard mask layer and the pad oxide layer and extends into the substrate.
[0050] Step S03: oxidizing the substrate exposed by the initial trench to form a sacrificial layer, so that the surface of the remaining substrate below the initial trench is lower than the surface of other parts of the substrate.
[0051] It should be noted that by oxidizing the substrate exposed by the initial trench into a sacrificial layer, the surface flatness of the substrate at the bottom of the initial trench can be improved, thereby reducing or eliminating the probability of cone-shaped defects in the subsequently formed isolation trenches.
[0052] Step S04: removing a portion of the hard mask layer to expose a portion of the surface of the pad oxide layer close to one side of the initial trench.
[0053] It should be noted that by forming a sacrificial layer on the substrate in the initial trench and removing it, it can be ensured that the remaining substrate at the bottom of the initial trench is lower than the surface of the substrate on both sides of the initial trench, thereby reducing or eliminating the probability of cone-shaped defects in the subsequently formed isolation trench.
[0054] Step S05: Continue etching the pad oxide layer and the substrate based on the initial trench and remove the sacrificial layer to form an isolation trench in the substrate, and the surface of the portion of the substrate located below the isolation trench is lower than the surface of other portions in the substrate.
[0055] The method for manufacturing a semiconductor device as described above forms an initial groove by etching in a substrate, oxidizes the substrate exposed by the initial groove to form a sacrificial layer, and then removes the sacrificial layer based on the initial groove etching to form an isolation groove, thereby ensuring that the surface of the portion of the substrate located below the isolation groove is lower than the surface of other portions of the substrate, reducing or even eliminating the pointed cone-shaped defects in the isolation groove, and helping to improve the electrical properties and reliability of the ultimately formed semiconductor device.
[0056] Figures 3 to 8 This is a schematic diagram of the structures corresponding to each step in the method for manufacturing a semiconductor device provided in one embodiment of the present application. Figures 3 to 8 The method for manufacturing the semiconductor device provided by the present application is described in detail.
[0057] First, see Figure 3 , perform step S01, provide a substrate 200, and a stacked pad oxide layer 210 (Pad Oxide) and a hard mask layer 220 (Hard Mask) are formed on the substrate 200. Optionally, the material of the substrate 200 includes silicon material, the material of the pad oxide layer 210 includes silicon oxide, and the material of the hard mask layer 220 includes silicon nitride.
[0058] Continue reading Figure 3 In one embodiment, after forming a pad oxide layer 210 and a hard mask layer 220 on a substrate 200, the method for manufacturing a semiconductor device further includes: forming a patterned photoresist layer 230 on the hard mask layer 220 to serve as a mask for the next etching process to facilitate the smooth progress of subsequent process steps.
[0059] Next, see Figure 4, step S02 is performed to etch the hard mask layer 220, the pad oxide layer 210 and the substrate 200 to form an initial trench 201, wherein the initial trench 201 penetrates the hard mask layer 220 and the pad oxide layer 210 and extends into the substrate 200. Optionally, the depth D of the portion of the initial trench 201 extending into the substrate 200 is in the range of 3% to 8% of the total thickness H of the substrate 200. Preferably, the depth of the portion of the initial trench 201 extending into the substrate 200 is 5% of the total thickness of the substrate 200.
[0060] Combination Figure 3 and Figure 4 In one embodiment, when a patterned photoresist layer 230 is formed on the hard mask layer 220, the process of forming the initial trench 201 specifically includes: etching the hard mask layer 220, the pad oxide layer 210 and the substrate 200 using the photoresist layer 230 as a mask to form the initial trench 201. Accordingly, after the initial trench 201 is formed, the method for manufacturing a semiconductor device further includes: removing the photoresist layer 230. Optionally, the initial trench 201 is formed by etching using a dry etching process.
[0061] In one embodiment, the photoresist layer can be removed by an ash process and a wet cleaning process. At the same time, the wet cleaning process of the photoresist layer can also remove particles generated during the etching process of the initial trench, as well as particles that already exist on the substrate before the etching process of the initial trench, thereby reducing or avoiding the occurrence of sharp cone defects in the subsequently formed isolation trenches due to residual particles.
[0062] Continue reading Figure 4 In one embodiment, when there are residual particles on the substrate 200, the etching speed of the substrate 200 below the particles is relatively slow, which will cause the first pointed cone portion 201a to be formed at the bottom of the initial groove 201, and the top of the first pointed cone portion 201a is flush with the surface of the substrate 200 on both sides of the initial groove 201. The manufacturing method of the semiconductor device provided in the present application can reduce the size of the subsequently formed pointed cone defect (the pointed cone defect is a defect formed based on the first pointed cone portion 201a in the subsequent process steps) through subsequent process steps, or eliminate the pointed cone defect that may be generated subsequently.
[0063] See also Figure 5 , step S03 is performed to oxidize the substrate 200 exposed by the initial trench 201 and form a sacrificial layer 240, so that the surface of the remaining substrate 200 below the initial trench 201 is lower than the surface of other parts of the substrate 200. Optionally, the thickness of the sacrificial layer 240 is the same as the thickness of the pad oxide layer 210. Optionally, the pad oxide layer 210 and the sacrificial layer 240 are made of the same material, both including silicon oxide.
[0064] In one embodiment, a thermal oxidation growth process or an in-situ steam generation process (ISSG process) is used to oxidize the substrate 200 exposed by the initial groove 201 and form a sacrificial layer 240. In other embodiments of the present application, other methods may also be used to oxidize the substrate exposed by the initial groove into a sacrificial layer, and the present application does not limit this.
[0065] See also Figure 4 and Figure 5 In the process of oxidizing the substrate 200 exposed by the initial groove 201 and forming the sacrificial layer 240 when the first conical portion 201a is formed at the bottom of the initial groove 201, the side of the first conical portion 201a away from the substrate 200 is also oxidized and becomes a part of the sacrificial layer 240, so as to ensure that the surface of the remaining substrate 200 below the initial groove 201 is lower than the surface of other parts of the substrate 200, thereby helping to reduce or eliminate the conical defects that may eventually be formed by removing the sacrificial layer.
[0066] See also Figure 6 , step S04 is performed to remove a portion of the hard mask layer 220 to expose a portion of the surface of the liner oxide layer 210 close to the initial trench 201 .
[0067] In one of the embodiments, a back etching process is used to remove a portion of the hard mask layer 220, so that a portion of the surface of the pad oxide layer 210 close to the initial groove 201 is exposed, and the orthographic projection of the remaining hard mask layer 220 toward the surface of the substrate 200 is spaced from the orthographic projection of the sacrificial layer 240 toward the surface of the substrate, so as to ensure that the sacrificial layer 240 can be completely removed in the next etching process.
[0068] Then, see Figure 7 , execute step S05, continue to etch the pad oxide layer 210 and the substrate 200 based on the initial trench 201 and remove the sacrificial layer 240 to form an isolation trench 202 in the substrate 200, and the surface of the portion of the substrate 200 located below the isolation trench 202 is lower than the surface of other portions of the substrate 200.
[0069] It should be emphasized that since the sacrificial layer 240 and the pad oxide layer 210 have the same thickness and the same material, during the etching process of the isolation trench 202, the etched portion of the pad oxide layer 210 and the sacrificial layer 240 will be removed at the same time, thereby ensuring the smooth progress of subsequent processes.
[0070] Continue reading Figure 7In the process of continuing to etch the pad oxide layer 210 and the substrate 200 based on the initial trench 201 and removing the sacrificial layer 240 to form an isolation trench 202 in the substrate 200, a second tapered portion 202a is formed at the bottom of the isolation trench 202, and the top of the second tapered portion 202a is lower than the surface of the substrate 200 on both sides of the isolation trench 202.
[0071] Combination Figure 4 and Figure 7 It should be noted that, since the second conical portion 202a is formed on the basis of the first conical portion 201a, the orthographic projections of the first conical portion 201a and the second conical portion 202a toward the surface of the substrate 200 at least partially overlap. Figure 5 and Figure 7 It can be seen that the size of the first cone portion 201a is reduced by forming and removing the sacrificial layer 240, so that the top of the second cone portion 202a finally formed is lower than the surface of the substrate 200 on both sides of the isolation groove 202, and the size of the cone-shaped defect (i.e., the second cone portion 202a) is reduced. In other embodiments of the present application, the effect of reducing or even eliminating the cone-shaped defect in the isolation groove can be achieved by adjusting the thickness or morphology of the sacrificial layer. For example, the first cone portion can be completely oxidized into a sacrificial layer, so as to avoid the second cone portion in the isolation groove by removing the sacrificial layer, thereby eliminating the cone-shaped defect. This is a technical solution that can be implemented by a person skilled in the art based on professional knowledge, and this application will not expand on this.
[0072] Then, see Figure 8 In one embodiment, after forming an isolation trench 202 in the substrate 200 , the method for manufacturing a semiconductor device further includes: filling the isolation trench 202 with an insulating layer 203 to form a shallow trench isolation structure 204 including the insulating layer 203 and the isolation trench 202 .
[0073] contrast Figure 1 and Figure 7 It can be seen that the shallow trench 101 prepared by the general semiconductor device manufacturing method has a cone defect 102, and the top of the cone defect 102 is flush with the surface of the substrate 100 on both sides of the shallow trench 101; while in the isolation trench 202 formed by the semiconductor device manufacturing method provided by the present application, the top of the second cone portion 202a is significantly lower than the surface of the substrate 200 on both sides of the isolation trench 202. It can be seen that the semiconductor device manufacturing method provided by the present application can significantly reduce the size of the cone-shaped defect in the shallow trench isolation structure, thereby helping to improve the electrical properties and reliability of the finally formed semiconductor device.
[0074] In summary, the present application forms an initial groove by etching in the substrate, oxidizes the substrate exposed by the initial groove to form a sacrificial layer, and then removes the sacrificial layer based on the initial groove etching to form an isolation groove, thereby ensuring that the surface of the portion of the substrate located below the isolation groove is lower than the surface of other portions of the substrate, reducing or even eliminating the cone-shaped defects in the isolation groove, and helping to improve the electrical properties and reliability of the ultimately formed semiconductor device.
[0075] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
[0076] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0077] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the application. It should be noted that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, on which a stacked pad oxide layer and a hard mask layer are formed; Etching the hard mask layer, the pad oxide layer and the substrate to form an initial trench, wherein the initial trench penetrates the hard mask layer and the pad oxide layer and extends into the substrate; Oxidizing the substrate exposed by the initial trench to form a sacrificial layer, so that the surface of the remaining substrate below the initial trench is lower than the surface of other parts of the substrate; Removing a portion of the hard mask layer to expose a portion of the surface of the liner oxide layer close to a side of the initial trench; The pad oxide layer and the substrate are continuously etched based on the initial trench and the sacrificial layer is removed to form an isolation trench in the substrate, wherein a surface of a portion of the substrate located below the isolation trench is lower than surfaces of other portions in the substrate.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: A first pointed cone portion is formed at the bottom of the initial trench, and the top of the first pointed cone portion is flush with the substrate surface at both sides of the initial trench; In the process of oxidizing the substrate exposed by the initial groove to form a sacrificial layer, a side of the first pointed cone portion away from the substrate is also oxidized and becomes a part of the sacrificial layer; In the process of continuing to etch the pad oxide layer and the substrate based on the initial groove and removing the sacrificial layer to form an isolation trench in the substrate, a second pointed cone portion is formed at the bottom of the isolation trench, and the orthographic projections of the first pointed cone portion and the second pointed cone portion toward the substrate surface at least partially overlap, and the top of the second pointed cone portion is lower than the substrate surface on both sides of the isolation trench.
3. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that: The thickness of the sacrificial layer is the same as the thickness of the pad oxide layer.
4. The method for manufacturing a semiconductor device according to claim 1, wherein: The depth of the portion of the initial trench extending into the substrate ranges from 3% to 8% of the total thickness of the substrate.
5. The method for manufacturing a semiconductor device according to claim 1, wherein: A back etching process is used to remove part of the hard mask layer, so that a part of the surface of the pad oxide layer close to the initial groove is exposed, and the orthographic projection of the remaining hard mask layer toward the substrate surface is spaced from the orthographic projection of the sacrificial layer toward the substrate surface.
6. The method for manufacturing a semiconductor device according to claim 1, wherein: The process of providing a substrate on which a stacked pad oxide layer and a hard mask layer are formed also includes: forming a patterned photoresist layer on the hard mask layer; The process of etching the hard mask layer, the pad oxide layer and the substrate to form an initial trench includes: Using the photoresist layer as a mask, etching the hard mask layer, the pad oxide layer and the substrate to form the initial trench; After forming the initial trench, the method for manufacturing the semiconductor device further includes: The photoresist layer is removed.
7. The method for manufacturing a semiconductor device according to claim 1, wherein: The substrate exposed by the initial trench is oxidized by a thermal oxidation growth process or an in-situ water vapor generation process to form a sacrificial layer.
8. The method for manufacturing a semiconductor device according to claim 1 or 7, characterized in that: The pad oxide layer and the sacrificial layer are made of the same material, and the hard mask layer is made of a different material from the pad oxide layer.
9. The method for manufacturing a semiconductor device according to claim 8, wherein: The materials of the pad oxide layer and the sacrificial layer both include silicon oxide, and the material of the hard mask layer includes silicon nitride.
10. The method for manufacturing a semiconductor device according to claim 1, wherein: After forming the isolation trench in the substrate, the method for manufacturing the semiconductor device further includes: An insulating layer is filled in the isolation trench to form a shallow trench isolation structure including the insulating layer and the isolation trench.