Chip packaging structure and chip packaging assembly

Abstract

The invention discloses a chip packaging structure and a chip packaging assembly. The chip packaging structure comprises a chip set and a substrate, a first chip and a second chip which are connected with each other are arranged in the chip set, and at least one of the first chip and the second chip is provided with an external connection pin; the substrate is arranged on at least one side of the chip group in the thickness direction, and an external connecting end is arranged on one side, deviating from the chip group, of the substrate; wherein the external connection pins are connected with the corresponding substrates. According to the chip packaging structure, the external connection pins directly connected with the substrate are arranged on the first chip and the second chip in the chip set, signal interaction between the first chip and the second chip and the outside is achieved through the external connection pins, an adapter plate does not need to be used, the cost is low, the signal transmission path is short, and the chip packaging structure is suitable for large-scale popularization and application. And signal attenuation can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a chip packaging structure and a chip packaging assembly. Background Art

[0002] The current chip packaging technology usually interconnects or connects multiple chips (such as main chips and memory chips) to the outside with the help of adapter boards to facilitate data transmission or signal transmission of the chips. However, the adapter board is expensive, and the introduction of the adapter board will increase the chip packaging volume and cost. At the same time, the signals of the main chip and the memory chip have a routing section on the adapter board, which will cause a certain amount of signal attenuation, and the signal routing distance is short, so the signals interfere with each other seriously. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a chip packaging structure. According to the chip packaging structure of the present invention, external connection pins directly connected to the substrate are set on the first chip and the second chip in the chipset, and the signal interaction between the first chip and the second chip and the outside world is realized through the external connection pins, without the need for an adapter board, with low cost and short signal transmission path, which can effectively reduce signal attenuation.

[0004] The present invention also provides a chip packaging assembly including the chip packaging structure.

[0005] The chip packaging structure according to the present invention includes a chipset and a substrate, wherein a first chip and a second chip connected to each other are arranged in the chipset, and at least one of the first chip and the second chip is provided with an external connection pin; the substrate is arranged on at least one side of the chipset in the thickness direction, and an external connection end is arranged on a side of the substrate away from the chipset; wherein the external connection pin is connected to the corresponding substrate.

[0006] According to the chip packaging structure of the present invention, a first chip and a second chip connected to each other are arranged in the chipset. The first chip and the second chip are directly connected to realize data exchange, and there is no need to set up an additional adapter plate structure, which can reduce the packaging volume and cost of the chip packaging structure. A substrate is respectively arranged on both sides of the chipset in the thickness direction. An external connection end connected to an external electrical device or a power supply is formed on the side of the substrate away from the chipset. External connection pins are respectively formed on the first chip and the second chip. When packaging, the external connection pins can be connected to the corresponding substrate, so that the first chip and the second chip are respectively connected to the outside world, so as to realize the signal interaction between the first chip and the second chip and the outside world. Different from the background technology, the chip packaging structure of the present invention cancels the adapter plate structure. Inside the chipset, the first chip and the second chip are directly connected. Outside the chipset, the first chip and the second chip are also directly connected to the substrate through the external connection pins formed on the chip to realize external interaction. Without the adapter plate structure, the overall chip packaging structure is more compact and has lower cost. It can also shorten the signal transmission path and reduce signal attenuation.

[0007] According to an embodiment of the present invention, the chipset and the substrate are overlapped in a thickness direction.

[0008] According to one embodiment of the present invention, a first connection area and a second connection area spaced apart from each other are formed on the first chip, and a first connection pin extending in the thickness direction is arranged in the first connection area; a third connection area and a fourth connection area spaced apart from each other are formed on the second chip, and a second connection pin extending in the thickness direction is arranged in the third connection area; wherein the first connection pin is connected to the second connection pin, and the first connection area and the third connection area are at least partially opposite in the thickness direction.

[0009] According to one embodiment of the present invention, the first connection area and the third connection area are respectively constructed as a plurality of ones corresponding to each other, each of the first connection areas is provided with a plurality of first connection pins spaced apart from each other, each of the third connection areas is provided with a plurality of second connection pins spaced apart from each other, and each of the second connection pins is connected to the corresponding first connection pin.

[0010] According to one embodiment of the present invention, a plurality of the first connection regions are arranged at intervals on at least a portion of the periphery of the second connection region; and / or a plurality of the third connection regions are arranged at intervals on at least a portion of the periphery of the fourth connection region.

[0011] According to an embodiment of the present invention, the first chips are configured to be a plurality of chips spaced apart from each other in a width direction, and the fourth connection region is disposed between two adjacent first chips.

[0012] According to one embodiment of the present invention, a first external connection pin is arranged in the second connection area, and the first external connection pin is connected to the substrate located on the side of the second chip away from the first chip; a second external connection pin is arranged in the fourth connection area, and the second external connection pin is connected to the substrate located on the side of the first chip away from the second chip.

[0013] According to an embodiment of the present invention, the chip packaging structure further includes: a protection layer, wherein the protection layer covers at least a portion of the periphery of the first chip and the second chip.

[0014] According to one embodiment of the present invention, the connecting plate is constructed as two connecting plates arranged on both sides of the chip packaging structure in the thickness direction, the chip unit is arranged on at least one side of the connecting plate away from the chip packaging structure; and / or the chip unit is arranged between the two connecting plates.

[0015] The chip package assembly according to the present invention is briefly described below.

[0016] The chip packaging assembly according to the present invention includes a connecting plate, a chip unit and a chip packaging structure, wherein the connecting plate is arranged on both sides of the chip packaging structure in the thickness direction, and the connecting plate is connected to the external connection end of the chip packaging structure. During assembly, multiple chip packaging structures can be arranged between the two connecting plates, and multiple chip packaging structures can also be arranged on both sides of a connecting plate in the thickness direction. The specific arrangement method can be determined according to actual needs. The chip packaging assembly realizes signal interaction between different chip packaging structures through the connecting plate, enhances the connectivity between components, ensures high-speed and stable signal transmission, and thus improves the performance and reliability of the entire chip packaging assembly. In addition, a chip unit can also be arranged on the connecting plate. Unlike the chipset, only one chip can be arranged in the chip unit. In the face of different use environments, the chip packaging assembly can adaptively arrange the number and position of the chip unit, the chip packaging structure or the connecting plate, so that the chip packaging assembly can interact with multiple signals and data at the same time, thereby improving the performance of the chip packaging assembly. At the same time, the connecting plate and the chip packaging structure overlap in the thickness direction, which can make the entire chip packaging assembly more compact and convenient for arrangement.

[0017] According to one embodiment of the present invention, the connecting plate is constructed as two connecting plates arranged on both sides of the chip packaging structure in the thickness direction, the chip unit is arranged on at least one side of the connecting plate away from the chip packaging structure; and / or the chip unit is arranged between the two connecting plates.

[0018] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0020] Figure 1 is a schematic diagram of a chip packaging structure according to an embodiment of the present invention;

[0021] Figure 2 is a schematic diagram of cooperation between a first chip and a second chip according to an embodiment of the present invention;

[0022] Figure 3 is a schematic diagram of a chip packaging assembly according to an embodiment of the present invention.

[0023] Reference numerals:

[0024] Chip packaging structure 1;

[0025] Chipset 11;

[0026] A first chip 111, a first connection area 1111, a second connection area 1112, a first connection pin 1113, and a first external connection pin 1114;

[0027] The second chip 112, the third connection area 1121, the fourth connection area 1122, the second connection pin 1123, and the second external connection pin 1124;

[0028] A substrate 12, an external connection terminal 121;

[0029] Protective layer 13;

[0030] Chip packaging assembly 2;

[0031] Connecting board 21 and chip unit 22. DETAILED DESCRIPTION

[0032] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0033] The current chip packaging technology usually interconnects or connects multiple chips (such as main chips and memory chips) to the outside with the help of adapter boards to facilitate data transmission or signal transmission of the chips. However, the adapter board is expensive, and the introduction of the adapter board will increase the chip packaging volume and cost. At the same time, the signals of the main chip and the memory chip have a routing section on the adapter board, which will cause a certain amount of signal attenuation, and the signal routing distance is short, so the signals interfere with each other seriously.

[0034] Reference below Figure 1-Figure 3 A chip packaging structure according to an embodiment of the present invention is described.

[0035] The chip packaging structure 1 according to the present invention includes a chipset 11 and a substrate 12. A first chip 111 and a second chip 112 connected to each other are arranged in the chipset 11, and at least one of the first chip 111 and the second chip 112 is provided with an external connection pin; the substrate 12 is arranged on at least one side of the chipset 11 in the thickness direction, and an external connection terminal 121 is provided on a side of the substrate 12 away from the chipset 11; wherein the external connection pin is connected to the corresponding substrate 12.

[0036] According to the chip packaging structure 1 of the present invention, a first chip 111 and a second chip 112 connected to each other are arranged in the chipset 11. The first chip 111 and the second chip 112 are directly connected to realize data exchange, and no additional adapter plate structure is required, which can reduce the packaging volume and cost of the chip packaging structure 1. A substrate 12 is respectively arranged on both sides of the chipset 11 in the thickness direction. An external connection terminal 121 connected to an external electrical device or power supply is formed on the side of the substrate 12 away from the chipset 11. External connection pins are respectively formed on the first chip 111 and the second chip 112. When packaging, the external connection pins can be connected to the corresponding substrate 12, so that the first chip 111 and the second chip 112 are respectively connected to the outside world, so as to realize the signal interaction between the first chip 111 and the second chip 112 and the outside world. Different from the background technology, the chip packaging structure 1 of the present invention cancels the adapter board structure. Inside the chipset 11, the first chip 111 and the second chip 112 are directly connected. Outside the chipset 11, the first chip 111 and the second chip 112 are also directly connected to the substrate 12 through external connection pins formed on the chips to achieve external interaction. Without the adapter board structure, the overall chip packaging structure 1 is more compact and lower in cost. It can also shorten the signal transmission path and reduce signal attenuation.

[0037] It should be noted that the substrate 12 is not the transfer plate structure in the background technology. The substrate 12 is a part used for connecting external devices in the chip packaging technology. The external connection terminal 121 on the substrate 12 can realize the external interaction of the chip. At the same time, the substrate 12 can also support the entire chip packaging structure 1, making the chip packaging structure 1 more stable. In the background technology, the chip and the transfer plate structure chain structure also need to pass through the substrate 12 to interact with the outside world.

[0038] During actual packaging, external connection pins may be provided on the first chip 111 or the second chip 112 as required, or external connection pins may be provided on both the first chip 111 and the second chip 112.

[0039] According to one embodiment of the present invention, the chipset 11 and the substrate 12 are overlapped in the thickness direction. Figure 1 As shown, during packaging, the chipset 11 and the substrate 12 can be overlapped in the thickness direction. The overlapping arrangement can improve the space utilization inside the packaging structure. Compared with the traditional side-by-side layout, the overlapping arrangement can more effectively utilize the space inside the package, thereby reducing the size of the entire packaging structure and making the chip packaging structure 1 more compact.

[0040] According to one embodiment of the present invention, a first connection area 1111 and a second connection area 1112 spaced apart from each other are formed on the first chip 111, and a first connection pin 1113 extending in the thickness direction is arranged in the first connection area 1111; a third connection area 1121 and a fourth connection area 1122 spaced apart from each other are formed on the second chip 112, and a second connection pin 1123 extending in the thickness direction is arranged in the third connection area 1121; wherein the first connection pin 1113 is connected to the second connection pin 1123, and the first connection area 1111 and the third connection area 1121 are at least partially opposite in the thickness direction.

[0041] The first chip 111 and the second chip 112 inside the chipset 11 are connected to each other, specifically: a first connection area 1111 and a second connection area 1112 are provided on the first chip 111, wherein a first connection pin 1113 is provided in the first connection area 1111, and correspondingly, a third connection area 1121 and a fourth connection area 1122 are provided on the second chip 112, and a second connection pin 1123 is provided in the third connection area 1121, the first connection pin 1113 and the second connection pin 1123 extend toward each other in the thickness direction respectively, and during packaging, the first connection area 1111 and the third connection area 1121 are directly opposite to each other in the thickness direction, at this time, the first connection pin 1113 and the second connection pin 1123 are connected to each other to realize the connection between the first chip 111 and the second chip 112, so as to facilitate signal interaction between the first chip 111 and the second chip 112. The first connection pin 1113 and the second connection pin 1123 are respectively arranged at corresponding specific positions (i.e., the first connection area 1111 and the third connection area 1121), so that the connection points on the first chip 111 and the second chip 112 can be more orderly. During packaging, it is only necessary to align the first connection area 1111 and the third connection area 1121 and then connect the first connection pin 1113 with the second connection pin 1123, which is easy to operate. The direct connection between the first connection pin 1113 and the second connection pin 1123 does not require an additional switching structure, shortens the connection path, reduces the attenuation and interference of the signal during the transmission process, and helps to improve the transmission quality of the signal and the overall performance of the system.

[0042] In addition, a second connection area 1112 is provided in the first chip 111, and a fourth connection area 1122 is provided in the second chip 112. Different partitions can realize different functions. During packaging, the first connection area 1111 and the third connection area 1121 realize signal interaction between the first chip 111 and the second chip 112, while the second connection area 1112 and the fourth connection area 1122 can realize functions such as signal input, signal output, and power connection.

[0043] According to an embodiment of the present invention, the first connection area 1111 and the third connection area 1121 are respectively configured as a plurality of one-to-one corresponding ones, and each first connection area 1111 is provided with a plurality of first connection pins 1113 spaced from each other, and each third connection area 1121 is provided with a plurality of second connection pins 1123 spaced from each other, and each second connection pin 1123 is connected to the corresponding first connection pin 1113. By designing the first connection area 1111 and the third connection area 1121 as a plurality of corresponding areas, and providing a plurality of spaced connection pins in each area, the first chip 111 and the second chip 112 have more connection points, so as to facilitate more complex and flexible data and signal transmission between the first chip 111 and the second chip 112. The provision of a plurality of first connection pins 1113 and a plurality of second connection pins 1123 can disperse the current and signal load between the first chip 111 and the second chip 112, reduce the pressure on a single connection point, and extend the service life of the chipset 11.

[0044] According to one embodiment of the present invention, a plurality of first connection areas 1111 are arranged at intervals on at least a portion of the periphery of the second connection area 1112 ; and / or a plurality of third connection areas 1121 are arranged at intervals on at least a portion of the periphery of the fourth connection area 1122 .

[0045] like Figure 1-Figure 2As shown, in the second chip 112, the third connection area 1121 is constructed as a plurality, and the plurality of third connection areas 1121 are distributed at intervals on the periphery of the fourth connection area 1122. The plurality of third connection areas 1121 are arranged at intervals on at least part of the periphery of the fourth connection area 1122, which can more effectively utilize the space in the packaging structure. Compared with concentrating all the connection areas together, this dispersed layout can leave more space for other components (such as capacitors, resistors, etc.) or signal paths, thereby improving the compactness and integration of the entire packaging structure. The third connection areas 1121 arranged at intervals can reduce electromagnetic interference, reduce signal distortion and noise, and also help to reduce the mechanical stress concentration caused by the connection area being too dense, thereby improving the reliability of the connection pins. In addition, the third connection area 1121 and the fourth connection area 1122 are distributed in different areas, which can make the signal interaction between the second chip 112 and the first chip 111 and the signal interaction between the second chip 112 and the outside world independent and non-interfering, thereby improving the stability of the chip packaging structure 1 when in use.

[0046] Likewise, the first chip 111 may also be arranged in the same manner as the second chip 112 .

[0047] In some embodiments, the first connection region 1111 and the second connection region 1112 of the first chip 111 may also be distributed on both sides of the first chip 111 in the width direction.

[0048] According to an embodiment of the present invention, the first chips 111 are configured to be multiple and spaced apart from each other in the width direction, and the fourth connection region 1122 is disposed between two adjacent first chips 111. Figure 1 As shown, multiple first chips 111 are arranged side by side in the width direction, which can make full use of the area of ​​the package substrate 12, improve the chip integration per unit area, help reduce the overall package size, and improve the packaging efficiency. The first connection area 1111 on each first chip 111 corresponds to a third connection area 1121, respectively, so that multiple first chips 111 can interact with the same second chip 112. Multiple first chips 111 are arranged at intervals, which can also improve the air circulation inside the chip package structure 1, thereby improving the heat dissipation efficiency.

[0049] According to an embodiment of the present invention, a first external connection pin 1114 is disposed in the second connection area 1112, and the first external connection pin 1114 is connected to the substrate 12 located on the side of the second chip 112 away from the first chip 111; a second external connection pin 1124 is disposed in the fourth connection area 1122, and the second external connection pin 1124 is connected to the substrate 12 located on the side of the first chip 111 away from the second chip 112. Figure 1-Figure 2As shown, the first chip 111 is provided with a first external connection pin 1114 in the second connection area 1112, and the second chip 112 is provided with a second external connection pin 1124 in the fourth connection area 1122. During packaging, the first connection area 1111 is directly opposite to the third connection area 1121. At this time, the second connection area 1112 can be directly opposite to the substrate 12 on the side of the second chip 112 away from the first chip 111. Similarly, the fourth connection area 1122 can also be directly opposite to the substrate 12 on the side of the first chip 111 away from the second chip 112, so that the first external connection pin 1114 and the second external connection pin 1124 can be respectively connected to the corresponding substrate 12 in the thickness direction of the chip packaging structure 1 without interfering with the chip. After packaging, the first external connection pin 1114 and the second external connection pin 1124 respectively connect the second chip 112 and the first chip 111 to the corresponding substrate 12, and with the help of the substrate 12, realize the connection with the external power supply or other electrical equipment, ensuring the reliability and integrity of the chip and external signal transmission, which helps to improve the performance of the overall system.

[0050] According to an embodiment of the present invention, the chip package structure 1 further includes: a protection layer 13, the protection layer 13 covers at least a portion of the periphery of the first chip 111 and the second chip 112. Figure 1 As shown, the periphery of the first chip 111 and the second chip 112 is coated with a protective layer 13, which can effectively prevent the chips from being physically damaged by the outside, such as scratches, impacts or wear, etc., thereby improving the durability and reliability of the chips. At the same time, the protective layer 13 can be made of insulating and corrosion-resistant materials to provide a certain environmental isolation effect for the chips, prevent moisture, dust, chemicals and other harmful substances from invading the chip packaging structure 1, thereby extending the service life of the chip packaging structure 1.

[0051] The chip package assembly 2 according to the present invention is briefly described below.

[0052] The chip packaging assembly 2 according to the present invention includes a connecting plate 21, a chip unit 22 and a chip packaging structure 1, wherein the connecting plate 21 is arranged on both sides of the chip packaging structure 1 in the thickness direction, and the connecting plate 21 is connected to the external connection end 121 of the chip packaging structure 1. During assembly, multiple chip packaging structures 1 can be arranged between two connecting plates 21, and multiple chip packaging structures 1 can also be arranged on both sides of a connecting plate 21 in the thickness direction. The specific arrangement method can be determined according to actual needs. The chip packaging assembly 2 realizes signal interaction between different chip packaging structures 1 through the connecting plate 21, enhances the connectivity between components, ensures high-speed and stable signal transmission, and thus improves the performance and reliability of the entire chip packaging assembly 2. In addition, a chip unit 22 can also be arranged on the connecting plate 21. Unlike the chipset 11, only one chip can be arranged in the chip unit 22. In the face of different use environments, the chip packaging assembly 2 can adaptively arrange the number and position of the chip unit 22, the chip packaging structure 1 or the connecting plate 21, so that the chip packaging assembly 2 can interact with multiple signals and data at the same time, thereby improving the performance of the chip packaging assembly 2. At the same time, the connection plate 21 and the chip packaging structure 1 overlap in the thickness direction, which can make the entire chip packaging assembly 2 more compact and convenient for layout.

[0053] According to an embodiment of the present invention, the connection board 21 is configured as two boards disposed on both sides of the chip packaging structure 1 in the thickness direction, and the chip unit 22 is disposed on at least one side of the connection board 21 away from the chip packaging structure 1; and / or the chip unit 22 is disposed between the two connection boards 21. Figure 2 As shown, the chip package assembly 2 is provided with two connecting plates 21, and the chip unit 22 can be arranged between the two connecting plates 21 or on one side of one of the connecting plates 21 in the thickness direction, so as to realize the signal interaction between the chip unit 22 and the chip package structure 1. During packaging, the chip unit 22 can be arranged in the space formed by the two connecting plates 21 and the chip package structure 1, or overlap with the connecting plates 21 and the chip package structure 1 in the thickness direction, so as to make the chip package assembly 2 more compact.

[0054] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0055] In the description of the present invention, "first feature" or "second feature" may include one or more of the features.

[0056] In the description of the present invention, "plurality" means two or more.

[0057] In the description of the present invention, a first feature being “on” or “under” a second feature may include that the first and second features are directly in contact with each other, or may include that the first and second features are not in direct contact with each other but are in contact with each other via another feature therebetween.

[0058] In the description of the present invention, “on”, “over” and “above” a first feature from a second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature.

[0059] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0060] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A chip packaging structure, characterized in that: include: A chipset (11), wherein a first chip (111) and a second chip (112) connected to each other are arranged in the chipset (11), and at least one of the first chip (111) and the second chip (112) is provided with an external connection pin; A substrate (12), the substrate (12) being arranged on at least one side of the chipset (11) in the thickness direction, and an external connection terminal (121) being arranged on a side of the substrate (12) facing away from the chipset (11); wherein The external connection pins are connected to the corresponding substrate (12).

2. The chip packaging structure according to claim 1, characterized in that: The chip group (11) and the substrate (12) are arranged to overlap in a thickness direction.

3. The chip packaging structure according to claim 2, characterized in that: A first connection area (1111) and a second connection area (1112) spaced apart from each other are formed on the first chip (111), and a first connection pin (1113) extending in a thickness direction is arranged in the first connection area (1111); A third connection area (1121) and a fourth connection area (1122) spaced apart from each other are formed on the second chip (112), and a second connection pin (1123) extending in the thickness direction is arranged in the third connection area (1121); The first connecting pin (1113) is connected to the second connecting pin (1123), and the first connecting area (1111) and the third connecting area (1121) are at least partially opposite to each other in the thickness direction.

4. The chip packaging structure according to claim 3, characterized in that: The first connection area (1111) and the third connection area (1121) are respectively constructed as a plurality of mutually corresponding first connection pins (1113) each spaced apart from each other, and each of the first connection areas (1111) is provided with a plurality of mutually spaced second connection pins (1123) each spaced apart from each other, and each of the second connection pins (1123) is connected to the corresponding first connection pin (1113).

5. The chip packaging structure according to claim 4, characterized in that: A plurality of the first connection areas (1111) are arranged at intervals on at least a portion of the periphery of the second connection area (1112); and / or The plurality of third connection regions (1121) are arranged at intervals on at least a portion of the periphery of the fourth connection region (1122).

6. The chip packaging structure according to claim 5, characterized in that: The first chips (111) are configured as a plurality of chips spaced apart from each other in a width direction, and the fourth connection region (1122) is disposed between two adjacent first chips (111).

7. The chip packaging structure according to claim 3, characterized in that: A first external connection pin (1114) is provided in the second connection area (1112), and the first external connection pin (1114) is connected to a substrate (12) located on a side of the second chip (112) facing away from the first chip (111); a second external connection pin (1124) is provided in the fourth connection area (1122), and the second external connection pin (1124) is connected to a substrate (12) located on a side of the first chip (111) facing away from the second chip (112).

8. The chip packaging structure according to claim 1, characterized in that: Also includes: A protective layer (13), the protective layer (13) covers at least a portion of the periphery of the first chip (111) and the second chip (112).

9. A chip packaging assembly, characterized in that: include: A chip packaging structure, wherein the chip packaging structure is constructed as the chip packaging structure according to any one of claims 1 to 8; A connecting plate (21), the connecting plate (21) being arranged on at least one side of the chip packaging structure in a thickness direction, and the connecting plate (21) being connected to an external connection end (121) of the chip packaging structure; A chip unit (22), the chip unit (22) is spaced apart from the chip packaging structure and connected to the connection board (21).

10. The chip package assembly according to claim 9, characterized in that: The connecting plate (21) is structured as two plates arranged on both sides of the chip packaging structure in a thickness direction, and the chip unit (22) is arranged on at least one side of the connecting plate (21) away from the chip packaging structure; and / or The chip unit (22) is arranged between the two connecting plates (21).

Images