Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention discloses a semiconductor device and a preparation method of the semiconductor device, the semiconductor device comprises a substrate, the substrate is provided with a memory device region and a protection device region, the protection device region surrounds the memory device region, and the protection device region contains doping ions of a first doping type; the multiple memory devices are arranged in the memory device area in a stacked mode in the direction perpendicular to the substrate; the protection contact is connected with the protection device region, the protection contact comprises doping ions of the second doping type, and the protection contact surrounds the memory device; wherein the first doping type is opposite to the second doping type. The combined action of the protection contact and the protection device area can release charges generated by plasma induction, the influence of the antenna effect on the chip manufacturing process is solved, meanwhile, the protection device area surrounds the storage device area, the area of the storage device is not occupied, the storage density can be improved, and a certain protection effect can be achieved on the storage device.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor device and a method for preparing the semiconductor device. Background Art

[0002] Due to the development of electronic technology, the miniaturization of semiconductor devices has developed rapidly. Three-dimensional memory has attracted extensive attention and research due to its small footprint, high storage density, and low production cost per unit storage unit.

[0003] However, as the number of storage unit layers in three-dimensional memories becomes higher and higher, when plasma processes are used for deposition or etching, the conductors will absorb conductive particles. The aggregation of conductive particles will induce the gate potential to be raised, which may break through the gate oxide layer and cause an antenna effect, thereby degrading the electrical performance of the semiconductor device. Summary of the invention

[0004] Based on this, the embodiments of the present application provide a semiconductor device and a method for preparing the semiconductor device, which can release the charges induced by plasma in a three-dimensional memory, prevent the gate oxide layer from being broken down, and solve the influence of the antenna effect on the chip manufacturing process.

[0005] In a first aspect, the present application provides a semiconductor device according to some embodiments, including: A substrate having a storage device region and a protection device region thereon, wherein the protection device region surrounds the storage device region and contains doping ions of a first doping type; A memory device, wherein a plurality of the memory devices are stacked on the memory device region in a direction perpendicular to the substrate; A protection contact, the protection contact being connected to the protection device region, the protection contact comprising doping ions of a second doping type, and the protection contact surrounding the memory device; A contact plug, wherein the contact plug is disposed on the guard contact and connected to the guard contact; The first doping type and the second doping type are opposite.

[0006] In some embodiments, the semiconductor device further includes, Partitioning posts, one or more of which divide the guard contact into two or more sections of guard contact.

[0007] In some embodiments, the semiconductor device further includes, A sidewall protection layer is disposed between the protected contact and the memory device.

[0008] In some embodiments, a cross-sectional shape of the sidewall protection layer in a direction perpendicular to the substrate is sawtooth-shaped.

[0009] In some embodiments, the semiconductor device further includes: A metal silicide layer is disposed between the protection contact and the contact plug.

[0010] In some embodiments, the semiconductor device further includes: A transistor is connected to the contact plug through a conductive line.

[0011] In a second aspect, the present application also provides a method for preparing a semiconductor device according to some embodiments, comprising: Providing a substrate, forming a storage device region and a protection device region on the substrate, wherein the protection device region surrounds the storage device region, and the protection device region contains doping ions of a first doping type; forming a plurality of memory devices on the device region, wherein the plurality of memory devices are stacked in a direction perpendicular to the substrate; forming a protection contact on the protection device region, the protection contact being connected to the protection device region, the protection contact containing doping ions of a second doping type, and the protection contact surrounding the memory device; forming a contact plug on the protection contact, wherein the contact plug is arranged to be connected to the protection contact; The first doping type and the second doping type are opposite.

[0012] In some embodiments, forming a protection contact on the protection device region includes: A first groove is formed in the protection device region, wherein the bottom of the first groove exposes the protection device region, and a sidewall protection layer is formed on the sidewall of the first groove, wherein the cross-sectional shape of the sidewall protection layer in a direction perpendicular to the substrate is a sawtooth shape; A deposited protective contact material is formed in the first groove, wherein the protective contact material contains dopant ions of the second doping type.

[0013] In some embodiments, before forming the first groove in the protection device region, the method further includes: Forming a stacked structure on the substrate, and patterning and etching to form an initial first groove, wherein the bottom of the initial first groove exposes the protection device area; doping the protection device region with first type doping ions through the initial first groove; The initial first groove is filled to form a plurality of memory devices in the device region, wherein the plurality of memory devices are stacked in a direction perpendicular to the substrate.

[0014] In some embodiments, before forming a contact plug on the protection contact, the method further includes: A metal silicide layer is formed on the protection contact, and the metal silicide layer is disposed between the protection contact and the contact plug.

[0015] The semiconductor structure and the method for preparing the same provided by the present application have at least the following beneficial effects: The present application provides a semiconductor device and a method for preparing the semiconductor device. In the semiconductor device, a substrate includes a storage device area and a protection device area. The protection device area surrounds the storage device area. The protection device area contains doped ions of a first doping type. A protection contact is formed on the protection device area. The protection contact contains doped ions of a second doping type. The first doping type and the second doping type are opposite. The protection contact and the protection device area work together to release the charge induced by plasma, which is broken down before the gate oxide layer is broken down, thereby solving the influence of the antenna effect on the chip process. At the same time, the protection device area surrounds the storage device area and does not occupy the storage device area. Multiple storage devices are stacked in a direction perpendicular to the substrate, which can improve the storage density and also play a certain protective role on the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A three-dimensional schematic diagram of a semiconductor device provided in an embodiment of the present application; Figure 2 A three-dimensional schematic diagram of another semiconductor device provided in an embodiment of the present application; Figure 3 For the embodiment of this application Figure 1 A schematic diagram of a semiconductor device along the AA cross section is provided; Figure 4 A schematic diagram of a cross-sectional view of a semiconductor device provided in an embodiment of the present application Figure 5 A flowchart of a method for preparing a semiconductor device provided in an embodiment of the present application; Figure 6-Figure 14 A schematic diagram of a cross-sectional view of a manufacturing method for forming a semiconductor device provided in an embodiment of the present application; Description of reference numerals: 10: substrate; 100: memory device area; 101: contact step area; 102: memory array area; 200: protection device area; 201: first doping type area; 202: protection contact; 110: memory device; 111: step contact; 203: partition column; 204: metal silicide layer; 300: contact plug; 400: transistor; 401: wire; 402: connection pad; 2011: initial first groove; 101: support layer; 102: sacrificial layer; 2012: initial first sidewall protection layer; 2013: initial first groove sacrificial layer; 2014: sidewall protection layer; 2015: first groove. DETAILED DESCRIPTION

[0018] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0020] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to," it may be directly on, adjacent to, or connected to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, a first doping region may be referred to as a second doping region, and similarly, a second doping region may be referred to as a first doping region; the first doping region and the second doping region are different doping regions.

[0021] Spatial relational terms such as "on..." may be used here to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relational terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, the element or feature described as "on..." will be oriented to be "below" other elements or features. Therefore, the exemplary term "on..." may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0022] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items. Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein, but include deviations in shapes due to, for example, manufacturing techniques, and the regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of regions of a device and do not limit the scope of the present invention.

[0023] Figure 1A three-dimensional schematic diagram of a semiconductor device provided in an embodiment of the present application. In some embodiments, the semiconductor device includes a substrate 10, on which a storage device region 100 and a protection device region 200 are provided, the protection device region 200 surrounds the storage device region 100, and the protection device region 200 contains doping ions of a first doping type, a storage device 110, a plurality of storage devices 110 are stacked in the storage device region 100 in a direction perpendicular to the substrate 10, and a protection contact 202 is connected to the protection device region 200, the protection contact 202 contains doping ions of a second doping type, and the protection contact surrounds the storage device 110, wherein the first doping type and the second doping type are opposite. The substrate 10 in the semiconductor device includes a storage device area 100 and a protection device area 200. The protection device area 200 surrounds the storage device area 100. The protection device area 200 includes a first doping type area 201 containing doping ions of a first doping type. A protection contact 202 is formed on the protection device area 200. The protection contact 202 contains doping ions of a second doping type. The first doping type and the second doping type are opposite. The protection contact 202 and the protection device area 202 work together to release the charges induced by plasma, ensure that the gate oxide layer is not broken down, and solve the influence of the antenna effect on the chip process. At the same time, the protection device area 200 surrounds the storage device area 100 and does not occupy the storage device area. Multiple storage devices 110 are stacked in a direction perpendicular to the substrate, which can improve the storage density and also play a certain protective role on the storage device 110.

[0024] Continue to refer Figure 1In some embodiments of the present application, the substrate 10 includes a plurality of storage device areas 100 and a protection device area 200 surrounding the storage device area 100, and the storage device area 100 includes a storage array area 102 and a contact step area 101 located on both sides of the storage array area 102. The substrate 10 can be a single crystal silicon wafer, a polycrystalline silicon wafer, a germanium silicon wafer, a sapphire wafer, a silicon carbide wafer, a silicon on insulator wafer, a germanium on insulator wafer, a glass wafer, a III-V compound wafer (such as silicon nitride or gallium arsenide, etc.), an oxide semiconductor wafer, or other wafers formed with semiconductor devices. The substrate may be doped with one or more of germanium, carbon, phosphorus, boron, arsenic, gallium or indium elements to improve the conductivity of the substrate. The protection device area 200 is doped with one or more of boron, gallium or indium elements to form a P-type doping area, that is, the first type of doping area is a P-type doping area. In other embodiments, phosphorus or arsenic may also be doped to form an N-type doping area. The doping ions in the substrate may be doped by ion implantation, and then high temperature annealing is performed to repair the damage caused by ion implantation and activate the doping ions. A plurality of memory devices 110 are located in the memory device area 100 and stacked in a direction perpendicular to the substrate 10. The step contacts 111 correspond to the memory devices 110 one by one and are used to connect the memory devices to the outside world. The memory devices may be one or more of random dynamic memory, ferroelectric memory, magnetic memory, resistive memory, flash memory or phase change memory. The plurality of memory devices 110 are stacked in a direction perpendicular to the substrate 10 to reduce the occupied area and improve the storage density.

[0025] Continue to refer Figure 1In some embodiments, the protection contact 202 is located on the protection device region 200 and connected to the substrate 10 in the protection device region 200. The protection contact 202 surrounds the stacked memory device 110, and contains doping ions of the second doping type. The protection contact 202 is a material with conductive properties, for example, it can be at least one of the following materials: single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single crystal silicon, germanium silicon, doped germanium silicon, etc. The protection contact 202 is doped with phosphorus or arsenic to form an N-type doping region. In other embodiments, it can also be doped with one or more of boron, gallium or indium elements to form a P-type doping region. The first doping type is opposite to the second doping type. If the first doping type in the protection device region is P-type doping, the doping type of the protection contact is N-type doping. If the first doping type in the protection device region is N-type doping, the doping type of the protection contact is P-type doping. The embodiment of the present application is described by taking the first doping type in the protection device region as P-type doping and the doping type of the protection contact as N-type doping as an example. Just as the protection device region 200 surrounds the memory device region, the protection contact 202 surrounds the stacked memory device 110, and the height of the protection contact 202 in the direction perpendicular to the substrate 10 is the same as the height of the memory device 110 in the direction perpendicular to the substrate 10. A certain amount of voltage is applied to the protection contact 202 to protect the memory device 110 from electromagnetic interference from adjacent memory devices, and at the same time, it can also reduce damage such as heat conduction and chemical corrosion between adjacent memory devices 110.

[0026] Figure 2 A three-dimensional schematic diagram of another semiconductor device provided in an embodiment of the present application. In some embodiments, the semiconductor device further includes a partition column 203, one or more partition columns 203 divide the protection contact 202 into two or more sections of sub-protection contacts, and the sizes of the divided sub-protection contacts can be the same or different. The partition column 203 is connected to the substrate 10, and the protection contact 202 is divided into two or more sections of sub-protection contacts. The sub-protection contacts of each section can be controlled separately, reducing energy consumption and improving control efficiency. The partition column 203 can be at least one of the following materials: silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxide, etc. The partition column 203 has good etching resistance and stability, can relieve the stress of the wafer, and at the same time play a certain protective role on the storage device 110. The partition column 203 can be a layer or a multi-layer, can include a double layer or a triple layer, the material of each layer can be the same or different, and can also include an air gap structure, which can reduce the parasitic capacitance between adjacent sub-protection contacts or between adjacent storage devices 110.

[0027] Figure 3 For the embodiment of this application Figure 1A schematic diagram of a semiconductor device along the AA cross section is provided. In some embodiments of the present application, the semiconductor device further includes a contact plug 300, which is disposed on the protective contact 202 and connected to the protective contact 202. The contact plug 300 is a material having a conductive property, for example, it can be at least one of the following materials: single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single crystal silicon, germanium silicon, doped germanium silicon, titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), metal silicide, etc. In some embodiments, a metal silicide layer 204 is further provided between the contact plug 300 and the protection contact 202. The metal silicide layer 204 may include one or more of tungsten silicide, cobalt silicide, nickel silicide or titanium silicide. The metal silicide layer 204 may reduce the contact resistance between the contact plug 300 and the protection contact 202, and improve the control capability of the protection contact 202.

[0028] Continue to refer Figure 3 In some embodiments, the semiconductor device further includes a sidewall protection layer 2014, which is located on both sides of the protection contact 202 to separate the protection contact 202 from the memory device 110. The sidewall protection layer 2014 can be at least one of the following materials: silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxide, etc. The sidewall protection layer 2014 has good etching resistance and stability, can relieve the stress of the wafer, and at the same time play a certain protective role for the protection contact 202. In some embodiments, the cross-sectional shape of the sidewall protection layer 2014 in the direction perpendicular to the substrate is a sawtooth shape, which can increase the volume of the protection contact 202 and reduce the resistance of the protection contact 202 itself. At the same time, the cross-sectional shape of the sidewall protection layer 2014 in the direction perpendicular to the substrate is a sawtooth shape, which can increase the stability of the sidewall protection layer itself. The sidewall protection layer 2014 may be a single layer or multiple layers, including double layers or triple layers. The material of each layer may be the same or different, and may also include an air gap structure to reduce the parasitic capacitance between the protection contact 202 and the storage device 110 .

[0029] Figure 4A schematic diagram of a cross-sectional view of a semiconductor device provided in an embodiment of the present application. In some embodiments of the present application, the semiconductor device further includes a transistor 400, and the transistor 400 is connected to the contact plug 300 through a wire 401. The transistor 400 may be an N-type transistor or a P-type transistor. The transistor 400 may be located on the substrate 10 or on another wafer, and is connected to the contact plug 300 after wafer bonding. The wire 401 is used to connect the contact plug 300 and the transistor 400. The wire 401 is a material having conductive properties, for example, it may be at least one of the following materials: single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single crystal silicon, germanium silicon, doped germanium silicon, titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), metal silicide, etc. The wire 401 can be a single layer or multiple layers, can be located on a single wafer substrate, or can be located on two or more wafer substrates, the materials of each layer or each section of the wire can be the same or different, and the wire is also connected to the connection pad, which can be connected to other wafers or circuits outside the wafer on the one hand, and on the other hand, can cause the induced charge to accumulate and then be released to the protection contact 202 and the protection device area in the substrate through the contact plug 300.

[0030] Continue to refer Figure 3 and Figure 4 In some embodiments, the transistor is located on the second wafer, connected to the contact plug 300 through wafer bonding, the wafer is flipped, the back side of the substrate (the side away from the protective contact 202) is ground thin, and a conductive structure is formed on the back side of the substrate 10. In the process of forming the conductive structure, a large amount of charge will be generated due to plasma technology. These charges will gather together to produce an antenna effect. The solutions of some embodiments of the present application can release the accumulated charges to alleviate the antenna effect. In some embodiments, after wafer bonding, a conductive structure can also be formed on the second wafer. Similarly, a large amount of charge will be generated due to plasma technology. The solutions of some embodiments of the present application can release the accumulated charges to alleviate the antenna effect.

[0031] Continue to refer Figure 1 , Figure 2 , Figure 3In some embodiments, a protection device region 200 containing doping ions of a first doping type is formed in the substrate 10, and a protection contact 202 containing doping ions of a second doping type is formed by deposition on the surface of the protection device region 200. The protection contact 202 and the protection device region 200 together form a diode. When the antenna effect occurs, the diode will be broken down first, and the charge collected on the antenna will be released, thereby achieving the effect of protecting the transistor and reducing the impact of the antenna effect on the semiconductor device. At the same time, the protection contact 202 is located around the memory device 110 and is at the same height as the memory device 110, which can prevent the memory device 110 from chemical or physical damage and play a certain protective role on the memory device.

[0032] Figure 5 A flowchart of a method for preparing a semiconductor device provided in an embodiment of the present application, Figure 6-Figure 14 A schematic diagram of a cross-sectional view of a manufacturing method for forming a semiconductor device provided in an embodiment of the present application.

[0033] refer to Figure 2 The semiconductor device manufacturing method comprises at least the following steps: S10: providing a substrate, forming a storage device region and a protection device region on the substrate, wherein the protection device region surrounds the storage device region, and the protection device region contains doping ions of a first doping type; S20: forming a plurality of memory devices on the memory device region, wherein the plurality of memory devices are stacked in a direction perpendicular to the substrate; S30: forming a protection contact on the protection device region, the protection contact being connected to the protection device region, the protection contact comprising doping ions of the second doping type, the protection contact surrounding the memory device, the first doping type being opposite to the second doping type; S40: forming a contact plug on the guard contact, wherein the contact plug is connected to the guard contact.

[0034] It should be understood that Figure 5 The operations shown in the preparation method are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some operations may be performed simultaneously, or in a different order than that shown in the figure. In addition, some operations may be performed simultaneously, or in a different order than that shown in the figure.

[0035] In the method for preparing a semiconductor device provided in an embodiment of the present application, a diode can be formed in a three-dimensional memory, which can alleviate the antenna effect, reduce the impact of the antenna effect on the semiconductor device, and prevent the three-dimensional memory device from chemical or physical damage.

[0036] refer to Figure 5 and Figure 6In some embodiments, a substrate 10 is provided, a storage device area 100 and a protection device area 200 are formed on the substrate 10, the protection device area 200 surrounds the storage device area 100, the storage device area 100 includes a storage array area 102 and a contact step area 101 located on both sides of the storage array area 102, and the protection device area 200 contains doping ions of a first doping type. The substrate 10 can be a single crystal silicon wafer, a polycrystalline silicon wafer, a germanium silicon wafer, a sapphire wafer, a silicon carbide wafer, a silicon on insulator wafer, a germanium on insulator wafer, a glass wafer, a III-V compound wafer (such as silicon nitride or gallium arsenide, etc.), an oxide semiconductor wafer or other wafers formed with semiconductor devices. The substrate can be doped with one or more of germanium, carbon, phosphorus, boron, arsenic, gallium or indium elements to improve the conductivity of the substrate. The doping ions in the substrate can be doped by ion implantation, and then high temperature annealing is performed to repair the damage caused by the ion implantation and activate the doping ions. In some embodiments, a stacked structure of a support layer 101 and a sacrificial layer 102 is formed on the surface of the substrate 10, and the support layer 101 and the sacrificial layer 102 are alternately stacked in a direction perpendicular to the substrate 10. The materials of the support layer 101 and the sacrificial layer 102 can be single crystal silicon and silicon germanium, respectively, formed by epitaxial growth and alternate stacking, or can be polycrystalline silicon, silicon oxide, silicon nitride and other dielectric materials, respectively, formed by alternate deposition of the stacked structure. A mask layer is deposited on the stacked layer, exposed and etched to form an initial first groove 2011, the initial first groove 2011 passes through the stacked structure, and the bottom exposes the protection device area 200 in the substrate 10, and the initial first groove 2011 surrounds the stacked structure of the storage device area. Figure 7 for Figure 6 Schematic diagram of the cross section along AA. Specifically, dry etching, such as plasma etching, or wet etching, such as chemical etching, can be used. The bottom of the initial first groove 2011 is lower than the surface of the substrate, that is, the initial first groove 2011 is embedded in the substrate, which can prevent the phenomenon of partial area not being etched through due to process differences, resulting in a circuit break.

[0037] refer to Figure 5 and Figure 8 An initial first sidewall protection layer 2012 is formed on the sidewall of the initial first groove 2011, and the initial first sidewall protection layer 2012 covers the bottom and both sides of the initial first groove 2011. Specifically, the initial first sidewall protection layer 2012 can be deposited on the bottom and both sides of the initial first groove 2011 by atomic layer deposition, chemical vapor deposition, plasma-assisted atomic layer vapor deposition, etc. The material of the initial first sidewall protection layer can be one or more of polysilicon, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, etc. Fig. 9, the initial first sidewall protection layer at the bottom of the initial first groove 2011 is etched away by plasma-assisted etching to expose the protection device region 200 in the substrate 10, and a first doping type region 201 is formed in the protection device region 200. The first doping type region 201 is located in the protection device region 200 in the substrate 10. The first doping type region 201 can be doped with one or more of boron, gallium or indium elements to form a P-type doping region. In other embodiments, phosphorus or arsenic can also be doped to form an N-type doping region. The embodiment of the present application takes the first doping type region 201 doped with one or more of boron, gallium or indium elements to form a P-type doping region as an example for explanation. The first doping type region 201 is formed by depositing a material doped with a large amount of boron, gallium or indium elements at the bottom of the initial first groove 2011, heating to diffuse the boron, gallium or indium elements into the substrate 10, or by ion implantation, implanting boron, gallium or indium elements at the bottom of the initial first groove 2011, and high temperature annealing to repair the damage caused by the ion implantation and activate the doped ions to form the first doping type region 201. The initial first sidewall protection layer can protect the stacked structure from being damaged when the first doping type region 201 is formed.

[0038] Continue to refer Figure 5 In some embodiments, a plurality of memory devices 110 and step contacts 111 are formed on the memory device region 100, and the plurality of memory devices 100 and step contacts 111 are stacked in a direction perpendicular to the substrate. In some embodiments, after forming a first doping type region 201 at the bottom of the initial first groove 2011, an initial first groove sacrificial layer 2013 is deposited in the initial first groove 201, the initial first groove sacrificial layer 2013 fills the initial first groove 2011, and is ground flat, referring to Fig.10 . Specifically, the sacrificial layer material may be deposited by chemical vapor deposition, atomic layer deposition, spin coating, plasma-assisted chemical vapor deposition, or the like. The material of the initial first groove sacrificial layer 2013 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, or the like. In some embodiments, the surface of the stacked structure on the storage device area 100 may be exposed and etched to form a groove, and the sacrificial layer 102 and a portion of the supporting layer 101 may be removed in sequence to form a stacked structure of a storage device 110 and a stepped contact 111 in the area of ​​the original sacrificial layer 102 and the supporting layer 101. The stepped contact 111 corresponds to the storage device 110 one-to-one and is used to connect the storage device to the outside world. See FIG. Fig.11Specifically, a stacked structure of multiple memory devices 110 and step contacts 111 is located on the memory device area 100 and is stacked in a direction perpendicular to the substrate 10. The memory device may be one or more of a random dynamic memory, a ferroelectric memory, a magnetic memory, a resistive memory, a flash memory, or a phase change memory. Multiple memory devices 110 and step contacts 111 are stacked in a direction perpendicular to the substrate 10, which can reduce the occupied area and improve the storage density.

[0039] Continue to refer Figure 5 In some embodiments, a protection contact 202 is formed on the protection device region 200, the protection contact 202 is connected to the protection device region 200, the protection contact 202 contains doping ions of the second doping type, the protection contact 202 surrounds the stacked structure of the memory device 110, and the first doping type and the second doping type are opposite. In some embodiments, after the stacked structure of the memory device 110 is formed, the initial first groove sacrificial layer 2013 is removed by selective etching to expose the first doping type region 201, referring to Fig.12 , the sidewall of the initial first groove 2011 is reinforced to form a sidewall protection layer 2014 and a first groove 2015. In other embodiments, the initial first sidewall protection layer 2012 can also be removed, and a layer of sidewall protection layer 2014 is re-deposited on the sidewall of the initial first groove 2011. The sidewall protection layer 2014 can be at least one of the following materials: silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxide, etc. The sidewall protection layer 2014 has good etching resistance and stability, can relieve the stress of the wafer, and at the same time play a certain protective role in protecting the contact 202. In some embodiments, the sidewall protection layer 2014 forms a serrated shape along the surface perpendicular to the substrate 10, refer to Fig.13 , the volume of the protection contact 202 can be increased, and the resistance of the protection contact 202 itself can be reduced. At the same time, the cross-sectional pattern of the sidewall protection layer 2014 in the direction perpendicular to the substrate is a sawtooth shape, which can increase the stability of the sidewall protection layer itself. The sidewall protection layer 2014 can be a single layer or multiple layers, and can include two layers or three layers. The material of each layer can be the same or different, and can also include an air gap structure, which can reduce the parasitic capacitance between the protection contact 202 and the storage device 110.

[0040] Continue to refer Figure 5 and Fig.14In some embodiments, a protective contact material is deposited in the first groove 2015, and the mask is flattened to form a protective contact 202. The protective contact 202 is located on the protective device area 200 and is connected to the substrate 10 in the protective device area 200. The protective contact 202 surrounds the stacked memory device 110, and the protective contact 202 contains doping ions of the second doping type. The protective contact 202 is a material with conductive properties, for example, it can be at least one of the following materials: single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single crystal silicon, germanium silicon, doped germanium silicon, etc. The protective contact 202 is doped with phosphorus or arsenic to form an N-type doping area. In other embodiments, it can also be doped with one or more of boron, gallium or indium elements to form a P-type doping area. The first doping type is opposite to the second doping type. The embodiment of the present application is described by taking the first doping type in the protective device area as P-type doping and the doping type of the protective contact as N-type doping as an example. Just as the protection device region 200 surrounds the memory device region, the protection contact 202 surrounds the stacked memory device 110, and the height of the protection contact 202 in the direction perpendicular to the substrate 10 is the same as the height of the stacked structure of the memory device 110 in the direction perpendicular to the substrate 10. A certain amount of voltage is applied to the protection contact 202 to protect the memory device 110 from electromagnetic interference from adjacent memory devices, and at the same time, it can also reduce the damage of heat conduction, chemical corrosion, etc. between adjacent memory devices 110. In some embodiments, a partition column 203 can also be formed, referring to Figure 2 , one or more partition columns 203 divide the protection contact 202 into two or more sections of sub-protection contacts, and the sizes of the divided sub-protection contacts can be the same or different. The partition column 203 is connected to the substrate 10, and the protection contact 202 is divided into two or more sections of sub-protection contacts. The sub-protection contacts of each section can be controlled separately, reducing energy consumption and improving control efficiency. The partition column 203 can be at least one of the following materials: silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxide, etc. The partition column 203 has good etching resistance and stability, can relieve the stress of the wafer, and at the same time play a certain protective role on the storage device 110. The partition column 203 can be a single layer or a multi-layer, can include a double layer or a triple layer, the material of each layer can be the same or different, and can also include an air gap structure, which can reduce the parasitic capacitance between adjacent sub-protection contacts or between adjacent storage devices 110.

[0041] Continue to refer Figure 5 and Figure 3In some embodiments, a contact plug 300 is formed on the protective contact 202, and the contact plug 300 is connected to the protective contact 202. Specifically, a dielectric layer is formed on the surface of the stacked structure of the protective contact 202 and the memory device 110, and is polished and flattened. An opening is formed by exposure and etching. The bottom of the opening exposes the top surface of the protective contact 202. A contact plug material is deposited in the opening, and the mask is flattened to form the contact plug 300. The contact plug 300 is a material having a conductive property, for example, it can be at least one of the following materials: single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single crystal silicon, germanium silicon, doped germanium silicon, titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), metal silicide, etc. In some embodiments, a metal silicide layer 204 is further formed between the contact plug 300 and the protection contact 202. The metal silicide layer 204 may include one or more of tungsten silicide, cobalt silicide, nickel silicide or titanium silicide. The metal silicide layer 204 may reduce the contact resistance between the contact plug 300 and the protection contact 202, and improve the control capability of the protection contact 202.

[0042] Continue to refer Figure 4 In some other embodiments, a wire 401 may be formed on the contact plug 300, and the wire 401 is connected to the transistor 400 and the connection pad 402. The transistor 400 may be an N-type transistor or a P-type transistor. The transistor 400 may be located on the substrate 10 or on another wafer, and is connected to the contact plug 300 after wafer bonding. The wire 401 is used to connect the contact plug 300 and the transistor 400. The wire 401 is a material with conductive properties, for example, it may be at least one of the following materials: single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single crystal silicon, germanium silicon, doped germanium silicon, titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), metal silicide, etc. The wire 401 can be a single layer or multiple layers, can be located on a single wafer substrate, or can be located on two or more wafer substrates, and the material of each layer or each section of the wire can be the same or different.

[0043] By forming a first doping type region 201 in the protection device region 200, and forming a protection contact 202 containing doping ions of the second doping type on the surface of the first doping type region 201, the protection contact 202 forms a diode with the first doping type region 201 in the protection device region 200. When the antenna effect occurs, the diode will be broken down first, and the charge collected on the antenna will be released, thereby achieving the effect of protecting the transistor and reducing the impact of the antenna effect on the semiconductor device. At the same time, the protection contact 202 is located around the memory device 110 and is at the same height as the stacked structure of the memory device 110, which can prevent the stacked structure of the memory device 110 from chemical or physical damage, and play a certain protective role for the memory device.

[0044] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0045] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate having a storage device region and a protection device region thereon, wherein the protection device region surrounds the storage device region and contains doping ions of a first doping type; A memory device, wherein a plurality of the memory devices are stacked on the memory device region in a direction perpendicular to the substrate; A protection contact, the protection contact being connected to the protection device region, the protection contact comprising doping ions of a second doping type, and the protection contact surrounding the memory device; A contact plug, wherein the contact plug is disposed on the guard contact and connected to the guard contact; The first doping type and the second doping type are opposite.

2. The semiconductor device according to claim 1, wherein: Also includes, Partitioning posts, one or more of which divide the guard contact into two or more sections of guard contacts.

3. The semiconductor device according to claim 1, wherein: Also includes, A sidewall protection layer is disposed between the protected contact and the memory device.

4. The semiconductor device according to claim 3, characterized in that The sidewall protection layer has a sawtooth-shaped cross-section in a direction perpendicular to the substrate.

5. The semiconductor device according to claim 1, wherein: Also includes, A metal silicide layer is disposed between the protection contact and the contact plug.

6. The semiconductor device according to any one of claims 1 to 5, further comprising: A transistor is connected to the contact plug through a conductive line.

7. A method for preparing a semiconductor device, characterized in that: Providing a substrate, forming a storage device region and a protection device region on the substrate, wherein the protection device region surrounds the storage device region, and the protection device region contains doping ions of a first doping type; forming a plurality of memory devices on the device region, wherein the plurality of memory devices are stacked in a direction perpendicular to the substrate; forming a protection contact on the protection device region, the protection contact being connected to the protection device region, the protection contact containing doping ions of a second doping type, and the protection contact surrounding the memory device; forming a contact plug on the protection contact, wherein the contact plug is arranged to be connected to the protection contact; The first doping type and the second doping type are opposite.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: Forming a protection contact on the protection device region includes: A first groove is formed in the protection device region, wherein the bottom of the first groove exposes the protection device region, and a sidewall protection layer is formed on the sidewall of the first groove, wherein the cross-sectional shape of the sidewall protection layer in a direction perpendicular to the substrate is a sawtooth shape; A deposited protective contact material is formed in the first groove, wherein the protective contact material contains dopant ions of the second doping type.

9. The method for manufacturing a semiconductor device according to claim 8, before forming the first groove in the protection device region, further comprising: Forming a stacked structure on the substrate, and patterning and etching to form an initial first groove, wherein the bottom of the initial first groove exposes the protection device area; doping the protection device region with first type doping ions through the initial first groove; The initial first groove is filled to form a plurality of memory devices in the device region, wherein the plurality of memory devices are stacked in a direction perpendicular to the substrate.

10. The method for manufacturing a semiconductor device according to any one of claims 7 to 9, further comprising: before forming a contact plug on the protection contact: A metal silicide layer is formed on the protection contact, and the metal silicide layer is disposed between the protection contact and the contact plug.

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