Low-power-consumption power switching circuit
By combining the bias current generation module and the power comparison module, and introducing Smit INV and inverter into the power switching circuit, the shortcomings of the existing power switching circuit in terms of low power consumption and low misjudgment are solved, and more efficient power switching and more stable power supply are achieved.
Patent Information
- Application Number
- CN202510300870.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-14
- Publication Date
- 2025-04-25
AI Technical Summary
The existing power switching circuit has shortcomings in low power consumption and low misjudgment, especially when the input power supply voltage is close, it is prone to misswitching and leakage.
By combining the bias current generation module and the power supply comparison module, setting up the Smit INV, and adding inverters to the power switching module, reducing missed switching and leakage, and improving noise immunity.
It realizes power switching with low power consumption and low misjudgment, reduces the area and power consumption of the power switching circuit, and improves noise immunity and stability.
Smart Images
Figure CN119891511A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a low-power power switching circuit. Background Art
[0002] The power switching circuit is an electronic circuit widely used in multi-power supply systems. It automatically compares two or more power supplies and selects a higher voltage power supply to power the internal circuit of the chip, such as switching electronic devices to different operating modes, battery energy saving management or mixed signal processing.
[0003] The power switching circuit of the two power supplies is a normally open module in the system, which requires the power switching circuit to maintain low power during operation. On the other hand, the power supply is automatically compared and powered on and off, which requires the power switching circuit to ensure timely switching of the power supply during operation and reduce the occurrence of misjudgment. Therefore, a power switching circuit with low power consumption and low misjudgment is needed. Summary of the invention
[0004] The purpose of the present invention is to provide a low-power power switching circuit. The present invention reduces the area and power consumption of the power switching circuit by combining a bias current generating module and a power comparison module. Schmidt INV is set in the power switching module to reduce the occurrence of erroneous switching and leakage when the input power voltage is close, thereby improving the anti-noise ability of the power switching circuit.
[0005] The purpose of the present invention is achieved by the following technical means: In a first aspect, the present invention provides a low-power power switching circuit, comprising: a bias current generating module, a power comparison module and a power switching module; The bias current generating module is used to generate a bias current and output the bias current to the power comparison module; The power comparison module is used to compare the first power supply (VDD1) and the second power supply (VDD2), and output a control signal (VDD_SEL) to the power switching module according to the comparison result; The power switching module is used to switch the output voltage (VOUT) according to the control signal (VDD_SEL).
[0006] Preferably, the bias current generating module comprises: a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1), a second NMOS transistor (MN2) and a first resistor (R1); The source of the first PMOS tube (MP1) is connected to the first power supply (VDD1), the drain is connected to the gate, and the gate is connected to the first input terminal of the power comparison module; The source of the first NMOS tube (MN1) is connected to the drain of the first PMOS tube (MP1), the drain is grounded, and the gate is connected to the second input terminal of the power comparison module; The source of the second PMOS tube (MP2) is connected to the first power supply (VDD1), the drain is connected to the gate of the first NMOS tube (MN1), and the gate is connected to the gate of the first PMOS tube (MP1); The source of the second NMOS tube (MN2) is connected to the drain of the second PMOS tube (MP2), the drain is connected to the first end of the first resistor (R1), and the gate is connected to the gate of the first NMOS tube (MN1); A second end of the first resistor (R1) is grounded.
[0007] Preferably, the area of the second NMOS transistor (MN2) is greater than the area of the first NMOS transistor (MN1).
[0008] Preferably, the power comparison module comprises: a third PMOS tube (MP3) and a third NMOS tube (MN3); The source of the third PMOS tube (MP3) is connected to the second power supply (VDD2), the drain is connected to the input end of the power switching module, and the gate is connected to the first output end of the bias current generating module; The source of the third NMOS tube (MN3) is connected to the drain of the third PMOS tube (MP3), the drain is grounded, and the gate is connected to the second output end of the bias current generating module.
[0009] Preferably, the bias current generating module and the power comparison module form a current mirror, which specifically includes: The bias current generating module comprises: a first PMOS tube (MP1) and a first NMOS tube (MN1); The power comparison module includes: a third PMOS tube (MP3) and a third NMOS tube (MN3); The source of the first PMOS tube (MP1) is connected to the first power supply (VDD1), the drain is connected to the gate, and the gate is connected to the gate of the third PMOS tube (MP3); The source of the first NMOS tube (MN1) is connected to the drain of the first PMOS tube (MP1), the drain is grounded, and the gate is connected to the gate of the third NMOS tube (MN3); The source of the third PMOS tube (MP3) is connected to the second power supply (VDD2), and the drain is connected to the source of the third NMOS tube (MN3); The drain of the third NMOS tube (MN3) is grounded.
[0010] Preferably, when the first power supply (VDD1) is greater than the second power supply (VDD2), the current of the first PMOS tube (MP1) is greater than the current of the third PMOS tube (MP3), and the output of the control signal (VDD_SEL) is low; When the second power supply (VDD2) is greater than the first power supply (VDD1), the current of the third PMOS tube (MP3) is greater than the current of the first PMOS tube (MP1), and the output of the control signal (VDD_SEL) is high.
[0011] Preferably, the power switching module comprises: a fourth PMOS tube (MP4), a fifth PMOS tube (MP5) and an inverter (INV); The source of the fourth PMOS tube (MP4) is connected to the first power supply (VDD1), the drain is connected to the output voltage (VOUT), and the gate is connected to the output end of the power comparison module; The source of the fifth PMOS tube (MP5) is connected to the second power supply (VDD2), the drain is connected to the drain of the fourth PMOS tube (MP4), and the gate is connected to the output end of the inverter (INV); An input end of the inverter (INV) is connected to an output end of the power comparison module.
[0012] Preferably, when the control signal (VDD_SEL) is outputted as low, the output of the inverter (INV) is high, the fourth PMOS tube (MP4) is turned on, the fifth PMOS tube (MP5) is turned off, and the output voltage (VOUT) is the first power supply (VDD1); When the control signal (VDD_SEL) is output high, the output of the inverter (INV) is low, the fourth PMOS tube (MP4) is turned off, the fifth PMOS tube (MP5) is turned on, and the output voltage (VOUT) is the second power supply (VDD2).
[0013] Preferably, the inverter (INV) is a Schmidt INV.
[0014] Preferably, the power switching module comprises: a first capacitor (C1); A first end of the first capacitor (C1) is connected to the output voltage (VOUT), and a second end is grounded.
[0015] Compared with the prior art, the present invention has the following beneficial effects: The present invention combines the bias current generation module and the power comparison module of the power switching circuit for setting, and sets a third PMOS tube MP3 and a third NMOS tube MN3 on the basis of the bias current generation module to form a current mirror for power comparison, thereby reducing the area and power consumption of the power switching circuit; The present invention sets the Schmit INV, and the control signal VDD_SEL is connected to the gate of the fifth PMOS tube MP5 through the Schmit INV, thereby reducing the occurrence of erroneous switching and leakage when the first power supply VDD1 and the second power supply VDD2 are close in size, and improving the anti-noise ability of the power switching circuit; The present invention reduces the noise of the output voltage VOUT and improves the anti-noise capability of the power switching circuit by setting the first capacitor C1 bypass. At the same time, it reduces the transient change of the output voltage VOUT during switching and improves the stability of the power switching circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.
[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0018] Figure 1 A schematic diagram of the structure of a low-power power switching circuit provided in this embodiment; Figure 2 A circuit schematic diagram of a low-power power switching circuit provided in this embodiment. DETAILED DESCRIPTION
[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0020] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.
[0021] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.
[0022] Embodiment 1 This embodiment provides a low-power power switching circuit. Figure 1 As shown, it includes: a bias current generating module 100, a power comparison module 200 and a power switching module 300; The bias current generating module 100 is used to generate a bias current and output the bias current to the power source comparing module 200; The power comparison module 200 is used to compare the first power source VDD1 and the second power source VDD2, and output a control signal VDD_SEL to the power switching module 300 according to the comparison result; The power switching module 300 is used to switch the output voltage VOUT according to the control signal VDD_SEL.
[0023] It should be noted that the power switching module 300 switches between the first power supply VDD1 and the second power supply VDD2 according to the control signal VDD_SEL output by the front-end module. The bias current generating module 100 and the power comparison module 200 can be two independent modules. The bias circuit module 100 is used to generate the bias current required by the power comparison module, and the power comparison module 200 is used to compare the size of the power supply and output the control signal VDD_SEL. The bias current generating module 100 and the power comparison module 200 can also be a combined front-end module, in which the bias current is generated and the power supply comparison is performed, thereby reducing the area and power consumption of the power switching circuit, and thus reducing the area and power consumption of the chip system. In actual implementation, the bias current generating module 100, the power comparison module 200 and the power switching module 300 can be multiple modules combined in one module. The specific structure is combined through the following embodiments. Figure 2 Provide explanation.
[0024] In some embodiments, Figure 2 As shown, the bias current generating module 100 includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2 and a first resistor R1; The source of the first PMOS transistor MP1 is connected to the first power source VDD1, the drain is connected to the gate, and the gate is connected to the first input terminal of the power comparison module 200; The source of the first NMOS transistor MN1 is connected to the drain of the first PMOS transistor MP1, the drain is grounded, and the gate is connected to the second input terminal of the power comparison module 200; The source of the second PMOS transistor MP2 is connected to the first power supply VDD1, the drain is connected to the gate of the first NMOS transistor MN1, and the gate is connected to the gate of the first PMOS transistor MP1; The source of the second NMOS transistor MN2 is connected to the drain of the second PMOS transistor MP2, the drain is connected to the first end of the first resistor R1, and the gate is connected to the gate of the first NMOS transistor MN1; A second end of the first resistor R1 is grounded; The area of the second NMOS transistor MN2 is greater than that of the first NMOS transistor MN1.
[0025] It should be noted that the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, the second NMOS transistor MN2 and the first resistor R1 together constitute the bias current generating module 100. Specifically, by setting the area ratio of the first NMOS transistor MN1 to the second NMOS transistor MN2 and the resistance value of the first resistor R1, the area of the second NMOS transistor MN2 is set to an integral multiple of the area of the first NMOS transistor MN1, so that there will be a voltage drop on the first resistor R1, and a stable bias current is provided through the voltage drop on the first resistor R1. When the circuit is stable, the magnitude of the current flowing through the first NMOS transistor MN1 is equal to the magnitude of the current flowing through the second NMOS transistor MN2, that is, I (MN1) = I (MN2).
[0026] In some embodiments, Figure 2 As shown, the power comparison module 200 includes: a third PMOS transistor MP3 and a third NMOS transistor MN3; The source of the third PMOS transistor MP3 is connected to the second power supply VDD2, the drain is connected to the input end of the power switching module 300, and the gate is connected to the first output end of the bias current generating module 100; The source of the third NMOS transistor MN3 is connected to the drain of the third PMOS transistor MP3 , the drain is grounded, and the gate is connected to the second output terminal of the bias current generating module 100 .
[0027] It should be noted that the power comparison module 200 outputs the control signal VDD_SEL by comparing the current flowing through the third PMOS transistor MP3 and the current flowing through the third NMOS transistor MN3. Specifically, when I (MP3) > I (MN3), the second power supply VDD2 is greater than the first power supply VDD1, and the control signal VDD_SEL is output as high, indicating that the second power supply VDD2 needs to be selected as the output voltage VOUT; similarly, when I (MN3) > I (MP3), the first power supply VDD1 is greater than the second power supply VDD2, and the control signal VDD_SEL is output as low, indicating that the first power supply VDD1 needs to be selected as the output voltage VOUT.
[0028] In some embodiments, Figure 2 As shown, the bias current generating module 100 and the power comparison module 200 form a current mirror, which specifically includes: The bias current generating module 100 includes: a first PMOS transistor MP1 and a first NMOS transistor MN1; The power comparison module 200 includes: a third PMOS transistor MP3 and a third NMOS transistor MN3; The source of the first PMOS transistor MP1 is connected to the first power supply VDD1, the drain is connected to the gate, and the gate is connected to the gate of the third PMOS transistor MP3; The source of the first NMOS transistor MN1 is connected to the drain of the first PMOS transistor MP1, the drain is grounded, and the gate is connected to the gate of the third NMOS transistor MN3; The source of the third PMOS transistor MP3 is connected to the second power supply VDD2, and the drain is connected to the source of the third NMOS transistor MN3; The drain of the third NMOS tube MN3 is grounded; When the first power source VDD1 is greater than the second power source VDD2, the current of the first PMOS tube MP1 is greater than the current of the third PMOS tube MP3, and the output of the control signal VDD_SEL is low; When the second power source VDD2 is greater than the first power source VDD1 , the current of the third PMOS transistor MP3 is greater than the current of the first PMOS transistor MP1 , and the output of the control signal VDD_SEL is high.
[0029] It should be noted that the first PMOS transistor MP1, the first NMOS transistor MN1, the third PMOS transistor MP3 and the third NMOS transistor MN3 form a current mirror, and the first NMOS transistor MN1 and the third NMOS transistor MN3 are in a mirror relationship, so the magnitude of I (MP1) and I (MN3) are the same. Since the gate of the first PMOS transistor MP1 is connected to the gate of the third PMOS transistor MP3, and their gate voltages are the same, the magnitude of the source voltage of the first PMOS transistor MP1 and the magnitude of the source voltage of the third PMOS transistor MP3 determine the magnitude relationship between I (MP1) and I (MP3), that is, the magnitude of the first power supply VDD1 and the magnitude of the second power supply VDD2 determine the magnitude relationship between I (MP1) and I (MP3). Specifically, when the first power supply VDD1 is greater than the second power supply VDD2, I(MP1)=I(MN3)>I(MP3), and the control signal VDD_SEL output is low, indicating that the first power supply VDD1 needs to be selected as the output voltage VOUT; when the second power supply VDD2 is greater than the first power supply VDD1, I(MP3)>I(MN3)=I(MP1), and the control signal VDD_SEL output is high, indicating that the second power supply VDD2 needs to be selected as the output voltage VOUT.
[0030] In this embodiment, the bias current generating module 100 and the power comparison module 200 of the power switching circuit are combined and arranged. By arranging a third PMOS transistor MP3 and a third NMOS transistor MN3 on the basis of the bias current generating module 100 to form a current mirror for power comparison, the area and power consumption of the power switching circuit are reduced.
[0031] In some embodiments, Figure 2 As shown, the power switching module 300 includes: a fourth PMOS tube MP4, a fifth PMOS tube MP5 and an inverter INV; The source of the fourth PMOS transistor MP4 is connected to the first power source VDD1, the drain is connected to the output voltage VOUT, and the gate is connected to the output end of the power comparison module 200; The source of the fifth PMOS transistor MP5 is connected to the second power supply VDD2, the drain is connected to the drain of the fourth PMOS transistor MP4, and the gate is connected to the output end of the inverter INV; The input end of the inverter INV is connected to the output end of the power comparison module 200; When the control signal VDD_SEL is low, the output of the inverter INV is high, the fourth PMOS tube MP4 is turned on, the fifth PMOS tube MP5 is turned off, and the output voltage VOUT is the first power supply VDD1; When the control signal VDD_SEL is output high, the output of the inverter INV is low, the fourth PMOS transistor MP4 is turned off, the fifth PMOS transistor MP5 is turned on, and the output voltage VOUT is the second power supply VDD2.
[0032] It should be noted that the working principle of the power switching module 300 is to control the switching of the fourth PMOS tube MP4 and the fifth PMOS tube MP5 through the control signal VDD_SEL. Specifically, the control signal VDD_SEL is connected to the gate of the fourth PMOS tube MP4 as the output of the power comparison module 200, and the control signal VDD_SEL is further connected to the gate of the fifth PMOS tube MP5 through the inverter INV, and the output voltage VOUT is connected to the drain of the fourth PMOS tube MP4 and the drain of the fifth PMOS tube MP5. Therefore, only one of the fourth PMOS tube MP4 and the fifth PMOS tube MP5 will be turned on at the same time, and output the corresponding power supply voltage to the output voltage VOUT. When the control signal VDD_SEL is output as low, the fourth PMOS tube MP4 is turned on, the fifth PMOS tube MP5 is turned off, and the source of the fourth PMOS tube MP4 is connected to the first power supply VDD1. At this time, the output voltage VOUT is equal to the first power supply VDD1; similarly, when the control signal VDD_SEL is output as high, the fifth PMOS tube MP5 is turned on, the fourth PMOS tube MP4 is turned off, and the source of the fifth PMOS tube MP5 is connected to the second power supply VDD2. At this time, the output voltage VOUT is equal to the second power supply VDD2.
[0033] In some embodiments, the inverter INV is a Schmitt INV.
[0034] It should be noted that when the size of the first power supply VDD1 is similar to the size of the second power supply VDD2, the size of I (MP3) is similar to the size of I (MN3). At this time, the output of the control signal VDD_SEL is unclear, resulting in frequent switching of the output voltage VOUT, which leads to problems such as mis-switching, noise and leakage in the circuit. Therefore, by using the INV of the Schmitt trigger type, the circuit's immunity to noise is improved while maintaining the function of the original power switching module 300. The Schmitt trigger is a comparator with hysteresis characteristics that can convert irregular signals into rectangular wave output signals. Specifically, the Schmitt trigger has two different threshold voltages, one for detecting the high threshold of the rising edge and the other for detecting the low threshold of the falling edge. When the voltage of the input Schmitt trigger exceeds the high threshold, the output flips to a low level; and when the voltage of the input Schmitt trigger is lower than the low threshold, the output flips to a high level. Therefore, the Schmitt INV can ensure that the input voltage has a sufficient amplitude change to trigger a change in state, thereby improving the circuit's immunity to noise.
[0035] In this embodiment, by setting the Schmit INV, the control signal VDD_SEL is connected to the gate of the fifth PMOS tube MP5 through the Schmit INV, thereby reducing the occurrence of erroneous switching and leakage when the first power supply VDD1 and the second power supply VDD2 are close in size, and improving the anti-noise capability of the power switching circuit.
[0036] In some embodiments, Figure 2 As shown, the power switching module 300 includes: a first capacitor C1; A first terminal of the first capacitor C1 is connected to the output voltage VOUT, and a second terminal of the first capacitor C1 is grounded.
[0037] It should be noted that the first capacitor C1 is located between the output voltage VOUT and the ground. The first capacitor C1 acts as a bypass of the output voltage VOUT, short-circuits the noise in the output voltage VOUT to the ground, and improves the purity of the output voltage VOUT. At the same time, when switching the power supply, the output voltage VOUT may experience transient voltage fluctuations, resulting in unstable output of the power switching circuit. The first capacitor C1 acts as a local energy storage element to help smooth the transient changes of the output voltage VOUT and improve the stability of the output voltage VOUT.
[0038] In this embodiment, by setting the first capacitor C1 bypass, the noise of the output voltage VOUT is reduced, the anti-noise capability of the power switching circuit is improved, and at the same time, the transient change of the output voltage VOUT during switching is reduced, and the stability of the power switching circuit is improved.
[0039] The above are only specific embodiments of the present invention, which enable those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features claimed herein.
Claims
1. A low-power power switching circuit, characterized in that: include: A bias current generating module, a power comparison module and a power switching module; The bias current generating module is used to generate a bias current and output the bias current to the power comparison module; The power comparison module is used to compare the first power supply (VDD1) and the second power supply (VDD2), and output a control signal (VDD_SEL) to the power switching module according to the comparison result; The power switching module is used to switch the output voltage (VOUT) according to the control signal (VDD_SEL).
2. A low-power power switching circuit according to claim 1, characterized in that: The bias current generating module comprises: a first PMOS tube (MP1), a second PMOS tube (MP2), a first NMOS tube (MN1), a second NMOS tube (MN2) and a first resistor (R1); The source of the first PMOS tube (MP1) is connected to the first power supply (VDD1), the drain is connected to the gate, and the gate is connected to the first input terminal of the power comparison module; The source of the first NMOS tube (MN1) is connected to the drain of the first PMOS tube (MP1), the drain is grounded, and the gate is connected to the second input terminal of the power comparison module; The source of the second PMOS tube (MP2) is connected to the first power supply (VDD1), the drain is connected to the gate of the first NMOS tube (MN1), and the gate is connected to the gate of the first PMOS tube (MP1); The source of the second NMOS tube (MN2) is connected to the drain of the second PMOS tube (MP2), the drain is connected to the first end of the first resistor (R1), and the gate is connected to the gate of the first NMOS tube (MN1); A second end of the first resistor (R1) is grounded.
3. A low-power power switching circuit according to claim 2, characterized in that: The area of the second NMOS transistor (MN2) is greater than the area of the first NMOS transistor (MN1).
4. The low-power power switching circuit according to claim 1, characterized in that: The power comparison module includes: a third PMOS tube (MP3) and a third NMOS tube (MN3); The source of the third PMOS tube (MP3) is connected to the second power supply (VDD2), the drain is connected to the input end of the power switching module, and the gate is connected to the first output end of the bias current generating module; The source of the third NMOS tube (MN3) is connected to the drain of the third PMOS tube (MP3), the drain is grounded, and the gate is connected to the second output end of the bias current generating module.
5. The low-power power switching circuit according to claim 1, characterized in that: The bias current generating module and the power supply comparing module form a current mirror, which specifically includes: The bias current generating module comprises: a first PMOS tube (MP1) and a first NMOS tube (MN1); The power comparison module includes: a third PMOS tube (MP3) and a third NMOS tube (MN3); The source of the first PMOS tube (MP1) is connected to the first power supply (VDD1), the drain is connected to the gate, and the gate is connected to the gate of the third PMOS tube (MP3); The source of the first NMOS tube (MN1) is connected to the drain of the first PMOS tube (MP1), the drain is grounded, and the gate is connected to the gate of the third NMOS tube (MN3); The source of the third PMOS tube (MP3) is connected to the second power supply (VDD2), and the drain is connected to the source of the third NMOS tube (MN3); The drain of the third NMOS tube (MN3) is grounded.
6. A low-power power switching circuit according to claim 5, characterized in that: When the first power supply (VDD1) is greater than the second power supply (VDD2), the current of the first PMOS tube (MP1) is greater than the current of the third PMOS tube (MP3), and the output of the control signal (VDD_SEL) is low; When the second power supply (VDD2) is greater than the first power supply (VDD1), the current of the third PMOS tube (MP3) is greater than the current of the first PMOS tube (MP1), and the output of the control signal (VDD_SEL) is high.
7. The low power consumption power switching circuit according to claim 1, characterized in that: The power switching module includes: a fourth PMOS tube (MP4), a fifth PMOS tube (MP5) and an inverter (INV); The source of the fourth PMOS tube (MP4) is connected to the first power supply (VDD1), the drain is connected to the output voltage (VOUT), and the gate is connected to the output end of the power comparison module; The source of the fifth PMOS tube (MP5) is connected to the second power supply (VDD2), the drain is connected to the drain of the fourth PMOS tube (MP4), and the gate is connected to the output end of the inverter (INV); An input end of the inverter (INV) is connected to an output end of the power comparison module.
8. The low-power power switching circuit according to claim 7, characterized in that: When the control signal (VDD_SEL) is outputted as low, the output of the inverter (INV) is high, the fourth PMOS tube (MP4) is turned on, the fifth PMOS tube (MP5) is turned off, and the output voltage (VOUT) is the first power supply (VDD1); When the control signal (VDD_SEL) is output high, the output of the inverter (INV) is low, the fourth PMOS tube (MP4) is turned off, the fifth PMOS tube (MP5) is turned on, and the output voltage (VOUT) is the second power supply (VDD2).
9. The low-power power switching circuit according to claim 7, characterized in that: The inverter (INV) is a Schmidt INV.
10. The low power consumption power switching circuit according to claim 1, characterized in that: The power switching module comprises: a first capacitor (C1); A first end of the first capacitor (C1) is connected to the output voltage (VOUT), and a second end is grounded.