Controller for resonant converter

Abstract

A controller for a resonant converter. The controller is configured to: receive a measured current signal representative of a current flowing in the resonant tank; receiving a measured voltage signal representative of a voltage at a predetermined point in the resonant tank; receiving a power setting signal defining a requested power level of the load; setting a protected power signal based on a time delay between a change in state of one of the first switch and the second switch and a subsequent zero crossing of the measured current signal; an upper voltage threshold and a lower threshold are set based on the lower of: i) the protected power signal; and ii) the power setting signal; in response to the measured voltage signal exceeding the upper limit voltage threshold, opening the first switch and closing the second switch; and in response to the measured voltage signal falling below the lower limit voltage threshold, opening the second switch and closing the first switch.

Description

Technical Field

[0001] The present disclosure relates to controllers and associated methods for resonant converters. Background Art

[0002] The possibility of resonant converters oscillating is a problem in the prior art. Summary of the invention

[0003] According to a first aspect of the present disclosure, a controller for a resonant converter is provided, wherein the resonant converter is used to supply electrical energy from a supply source to a load, and the resonant converter comprises:

[0004] a first switch and a second switch, the first switch and the second switch being connected in series with each other between a supply source and a reference terminal, wherein when the first switch is closed and the second switch is open, the resonant converter has a high-side switching half-cycle, and wherein when the first switch is open and the second switch is closed, the resonant converter has a low-side switching half-cycle; and

[0005] a resonant tank electrically connected to the first switch and the second switch, wherein the resonant tank includes a resonant capacitor;

[0006] The controller is configured to:

[0007] receiving a measured current signal representative of a current flowing in the resonant tank;

[0008] receiving a measured voltage signal representative of a voltage at a predetermined point in the resonant tank;

[0009] receiving a power setting signal defining a requested power level for the load;

[0010] setting a protected power signal based on a time delay between a change in state of one of the switches and a subsequent zero crossing of the measured current signal;

[0011] setting an upper voltage threshold and a lower voltage threshold based on the lower of: i) the protected power signal; and ii) the power setting signal;

[0012] In response to the measured voltage signal exceeding the upper voltage threshold, opening the first switch and closing the second switch; and

[0013] In response to the measured voltage signal falling below the lower voltage threshold, the second switch is opened and the first switch is closed.

[0014] Setting the upper voltage threshold and the lower voltage threshold in this manner can advantageously reduce the likelihood of the resonant converter entering a capacitive operation mode, thereby improving the performance of the resonant converter.

[0015] In one or more embodiments, the protected power signal corresponds to a power level at which the measured voltage signal will intersect: the upper voltage threshold during the high-side switching half cycle; and the lower voltage threshold during the low-side switching half cycle.

[0016] In one or more embodiments, the protected power signal is arranged such that its application causes:

[0017] a fixed distance between the end of a switching half-cycle and the next zero crossing of the measured current signal; or

[0018] An adaptive distance between the end of a switching half cycle and the next zero crossing of the measured current signal.

[0019] In one or more embodiments, the distance is represented by a time delay.

[0020] In one or more embodiments, the distance is represented as a value of an integral of the measured current signal between: the time when the state of one of the switches changes; and the time when the measured current signal next crosses zero.

[0021] In one or more embodiments, the controller is further configured to:

[0022] The protected power signal is set based on the lower of:

[0023] i) a time delay between a change of state of the first switch and a subsequent zero crossing of the measured current signal; and

[0024] ii) A time delay between a change of state of the second switch and a subsequent zero crossing of the measured current signal.

[0025] In one or more embodiments, operation of the resonant converter in accordance with the protected power signal causes a predetermined time delay between the change in state of one of the switches and the subsequent zero crossing of the measured current signal.

[0026] In one or more embodiments, operation of the resonant converter in accordance with the protected power signal causes a predetermined phase delay between the state change of one of the switches and the subsequent zero crossing of the measured current signal, wherein the phase delay corresponds to a proportion of a switching cycle.

[0027] In one or more embodiments, the controller is further configured to:

[0028] The protected power signal is set based on an integral of the measured current signal between: a time when the state of one of the switches changes state; and a time when the measured current signal next crosses zero.

[0029] In one or more embodiments, operation of the resonant converter in accordance with the protected power signal causes a predetermined value of an integral of the measured current signal between: the time when a state of one of the switches changes; and the time when the measured current signal next crosses zero.

[0030] In one or more embodiments, the controller is further configured to set the protected power signal based on the lower of:

[0031] i) an integration of the measured current signal between: the time when the state of the first switch changes; and the time when the measured current signal next crosses zero; and

[0032] ii) an integration of the measured current signal between: the time at which the state of the second switch changes; and the time at which the measured current signal next crosses zero.

[0033] In one or more embodiments, the controller is configured to set the protected power signal based on the lower of:

[0034] i) an integration of the measured current signal between: the time when the first switch is opened; and the time when the measured current signal next crosses zero; and

[0035] ii) an integration of the measured current signal between: the time when the second switch is opened; and the time when the measured current signal next crosses zero.

[0036] In one or more embodiments, the controller is configured to:

[0037] converting the time delay into a detected ratio of switching cycles; and

[0038] The protected power signal is set based on the detected proportion of the switching cycles.

[0039] Also disclosed is a resonant converter comprising any controller disclosed herein.

[0040] According to another aspect of the present disclosure, there is provided a method of operating a resonant converter, wherein the resonant converter is used to supply electrical energy from a supply source to a load, the resonant converter comprising:

[0041] a first switch and a second switch, the first switch and the second switch being connected in series with each other between a supply source and a reference terminal, wherein when the first switch is closed and the second switch is open, the resonant converter has a high-side switching half-cycle, and wherein when the first switch is open and the second switch is closed, the resonant converter has a low-side switching half-cycle; and

[0042] a resonant tank electrically connected to the first switch and the second switch, wherein the resonant tank includes a resonant capacitor;

[0043] The method comprises:

[0044] receiving a measured current signal representative of a current flowing in the resonant tank;

[0045] receiving a measured voltage signal representative of a voltage at a predetermined point in the resonant tank;

[0046] receiving a power setting signal defining a requested power level for the load;

[0047] setting a protected power signal based on a time delay between a change in state of one of the switches and a subsequent zero crossing of the measured current signal;

[0048] setting an upper voltage threshold and a lower voltage threshold based on the lower of: i) the protected power signal; and ii) the power setting signal;

[0049] In response to the measured voltage signal exceeding the upper voltage threshold, opening the first switch and closing the second switch; and

[0050] In response to the measured voltage signal falling below the lower voltage threshold, the second switch is opened and the first switch is closed.

[0051] Although the present disclosure allows various modifications and alternative forms, the details have been shown in the drawings by way of example and will be described in detail. However, it should be understood that other embodiments other than the specific embodiments described are also possible. All modifications, equivalents and alternative embodiments falling within the spirit and scope of the appended claims are also encompassed.

[0052] The above discussion is not intended to represent every example embodiment or every implementation within the scope of the current or future claim sets. The following figures and detailed description also illustrate various example embodiments. The various example embodiments can be more fully understood by considering the following detailed description in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0054] Figure 1 A resonant converter is shown as part of the overall power supply;

[0055] Figure 2A and Figure 2B The basic principle of capacitor voltage control for a resonant converter is shown, where the resonant capacitor is on the ground side (shunt);

[0056] Figure 3 An example embodiment of a resonant converter is shown, the resonant converter including a controller according to the present disclosure;

[0057] Figure 4 shows the case where the capacitor mode feedback loop is not enabled. Figure 3 A timing diagram of the operation of the resonant converter;

[0058] Figure 5 shows a graph of the half-bridge node (Vhb, upper curve) versus the resonant current (Icr, lower curve);

[0059] Figure 6 shows a top-level block diagram of a time-based capacitive mode control interface;

[0060] Fig. 7A and Figure 7B shows a detailed block diagram of a time-based capacitor mode control loop;

[0061] Figure 8 Detailed block diagram showing the delay measurement setup between Vhb commutation and resonant current zero crossing;

[0062] Fig. 9 Shows a way to measure the actual delay dT and a way to average the actual delay dT using an IIR function to obtain Tmeet;

[0063] Fig.10 The min delay function and the error signal function are shown;

[0064] Fig.11 shows a block diagram showing the calculation of phase error and connection to a capacitive mode control loop;

[0065] Fig. 12A and Fig. 12B shows a power control block diagram;

[0066] Fig.13 shows the relationship between the converter switching period and the DCM-CCM mode; and

[0067] Fig.14An example embodiment of a method of operating a resonant converter according to the present disclosure is shown. DETAILED DESCRIPTION

[0068] The present disclosure relates to a resonant power converter including a regulated capacitive mode prevention control function. As will be discussed below, the examples disclosed herein can reduce the likelihood of capacitive mode oscillations by reducing the power of the converter to maintain a certain distance from the capacitive mode boundary.

[0069] The resonant power converter may use a half-cycle-by-half-cycle shutdown mechanism that involves sensing the resonant capacitor voltage (Vcap) and comparing Vcap to a power reference level for closed loop operation. This may be referred to as capacitor voltage control. Instead of directly controlling the switch by forcing the switching frequency, the switching frequency is generated by the Vcap control mechanism.

[0070] Figure 1 A resonant converter is shown as part of the overall power supply, which in this example is used in an adapter. The adapter includes the following blocks:

[0071] ●Active bridge controller (power rectification);

[0072] PFC controller section (power factor correction using boost converter architecture);

[0073] The resonant LLC controller section (driving half-bridge stage plus LLC resonant tank including tapped winding transformer); and

[0074] ●SR controller (synchronous rectifier stage for generating the rectified output voltage Vout).

[0075] The resonant converter can be sized using the first harmonic approximation. In addition, controlling the output power using the capacitor voltage control method can provide the following advantages:

[0076] ●Possibility to use a dedicated low power mode.

[0077] • Better dynamics, since the delivered power follows the set point of the resonant tank variable almost instantly. This simplifies the control loop design.

[0078] The resonant converter may have a resonant capacitor in series with the half-bridge node, and the information for controlling the switch may be derived from the voltage across the resonant capacitor (the side not connected to the half-bridge node).

[0079] This method actually senses the voltage across the transformer, and therefore the DC component of the sensed signal is zero. In some applications, the high voltage signal at the resonant capacitor / transformer node should be attenuated to a low voltage signal that can be processed by an integrated circuit (IC). For this purpose, a capacitive voltage divider can be used, because a resistive voltage divider may provide undesirable low-pass filtering. Due to the fact that the DC component is zero, no information about the DC component is needed, so a capacitive voltage divider (which cannot transmit a DC component) is sufficient.

[0080] As an alternative, the resonant capacitor can also be placed in the ground branch in series with the primary winding of the transformer, such as Figure 1 as shown in .

[0081] Figure 2A and Figure 2B The basic principle of capacitor voltage control for a resonant converter is shown, where the resonant capacitor is on the ground side (shunted). That is, the resonant capacitor is shunted between ground and the voltage source (Vbus) in order to reduce the ripple current in the ground path and the supply path.

[0082] Figure 2A and Figure 2B The timing control principle of the switch using this embodiment is also shown.

[0083] Figure 2A and Figure 2B The resonant converter includes a controller (not shown) that operates a first controllable switch and a second controllable switch arranged in series. These switches are connected between a supply source (Vbus) and a reference terminal (ground). The controller controls the first high-side switch using a signal marked as gh. The controller controls the second low-side switch using a signal marked as gl. The voltage at the half-bridge node (the node between the high-side switch and the low-side switch) is marked as Vhb.

[0084] The controller receives a measured voltage signal (Vcr) representing the voltage at a predetermined point in the resonant tank. In this example, the measured voltage signal (Vcr) represents the voltage across the resonant capacitor. Figure 2A and Figure 2BAs shown in , the controller compares the measured voltage signal (Vcr) with the upper voltage threshold (VCRH) and the lower threshold (VCRL). Based on the comparison, the switch half cycle ends. More specifically, in response to the measured voltage signal (Vcr) exceeding the upper voltage threshold (VCRH), the second low-side switch is closed, and the first high-side switch is disconnected. In response to the measured voltage signal (Vcr) falling below the lower voltage threshold (VCRL), the second low-side switch is disconnected, and the first high-side switch is closed. It should be understood that in an alternative embodiment of the full bridge, the polarity of the signal can be reversed so that: in response to the reversed measured voltage signal (Vcr) falling below the lower voltage threshold, the second low-side switch is closed, and the first high-side switch is disconnected; and in response to the measured voltage signal (Vcr) exceeding the upper voltage threshold, the second low-side switch is disconnected, and the first high-side switch is closed. In this example, a non-overlapping time is implemented after one of the switches is disconnected and before the other switch is closed. In this way, there is a slight delay between the end of one half cycle and the beginning of the next half cycle. For simplicity, the attenuation of the Vcr voltage for the controller IC is not included. Figure 2A and Figure 2B middle.

[0085] for Figure 2A and Figure 2B As shown in the graph, the resonant converter uses an input voltage Vbus of 400V, and therefore Vhb switches between 400V and 0V. For this example:

[0086] ΔV = 360-40 = 320V;

[0087] VCRH = Vbus / 2 + ΔV / 2 = 200 + 160 = 360 V; and

[0088] VCRl=Vbus / 2-ΔV / 2=200-160=40V.

[0089] gh and gl have an amplitude of 1V, which is a convenient representation of true = 1 and false = 0.

[0090] Figure 2A and Figure 2B The setting of also takes into account the DC component of the resonant capacitor. The DC component is defined by the input voltage to the half-bridge (Vbus) multiplied by the duty cycle of the half-bridge voltage (typically Vbus / 2 at 50% duty cycle operation).

[0091] Due to parasitics, in practice, the capacitive divider cannot represent the DC component of the resonant capacitor due to leakage, and the resistive divider cannot reliably attenuate the high frequency part of the Vcr signal due to parasitic capacitance. In the case of a resistive divider and a capacitive divider in parallel, it is difficult to maintain the same attenuation ratio due to component tolerances. The DC component across the capacitive divider (and optionally the resistive divider in parallel) can be restored in a practical circuit by adding a so-called symmetry loop.

[0092] The symmetry loop compares the measured duty cycle with the expected value of 50% and corrects the capacitive divider DC component so that a 50% duty cycle is achieved. The switch, together with the voltage divider, produces a DC component at the voltage divider. This DC component, together with the vcrh level and the vcrl level, defines the duty cycle and symmetry / asymmetry. The DC symmetry loop senses the duty cycle and adjusts the DC value so that a 50% duty cycle occurs with a symmetrical half cycle. The symmetry loop can rely on completing each half cycle by Vcr crossing one of the thresholds (VRCH or VCRL) so that a direct correlation is maintained with the divided resonant capacitor voltage. This includes the DC level and the difference between the two threshold levels (VRCH or VCRL).

[0093] The following includes calculations based on ΔV Figure 2A and Figure 2B The converted power of the resonant converter is ΔV, which is the difference between two threshold levels VCRH and VCRL (these thresholds may also be referred to as vcaph and vcapl).

[0094] ●ΔV across Cr between the start and end of each half cycle => charge difference

[0095] ○Power = average current × input voltage = I × Vbus

[0096] ○I=Q×Fswitch

[0097] ○Q=Cr×ΔV

[0098] ○Power = Cr × ΔV × Fswitch × Vbus can be set according to the switch cycle

[0099] It can be seen that the converted energy per switching cycle is proportional to ΔV.

[0100] The transfer function of the LLC resonant tank circuit shows a frequency response with two characteristic peaks. Typically, the LLC converter operates in a region where the transfer function is dominated by the inductance of the circuit. This mode of operation is called inductive mode and will achieve safe operation of the converter with zero voltage switching.

[0101] During operation, the steady-state operating point shifts along the voltage gain transfer curve depending on, for example, the load current and the input bus voltage (Vbus) in order to provide the required power at the desired output voltage. If the operating point becomes close to the low frequency resonant peak or when the operating point is below the low frequency resonant peak, the converter is said to operate in capacitive mode. If no action is taken, a large asymmetry between the rectified half cycles of the secondary current will result. This is because the symmetry loop controls the symmetry via the capacitor voltage control, but since the circuit is in capacitive mode, the capacitor voltage control is overruled. Therefore, the symmetry loop becomes an open loop and the symmetry cannot be properly controlled.

[0102] During voltage or current transients, the converter's operating frequency will shift along the transfer function depending on the load conditions and eventually settle to a stable steady-state point. Changes in input voltage, load current, or output voltage may cause the operating point to shift too much in the direction of lower frequencies. This may cause the converter to behave erratically because the operating point becomes too close to capacitive operation mode.

[0103] If the converter becomes unstable due to operating too close to the capacitor mode set point, a large change in input voltage or load current is required to recover from this condition and return to a stable operating point again.

[0104] Although the amount of energy transferred per switching cycle is proportional to ΔV, there is no guarantee that this energy transfer will occur under all circumstances.

[0105] As ΔV increases, it causes the resonance amplitude to be larger. However, the larger amplitude also causes the resonant current to become closer to zero at the end of each half cycle. If the moment when the resonant current becomes zero coincides with the moment when the half cycle is completed, this is called the capacitive mode boundary. Since the dv / dt of Vcr is proportional to the resonant current, no larger power transfer is possible. This means Figure 2A and Figure 2B The Vcr voltage will not be able to reach the VCRH and VCRL levels because the peak of the Vcr voltage cannot get higher. In other words, when the resonant current crosses zero before the half cycle is completed, the Vcap peak-to-peak voltage is too small and remains between VCRH and VCRL. Once the current has crossed zero, the Vcr voltage level will start to decrease or increase in the opposite direction towards the DC level.

[0106] In more detail, the region around the capacitive mode can be divided into two sub-regions:

[0107] ● Near Capacitive Mode : Partial hard switching, while the primary current at the start of the half-bridge slope is still in the appropriate direction to charge the half-bridge node towards the opposite supply rail (partially).

[0108] ● Capacitive Mode : Full hard switching, with the primary current already in the opposite direction at the start of the half-bridge slope (capacitive mode is destructive for switching).

[0109] If it is expected that control using the normal regulation loop will cause the resonant converter to operate too close to a capacitive mode of operation, examples of the present disclosure use a so-called capacitive mode feedback loop to reduce the energy transfer per switching cycle. The capacitive mode feedback loop reduces the energy transfer only when necessary due to limited operating conditions.

[0110] Figure 3 An example embodiment of a resonant converter 300 is shown, the resonant converter 300 including a controller 301 according to the present disclosure. The resonant converter 300 is used to supply power from a supply source (Vbus) to a load at the secondary side of a transformer. The resonant converter 300 is described above with reference to Figure 2A and Figure 2B The capacitor voltage control method is described for control.

[0111] The resonant converter includes a first switch 302 and a second switch 303 connected in series with each other between a supply source (Vbus) 304 and a reference terminal (ground in this example) 305. When the first switch 302 is closed and the second switch 303 is open, the resonant converter 300 has a high-side switching half-cycle. When the first switch 302 is open and the second switch 303 is closed, the resonant converter also has a low-side switching half-cycle. The resonant converter 300 also has a resonant tank electrically connected to the first switch 302 and the second switch 303. In this example, the resonant tank includes a resonant capacitor (Cr) and two inductors (Lr and Lm, where the resonant inductor Lr is generally defined by the leakage inductance of the transformer), one of the two inductors being the primary winding of the transformer. The transformer has a secondary winding connected to the secondary side of the resonant converter 300. Therefore, Figure 3 The resonant converter 300 is an LLC converter (because the resonant tank includes two inductors and one capacitor), but it should be understood that the examples disclosed herein can be used with different types of resonant converters having different types of resonant tanks.

[0112] The controller 301 receives a measured current signal (Ires) 306 representing the current flowing in the resonant tank. In this example, the current flowing through Cr and Lr is sensed to provide the measured current signal (Ires) 306. However, it should be appreciated that in other examples, the current in the resonant tank may be sensed at a different location. The controller 301 also receives a measured voltage signal (Vcr) 307 representing the voltage at a predetermined point in the resonant tank. In this example, the voltage dropped across the resonant capacitor (Cr) is sensed to provide the measured voltage signal (Vcr) 307. However, it should be appreciated that in other examples, the voltage dropped across different components in the resonant tank may be sensed.

[0113] In this example, the controller 301 includes a normal mode regulator functional block 308. The normal mode regulator 308 processes the feedback signal from the secondary side of the resonant converter to provide a power setting signal (Ps). The power setting signal (Ps) defines the requested power level of the load. Therefore, in this example, the power setting signal (Ps) is generated by the controller 301 itself. In other examples, the controller 301 can receive the power setting signal (Ps) from another component associated with the resonant converter 300.

[0114] In this example, the controller 301 also includes a capacitive mode distance detector 310 and a capacitive mode regulator 311, which together set the protected power signal (Pr). The protected power signal is based (directly or indirectly) on the time delay between the state change of one of the switches and the subsequent zero crossing of the measured current signal (Ires) 306. The capacitive mode distance detector 310 receives a Vhb slope start signal, which provides an indication of when one of the switches 302, 303 changes state. It should be understood that the change in voltage at the half-bridge node is only one of several ways in which a state change of one of the switches 302, 303 can be detected. The capacitive mode distance detector 310 also receives the measured current signal (Ires) 306, so that the zero crossing of the measured current signal (Ires) 306 after the state change of one of the switches 302, 303 can be identified. As will be discussed in detail below, the controller 301 may set the protected power signal (Pr) 312 directly based on the time delay between the change in state of one of the switches and the subsequent zero crossing of the measured current signal (Ires) 306. Alternatively, the controller 301 may set the protected power signal (Pr) 312 based on the integral of the measured current signal (Ires) between: the time when the state of one of the switches changes state; and the time of the next zero crossing of the measured current signal; thereby indirectly setting the protected power signal based on the time delay between the change in state of one of the switches and the subsequent zero crossing of the measured current signal.

[0115] Figure 3 The controller 301 also includes a minimum detector block 313 that selects the lowest of: i) the protected power signal (Pr) 312; and ii) the power setting signal (Ps) 309. The minimum detector block 313 then provides the signal to the control block 314. The control block 314 sets an upper voltage threshold (VCRH) and a lower threshold (VCRL) based on the lower of: i) the protected power signal (Pr) 312; and ii) the power setting signal (Ps) 309. In this way, if the power setting signal (Ps) 309 becomes too high, such that the operation of the resonant converter is deemed too close to the capacitive mode boundary, the protected power signal (Pr) 312 can take over. As will be discussed in detail below, setting the upper voltage threshold (VCRH) and the lower threshold (VCRL) in this manner can advantageously reduce the likelihood that the resonant converter 300 enters a capacitive mode of operation, thereby improving the performance of the resonant converter 300.

[0116] In the same manner as discussed above, the controller 301 then operates the first switch 302 and the second switch 303 as follows:

[0117] In response to the measured voltage signal (Vcr) 305 exceeding the upper voltage threshold (VCRH), opening the first switch 302 and closing the second switch 303; and

[0118] In response to the measured voltage signal (Vcr) 305 falling below the lower voltage threshold (VCRL), the second switch 303 is opened and the first switch 302 is closed (there may be a non-overlapping delay between the 2 switching operations).

[0119] Also in the same manner as discussed above, a non-overlap time may be implemented after opening one of the switches and before closing the other switch.

[0120] The capacitive mode distance detector 310 and the capacitive mode regulator 311 are implemented such that when the measured distance between a change in state of one of the switches and a subsequent zero crossing of the measured current signal (which may simply be a detected time delay, or a parameter derived from the detected time delay, such as the integral of the measured current signal (Ires) 306 over the period) falls below a predefined threshold, the controller reduces the ΔV level. Figure 3This functionality is performed by having a capacitive mode regulation loop (providing a protected power signal (Pr) 312) take over from the normal feedback control loop (providing a power setting signal (Ps) 309) in this example. In this case, the capacitive mode feedback loop regulates the output power of the resonant converter 300 so that the converter remains operating in a predefined mode close to the capacitive mode. That is, not too close to the capacitive mode. In this way, it is possible to reduce power and maintain a predefined safe distance from the capacitive mode boundary. This is achieved by defining the end of the switching half cycle using the same control mechanism as the VCRH and VCRL levels. When the operating conditions that cause the normal control feedback control loop to approach the capacitive operating mode are removed, the ΔV level control will automatically be taken over by the normal feedback loop because the power setting signal (Ps) 309 will drop back below the protected power signal (Pr) 312.

[0121] Figure 4 shows the case where the capacitor mode feedback loop is not enabled. Figure 3 The timing diagram of the operation of the resonant converter. That is, the first switch and the second switch of the resonant converter are controlled by the normal feedback control loop. Figure 4 For each of the graphs, time is shown on the horizontal axis.

[0122] Figure 4 The uppermost graph in 400 shows the control signals of the first and second switches. The control signal (gh) of the first high-side switch is identified by reference numeral 420. The control signal (gl) of the second low-side switch is identified by reference numeral 421.

[0123] The second graph shows the current (Ires) 422 through the resonant tank. Also shown in the second graph are: a magnetizing current 427, an upper current threshold (Iend_pos) 428, and a lower current threshold (Iend_neg) 429.

[0124] Figure 4 The third graph in shows the measured voltage signal (Vcr) 423 , together with an upper voltage threshold (VCRH) 424 and a lower voltage threshold (VCRL) 425 .

[0125] at last, Figure 4 The lowermost graph in shows the value of ΔV 426 ; ie, the difference between the upper voltage threshold (VCRH) 424 and the lower voltage threshold (VCRL) 425 .

[0126] Figure 4 It is shown that as the power requested by the load increases, as provided by the increasing value of the power setting signal (Ps), the value of ΔV 426 also increases. Figure 4, the measured voltage signal (Vcr) 423 is able to reach an upper voltage threshold (VCRH) 424 and a lower voltage threshold (VCRL) 425. As discussed above, it is the intersection between the measured voltage signal (Vcr) 423 and one of the thresholds (VCRH, VCRL) 424, 425 that triggers the controller of the resonant converter to change the state of the first switch and the second switch (e.g. Figure 4 However, for Figure 4 In about the last third of the graph shown in , the measured voltage signal (Vcr) 423 does not reach the upper voltage threshold (VCRH) 424 and the lower voltage threshold (VCRL) 425. This means that the resonant converter is not operating in the capacitive operation mode undesirably. Figure 4 , in this operating mode, the controller of the resonant converter changes the state of the first switch and the second switch when the current (Ires) 422 through the resonant tank crosses: an upper current threshold (Iend_pos) 428 of the high-side switching half cycle, and a lower current threshold (Iend_neg) 429 of the low-side switching half cycle.

[0127] Figure 3 The advantage of the capacitive mode feedback loop is that the resonant converter is less likely to enter capacitive mode, during which Vcr 423 does not reach the upper threshold (VCRH) 424 and the lower threshold (VCRL) 425. Figure 4 Not shown in , this is because the level of the protected power signal (Pr) is set so that if the normal feedback control is to provide a power setting signal (Ps) that will make ΔV impossible to achieve, the power setting signal (Ps) will exceed the value of the protected power signal (Pr). Therefore, the protected power signal (Pr) will become lower than the power setting signal (Ps). In this case, it is the protected power signal (Pr) that is used to set the values ​​of the upper voltage threshold (VCRH) and the lower voltage threshold (VCRL), and therefore ΔV is also set. Therefore, the protected power signal (Pr) can be set to a value that prevents the resonant converter from entering the capacitive operation mode. In other words, the protected power signal (Pr) corresponds to the power level at which the measured voltage signal (Vcr) 423 will intersect with: the upper voltage threshold (VCRH) during the high-side switch half cycle; and the lower voltage threshold (VCRL) during the low-side switch half cycle.

[0128] In addition, use Figure 3The capacitive mode feedback loop means that the resonant converter is unlikely to complete the switching half-cycle by having Ires 422 cross Iend_pos 428 or Iend_neg 429 during some half-cycles and Vcr 423 cross VCRH 424 or VCRL 425 in other half-cycles. Such switching will result in irregular switching behavior and will also cause complications for the symmetrical loop because the symmetrical loop relies on double-sided Vcr 423 control (i.e., the end of both half-cycles is defined by Vcr 423 crossing VCRH 424 or VCRL 425).

[0129] Additional details of a regulated capacitive mode prevention method will now be provided, wherein the energy transfer per switching cycle is reduced and controlled via a capacitive mode feedback loop. Due to limiting operating conditions, the loop reduces energy transfer only when needed. The control loop can check the distance from the capacitive mode boundary based on time (phase) or area (charge) measurements. In this context, "distance" can be considered to be directly or indirectly based on the time delay between a change of state of one of the switches and a subsequent zero crossing of the current in the resonant tank.

[0130] Such an example may be considered as a resonant converter controller comprising a regulation loop that regulates the power level back based on the detected distance to the near capacitive mode boundary and is able to maintain a predefined distance to the (near) capacitive mode region. The distance may be used to define an error signal in order to regulate the instantaneous power back.

[0131] The basic idea behind a detector that detects the distance to a near capacitive mode boundary will now be described.

[0132] The near capacitive mode region is the region where, during the non-overlapping time between two half cycles, there is not enough energy available to charge the switch node to the opposite supply rail as required to maintain soft switching. This energy is determined by the capacitance Chb to ground at the half-bridge node and the supply voltage Vsupply as follows:

[0133] W=1 / 2.Chb.Vsupply 2

[0134] Therefore, to prevent the converter from operating in the near-capacitive mode region or the capacitive mode region, sufficient energy needs to be available that is greater than W in the above equation.

[0135] In connection with the resonant tank, the energy used to charge the half-bridge node is stored in the resonant tank.

[0136] Figure 5A graph of the half-bridge node (Vhb, upper curve) versus the resonant current (Icr, lower curve) is shown. For the left graph, Vbus = 400V and Iload = 20A, where Iload is the current through the load. For the right graph, Vbus = 400V and Iload,max = 42.6A.

[0137] In the near-capacitive mode region, as represented by the right-hand graph, Vhb reaches a valley or top and then retreats because Icr reaches zero and changes sign at the top or valley. There is a zero time delay between the change in state of the switch and the subsequent zero crossing of the measured current signal. Based on the requirement that hard switching should be prevented (as occurs in the left-hand graph), there needs to be enough energy available to prevent Icr from reaching zero before the start of the next half cycle. For the left-hand graph, there is a time delay of 23° between the change in state of the switch and the subsequent zero crossing of the measured current signal. That is, a phase delay of 23 degrees is taken from the spectrum diagram as the phase difference between: i) the moment when Vhb crosses 0; and ii) the moment when Icr crosses 0. Any time delay described herein can be expressed as an absolute value (i.e., in seconds) or as a ratio of one switching cycle or half a switching cycle (e.g., in degrees or radians).

[0138] Based on the requirements, a criterion representing a specific distance from the near capacitive mode region can be derived. The proposed criterion is related to the energy stored in the resonant inductor. The energy delivered to the half-bridge capacitor is defined as:

[0139]

[0140] Here, t1 defines the moment when the first switch opens, allowing the HB node to charge towards the opposite supply rail. t2 defines the moment when the peak voltage at Chb is reached (reaching the valley or top of the opposite supply rail voltage), which represents the zero crossing of the measured current signal.

[0141] Ideally, one could calculate the integral between t1 and t2 by sensing both Vhb and Ires, and then use the calculated value as a representation of the distance to the capacitive mode boundary.

[0142] When more energy is available than the minimum required, the result is that Vhb remains at the supply rail, while energy from the resonant tank is still delivered to the half-bridge node. This basically means that the excess energy is delivered back to the supply source.

[0143] Return to Figure 3, the capacitive further distance detector output signal is an input to a capacitive mode regulator block 311 which compares the distance detector output signal with a reference value and produces a protected power signal (Pr) 312. This reference value may be set such that regulation using the protected power signal (pr) 312 causes: i) a predetermined time delay between a change in state of one of the switches and a subsequent zero crossing of the measured current signal; or ii) a predetermined phase delay between a change in state of one of the switches and a subsequent zero crossing of the measured current signal; or iii) a predetermined value of the integral of the measured current signal (Ires) 306 between a change in state of one of the switches and a subsequent zero crossing of the measured current signal. Each of these alternatives may be considered to operate the resonant converter such that a predefined distance from the capacitive mode boundary is maintained.

[0144] The protected power signal (Pr) 312 is the regulator output that is provided to the minimum detector block 313. As discussed above, the minimum detector block 313 then takes the minimum of the normal regulator output (represented by the power setting signal (Ps) 309) and the capacitive mode regulator (represented by the protected power signal (Pr) 312). The result will be that in normal conditions where the system is operating at a sufficiently large distance from the capacitive mode boundary, the normal control loop regulates the power delivered to the load.

[0145] When the distance to the capacitive mode boundary is less than the reference value used by the capacitive mode regulator block 311, the capacitive mode control loop takes over and forces the output power level below the normal power control level. The lowest level of the two control loops determines the output power delivered to the load, which in this case is the capacitive mode control loop.

[0146] The second general feature includes separate distance detection of the near capacitive mode boundary for both half cycles. The resonant converter can also be used asymmetrically or asymmetrically in temporary situations. Since the symmetrical loop is not yet stable, it may happen that one half cycle operates in the near capacitive mode region and the other half cycle does not operate in the near capacitive mode region.

[0147] Therefore, the distance detector detects the distance of each half cycle and takes the minimum of the two distances as the most critical distance for the capacitive mode regulator.

[0148] Figure 3Another feature that the resonant converter of can provide is that the primary signal and replica function can be applied to prevent overshoot when taking over power control between the two regulators. If the normal mode regulator 308 controls the output power as the primary signal (its control signal is the lowest of the two signals), the output signal of the capacitor mode regulator 311 (i.e., the protected power signal (Pr) 312) can be set to be slightly higher than the output signal of the normal mode regulator 308 (i.e., the power setting signal (Ps) 309) instead of clipping it to the maximum value. When the capacitor mode regulator 311 output signal (i.e., the protected power signal (Pr) 312) takes over control, it does not need to be adjusted back within a large range, because this will cause a disabling time and overshoot. This also applies to another situation, where the capacitor mode regulator 311 is the primary signal, and the normal mode regulator 308 output signal (i.e., the power setting signal (Ps) 309) can be set to be slightly higher than the capacitor mode regulator 311 output signal (i.e., the protected power signal (Pr) 312) instead of clipping it to the maximum value. When the normal mode regulator 308 takes over power control, it does not need to adjust back over a larger range, as this will also result in dead time and overshoot. In this way, the primary signal and replica functions can be applied so that the signal that defines the power is the primary signal, and another signal that follows (e.g., at a predefined distance) is the replica.

[0149] refer to Figure 3 The method described is the most accurate representation of the measured "distance" to the near capacitive mode boundary. However, the method described may also be relatively complex to implement. Therefore, in other embodiments, simplifications are used.

[0150] The first simplification involves removing the Vhb signal from the integral of equation (1) above (replacing it with a constant). Thus, the "distance" between a change of state of one of the switches and the subsequent zero crossing of the measured current signal is defined as:

[0151]

[0152] Further simplification can be achieved by omitting the Ires signal and treating it as a constant as well. In this case, only the duration between t1 and t2 contains information about the distance. This is called a "time-based capacitive mode control method" because only the timing information is used, which makes the digital implementation simpler because no analog values ​​are required.

[0153] Next, an embodiment of a time-based capacitive mode control method is described.For the time-based version, as explained below, some additional functionality is used to compensate for the lack of knowledge of not taking into account the omitted signals.

[0154] Figure 6shows a top-level block diagram of a time-based capacitive mode control interface.

[0155] The main input signals, parameters and output signals are depicted and specified as follows:

[0156] ●Two input signals:

[0157] 1. Minimum time of two half-cycle delays, measured between half-bridge voltage commutation and primary current zero crossing.

[0158] 2. The instantaneous cycle period, which is used to indirectly determine the converter’s DCM-CCM operation mode (discontinuous conduction mode-continuous conduction mode).

[0159] ●Two parameters:

[0160] 1. Tdelay specifies the minimum delay between Vhb commutation (ie, the change in state of the first and second switches, which defines the start and end of a switching half-cycle) and the primary current zero crossing when the cycle period is equal to Tcross-over.

[0161] 2. Tcross-over specifies the converter cycle period, where the Tdelay parameter is used as the minimum delay between Vhb commutation and primary current zero crossing.

[0162] ●One output signal:

[0163] 1. Capacitor mode power control takes precedence over output power control to achieve the desired minimum delay between Vhb commutation and primary current zero crossing. Capacitor mode control is only effective when the power control output level is adjusted below the normal power level, which can be set by the optocoupler control loop. If the measured delay is greater than the minimum delay, the delivered output power is limited by the normal power level. In this case, capacitor mode control is invalid and its power control level remains a small distance (e.g., 0.2=20%) above the normal power control level.

[0164] Fig. 7A and Figure 7B A detailed block diagram of a time-based capacitive mode control loop is shown. This diagram contains three main blocks that implement the required functionality.

[0165] The left block measures the converter cycle period (Tperiod) and the delays between the commutation of Vhb and the zero crossing of ICres (Tmeas,h and Tmeas,l). A timer with a resolution of 20ns starts counting at the rising and falling edges of the slope_HB signal. If the snscurllc comparator detects a zero crossing of the resonant capacitor current, the timer captures the Tmeas,h and Tmeas,l count values ​​for two half cycles. The minimum of the two count values ​​is considered the most critical delay for this cycle period. When there is an asymmetry, one of the two cases will occur first. Therefore, the distance to the capacitive mode is limited by the minimum value.

[0166] This means that the resonant converter can set the protected power signal (Pr) based on the lower of:

[0167] i) a time delay between a change of state of the first switch and a subsequent zero crossing of the measured current signal; and

[0168] ii) The time delay between the change of state of the second switch and the subsequent zero crossing of the measured current signal.

[0169] In the example where the distance between the change of state of the switch and the subsequent zero crossing of the measured current signal is measured as the integral of the measured current signal over this time period, the protected power signal (Pr) may be set based on the lower of:

[0170] i) integration of the measured current signal between a change of state of the first switch and a subsequent zero crossing of the measured current signal; and

[0171] ii) Integration of the measured current signal between a change of state of the second switch and a subsequent zero crossing of the measured current signal.

[0172] In addition, the effective minimum delay (Tdelay_eff) that must be maintained between Vhb commutation and ICres current zero crossing is determined. The effective delay (Tdelay_eff) is subtracted from the measured delay. This produces a correction signal (Tcor) for the control loop that will maintain the minimum delay when capacitive mode control is active. The effective delay (Tdelay_eff) depends on the converter switching period (Tperiod) and two parameters that are predefined for each use case.

[0173] The crossover parameter (Tcross-over) typically defines the converter period between CCM mode and DCM mode. The associated delay parameter (Tdelay) specifies the minimum delay at the crossover cycle period to prevent capacitive mode oscillations. A timer with a resolution of, for example, 20ns measures the converter cycle period. The timer is started in state 1 (LCC_EC) and captures the count value in state 5 (decision). State 1 and state 5 are part of the main control state machine in the simplified model and are used here only as a reference. After passing through a first-order low-pass filter with a bandwidth of, for example, 7.5kHz, the average measured cycle period (Tperiod) is generated.

[0174] Next, a quadratic transfer function is implemented that modulates the effective delay (Tdelay_eff) as a function of the converter cycle period. First, the normalized converter period is obtained by dividing the cycle period by the crossover parameter (Tcross-over). The result is clipped so that the effective delay can only vary between zero and 1.5*Tdelay. If the converter is operated at the crossover frequency (Tperiod=Tcross-over), the effective delay corresponds exactly to the value of the Tdelay parameter.

[0175] Long cycle periods above Tcross-over are associated with DCM mode, and the effective delay increases. This mechanism creates more margin and robustness to avoid capacitive mode oscillations. On the other hand, short cycle periods below Tcross-over are associated with CCM mode, and the effective delay is significantly reduced. This time more output power can be delivered because the distance to the capacitive mode boundary is greater.

[0176] The upper right block implements a control loop that maintains a minimum delay between Vhb commutation and ICres zero crossing. This is achieved by integrating the error resulting from comparing the correction delay (Tcor) to zero (Tref). The correction delay is divided by the cycle period (normalized) to make the control loop response independent of frequency. If the correction delay is positive, capacitive mode control is invalid. In this case, the capacitive mode power control signal (ctrl_p_caplim) is forced to a level (max_delta) that is maintained, for example, 20% higher than the normal power control signal (ctrl_p_nocaplim).

[0177] When the correction delay falls below zero, the capacitive mode power control signal (ctrl_p_caplim) falls below normal power control and capacitive mode control becomes active. The control loop now adjusts the output power so that the error injected into the integrator becomes zero. This causes the correction delay (Tcor) to be zero when steady state is reached and thus maintains the desired minimum delay between Vhb commutation and ICres zero crossing.

[0178] The lower right block controls the low and high levels of the Vcap comparator (vcrl and vcrh). The minimum of the two power control signals (ctrl_p) adjusts the comparator levels symmetrically about the 2.5V reference. By changing the levels, the power delivered to the output is controlled.

[0179] Figure 8 Figure 1 shows a detailed block diagram of the delay measurement setup between Vhb commutation and ICres zero crossing. Figure 8 Included are graphs of the Vhb voltage (lower graph) and ICres current (reference numeral 830 in the upper graph). Also indicated in the graphs are the half-cycle delays (Tmeasl and Tmeash) measured at the output of the integ_ncm state machine.

[0180] The integ_ncms state machine implements the timer and performs some basic filtering to increase the resolution of the measured delay. For each half cycle, a start trigger (tmeasstart_h, tmeasstart_l) is generated by the half-bridge falling edge detector and the half-bridge rising edge detector. Iprim_I_p0 and Iprim_s_mo capture the half-cycle delay from the timer. The trigger is generated by comparing the sensed primary current to zero.

[0181] Fig. 9 A basic implementation of a state machine is shown that measures the delay between half-bridge commutation and current zero crossing, including filtering (IIR) to improve time resolution. The half-cycle delay is measured by first capturing the start time (tstart) in state 1. State 1 is entered on the rising edge of the EC signal, associated with Vhb commutation. The delay is calculated and filtered on the falling edge of the I_I_0 signal in state 2, associated with current zero crossing.

[0182] The half-cycle delay dT is calculated by subtracting the previously captured tstart from the current time. The state machine is executed with a step time of 20ns, which determines the resolution of the measured delay. By applying a simple IIR (Infinite Impulse Response) filter, the resolution of the half-cycle delay is improved by a factor of two (the k parameter is fixed to 2).

[0183] Fig.10Modulation of the capacitive mode minimum delay is shown. Fig.10 The block diagram implements a delay correction signal (tmeas_cor) that will be used later in the control loop to prevent capacitor mode oscillations. Basically, the minimum of the two half-cycle delays is taken from the integ_ncm state machine, and a predetermined delay is subtracted from the result to produce a delay correction signal. When the capacitor mode control loop is effective, the output power will decrease so that the delay correction becomes zero. Once steady state is reached, the delay between Vhb commutation and the resonant current zero crossing is equal to the predetermined delay. The minimum delay required to prevent capacitor mode oscillations depends on the input voltage, output voltage and load current. As these properties change over time, the DCM-CCM operation mode and cycle period of the converter dynamically adapt and stabilize to the appropriate steady-state operating point.

[0184] When choosing the minimum delay based on different converter properties, trade-offs must be considered. If the minimum delay becomes too small, capacitive mode oscillation may occur. Otherwise, too large a delay may severely limit the maximum output power capability of the converter. In this case, the converter may not meet the requirement of being able to deliver 150% output power.

[0185] Another aspect that plays an important role in selecting the minimum delay relates to the robustness of the time-based capacitive mode control to component spread and delay tolerance. This is one of the reasons for implementing a nonlinear transfer based on the actual normalized converter cycle period to modulate the minimum delay. Fig.10 An example of a transfer curve is shown. Two parameters are used to define the curve:

[0186] ●Cycle crossover period between CCM mode and DCM mode (Tcross-over). This parameter specifies the converter cycle period, which is normalized to 1 by calculating the relative period as the actual cycle period divided by Tcross-over.

[0187] • A "nominal" minimum delay associated with the cross-over cycle period (nominal caplim delay). When the actual converter cycle period is equal to the Tcross-over period, the nominal caplim delay is used as the minimum delay criterion.

[0188] A typical converter application may temporarily deliver 150% output power at 12V. This means that the resonant tank should be designed to handle 1.5 times the nominal output current with enough margin to avoid capacitive mode operation. When the converter's operation approaches this point, the crossover period and nominal delay parameters are approximated based on the converter signal.

[0189] If the Vbus input voltage drops below the nominal 400V, the cycle period increases and the resonant tank operates at a frequency closer to the capacitive mode crossover frequency. This resonant frequency defines the takeover point between the capacitive mode and the inductive mode. In this case, more margin can be created by increasing the minimum delay. Now, the actual normalized cycle period of the converter is above unity.

[0190] The minimum delay is increased by squaring the nominal period and multiplying the result by the caplim delay parameter. Since the increased delay results in a larger reduction in delivered power, the output voltage drops slightly faster. This is not a problem because at lower voltages the output current increases until a stable operating point is found.

[0191] If the Vbus voltage rises and returns to the nominal 400V, first the cycle period also decreases rapidly. Therefore, the minimum delay also decreases significantly, which enables the converter to deliver enough power to quickly increase the output voltage. At this point, the normalized cycle period is less than one. By taking the square of the normalized period, the minimum delay becomes small enough so that normal operation can be quickly restored. During the output voltage rise, the converter period increases and eventually the minimum delay returns to its nominal value. Continuously adjusting the minimum delay during the output voltage rise prevents capacitive mode oscillations.

[0192] Fig.11 A block diagram showing the calculation of the phase error and its integrator is shown. The correction delay (Tmeas_cor) represents the difference between the measured minimum delay and the desired minimum delay. The control loop adjusts the output power of the converter (ctrl_p_caplim) until the correction delay becomes zero. The correction delay is converted into a proportional phase that is independent of the converter cycle period. K in the control loop i The coefficients can now be used as fixed constants over a larger range of operating frequencies.

[0193] The phase error is calculated by subtracting the phase obtained, it is injected into the input of a continuous integrator whose integration constant K i For 10 5 For a digital implementation, the constants need to be converted to their discrete counterparts:

[0194] K i,discrete =K i ·T sample

[0195] When the amplitude is lower than the normal power control signal (ctrl_p_nocaplim), the integrator output (ctrl_p_caplim) controls the power delivered at the output. In this case, the capacitive mode control loop is said to be active. If the correction delay is positive, the induced phase error will increase the integrator output (ctrl_p_caplim) until it stabilizes at a value 0.2 higher than the normal power control level. In effect, this will deactivate the capacitive mode control loop. This behavior is arranged with an additional control loop, using the normal power control and a parameter (max_delta) to define the offset level.

[0196] Fig. 12A and Fig. 12B A power control block diagram is shown. Fig. 12A and Fig. 12B The circled area in the diagram of shows a basic implementation of a power control overrule mechanism to prevent capacitive mode.

[0197] The minimum of the two power control levels (ctrl_p_caplim and ctrl_p) is taken to regulate the delivered circulating energy via the so-called vcap high and vcap low comparator levels (vcrh and vcrl).

[0198] The lower left diagram shows two power controls over time. During the first 4 ms, the normal power control (ctrl_p, Fig. 12A and Fig. 12B 1290 in the figure) is regulating. A short time after 4ms, the capacitor mode power control (ctrl_p_caplim) takes over to avoid capacitor mode oscillations. When the optocoupler regulates the circulating energy (ctrl_p), the invalid capacitor mode control (ctrl_p_caplim) signal remains higher than the normal power control and follows ctrl_p with an offset of 0.2. This is done to ensure that the capacitor mode control can respond quickly when taking over the circulating energy regulation to prevent oscillations. During the capacitor mode prevention, the normal power control (ctrl_p) increases linearly until it clips at a predetermined value. Here, the ctrl_p signal does not follow the capacitor mode control signal.

[0199] If normal conditions are restored, the saturated ctrl_p signal will drop quickly, taking over the loop energy regulation again. Typically, this happens when the output voltage overshoots by a certain acceptable tolerance about the desired value and then returns to its expected set point. If ctrl_p is kept above ctrl_p_caplim by maintaining a small offset of, for example, 0.2, this will improve the output voltage overshoot.

[0200] Fig.13The relationship between the converter switching period and the DCM-CCM mode is shown.

[0201] It has been found that when capacitor mode oscillations occur, the converter is usually operated in DCM mode, close to the critical delay criterion. On the other hand, when the converter has to deliver a lot of power, it is operated in CCM mode, and capacitor mode oscillations are much less of a problem. This observation gave rise to the idea of ​​creating enough margin for capacitor mode operation by adjusting the critical delay in the control loop according to the converter switching period. Fig.13 The relationship between the converter switching period and the DCM-CCM mode during a Vbus voltage step is shown.

[0202] The converter starts at a Vbus voltage of 400V, a load current of 25A, and reaches a 12V steady-state output voltage after 4ms. During startup, the converter operates in a high-power CCM mode (lower left insert) to quickly charge the large output capacitor and also deliver output current. As can be depicted in the top row of the diagram, once the output becomes close to 12V, the converter switching cycle increases toward the Tcross-over cycle. If the converter cycle is operated above or below Tcross-over, the delay in the time-based capacitor mode control loop increases or decreases.

[0203] In the interval between 4ms and 10ms, the Vbus voltage drops to 250V. The converter starts operating in DCM mode, the cycle period is longer, and the control loop delay is significantly increased to avoid capacitor mode oscillation. When the output voltage (smps_vo) drops, the converter switching period is reduced, and the operation mode is transformed between DCM mode and CCM mode. During the interval, the control loop delay is slowly reduced so that the converter finally delivers 50W (2V / 25A) of output power in CCM mode and in the absence of any capacitor mode oscillation.

[0204] After 10ms, the Vbus voltage returns to 400V, resulting in a smaller converter cycle and control loop delay. With the shorter delay in CCM mode, the converter can deliver enough power to quickly increase the output voltage. Once the output voltage becomes close to 12V, the converter transitions back to DCM mode. The control loop delay returns to nominal (Tdelay) as the switching cycle becomes close to Tcross-over.

[0205] Examples of the present disclosure can be summarized as follows:

[0206] ● For each half cycle, the distance between the current operating point and the capacitive mode boundary is measured as the time difference between the commutation of the half-bridge voltage (Vhb) and the zero crossing of the resonant current (ICres). The lowest value of the two half-cycle measurements represents the current distance to the capacitive mode boundary.

[0207] ● Based on the two parameters and the current converter switching period, a minimum time distance threshold is determined. This is done in the following way:

[0208] ○ Normalize the converter switching period by scaling it with the Tcross-over parameter;

[0209] ○ The minimum time distance threshold is determined by multiplying the Tdelay parameter by the square of the normalized switching period.

[0210] If the converter is operating above its resonant frequency, CCM mode is used and the minimum time threshold is reduced, otherwise the minimum time threshold is increased. The Tcross-over parameter defines the cycle period at which the minimum threshold is equal to the Tdelay parameter.

[0211] • When the measured time difference drops below a minimum time threshold, the capacitive mode control loop reduces the power output, thereby taking over the normal ΔV feedback loop.

[0212] • The capacitor mode control loop keeps the converter operating at a minimum time threshold as long as the limiting conditions apply.

[0213] When conditions permit, the capacitor-mode control loop increases power output to the point where the normal feedback loop automatically takes over power control again.

[0214] ● By using the same mechanism for power control, a smooth transition between capacitor mode control and normal feedback control is guaranteed.

[0215] ● Robustness for changing Vbus and Vout voltages. In the event that the Vboost voltage is low for a longer period of time, the output current eventually increases so that the output voltage can settle at a stable level. When Vbus returns to its nominal level while Vout is still low, the converter delivers enough current to quickly rise to the nominal output voltage.

[0216] • Robustness for spread and component tolerances is achieved by adjusting the minimum time threshold based on the converter cycle period with a quadratic relationship. The available power budget increases or decreases depending on the CCM-DCM mode, which is indirectly derived from the converter cycle period.

[0217] =Digital implementation with small footprint. Delay measurements can be derived from a single clock edge, where the clock (e.g., 50 MHz) is approximately 100 times the cycle frequency (500 kHz). Digital functions can operate at lower sampling frequencies. Simple filters with small footprint are used.

[0218] • Use the time or integral of the resonant current between the mentioned intervals.

[0219] • The idea of ​​detecting the distance to the non-capacitive mode region and a way to define that distance and use that distance to adjust the actual power back.

[0220] • The idea of ​​detecting the distance to a specific capacitive mode boundary for each half cycle and using the minimum value in two half cycles to generate an error signal.

[0221] • The idea of ​​using the resonant capacitor voltage (the sampled peak value and the actual value, where the difference between the two is used to generate the error signal).

[0222] • The method using the criterion "Vhb crosses α×Vbus" associated with capacitive mode control measures the point where the state of one of the switches changes.

[0223] Examples disclosed herein involve detecting near capacitive mode using a capacitive mode distance signal based on t1 and t2 (where t1 is the time when one of the switches changes state and t2 is the time when a subsequent zero crossing of the measured current signal occurs) to define the distance to the capacitive mode boundary in three ways:

[0224] ●t2-t1 is directly used as the time difference;

[0225] The integral of Ires over the interval t1, t2; and

[0226] ●Integral of Ires×Vhb in the interval t1, t2.

[0227] The time method measures the time difference between half-bridge commutation and resonant current zero crossing for two half cycles. The minimum time difference in the two half-cycle measurements can be used to represent the distance to the capacitive mode boundary. As an alternative, the time difference can be converted into a ratio (phase) of the switching cycle, and the controller can set the protected power signal (Pr) based on the ratio (phase) of the switching cycle.

[0228] The integral / area method captures the area under the resonant current plot, starting from the moment the half cycle ends until the resonant current crosses zero. The area represents the distance to the capacitive mode boundary.

[0229] When the converter operating point approaches a predefined distance from the capacitive mode boundary, the capacitive mode control loop takes over the normal control loop to reduce the output power until steady state is reached. If the limiting condition is removed, the output power gradually increases until the normal power control loop takes over the output power regulation.

[0230] Examples disclosed herein may provide one or more of the following advantages:

[0231] ●Always ensure that the converter operates in the inductive mode region, thereby achieving safe and stable operation under zero voltage switching.

[0232] ● Measuring the proximity of the operating point to the capacitive mode boundary based on methods that consider time or area requirements.

[0233] • Preventing capacitive mode instability by reducing the output power via the normal power control mechanism.

[0234] By adding a capacitive mode prevention control function, the possibility of unstable capacitive mode operation can be reduced.Measuring the distance to the capacitive mode boundary can be based on time (phase) or area (charge) information.

[0235] The examples disclosed herein may solve the problems associated with the prior art by regulating the power back sufficiently away from the non-capacitive mode boundary while the system (including the symmetrical loop) remains under stably controlled because vcap control is maintained within two half cycles.

[0236] A brief overview of the key features of the capacitive mode prevention approach is presented below.

[0237] 1. A resonant converter controller comprising a regulation loop that reduces the power level based on a detected distance to a near capacitive mode boundary, capable of maintaining a predefined distance to a so-called (near) capacitive mode zone. A distance defines an error signal in order to regulate the instantaneous power back.

[0238] 2. Feature 1, including separate detection distances to the capacitive mode boundary for both half cycles (taking the minimum of the two measured distances).

[0239] 3. Features 1, 2, wherein the detected distance is based on the integral of the resonant current between the time when the half cycle is completed by the half cycle completion criteria (Vcap, duration) and the time when the primary current crosses zero.

[0240] 4. Features 1, 2, wherein the detected distance is based on the time difference between the moment a half cycle is completed by a half cycle completion criterion (Vcap, duration) and the moment the primary current crosses zero.

[0241] 5. Features 3 and 4, including a method of replacing the criterion "half cycle completed" with the criterion "Vhb crosses α×Vbus".

[0242] 6. Feature 5, where α = 0.5.

[0243] 7. Features 3, 4, and 6, wherein as a measure of the "moment when the primary current crosses zero", the sampled peak value of the voltage across the resonant capacitor (or the voltage on one side of the resonant capacitor) is taken. In this case, the distance is based on the difference between the actual resonant capacitor voltage and the sampled peak value of the resonant capacitor voltage.

[0244] 8. Features 1-5, wherein the predefined distance to the capacitive mode boundary depends quadratically on the normalized converter switching frequency and a reference delay.

[0245] 9. Feature 7, wherein the converter maintains a predefined distance from the capacitive mode boundary when the output voltage decreases. During this transient, the converter switching period is reduced, thereby increasing the output current until steady-state operation is achieved.

[0246] 10. Feature 8, wherein the Vbus voltage returns to nominal when the converter is operating at a predefined distance from the capacitive mode boundary. The Vbus transient will even further rapidly reduce the converter switching period, thereby generating sufficient output current to quickly raise the output voltage to its nominal level. During the last part of the transient, the switching period slowly increases until the normal control loop takes over power regulation.

[0247] 11. Feature 9, wherein the capacitor mode control loop implementation only requires the I regulator to maintain a constant bandwidth when active. When capacitor mode constraints apply, the bandwidth can be optimized to achieve a good step response. In this case, short bursts of capacitor mode oscillations can be avoided due to the fast reaction speed of the control loop.

[0248] 12. Feature 3, wherein the capacitive mode prevention control uses a time-based approach to prevent capacitive mode oscillations. With this approach, a straightforward and simple digital implementation can be achieved because measuring time is easy in the digital domain.

[0249] 13. Feature 10, wherein a signal is added to indicate that the capacitive mode loop is valid to restart, latch the system, or initiate a warning.

[0250] Fig.14 An example embodiment of a method of operating a resonant converter according to the present disclosure is shown.

[0251] A resonant converter is used to supply electrical energy from a supply source to a load, and the resonant converter comprises:

[0252] a first switch and a second switch, the first switch and the second switch being connected in series with each other between a supply source and a reference terminal, wherein when the first switch is closed and the second switch is open, the resonant converter has a high-side switching half-cycle, and wherein when the first switch is open and the second switch is closed, the resonant converter has a low-side switching half-cycle; and

[0253] A resonant tank is electrically connected to the first switch and the second switch, wherein the resonant tank includes a resonant capacitor.

[0254] At step 1450, the method includes receiving a measured current signal representing a current flowing in the resonant tank. At step 1451, the method includes receiving a measured voltage signal representing a voltage at a predetermined point in the resonant tank. At step 1452, the method includes receiving a power setting signal (e.g., via a normal mode regulator) that defines a requested power level for the load. It should be appreciated that each of these steps may be performed in any order or simultaneously.

[0255] At step 1453, the method involves setting a protected power signal (e.g., via a capacitive mode regulator) based on a time delay between a change in state of one of the switches and a subsequent zero crossing of the measured current signal. As discussed above, the protected power signal can be set so that its application will cause the resonant converter to avoid a capacitive mode of operation. That is: to avoid the current in the resonant tank from reaching zero before the end of a switching half cycle. In addition, the protected power signal can be set so that its application causes a fixed "distance" between the end of the switching half cycle and the next zero crossing of the measured current signal. Alternatively, the protected power signal can be set so that its application causes an adaptive "distance" between the end of the switching half cycle and the next zero crossing of the measured current signal, whereby the adaptive distance can be set, for example, based on the measured cycle / switching period. In either case, such a "distance" can be represented by a time delay, or it can be represented as a value of the integral of the current in the resonant tank between: a change in state of one of the switches and a subsequent zero crossing of the current in the resonant tank.

[0256] At step 1454, the method involves setting an upper voltage threshold (VCRH) and a lower voltage threshold (VCRL) based on the lower of: i) a protected power signal; and ii) a power setting signal.

[0257] Next, in response to the measured voltage signal exceeding the upper voltage threshold (VCRH), the method involves opening the first switch and closing the second switch at step 1455. Similarly, in response to the measured voltage signal falling below the lower voltage threshold (VCRL), in step 1456, the method involves opening the second switch and closing the first switch.

[0258] Unless a specific order is explicitly stated, the instructions and / or flow chart steps in the above figures may be performed in any order. Also, those skilled in the art will recognize that although an example instruction set / method has been discussed, the materials in this specification may be combined in a variety of ways to produce other examples and should be understood within the context provided in this detailed description.

[0259] In some example embodiments, the instruction set / method steps described above are implemented as functions and software instructions embodied as an executable instruction set, which is implemented on a computer or a machine programmed with and controlled by the executable instructions. Such instructions are loaded for execution on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, a microcontroller, a processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing devices. A processor may refer to a single component or to multiple components.

[0260] In other examples, the instruction sets / methods shown herein and the data and instructions associated therewith are stored in corresponding storage devices, which are implemented as one or more non-transitory machine or computer readable or computer usable storage media. Such computer readable or computer usable storage media are considered to be part of an article (or product). An article or product may refer to a single component or multiple components of any manufacture. A non-transitory machine or computer usable medium as defined herein does not include signals, but such a medium is capable of receiving and processing information from signals and / or other transient media.

[0261] Example embodiments of the materials discussed in this specification may be implemented in whole or in part through a network, computer or data-based device and / or service. The network, computer or data-based device and / or service may include a cloud, the Internet, an intranet, a mobile device, a desktop computer, a processor, a lookup table, a microcontroller, a consumer device, an infrastructure, or other enabling devices and services. As may be used herein and in the claims, the following non-exclusive definitions are provided.

[0262] In one example, one or more instructions or steps discussed herein are automated. The term automation or automatic (and similar variations thereof) means the use of computers and / or mechanical / electrical devices to control the operation of a device, system, and / or process without human intervention, observation, effort, and / or decision making.

[0263] It should be understood that any components that are said to be coupled may be coupled or connected directly or indirectly. In the case of indirect coupling, additional components may be located between the two components that are said to be coupled.

[0264] In this specification, example embodiments have been presented according to a selected set of details. However, one of ordinary skill in the art will appreciate that many other example embodiments including different selected sets of these details may be practiced. It is intended that the appended claims cover all possible example embodiments.

Claims

1. A controller for a resonant converter, characterized in that: The resonant converter is used to supply electric energy from a supply source to a load, and the resonant converter comprises: a first switch and a second switch, the first switch and the second switch being connected in series with each other between the supply source and a reference terminal, wherein when the first switch is closed and the second switch is open, the resonant converter has a high-side switching half-cycle, and wherein when the first switch is open and the second switch is closed, the resonant converter has a low-side switching half-cycle; and a resonant tank electrically connected to the first switch and the second switch, wherein the resonant tank includes a resonant capacitor; The controller is configured to: receiving a measured current signal representative of a current flowing in the resonant tank; receiving a measured voltage signal representative of a voltage at a predetermined point in the resonant tank; receiving a power setting signal defining a requested power level for the load; setting a protected power signal based on a time delay between a change in state of one of the switches and a subsequent zero crossing of the measured current signal; setting an upper voltage threshold and a lower voltage threshold based on the lower of: i) the protected power signal; and ii) the power setting signal; In response to the measured voltage signal exceeding the upper voltage threshold, opening the first switch and closing the second switch; and In response to the measured voltage signal falling below the lower voltage threshold, the second switch is opened and the first switch is closed.

2. The controller according to claim 1, characterized in that: the protected power signal corresponds to a power level at which the measured voltage signal will intersect: the upper voltage threshold during the high-side switch half-cycle; and the lower voltage threshold during the low-side switch half cycle.

3. The controller according to claim 1 or claim 2, characterized in that: The protected power signal is arranged such that application of the protected power signal causes: a fixed distance between the end of a switching half-cycle and the next zero crossing of the measured current signal; or An adaptive distance between the end of a switching half cycle and the next zero crossing of the measured current signal.

4. The controller according to claim 3, characterized in that: The distance is represented by a time delay.

5. The controller according to claim 3, characterized in that: The distance is represented as the value of the integral of the measured current signal between: the time at which the state of one of the switches changes; and the time at which the measured current signal next crosses zero.

6. A controller according to any preceding claim, characterised in that Additionally configured as: The protected power signal is set based on the lower of: i) a time delay between a change of state of the first switch and a subsequent zero crossing of the measured current signal; and ii) A time delay between a change of state of the second switch and a subsequent zero crossing of the measured current signal.

7. The controller according to claim 1 or claim 2, characterized in that: Operation of the resonant converter in accordance with the protected power signal causes a predetermined time delay between the change in state of one of the switches and the subsequent zero crossing of the measured current signal.

8. The controller according to claim 1 or claim 2, characterized in that: The controller is further configured to: The protected power signal is set based on an integral of the measured current signal between: a time when the state of one of the switches changes state; and a time when the measured current signal next crosses zero.

9. A resonant converter, characterized in that: Comprising a controller according to any preceding claim.

10. A method of operating a resonant converter, characterized in that The resonant converter is used to supply electric energy from a supply source to a load, and the resonant converter comprises: a first switch and a second switch, the first switch and the second switch being connected in series with each other between the supply source and a reference terminal, wherein when the first switch is closed and the second switch is open, the resonant converter has a high-side switching half-cycle, and wherein when the first switch is open and the second switch is closed, the resonant converter has a low-side switching half-cycle; and a resonant tank electrically connected to the first switch and the second switch, wherein the resonant tank includes a resonant capacitor; The method comprises: receiving a measured current signal representative of a current flowing in the resonant tank; receiving a measured voltage signal representative of a voltage at a predetermined point in the resonant tank; receiving a power setting signal defining a requested power level for the load; setting a protected power signal based on a time delay between a change in state of one of the switches and a subsequent zero crossing of the measured current signal; setting an upper voltage threshold and a lower voltage threshold based on the lower of: i) the protected power signal; and ii) the power setting signal; In response to the measured voltage signal exceeding the upper voltage threshold, opening the first switch and closing the second switch; and In response to the measured voltage signal falling below the lower voltage threshold, the second switch is opened and the first switch is closed.

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