High-side NMOS (N-channel metal oxide semiconductor) driving circuit and chip
By using a combination of Zener diode, P-type MOS tube and resistor in the high-side NMOS drive circuit for voltage clamping and optimizing the shutdown branch, the problems of limited voltage clamp adjustment range, insufficient shutdown speed and excessive circuit area in the driving of high-side NMOS power devices are solved, and high-precision voltage clamping and rapid shutdown are achieved, reducing circuit area and design costs.
Patent Information
- Application Number
- CN202411826728.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-12
- Publication Date
- 2025-04-25
AI Technical Summary
In the driving of high-side NMOS power devices, there are problems such as limited voltage clamp adjustment range, insufficient shutdown speed and excessive circuit area in the driving of high-side NMOS power devices, which may damage or affect system performance when switching operating states frequently.
A high-side NMOS driving circuit is designed, and voltage clamping is used to use a combination of Zener diode, P-type MOS tube and resistor for voltage clamping. The shutdown speed of the high-side NMOS power device is optimized through two shutdown branches based on different control principles, and the clamping branch is simplified to reduce the circuit area.
High-precision gate-source voltage clamping of high-side NMOS power devices is achieved, which improves shutdown speed and stability, and reduces circuit area and design costs.
Smart Images
Figure CN119891689A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of motor driving, and in particular to a high-side NMOS driving circuit and a chip. Background Art
[0002] In the field of motor drive, the use of PWM (pulse width modulation) to control motor drive devices has become the mainstream design. Especially in the dual N-type power tube H-bridge structure, the PWM signal controls the opening of the high-side NMOS power device through level conversion.
[0003] The gate-source voltage difference of the high-side NMOS power device is a very important concern. For the high-side NMOS power device, its gate-source voltage difference cannot exceed its gate-source breakdown voltage. This requires designers to design a suitable voltage clamping structure in the driving part of the power tube to ensure that the high-side NMOS power device will not be damaged in all working states.
[0004] At the same time, when the high-side NMOS power device drives the motor to rotate, the high-side NMOS power device itself is in a situation where the working state is frequently switched, which places higher requirements on the switching speed and stability of the high-side NMOS power device. In practical applications, when the driving signal controls the high-side NMOS power device, it needs to pass through different paths. When controlling the high-side power tube, a level shift circuit is required to convert the signal into voltage. This difference between the high-side and low-side control methods leads to inconsistent signal delays during transmission, which will cause the high-side and low-side MOS power devices to be turned on at the same time, causing a power short circuit. In response to the above situation, traditional technology pre-processes the control signal by setting a delay for the high and low-side switches on the same side or adding a dead zone generation circuit. However, the problems existing in the prior art are: 1. The voltage clamping adjustment range is limited. The existing solution of voltage clamping through a voltage zener diode or a series diode has the problem of a fixed adjustment range, which makes it difficult to meet the demand for fine adjustment of the gate-source clamping voltage of a high-side NMOS power device.
[0005] 2. Insufficient turn-off speed: The high-side NMOS power device frequently switches working states, which places higher requirements on turn-off speed and stability. The existing circuit design fails to fully optimize the turn-off rate of the high-side NMOS power device, which may affect system performance.
[0006] 3. Circuit area problem. In existing designs, delays for high and low side switches on the same side are often set and dead zone generation circuits are added to pre-process the control signal to avoid the high and low side MOS power devices on the same side being turned on at the same time, causing a power short circuit. However, this will cause the circuit area to be too large, increasing design and manufacturing costs.
[0007] Therefore, it is also a very effective method to design a corresponding circuit structure in the high-side NMOS power device driving part to make the high-side MOS driver device shut down faster at the circuit level. Summary of the invention
[0008] The present invention provides a high-side NMOS drive circuit and chip. In order to achieve the above-mentioned purpose, the present invention adopts the following technical solutions: A high-side NMOS driving circuit comprises an opening branch, a first closing branch, a second closing branch and a voltage clamping branch; The control end of the opening branch receives the switch control signal SW1, the input end is connected to the power input, and the output end is connected to the gate of the high-side NMOS power device; the control end of the first closing branch receives the switch control signal SW2, the input end is connected to the gate of the high-side NMOS power device, and the output end is grounded; the control end of the second closing branch receives the switch control signal SW2, the input end is connected to the gate of the high-side NMOS power device, the current storage compensation control end is connected to the control end of the voltage clamping branch, and the output end is grounded; the input end of the voltage clamping branch is connected to the gate of the high-side NMOS power device, and the output end is connected to the source of the high-side NMOS power device; the high-side NMOS power device is an N-type MOSFET, the drain of the high-side NMOS power device receives the power input, and the source is connected to the motor.
[0009] Furthermore, the open branch includes a P-type MOS tube MP1 and a resistor R1.
[0010] The gate of the P-type MOS tube MP1 serves as a control terminal to receive the switch control signal SW1, the source serves as an input terminal to connect to the power input, and the drain serves as a drain connected to one end of the resistor R1; the other end of the resistor R1 serves as an output terminal to connect to the gate of the high-side NMOS power device.
[0011] Furthermore, the first shut-off branch includes a resistor R2 and an N-type MOS transistor MN2.
[0012] One end of the resistor R2 is connected to the gate of the high-side NMOS power device as an input end, and the other end of the resistor R2 is connected to the drain of the N-type MOS transistor MN2; the gate of the N-type MOS transistor MN2 is used as a control end to receive the switch control signal SW2, and the source is grounded as an output end.
[0013] Furthermore, the second shut-off branch includes a resistor R3, an N-type MOS transistor MN1 and a current source IB1; One end of the resistor R3 is connected to the gate of the high-side NMOS power device as an input end, and the other end of the resistor R3 is connected to the drain of the N-type MOS transistor MN1 and serves as a current storage compensation control end; the gate of the N-type MOS transistor MN1 receives the switch control signal SW2 as a control end, and the source is connected to the positive electrode of the current source IB1; the negative electrode of the current source IB1 is grounded as an output end.
[0014] Furthermore, the voltage clamping branch includes a Zener diode D1, a P-type MOS tube MP2 and a resistor R0; The source of the P-type MOS tube MP2 is connected to the gate of the high-side NMOS power device and the negative electrode of the Zener diode D1 as an input terminal, the gate is connected to the positive electrode of the Zener diode and the current storage compensation control terminal of the second shutdown branch as a control terminal, and the drain is connected to one end of the resistor R0; the other end of the resistor R0 is connected to the source of the high-side NMOS power device as an output terminal.
[0015] Furthermore, the resistance value of the resistor R3 is at least ten times the resistance value of the resistor R2.
[0016] The present invention also provides a chip integrating the high-side NMOS driving circuit described above.
[0017] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects: 1. The voltage clamping branch replaces the traditional pure voltage regulator diode solution through the combination of Zener diode, P-type MOS tube and resistor, breaking through the fixed voltage drop limitation of the traditional voltage regulator diode. High-precision gate-source voltage clamping of high-side NMOS power devices can be achieved by adjusting relevant parameters.
[0018] 2. Two shutdown branches based on different control principles. The first shutdown branch is the main shutdown branch used to discharge the charge and has controllable time. The second shutdown branch is an auxiliary shutdown circuit controlled by a current source and assisted by a resistor to control the shutdown time. They respectively shut down the high-side NMOS power device to ensure that the high-side NMOS power device can be shut down quickly and reliably.
[0019] 3. By simplifying the clamping branch and optimizing the shutdown path, the complex control scheme that requires the addition of an additional dead zone circuit is replaced, thereby effectively reducing the circuit area and reducing the design and manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 It is a module structure diagram of an embodiment of the present invention; Figure 2 is a circuit structure diagram of an embodiment of the present invention; Figure 3 A circuit diagram of a switch control module according to an embodiment of the present invention; Figure 4 The figure is a connection diagram of a switch control module and a high-side drive circuit according to an embodiment of the present invention.
[0021] In the above figures: 1-high-side drive circuit; 2-open branch; 3-first shut-off branch; 4-second shut-off branch; 5-voltage clamping branch; 6-high-side NMOS power device; 7-switch control module; MP1-P-type MOS tube; R1-resistor; MN2-N-type MOS tube; R2-resistor; R3-resistor; MN1-N-type MOS tube; IB1-current source; D1-Zener diode; MP2-P-type MOS tube; R0-resistor. DETAILED DESCRIPTION
[0022] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings. The example implementation methods can be implemented in various forms and should not be understood as being limited to the examples described herein. On the contrary, these implementation methods are provided so that the invention will be more comprehensive and complete, and the concepts of the example implementation methods are fully conveyed to those skilled in the art. In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, and it can be the internal connection of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0023] The high-side drive circuit module of this embodiment is shown in the figure Figure 1 As shown, the high-side driving circuit 1 includes a turn-on branch 2 , a first turn-off branch 3 , a second turn-off branch 4 and a voltage clamping branch 5 .
[0024] The control end of the opening branch 2 receives the switch control signal SW1, the input end is connected to the power input, and the output end is connected to the gate of the high-side NMOS power device 6 of the motor; the control end of the first closing branch 3 receives the switch control signal SW2, the input end is connected to the gate of the high-side NMOS power device 6, and the output end is grounded; the control end of the second closing branch 4 receives the switch control signal SW2, the input end is connected to the gate of the high-side NMOS power device 6, the current storage compensation control end is connected to the control end of the voltage clamping branch 5, and the output end is grounded; the input end of the voltage clamping branch 5 is connected to the gate of the high-side NMOS power device 6, and the output end is connected to the source of the high-side NMOS power device 6; in this embodiment, the high-side NMOS power device 6 connected to the driving circuit is an N-type MOSFET. When the opening branch 2 applies a voltage to the gate of the high-side NMOS power device 6, the high-side NMOS power device 6 is turned on and drives the motor.
[0025] The control signal SW1 and the control signal SW2 are provided to the circuit by the switch control module 7. The function of the switch control module 7 can be adjusted and optimized according to the actual circuit design requirements and application scenarios. Figure 3 As shown, the switch control module 7 converts the enable signal input by the digital circuit into a corresponding control logic signal through logic control; while performing the logic conversion, the level matching between the high voltage and the low voltage is achieved by cascading multiple MOS tubes in the circuit and switching different power supplies. The switch control module 7 divides the output into two branches (control signal SW1 and control signal SW2), and cooperates with the control of the opening and closing branches of the high-side drive circuit. The connection diagram of the switch control module and the high-side drive circuit is shown in FIG. Figure 4 shown.
[0026] The high-side drive circuit structure of this embodiment is shown in FIG. Figure 2 As shown, the opening branch 2 includes a P-type MOS tube MP1 and a resistor R1; the gate of the P-type MOS tube MP1 receives the switch control signal SW1 as a control terminal, the source is connected to the voltage VCP generated by the charge pump as an input terminal, and the drain is connected to one end of the resistor R1; the other end of the resistor R1 is connected to the gate of the high-side NMOS power device 6 as an output terminal. Here, the high level of the switch signal SW1 is VCP, and the low level is VCC. The opening time of the high-side NMOS power device 6 is mainly determined by the size of the high-side NMOS power device 6 and the resistor R1. Designers can set relevant parameters according to their own needs when designing circuits.
[0027] The first shutdown branch 3 is a main shutdown branch, which is composed of a resistor R2 and an N-type MOS transistor MN2; one end of the resistor R2 is connected to the gate of the high-side NMOS power device 6 as an input end, and the other end of the resistor R2 is connected to the drain of the N-type MOS transistor MN2; the gate of the N-type MOS transistor MN2 is used as a control end to receive the switch control signal SW2, and the source is used as an output end to be grounded.
[0028] The low level of the switch signal SW2 here is GND, and the high level can be selected according to the power domain of the circuit itself and the type of NMOS. The current size of this branch directly affects the turn-off speed of the high-side NMOS power device 6, and the resistance value of the resistor R2 directly affects the size of the branch current. This requires the setting of the resistor R2, that is, the resistance value of the resistor R2 should be much smaller than R3 (the resistor R3 is at least ten times the resistor R2). The specific ratio is selected by the gate equivalent capacitance of the high-side NMOS power device 6. The resistor R2 must be selected to satisfy the time constant Small enough:
[0029] For example, if If the resistor R2 is several hundred picofarads (pF), the resistor R2 is usually selected to be several hundred ohms, and the specific parameters should be set according to actual needs.
[0030] The second shutdown branch 4 as an auxiliary shutdown circuit includes a resistor R3, an N-type MOS transistor MN1 and a current source IB1; one end of the resistor R3 is connected to the gate of the high-side NMOS power device 6 as an input end, and the other end of the resistor R3 is connected to the drain of the N-type MOS transistor MN1 and serves as a current storage compensation control end; the gate of the N-type MOS transistor MN1 receives the switch control signal SW2 as a control end, and the source is connected to the positive electrode of the current source IB1; the negative electrode of the current source IB1 is grounded as an output end. The current source IB1 can be realized by a current mirror structure, and the current flowing through the second shutdown branch 4 is mainly determined by the current source IB1. The current source IB1 provides a constant discharge current, which directly affects the charge discharge speed when the high-side NMOS power device 6 is turned off; at the same time, the resistance value of the resistor R3 will also have a certain influence on the shutdown charge discharge time, so the resistance value of the resistor R3 should match the current value of the current source IB1 to achieve the fastest charge release speed. Secondly, the interaction between the resistance value of resistor R3 and the current value of the current source has a certain impact on the MOS device of the voltage clamping branch: if the resistor R3 is too large or the current of the current source IB1 is too small, the gate voltage drops slowly, the turn-off time is prolonged and the uncertainty increases, which may cause the working area of the clamping branch to be blurred.
[0031] The voltage clamping branch 5 in this embodiment mainly realizes the gate-source voltage clamping function of the high-side NMOS power device 6 in the current storage stage, and includes a Zener diode D1, a P-type MOS tube MP2 and a resistor R0; the source of the P-type MOS tube MP2 is connected to the gate of the high-side NMOS power device 6 and the negative electrode of the Zener diode D1 as an input end, the gate is connected to the positive electrode of the Zener diode D1 and the current storage compensation control end of the second shutdown branch 4 as a control end, and the drain is connected to one end of the resistor R0; the other end of the resistor R0 is connected to the source of the high-side NMOS power device 6 as an output end. When the high-side NMOS power device 6 is turned off, the opening branch is closed and the closing branch is turned on. Under reasonable conditions, the interaction between the current in the second closing branch 4 and the resistor R3 causes the P-type MOS tube MP2 to turn on, providing a discharge path from the gate to the source of the high-side NMOS power device 6. The excess charge of the gate flows to the source through the P-type MOS tube MP2 and the resistor R0, thereby accelerating the gate charge release speed of the high-side NMOS power device 6. At the same time, the reasonable selection of the resistor R0 can ensure that the gate-source voltage of the high-side NMOS power device 6 will not exceed its breakdown voltage, and the gate-source clamping voltage of the high-side NMOS power device 6 can be accurately set by adjusting the resistance value of the resistor R0. The Zener diode D1 can not only be used to protect the P-type MOS tube MP2 from being damaged, but also when the high-side NMOS power device 6 is turned off, if the discharge current is too large to cause the Zener diode D1 to be reverse biased, the charge accumulated on the gate of the high-side NMOS power device 6 will discharge current through the reverse-biased Zener diode D1. When the P-type MOS tube MP2 is turned on, a current discharge path from the reverse-biased Zener diode D1 to the ground via the current source IB1 is provided. At this time, the MOS device constituting the sub-current mirror in the current source IB1 is separated from the original working area, and the current of the second shut-off branch 4 is mainly determined by the reverse-biased current of the Zener diode D1. The rapid discharge of charge accelerates the drop of the gate voltage of the high-side NMOS power device 6, and the Zener diode D1 is separated from the reverse-biased state. This regulating discharge function ensures that the gate voltage of the high-side NMOS power device 6 can be quickly corrected during the dynamic working process to keep the circuit stable. When designing the circuit, the designer can reasonably set the resistance value of the resistor R0 according to the application requirements to achieve precise adjustment of the gate-source voltage of the high-side NMOS power device 6. For the driving stage of the high-side NMOS power device 6, the voltage difference between the voltage VCP and VCC generated by the charge pump needs to be at a reasonable stage, so the gate-source voltage clamping circuit for the driving stage of the high-side NMOS power device 6 is not designed here. The voltage clamping branch 5 replaces the traditional pure voltage regulator diode solution through the combination of the Zener diode D1, the P-type MOS tube MP2 and the resistor R0, breaking through the fixed voltage drop limit of the traditional voltage regulator diode, and can achieve high-precision gate-source voltage clamping of the high-side NMOS power device 6 by adjusting the relevant parameters.
[0032] The present invention also provides a chip integrating the high-side NMOS drive circuit described above, which replaces the complex control scheme that requires the additional addition of a dead zone circuit by simplifying the clamping branch and optimizing the shutdown path, thereby effectively reducing the circuit area and reducing the design and manufacturing costs.
[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions of the present invention, which should be covered in the present invention. within the scope of the claims.
Claims
1. A high-side NMOS driving circuit, characterized in that: It includes an opening branch, a first closing branch, a second closing branch and a voltage clamping branch; The control end of the opening branch receives the switch control signal SW1, the input end is connected to the power input, and the output end is connected to the gate of the high-side NMOS power device; The control end of the first shut-off branch receives the switch control signal SW2, the input end is connected to the gate of the high-side NMOS power device, and the output end is grounded; The control end of the second shut-off branch receives the switch control signal SW2, the input end is connected to the gate of the high-side NMOS power device, the current storage compensation control end is connected to the control end of the voltage clamp branch, and the output end is grounded; The input end of the voltage clamping branch is connected to the gate of the high-side NMOS power device, and the output end is connected to the source of the high-side NMOS power device.
2. A high-side NMOS driving circuit according to claim 1, characterized in that: The open branch includes a P-type MOS tube MP1 and a resistor R1; The gate of the P-type MOS transistor MP1 serves as a control terminal to receive the switch control signal SW1, the source serves as an input terminal to connect to the power input, and the drain is connected to one end of the resistor R1; The other end of the resistor R1 is connected to the gate of the high-side NMOS power device as an output end.
3. A high-side NMOS driving circuit according to claim 1, characterized in that: The first shut-off branch includes a resistor R2 and an N-type MOS transistor MN2; One end of the resistor R2 is connected to the gate of the high-side NMOS power device as an input end, and the other end of the resistor R2 is connected to the drain of the N-type MOS transistor MN2; The gate of the N-type MOS transistor MN2 serves as a control terminal to receive the switch control signal SW2, and the source serves as an output terminal to be grounded.
4. A high-side NMOS driving circuit according to claim 1, characterized in that: The second turn-off branch includes a resistor R3, an N-type MOS transistor MN1 and a current source IB1; One end of the resistor R3 is connected to the gate of the high-side NMOS power device as an input end, and the other end of the resistor R3 is connected to the drain of the N-type MOS tube MN1 and serves as a current storage compensation control end; The gate of the N-type MOS transistor MN1 serves as a control terminal to receive the switch control signal SW2, and the source is connected to the positive electrode of the current source IB1; The negative electrode of the current source IB1 is grounded as an output terminal.
5. A high-side NMOS driving circuit according to claim 1, characterized in that: The voltage clamping branch includes a Zener diode D1, a P-type MOS tube MP2 and a resistor R0; The source of the P-type MOS tube MP2 is connected to the gate of the high-side NMOS power device and the negative electrode of the Zener diode D1 as an input terminal, the gate is connected to the positive electrode of the Zener diode D1 and the current storage compensation control terminal of the second shutdown branch as a control terminal, and the drain is connected to one end of the resistor R0; The other end of the resistor R0 is connected to the source of the high-side NMOS power device as an output end.
6. A high-side NMOS driving circuit according to claim 2 or 3, characterized in that: The resistance value of the resistor R3 is at least ten times the resistance value of the resistor R2.
7. A chip, characterized in that: A high-side NMOS driving circuit as claimed in claim 1 is integrated.