Adaptive slew rate detection of synchronous rectifiers for synchronous flyback converters

Abstract

A controller for a synchronous rectifier of a synchronous flyback converter is presented. The synchronous rectifier includes a switch switchable by the controller. The controller includes an adaptive slew rate detection circuit configured to add a current to a base slew rate current according to an off-time of the switch to obtain a slew rate current. The slew rate current determines a slew rate set voltage. The controller is configured to turn on a switch of the synchronous rectifier according to a slew rate set voltage.

Description

Technical Field

[0001] The present disclosure relates to a controller of a synchronous rectifier, a synchronous flyback converter including the controller, and a switching power supply including the synchronous flyback converter. Background Art

[0002] FIGS. 1 and 2 show two examples of known rectification schemes that can be used in the secondary side of an isolated switching converter. FIG. 1 shows a rectification scheme 100 for non-synchronous rectification using a diode D, and FIG. 2 shows a rectification scheme 200 for synchronous rectification using a synchronous rectifier SR, for example, an n-channel metal oxide semiconductor field effect transistor (N-MOSFET), or more generally any synchronous rectifier FET combined with a body diode D2. The rectification schemes 100, 200 typically include a transformer T1, with a primary switch S1 driving the primary winding of the transformer T1. The diode D and the synchronous rectifier SR are connected to the secondary winding of the transformer T1. A capacitor C and control signals G for input voltage Vin, output voltage Vout, secondary voltage Vse, forward voltage VF, forward current IF, source S at SR, drain D at SR, and SR are also shown.

[0003] In FIG3, an exemplary power dissipation-current characteristic 300 of the diode D of FIG1 and the synchronous rectifier SR of FIG2 is plotted. Compared to the relatively fixed forward voltage drop of the diode, the voltage drop of the synchronous rectifier FET is proportional to the current and the on-resistance. Therefore, the synchronous rectifier solution can achieve better efficiency and thermal performance than the traditional diode solution, which is an important requirement for high power adapter design, for example.

[0004] Therefore, synchronous rectifiers are increasingly used in devices that are sensitive to power efficiency, such as notebook adapters, wireless equipment, LCD power management modules, Power over Ethernet, and so on.

[0005] A synchronous rectification scheme such as that shown in Figure 2 may be used in a synchronous flyback converter. A flyback converter is a type of switching power supply topology that is commonly used in applications such as power adapters, battery chargers, and voltage converters, and operates by storing energy in a transformer during the on-time and then releasing the energy to the output during the off-time.

[0006] FIG4 schematically illustrates an exemplary waveform 400 of a drain-source voltage VDS and a control signal G of a synchronous rectifier in a synchronous flyback converter in a discontinuous current mode (DCM), such as the synchronous rectifier SR of FIG2 . The drain-source voltage VDS may also be referred to as a switching voltage or a voltage across the synchronous rectifier SR. Typically, when the primary switch S1 coupled to the primary winding of the transformer T1 is turned on, the input voltage Vin as shown in FIG2 is configured to the dotted terminal of the primary winding. Then, the dotted terminal of the secondary winding is positive, and the drain-source voltage VDS is also positive. Therefore, the body diode D2 of the synchronous rectifier SR is reverse biased. At time t0, the primary switch S1 is turned off, and the energy stored in the primary winding is transferred to the secondary winding of the transformer T1. The current flowing from the dotted terminal through the secondary winding causes the body diode D2 to be forward biased. Therefore, the drain-source voltage VDS=-VF decreases to a negative value, where VF is the forward voltage drop of the body diode D2 of the synchronous rectifier SR. In some applications, the turning on and off of the synchronous rectifier SR can be determined by the comparison result of the drain-source voltage VDS with a preset threshold, where the comparison result is reflected by the control signal G. In this example, when the drain-source voltage VDS of the synchronous rectifier SR decreases to a first preset value, such as -100mV, the synchronous rectifier SR is turned on by the secondary control signal G, and when the drain-source voltage VDS of the synchronous rectifier SR increases to a second preset value, such as 0V, the synchronous rectifier is turned off by the secondary control signal G. It can be seen from Figure 4 that when the drain-source voltage VDS increases to 0V, the synchronous rectifier SR should be turned off after time t1. However, when the flyback converter operates in DCM in an actual application, after the synchronous rectifier SR is turned off, the drain-source voltage VDS may ring (i.e., experience oscillatory behavior), and in this example, rings down to -100 mV at time t2. Therefore, the synchronous rectifier SR is accidentally turned on (falsely triggered) by the secondary control signal G at time t2. Summary of the invention

[0007] The following describes an overview of aspects of some examples disclosed herein. It should be understood that these aspects are presented only to provide the reader with a brief overview of these specific embodiments, and these aspects are not intended to limit the scope of the present disclosure. In fact, the present disclosure may include multiple aspects and / or a combination of multiple aspects that may not be described.

[0008] The present disclosure is directed to overcoming the disadvantages described in the background section. Specifically, the present disclosure is directed to preventing false triggering due to DCM ringing in a synchronous rectifier at the second side of a transformer in a synchronous flyback converter.

[0009] The present disclosure proposes a solution for preventing false triggering of synchronous rectifiers during DCM ringing. Advantageously, the synchronous rectifiers of the present disclosure can perform under all load conditions (ie, heavy load and light load).

[0010] According to aspects of the present disclosure, a controller for a synchronous rectifier is provided. The synchronous rectifier may include a switch that can be switched by a controller. The controller may include an adaptive slew rate detection circuit. The adaptive slew rate detection circuit may be configured to add a current to a basic slew rate current according to an off time of the switch to obtain a slew rate current. The slew rate current may determine a slew rate setting voltage. The controller may be configured to turn on the switch according to the slew rate setting voltage.

[0011] In an embodiment, the controller may further include a gate state detection circuit configured to detect an off state of the switch.The adaptive slew rate detection circuit may be configured to add a current to the base slew rate current when the switch is in an off state.

[0012] In an embodiment, the adaptive slew rate detection circuit may include a plurality of current selectors. Each current selector may be configured to detect a different off-time of the switch based on a voltage generated during the off-time of the switch due to the charging characteristics of the capacitor. Each current selector may be configured to include a different current source in the adaptive slew rate detection circuit to add a corresponding current to the base slew rate current.

[0013] In an embodiment, each current selector may be configured to switch a current switch to include a corresponding current source into the slew rate detection circuit.

[0014] In another embodiment, the adaptive slew rate detection circuit may include a current selector. The current selector may be configured to incrementally add current according to the off-time of the switch based on a voltage generated during the off-time of the switch due to the charging characteristics of the capacitor.

[0015] In an embodiment, the synchronous rectifier may be configured to operate in a discontinuous current mode.

[0016] In an embodiment, the switch may include a field effect transistor.

[0017] According to aspects of the present disclosure, a synchronous flyback converter is provided. The synchronous flyback converter may include a transformer. The synchronous flyback converter may include a primary switch coupled to a primary winding of the transformer. The synchronous flyback converter may include a synchronous rectifier coupled to a secondary winding of the transformer. The synchronous rectifier may include a secondary switch that may be switched under the control of a controller having one or more of the above features.

[0018] According to an aspect of the present disclosure, a switching power supply is provided, which may include a synchronous flyback converter having one or more of the above features. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying schematic drawings, in which corresponding reference characters indicate corresponding parts, and in which:

[0020] FIG1 shows a known rectification scheme using a diode D for non-synchronous rectification;

[0021] FIG. 2 shows a known rectification scheme using a synchronous rectifier for synchronous rectification;

[0022] FIG3 shows an exemplary current-voltage characteristic of a switching converter having a non-synchronous rectifier as in FIG1 and a synchronous rectifier as in FIG2;

[0023] FIG4 schematically shows waveforms of a drain-source voltage and a control signal of a known synchronous rectifier of a synchronous flyback converter in DCM;

[0024] Figure 5 schematically illustrates an exemplary synchronous rectification scheme for an exemplary flyback converter;

[0025] Figure 6 Shows Figure 5 An exemplary graph of various voltage characteristics of a synchronous rectification scheme;

[0026] Figure 7 Schematically illustrates a secondary controller of an exemplary embodiment of the present disclosure;

[0027] Figure 8 and Fig.10 Schematically illustrates different implementations of a dynamic slew rate detection circuit of a secondary controller of an exemplary embodiment of the present disclosure; and

[0028] Fig. 9 and Fig.11 They are shown respectively Figure 8 and Fig.10 An exemplary graph of the voltage and current characteristics of a dynamic slew rate detection circuit.

[0029] The drawings are for illustrative purposes only and are not intended to limit the scope of protection defined by the claims. DETAILED DESCRIPTION

[0030] It is readily understood that the components of the embodiments as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following more detailed description of various embodiments, as shown in the accompanying drawings, is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments. Although various aspects of the embodiments are presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0031] The described embodiments are to be considered in all respects only as illustrative and not restrictive. Therefore, the scope of the present disclosure is indicated by the appended claims rather than the detailed description. All changes within the meaning and range of equivalents of the claims are included within the scope of the claims.

[0032] References to features, advantages, or similar language throughout this specification do not imply that all features and advantages that can be realized by the present disclosure should be or are in any single example of the present disclosure. Instead, language referring to features and advantages is understood to mean that a particular feature, advantage, or characteristic described in conjunction with an embodiment is included in at least one embodiment of the present disclosure. Therefore, throughout this specification, discussions of features and advantages and similar language may, but do not necessarily, refer to the same example.

[0033] In addition, the features, advantages and characteristics of the present disclosure may be combined in one or more embodiments in any suitable manner. According to the description herein, those skilled in the relevant art will recognize that the present disclosure can be practiced without one or more specific features or advantages of a particular embodiment. In other cases, additional features and advantages that may not be present in all embodiments of the present disclosure may be recognized in certain embodiments. Throughout this specification, references to "one embodiment", "embodiment" or similar language mean that the specific features, structures or characteristics described in conjunction with the illustrated embodiment are included in at least one embodiment of the present disclosure. Therefore, throughout this specification, the phrases "in one embodiment", "in an embodiment" and similar language may but do not necessarily all refer to the same embodiment.

[0034] In the following exemplary embodiments, numerous specific details are provided, such as examples of circuits, components, and methods, to provide a thorough understanding of the embodiments of the present technology. However, one of ordinary skill in the art will recognize that the technology can be practiced without one or more of the specific details. In other cases, well-known details are not shown or described to avoid obscuring various aspects of the technology.

[0035] In the context of flyback topologies and power electronics, the term "slew rate" generally refers to the rate of change of voltage or current in a circuit.

[0036] The present disclosure proposes an adaptive conversion rate detection method for synchronous rectification, wherein the conversion rate can be set differently based on the length of the off time of the synchronous rectifier at the second side of the transformer. The shorter the off time, the higher the conversion rate, which can advantageously prevent the switch (i.e., the switch of the synchronous rectifier) ​​from being falsely triggered during DCM ringing. At the same time, the solution of the present invention ensures that the switch tube is more reliably turned on under light load conditions, and thus improves the light load efficiency.

[0037] To better understand the concepts of conversion rate and false triggering, Figure 5 and Figure 6 An example of a synchronous rectification scheme 500 for a flyback converter and exemplary voltage characteristics of this rectification scheme are shown, respectively. Figure 5 The rectification scheme of FIG. 2 is similar to that of FIG. 2 , with the addition of switch controllers 502 and 504 and an energy storage circuit including a diode D1 , a resistor R1 , and a capacitor C1 at the primary side of the transformer T1 .

[0038] The synchronous rectifier scheme 500 includes a transformer T1. A primary switch S1 can be coupled to a primary winding of the transformer T1. The primary switch S1, such as a FET, can be turned on and off under the control of a primary controller 502. The primary switch S1 can be further coupled to an energy storage circuit. A synchronous rectifier SR can be coupled to a secondary winding of the transformer T1. A secondary switch S2 of the synchronous rectifier SR, such as a FET, can be turned on and off via its gate G under the control of a secondary controller 504. Figure 5 Also shown are resistor R2, capacitor C3 and output voltage pins V+ and V-.

[0039] The primary controller 502 and the secondary controller 504 may be connected to the gate G of the primary switch S1 and the gate G of the secondary switch S2, respectively, to control the on and off states of the switches S1 and S2. Figure 5 In the example of FIG. 5 , the secondary controller 504 may be preconfigured to detect a specific slew rate in the drain-source voltage Vds_S2 of the secondary switch S2 , which may trigger the secondary controller 504 to switch the switch S2 .

[0040] exist Figure 6 , the drain-source voltage Vds_S1 of the first switch S1 and the drain-source voltage Vds_S2 of the second switch S2 are plotted over time as lines 602 and 604. In this example, between t0 and t1, the system is under heavy load, while between t1 and t4, the system is under light load. The portion of the graph 604 of Vds_S2 in the dashed circle at t1, t3, and t4 is enlarged and displayed as an enlarged section 606 below the graph.

[0041] exist Figure 6 In the example of , under normal operation, from time t1 to t2, the primary switch S1 can be turned on at t1. The high slew rate in Vds_S2 can then trigger the secondary controller 504 to turn on the secondary switch S2 of the synchronous rectifier SR, which is shown by the curve graph 608, where the control signal at the gate G of the secondary switch S2 goes high at t1. Under normal operation, as long as Vds_S2 is at 0V, the control signal at the gate G should remain high, thereby keeping the synchronous rectifier SR in the on state. At time t2, the transformer T1 can be demagnetized, and as Vds_S1 drops, Vds_S2 begins to rise, and therefore the secondary switch S2 can be turned off. When the slew rate of the voltage drop is slower than the slew setting of the secondary controller 504, the secondary switch S2 can remain off during the DCM ringing period between t2 and t3b. In Figure 6 In the example of , at time t3b, the Vds_S2 signal 604 stabilizes (DCM ringing stops) and the secondary switch S2 remains in the off state. At time t4, the secondary controller 504 may detect a low slew rate, thereby triggering the control signal at the gate G to go high, thereby turning on the secondary switch S2.

[0042] In the known secondary controller 504, the slew rate setting of the control signal at the gate G that triggers the secondary switch S2 has a fixed value. Under light load conditions, the magnitude of the DCM ringing in Vds_S1 caused by the magnetic induction of the primary switch S1 and the output capacitance (Coss) can increase significantly after the secondary switch S2 is turned off. Figure 6 In the example of , at t2, this can cause Vds_S2 to also become strongly resonant. Therefore, the waveform of Vds_S2 can change from the original sine wave to an approximate trapezoidal wave, which is shown as the second clipped line on the top of the sine waveform in the graph 604. Figure 6 In the example of FIG. 6 , the slope of Vds_S2 at the zero-crossing time t3 may increase significantly, which is shown in the enlarged graph 606 by the high transition below the low transition at t3 .

[0043] If the detected slew rate is faster than the internal setting of the secondary controller 504, the high transition at t3 may falsely trigger the secondary controller 504, thereby causing the secondary switch S2 to be erroneously switched. This is shown in graph 610, where the gate signal at gate G goes high at t3, where it should remain low, as shown in graph 608.

[0044] Another example of false triggering may occur at t4. When S1 is turned off at t1, the leakage inductance and Coss of the primary switch S1 may resonate. The slew rate of Vds_S2 at t4 (under light load) may be much lower than the slew rate of Vds_S2 at t1 (under heavy load). Therefore, if the detected slew rate is slower than the internal setting of the secondary controller 504, the secondary switch S2 may not be triggered. This is shown in the graph 612, where the gate signal G remains low at t4, where it should go high as shown in the graph 608.

[0045] If the slew rate is set too fast, the secondary switch S2 may not be falsely triggered during the DCM ringing, but the secondary switch S2 generally cannot be turned on under most load conditions. On the other hand, if the slew rate is set too low, the secondary switch S2 may be turned on even under light loads, but may be falsely triggered during the DCM ringing. Therefore, with a fixed slew rate setting, it is difficult to correctly turn on the secondary switch S2 while preventing the secondary switch S2 from being falsely triggered during the DCM ringing.

[0046] The present disclosure proposes solutions to the above-mentioned shortcomings of known synchronous flyback converters, and in particular proposes adaptive slew rate setting / detection at the secondary controller of the synchronous rectifier SR. To this end, the secondary controller 504 can be adapted to detect the time off period of the secondary switch S2, and adjust the slew rate setting accordingly. For example, the longer the secondary switch S2 is off (the control signal at the gate G is likely to be low), the lower the slew rate setting. Figure 6 In the example of , the slew rate setting at t4 can be dynamically set to be lower than the slew rate setting at t3b, the slew rate setting at t3b can be dynamically set to be lower than the slew rate setting at t3a, and the slew rate setting at t3a can be dynamically set to be lower than the slew rate setting at t3. In this example, the slew rate setting at t3 can therefore be the fastest, thereby preventing the secondary switch S2 from falsely triggering during DCM ringing. In this example, the slew rate setting at t4 can therefore be the slowest, so that the secondary switch S2 can be turned on even under light load conditions.

[0047] Figure 7 An exemplary embodiment of an improved secondary controller 704 is shown, which may replace Figure 5 The secondary controller 504. Figure 7 Only the parts of the controller 704 that are involved in adaptive slew rate setting and detection are shown. Other parts not shown may be implemented in a manner known per se, for example, similar to any known secondary controller.

[0048] exist Figure 7In the embodiment, a detector 710 implemented, for example, using a comparator, can detect the current slew rate in the Vds_S2 signal. The output of the detector 710 can be a voltage indicating the degree of decrease of Vds_S2. Figure 7 is depicted as Vslew_dec, thus indicating the detected slew rate. Figure 7 In the example of FIG. 4 , capacitor C2 induces a current Ic2 .

[0049] The comparator 712 may compare the detected slew rate Vslew_dec with an adaptive slew rate setting Vslew_set, which may be determined by an adaptive slew rate circuit, an example of which will be described with reference to FIG. Figures 8 to 11 Explain. Figure 7 In the example of , the detected slew rate Vslew_dec can be input to the negative input of the comparator 712, and the adaptive slew rate setting Vslew_set can be input to the positive input of the comparator 712. The output of the comparator 712 is the trigger signal Vslew_out, which can or can be used to generate a control signal that triggers switching of the gate G of the secondary switch S2.

[0050] Figure 7 It should be understood as a non-limiting example. Other components or configurations may be used instead of the detector 710, i.e. the detection of the current slew rate in the Vds_S2 signal may be performed in any manner known per se, for example, by the known secondary controller 504 using a fixed slew rate setting. Other components or configurations may be used instead of the comparator 712 to compare the detected slew rate Vslew_dec with the adaptive slew rate setting Vslew_set and generate the trigger signal Vslew_out.

[0051] Figure 8 and Fig.10 1 shows a block diagram of an exemplary embodiment of an adaptive slew rate circuit 800, 1000 for determining an adaptive slew rate setting Vslew_set. The adaptive slew rate circuit 800, 1000 is typically part of the secondary controller 704. Figure 8 In an exemplary embodiment of the present invention, the adaptive conversion rate setting can be a step mode, thereby producing Fig. 9 The example shows the slew rate setting Vslew_set. Fig.10 In the example of FIG. 1 , the adaptive conversion rate setting can be a continuous mode, resulting in Fig.11 The example shown in FIG. 1 shows the slew rate setting Vslew_set.

[0052] When the secondary switch S2 is closed, that is, when the control signal of the gate G of the secondary switch S2 is low, the slew rate detection circuit, such as the circuit 800 or 1000, is usually active. Figure 6 In the example of , this corresponds to the period before t1 and the period between t2 and t4, where the slew rate is used to trigger the turning on of the secondary switch S2.

[0053] The closed state of the secondary switch S2 can be detected by the gate state detection circuit 802, 1002, for example Figure 8 and Fig.10 . When the control signal at the gate G is low, the gate voltage VG may be low, causing the inverter 804, 1004 to generate a high signal that closes the switch 806, 1006. The slew rate detection circuit 800, 1000 may then be connected to the voltage source VCC. The other switch 808, 1008 of the gate state detection circuit 802, 1002 may then be opened.

[0054] Similarly, the open state of the secondary switch S2 can be detected by the gate state detection circuit 802, 1002. When the control signal at the gate G is high, the gate voltage VG may be high, causing the inverter 804, 1004 to generate a low signal, thereby opening the switch 806, 1006. Then, the slew rate detection circuit 800, 1000 can be disconnected from the voltage source VCC. Another switch 808, 1008 of the gate state detection circuit 802, 1002 can then be closed.

[0055] When the secondary switch S2 is closed, that is, VG is low, the switch 806 / 1006 is closed, and the switch 808 / 1008 is open, and the capacitor C1 is charged by the current I1. Therefore, the longer the secondary switch S2 is turned off, the higher the voltage of Vc1.

[0056] exist Figure 8 In the example of FIG. 8 , the slew rate detection circuit 800 includes a plurality of current selectors 810, each of which controls a switch 812 for including a current source into the circuit 800. The current flowing through the slew rate resistor Rslew, depicted as the slew rate current Ir, can generate an adaptive slew rate setting voltage Vslew_set used by the secondary controller 704, such as Figure 7 shown.

[0057] exist Figure 8In the example, the slew rate resistor Rslew can be charged by the base current Ir1 at the beginning. If Vc1 is higher than Vr1, the current selector 810 at Vr1 can close the corresponding switch 812, and the current Ir2 can be added to Ir. If Vc1 is higher than Vr2, the current selector 810 at Vr2 can close its corresponding switch 812, and the current Ir3 can be added to Ir. If Vc1 is higher than Vr3, the current selector 810 at Vr3 can close its corresponding switch 812, and the current Ir4 can be added to Ir. According to the requirements of the embodiment, any number of boost converters 810 can be present to gradually add current to Ir.

[0058] Fig. 9 An example of the gradual increase of the current Ir as a result of adding a current source to the circuit through the current selector 810 is shown. The top graph shows the level of the voltage Vc1 over time. When Vc1 reaches Vr1, the current source Ir2 can be added to the circuit, such that the current boosts from Ir to Ir+Ir2, as Fig. 9 shown in the middle graph. When Vc1 reaches Vr2, the current source Ir3 can be added to the circuit, such that the current further boosts from Ir+Ir2 to Ir+Ir2+Ir3. When Vc1 reaches Vr3, the current source Ir4 can be added to the circuit, such that the current further boosts from Ir+Ir2+Ir3 to Ir+Ir2+Ir3+Ir4. The corresponding slew rate set voltage Vslew_set is shown in Fig. 9 the bottom graph.

[0059] In Fig.10 the example, the slew rate detection circuit 1000 includes a current selector 1010 for continuously increasing the output current Ir2 according to the voltage Vc1. The current flowing through the slew rate resistor Rslew, depicted as the slew rate current Ir, can generate an adaptive slew rate set voltage Vslew_set used by the secondary controller 704, such as Figure 7 shown.

[0060] In Fig.10 the example, the slew rate resistor Rslew can be charged by a first current source Ir1 that increases with the current I2 from the current selector 1010. For example, when Vc1 < Vr1, the current Ir2 can be set to zero, and when Vr1 < Vc1 < Vr2, the current Ir2 can be set to (Vc1 - Vr1)*K.

[0061] Fig.11An example of a continuous increase in current Ir as a result of adding current Ir2 to the circuit through current selector 1010 is shown. The top graph shows the level of voltage Vc1 over time. When Vc1 reaches Vr1, current Ir2 can be added to the circuit and current I2 continues to increase until Vc1 reaches Vr2. The corresponding slew rate setting voltage Vslew_set is Fig.11 is shown in the bottom graph.

[0062] refer to Figure 7 , for example, the higher the Vslew_set determined by the slew rate detection circuit 800 or 1000, the longer it takes for C2 to charge to the voltage level of Vslew_set, and therefore the slower the slew rate Vslew_out. Figure 7 In the example of FIG. 1 , the slew rate Vslew_out may be determined to be 2V (ie, Figure 7 In the example above, the maximum value of Vds_S2 is divided by the charging time of C2.

[0063] The present application can be advantageously used in fast chargers and power adapters.

Claims

1. A controller (704) of a synchronous rectifier (SR), The synchronous rectifier (SR) comprises a switch (S2) switchable by the controller (704), and The controller (704) includes an adaptive slew rate detection circuit (800, 1000), wherein the adaptive slew rate detection circuit (800, 1000) is configured to add a current (Ir2, Ir3, Ir4) to a basic slew rate current (Ir1) according to an off time of the switch (S2) to obtain a slew rate current (Ir), wherein the slew rate current (Ir) determines the slew rate setting voltage (Vslew_set), And wherein the controller (704) is configured to turn on the switch (S2) according to the slew rate setting voltage (Vslew_set).

2. The controller (704) according to claim 1, Also includes a gate state detection circuit (802, 1002) configured to detect the off state of the switch (S2), And wherein the adaptive slew rate detection circuit (800, 1000) is configured to add the current (Ir2, Ir3, Ir4) to the basic slew rate current (Ir1) when the switch (S2) is in the off state.

3. The controller (704) according to claim 1 or claim 2, The adaptive conversion rate detection circuit (800) comprises a plurality of current selectors (810), wherein each current selector (810) is configured to detect different off-times of the switch (S2) based on a voltage (Vc1) generated due to a charging characteristic of a capacitor (C1) during the off-time of the switch (S2); And wherein each current selector (810) is configured to include a different current source in the adaptive slew rate detection circuit (800) to add a corresponding current (Ir2, Ir3, Ir4) to the base slew rate current (Ir1).

4. The controller (704) of claim 3, wherein each current selector (810) is configured to switch a current switch (812) to include the corresponding current source into the slew rate detection circuit (800).

5. The controller (704) according to claim 1 or claim 2, The adaptive slew rate detection circuit (1000) comprises a current selector (1010), And wherein the current selector (1010) is configured to incrementally add the current (Ir2) according to the off time of the switch (S2) based on a voltage (Vc1) generated due to charging characteristics of the capacitor (C1) during the off time of the switch (S2).

6. The controller (704) according to any one of the preceding claims, wherein the synchronous rectifier (SR) is configured to operate in a discontinuous current mode (DCM).

7. The controller (704) according to any one of the preceding claims, wherein the switch (S2) comprises a field effect transistor (FET).

8. A synchronous flyback converter, comprising: Transformer (T1), a primary switch (S1) coupled to the primary winding of the transformer (T1), and a synchronous rectifier (SR), coupled to the secondary winding of the transformer (T1), The synchronous rectifier (SR) comprises a secondary switch (S2) which can be switched under the control of a controller (704) according to any one of claims 1 to 6.

9. A switching power supply comprising the synchronous flyback converter according to claim 8.

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