Dead time adjusting circuit and method

Abstract

The invention provides a dead time adjusting circuit and method. The dead time adjusting circuit comprises a first phase discriminator, a second phase discriminator, a charge pump circuit and a driving circuit, the first phase discriminator generates a first pulse control signal by detecting the phase difference between node signals of the two power tubes and a first driving feedback signal, the second phase discriminator generates a second pulse control signal by detecting the phase difference between the two driving feedback signals, and the charge pump circuit converts the two pulse control signals into voltage signals and outputs the voltage signals to the power tube. The voltage signal can change the phase difference of the signal by adjusting the transmission time delay of the driving signal output to the second power tube by the driving circuit, and then through the detection and feedback of the phase discriminator, when the direct current voltage signal output by the charge pump circuit is stable, the phase difference of the signal is locked, that is, the dead time is locked, and the dead time is locked. Therefore, self-adaptive adjustment and stabilization of dead time are completed, and circuit power consumption is reduced while circuit conversion reliability is guaranteed.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a dead time adjustment circuit and method. Background Art

[0002] The DC / DC switching power supply circuit is a voltage converter that converts the input DC voltage into a DC output voltage. The current mainstream architecture is the synchronous DC / DC converter. Due to the delay of the drive control signal in the actual circuit, there will be a phenomenon that the high-side power tube and the low-side power tube in the power stage circuit are turned on at the same time, which will not only reduce the conversion efficiency, but also may cause the risk of chip burning. By introducing a "dead time" in the high-side and low-side power tube drive circuits of the DC / DC converter, the drive signal becomes a non-overlapping clock, which can avoid the situation where the power tubes are turned on at the same time. During the dead time, the power stage circuit uses the parasitic body diode of the power MOS tube for freewheeling, ensuring that the circuit can work normally but increasing some static losses. The longer the dead time, the greater the loss.

[0003] Traditional dead time design circuits mostly use the RC delay method. This design method does not have a feedback detection signal. If the dead time is too small, the reliability of the circuit under various working conditions cannot be guaranteed. If the dead time is too large, the freewheeling diode will be turned on for too long, causing greater energy loss and reducing the circuit conversion efficiency. Summary of the invention

[0004] The main purpose of the present application is to provide a dead time adjustment circuit and method, which can at least solve the problem in the related art that the dead time cannot be adaptively adjusted, resulting in large losses in circuit energy and conversion efficiency.

[0005] To achieve the above-mentioned purpose, the first aspect of the present application provides a dead time adjustment circuit, including: a first phase detector, a second phase detector, a charge pump circuit and a drive circuit; the first phase detector is electrically connected to the drive circuit and is used to be electrically connected to the node of the first power tube and the second power tube in the external power stage switch power supply circuit, and the first phase detector is configured to: generate a first pulse control signal according to the phase difference between the node signal and the first drive feedback signal transmitted by the drive circuit; wherein the node signal is a signal at the node between the first power tube and the second power tube; the second phase detector is electrically connected to the drive circuit, and the second phase detector is configured to: generate a first pulse control signal according to the node signal and the phase difference between the first drive feedback signal transmitted by the drive circuit The phase difference between the first drive feedback signal and the second drive feedback signal transmitted by the driving circuit generates a second pulse control signal; the charge pump circuit is electrically connected to the first phase detector and the second phase detector respectively, and the charge pump circuit is configured to: generate a corresponding voltage signal according to the first pulse control signal and the second pulse control signal; the driving circuit is electrically connected to the charge pump circuit and is used to be electrically connected to the first power tube and the second power tube respectively, and the driving circuit is configured to: generate a driving signal to transmit to the first power tube and the second power tube, and adjust the delay time of the driving signal transmitted to the second power tube according to the voltage signal.

[0006] The second aspect of the present application provides a dead time adjustment method, including the dead time adjustment circuit as described in the first aspect of the present application, including: a first phase detector generates a first pulse control signal according to the phase difference between a node signal and a first drive feedback signal transmitted by a drive circuit; wherein the node signal is a signal at a node between the first power tube and the second power tube; a second phase detector generates a second pulse control signal according to the phase difference between the first drive feedback signal and the second drive feedback signal transmitted by the drive circuit; a charge pump circuit generates a corresponding voltage signal according to the first pulse control signal and the second pulse control signal; the drive circuit generates a drive signal and transmits it to the first power tube and the second power tube, and adjusts the delay duration of the drive signal transmitted to the second power tube according to the voltage signal.

[0007] As can be seen from the above description, in the present application, the first phase detector generates a first pulse control signal by detecting the phase difference between the node signal of the two power tubes and the first drive feedback signal transmitted by the drive circuit, and the second phase detector generates a second pulse control signal by detecting the phase difference between the first drive feedback signal and the second drive feedback signal. The charge pump circuit converts the two pulse control signals into voltage signals, and the voltage signal can change the phase difference between the node signal and the first drive feedback signal, and the phase difference between the first drive feedback signal and the second drive feedback signal by adjusting the transmission delay of the drive signal output by the drive circuit to the second power tube. After the detection and feedback of the first phase detector and the second phase detector, when the DC voltage signal output by the charge pump circuit is stable, the phase difference between the switch node and the first drive feedback signal, and the phase difference between the first drive feedback signal and the second drive feedback signal are locked, that is, the dead time of the two stages are locked, thereby completing the adaptive adjustment and stabilization of the dead time through phase detection and signal feedback, ensuring the reliability of circuit conversion while reducing circuit power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0009] Figure 1 is a structural schematic diagram of a dead time adjustment circuit according to an embodiment of the present application;

[0010] Figure 2 is a circuit schematic diagram of a first phase detector according to an embodiment of the present application;

[0011] Figure 3 is a working signal waveform diagram of the first phase detector in an embodiment of the present application;

[0012] Figure 4 is a circuit schematic diagram of a second phase detector according to an embodiment of the present application;

[0013] Figure 5 is a waveform diagram of working signals in the second phase detector of an embodiment of the present application;

[0014] Figure 6 is a circuit schematic diagram of a charge pump circuit according to an embodiment of the present application;

[0015] Figure 7 is a circuit schematic diagram of a driving circuit according to an embodiment of the present application;

[0016] Figure 8is a structural schematic diagram of another dead time adjustment circuit in an embodiment of the present application;

[0017] Fig. 9 is a waveform diagram of working signals in the driving circuit of an embodiment of the present application;

[0018] Fig.10 It is a basic flow chart of a dead time adjustment method according to an embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the purpose, features, and advantages of the invention of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0020] In the related art, since the dead time cannot be adaptively adjusted, the circuit energy and conversion efficiency are greatly lost. Therefore, an embodiment of the present application provides a dead time adjustment circuit.

[0021] like Figure 1 The figure shows a schematic diagram of the structure of a dead time adjustment circuit provided by an embodiment of the present application, wherein the dead time adjustment circuit comprises: a first phase detector 100, a second phase detector 200, a charge pump circuit 300 and a drive circuit 400; the first phase detector 100 is electrically connected to the drive circuit 400 and is used to be electrically connected to the nodes of the first power tube H_MOS and the second power tube L_MOS in the external power stage switch power supply circuit 500, and the first phase detector 100 is configured to: generate a first pulse control signal according to the phase difference of the node signal and the first drive feedback signal transmitted by the drive circuit 400; the second phase detector 200 is electrically connected to the drive circuit 400, and the second phase detector 200 is configured to: generate a first pulse control signal according to the phase difference of the node signal and the first drive feedback signal transmitted by the drive circuit 400; 0 to generate a second pulse control signal; the charge pump circuit 300 is electrically connected to the first phase detector 100 and the second phase detector 200 respectively, and the charge pump circuit 300 is configured to: generate a corresponding voltage signal according to the first pulse control signal and the second pulse control signal; the drive circuit 400 is electrically connected to the charge pump circuit 300 and is used to be electrically connected to the first power tube H_MOS and the second power tube L_MOS respectively, and the drive circuit 400 is configured to: generate a drive signal to transmit to the first power tube H_MOS and the second power tube L_MOS, and adjust the delay time of the drive signal transmitted to the second power tube L_MOS according to the voltage signal.

[0022] Specifically, in the present embodiment, the first phase detector 100 generates a first pulse control signal by detecting the phase difference between the node signal at the common connection end (i.e., the node) of the two power tubes and the first drive feedback signal, wherein the first pulse control signal is used to indicate the rising edge dead time (i.e., when the turn-on drive signal of the first power tube H_MOS arrives, the delay time required for the turn-off drive signal of the second power tube L_MOS to arrive, i.e., the interval time between the turn-on moment of the first power tube H_MOS and the turn-off moment of the second power tube L_MOS), and the second phase detector 200 generates a second pulse control signal by detecting the phase difference between the first drive feedback signal and the second drive feedback signal, wherein the second pulse control signal is used to indicate the falling edge dead time (i.e., when the turn-off drive signal of the first power tube H_MOS arrives, the delay time required for the turn-on drive signal of the second power tube L_MOS to arrive, i.e., the interval time between the turn-on moment of the first power tube H_MOS and the turn-off moment of the second power tube L_MOS). The charge pump circuit 300 converts the two pulse control signals into a DC voltage signal, and the DC voltage signal is transmitted through the drive circuit 400 to the second power tube L_MOS by adjusting the transmission delay of the drive signal transmitted to the second power tube L_MOS, wherein the drive signal transmitted to the second power tube L_MOS is the same as the first drive feedback signal, so that the phase difference between the node signal and the first drive feedback signal, and the phase difference between the first drive feedback signal and the second drive feedback signal can be changed. After detection and feedback by the first phase detector 100 and the second phase detector 200, when the DC voltage signal output by the charge pump circuit 300 is stable, the phase difference between the switch node and the first drive feedback signal, and the phase difference between the first drive feedback signal and the second drive feedback signal are locked, that is, the rising edge dead time and the falling edge dead time are locked, thereby completing the adjustment and stabilization of the dead time, avoiding the dead time being fixed, causing energy loss when it is too large, and failing to ensure the reliability of the circuit when it is too small. Under the condition that the driving clock signals are not overlapped, this embodiment can reduce the dead time to a smaller value by means of phase detection and feedback, thereby reducing the power consumption of the circuit while ensuring the reliability of circuit conversion.

[0023] like Figure 2 FIG. 1 is a circuit diagram of a first phase detector 100 provided in this embodiment. Figure 2 , the first phase detector 100 includes a first pulse signal generating circuit 110, a first level conversion circuit, a first buffer BUFF1, a first NOR gate NOR1 and a first NAND gate NAND1, the first pulse signal generating circuit 110 is electrically connected to the driving circuit 400, the first NOR gate NOR1 and the first NAND gate NAND1 respectively, the first buffer BUFF1 is electrically connected to the first level conversion circuit, the first NOR gate NOR1 and the first NAND gate NAND1 respectively, and the first level conversion circuit is also used to be electrically connected to the node; wherein:

[0024] The first pulse signal generating circuit 110 is configured to: generate a first pulse signal and a second pulse signal according to a first driving feedback signal; wherein, the high-level pulse width of the first pulse signal is equal to the low-level pulse width of the second pulse signal, and the rising edge of the first pulse signal, the falling edge of the second pulse signal and the falling edge of the first driving feedback signal occur simultaneously; the first level conversion circuit is configured to: perform level conversion on the node signal of the high voltage domain to obtain a target node signal; the first NOR gate NOR1 is configured to: generate a first sub-pulse control signal according to the phase difference between the rising edge of the target node signal and the falling edge of the second pulse signal; the first NAND gate NAND1 is configured to: generate a second sub-pulse control signal according to the phase difference between the rising edge of the target node signal and the falling edge of the first pulse signal.

[0025] For further information, see Figure 2 The first pulse signal generating circuit 110 includes a first inverter INV1, a second inverter INV2 and a first pulse generator; the first inverter INV1 is electrically connected to the driving circuit 400 and one end of the first pulse generator respectively, the other end of the first pulse generator is electrically connected to one end of the second inverter INV2 and the first NAND gate NAND1 respectively, and the other end of the second inverter INV2 is electrically connected to the first NOR gate NOR1.

[0026] Specifically, in this embodiment, the two input ends of the first phase detector 100 are respectively connected to the nodes of the two power tubes in the power stage switching power supply circuit 500 and the output end of the driving circuit 400, and the first phase detector 100 is used to detect the phase difference between the rising edge of the node signal SW and the falling edge of the first drive feedback signal LO_FB corresponding to the second power tube L_MOS (the first drive feedback signal is the same as the drive signal of the second power tube), and generate a pulse control signal. Among them, the first level conversion circuit in the first phase detector 100 is a high-speed level conversion circuit from a high voltage domain to a low voltage domain, which is used to convert the node signal SW in the high voltage domain into a target node signal SW_SENSE suitable for the internal voltage domain of the circuit, and the target node signal SW_SENSE is transmitted to the first NOR gate NOR1 and the first NAND gate NAND1 after passing through the first buffer BUFF1. The first drive feedback signal LO_FB reaches the first pulse generator after passing through the first inverter INV1. The first pulse generator generates a first pulse signal LO_SENSE_N with a high level pulse width of TON1. The first pulse signal LO_SENSE_N becomes a second pulse signal LO_SENSE_A with a low level pulse width of TON1 after passing through the second inverter INV2. Figure 3The pulse signal waveform diagram shows that the rising edge of the first pulse signal LO_SENSE_N and the falling edge of the second pulse signal LO_SENSE_A are aligned with the falling edge of the first drive feedback signal LO_FB, that is, the three occur at the same time. The first NOR gate NOR1 is used to detect the phase difference between the rising edge of the target node signal SW_SENSE and the falling edge of the second pulse signal LO_SENSE_A, and generate the first sub-pulse control signal VDOWN1; the first NAND gate NAND1 is used to detect the phase difference between the rising edge of the target node signal SW_SENSE and the falling edge of the first pulse signal LO_SENSE_N, and generate the second sub-pulse control signal VUP1; thus, the sum of the single high-level pulse width of the first sub-pulse control signal VDOWN1 and the single low-level pulse width of the second sub-pulse control signal VUP1 is TON1, that is, VUP1_TOFF+VDOWN1_TON=TON1.

[0027] like Figure 4 FIG. 1 is a circuit diagram of a second phase detector 200 provided in this embodiment. Figure 4 The second phase detector 200 includes a second pulse signal generating circuit 210, a second level conversion circuit, a second buffer BUFF2, a second NOR gate NOR2 and a second NAND gate NAND2. The second buffer BUFF2 is electrically connected to the driving circuit 400, the second NOR gate NOR2 and the second NAND gate NAND2 respectively. The second pulse signal generating circuit 210 is electrically connected to the second level conversion circuit, the second NOR gate NOR2 and the second NAND gate NAND2 respectively. The second level conversion circuit is also electrically connected to the driving circuit 400; wherein:

[0028] The second level conversion circuit is configured to: perform level conversion on the second drive feedback signal in the high voltage domain to obtain a target drive feedback signal; the second pulse signal generating circuit 210 is configured to: generate a third pulse signal and a fourth pulse signal according to the target drive feedback signal; wherein the high level pulse width of the third pulse signal is equal to the low level pulse width of the fourth pulse signal, and the rising edge of the third pulse signal, the falling edge of the fourth pulse signal, and the falling edge of the target drive feedback signal occur simultaneously; the second NOR gate NOR2 is configured to: generate a third sub-pulse control signal according to the phase difference between the rising edge of the first drive feedback signal and the falling edge of the fourth pulse signal; the second NAND gate NAND2 is configured to: generate a fourth sub-pulse control signal according to the phase difference between the rising edge of the first drive feedback signal and the falling edge of the third pulse signal.

[0029] For further information, see Figure 4The second pulse signal generating circuit 210 includes a third inverter INV3 and a second pulse generator; one end of the second pulse generator is electrically connected to the second level conversion circuit, the other end of the second pulse generator is electrically connected to the second NAND gate NAND2 and one end of the third inverter INV3 respectively, and the other end of the third inverter INV3 is electrically connected to the second NOR gate NOR2.

[0030] Specifically, in this embodiment, the two input ends of the second phase detector 200 are connected to the output end of the driving circuit 400, and the second phase detector 200 is used to detect the phase difference between the falling edge of the second drive feedback signal HO_FB (the second drive feedback signal is the same as the drive signal of the first power tube) corresponding to the first power tube H_MOS and the rising edge of the first drive feedback signal LO_FB corresponding to the second power tube L_MOS, and generate a pulse control signal. Among them, the second level conversion circuit in the second phase detector 200 is a high-speed level conversion circuit from the high voltage domain to the low voltage domain, which is used to convert the second drive feedback signal HO_FB in the high voltage domain into a target drive feedback signal suitable for the internal voltage domain of the circuit, and then transmit it to the second pulse generator. The second pulse generator will generate a third pulse signal HO_SENSE_N with a high level pulse width of TON2. After passing through the third inverter INV3, the third pulse signal HO_SENSE_N becomes a fourth pulse signal HO_SENSE_A with a low level pulse width of TON2, see Figure 5 The pulse signal waveform diagram shows that the rising edge of the third pulse signal HO_SENSE_N and the falling edge of the fourth pulse signal HO_SENSE_A are aligned with the falling edge of the second drive feedback signal HO_FB, that is, the three occur at the same time. The first drive feedback signal LO_FB is transmitted to the second NOR gate NOR2 and the second NAND gate NAND2 after passing through the second buffer BUFF2. The second NOR gate NOR2 is used to detect the phase difference between the rising edge of the first drive feedback signal LO_FB and the falling edge of the fourth pulse signal HO_SENSE_A (that is, the falling edge of HO_FB), and generate a third sub-pulse control signal VDOWN2; the second NAND gate NAND2 is used to detect the phase difference between the rising edge of the first drive feedback signal LO_FB and the falling edge of the third pulse signal HO_SENSE_N, and generate a fourth sub-pulse control signal VUP2; thus, the sum of a single high-level pulse width of the third sub-pulse control signal VDOWN2 and a single low-level pulse width of the fourth sub-pulse control signal VUP2 is TON2, that is, VUP2_TOFF+VDOWN2_TON=TON2.

[0031] like Figure 6 FIG. 1 is a circuit diagram of a charge pump circuit 300 provided in this embodiment. Figure 6The charge pump circuit 300 includes a first current mirror 310, a second current mirror 320, a first MOS transistor PM3, a second MOS transistor NM3, a third MOS transistor PM5, a fourth MOS transistor NM5, a first capacitor C1 and a second capacitor C2; the source electrodes of the first MOS transistor PM3 and the third MOS transistor PM5 are electrically connected to the first current mirror 310, the source electrodes of the second MOS transistor NM3 and the fourth MOS transistor NM5 are electrically connected to the second current mirror 320, and the gate electrodes of the first MOS transistor PM3 and the second MOS transistor NM3 are electrically connected to the first phase detector 100. The gates of the third MOS transistor PM5 and the fourth MOS transistor NM5 are electrically connected to the second phase detector 200, the drain of the first MOS transistor PM3 is electrically connected to the drain of the second MOS transistor NM3 and the charge pump circuit 300, the drain of the third MOS transistor PM5 is electrically connected to the drain of the fourth MOS transistor NM5 and the charge pump circuit 300, the first capacitor C1 is electrically connected to the drain of the first MOS transistor PM3 and the first current mirror 310, and the second capacitor C2 is electrically connected to the drain of the third MOS transistor PM5 and the second current mirror 320.

[0032] For further information, see Figure 6 The first current mirror 310 includes a fifth MOS transistor PM1, a sixth MOS transistor PM2 and a seventh MOS transistor PM4; the sources of the fifth MOS transistor PM1, the sixth MOS transistor PM2 and the seventh MOS transistor PM4 are all electrically connected to the power supply, the gate of the fifth MOS transistor PM1 is electrically connected to the gate of the sixth MOS transistor PM2, the drain of the fifth MOS transistor PM1, the gate of the seventh MOS transistor PM4 and the second current mirror 320 respectively, the drain of the sixth MOS transistor PM2 is electrically connected to the source of the first MOS transistor PM3, and the drain of the seventh MOS transistor PM4 is electrically connected to the source of the third MOS transistor PM5.

[0033] For further information, see Figure 6The second current mirror 320 includes an eighth MOS tube NM1, a ninth MOS tube NM2, a tenth MOS tube NM4, an eleventh MOS tube NM6 and a constant current source IQ1; the gates of the eighth MOS tube NM1, the ninth MOS tube NM2, the tenth MOS tube NM4 and the eleventh MOS tube NM6 are electrically connected to one end of the constant current source IQ1, the other end of the constant current source IQ1 is electrically connected to the power supply, the drain of the eighth MOS tube NM1 is electrically connected to one end of the constant current source IQ1, the drain of the ninth MOS tube NM2 is electrically connected to one end of the constant current source IQ1, The drain is electrically connected to the first current mirror 310, the drain of the tenth MOS tube NM4 is electrically connected to the source of the second MOS tube NM3, the drain of the eleventh MOS tube NM6 is electrically connected to the source of the fourth MOS tube NM5, the sources of the eighth MOS tube NM1, the ninth MOS tube NM2, the tenth MOS tube NM4 and the eleventh MOS tube NM6 are all grounded, the source of the tenth MOS tube NM4 is also electrically connected to the first capacitor C1, and the source of the eleventh MOS tube NM6 is also electrically connected to the second capacitor C2.

[0034] Specifically, in this embodiment, the charge pump circuit 300 is used to adjust its own output voltage signals VCTRL1 and VCTRL2 according to the pulse control signals output by the first phase detector 100 and the second phase detector 200 , where VCTRL1 and VCTRL2 are DC voltage signals. Among them, MOS transistors NM1, NM2, NM4, and NM6 form a second current mirror 320, namely, an NMOS tube current mirror; MOS transistors PM1, PM2, and PM4 form a first current mirror 310, namely, a PMOS tube current mirror; MOS transistors PM3, NM3, PM5, and NM5 act as switches in the circuit. According to the ratio of the NMOS tube current mirror and the ratio of the PMOS tube current mirror, it can be obtained that 2IPM3=2IPM2=INM3=INM4, 2IPM4=2IPM5=INM5=INM6. According to the charge conservation principle, after multiple cycles of adjustment, when the voltage signal VCTRL1 and the voltage signal VCTRL2 are stable, the charge amount injected into the capacitor C1 through the switch PM3 and the charge amount discharged from the capacitor C1 through the switch should be equal, and then:

[0035] IPM2×VDOWN1_TON=INM3×VUP1_TOFF

[0036]

[0037] Similarly, we can get:

[0038] IPM4×VDOWN2_TON=INM6×VUP2_TOFF

[0039]

[0040] In the first phase detector 100 and the second phase detector 200:

[0041] VUP1_TOFF+VDOWN1_TON=TON1

[0042] VUP2_TOFF+VDOWN2_TON=TON2

[0043] Then when the voltage signal VCTRL1 is stable and the voltage signal VCTRL2 is stable, we have:

[0044]

[0045]

[0046] like Figure 7 FIG. 4 is a circuit diagram of a driving circuit 400 provided in this embodiment. Figure 7 , the driving circuit 400 includes a first power tube driving unit 410 and a second power tube driving unit 420, the first power tube driving unit 410 is electrically connected to the second phase detector 200, and the first power tube driving unit is respectively used to be electrically connected to the first power tube H_MOS and the external control signal generating circuit, the second power tube driving unit 420 is respectively electrically connected to the first phase detector 100, the second phase detector 200, and the charge pump circuit 300, and the second power tube driving unit 420 is respectively used to be electrically connected to the second power tube L_MOS and the control signal generating circuit; wherein:

[0047] The first power tube driving unit 410 is configured to generate a corresponding first driving signal to the first power tube H_MOS according to the control signal transmitted by the control signal generating circuit; the second power tube driving unit 420 is configured to generate a corresponding second driving signal according to the control signal transmitted by the control signal generating circuit, and adjust the delay time of the second driving signal transmitted to the second power tube L_MOS according to the voltage signal transmitted by the charge pump circuit 300.

[0048] For further information, see Figure 7The second power tube driving unit 420 includes a twelfth MOS tube PM6, a thirteenth MOS tube NM7, a fourteenth MOS tube PM7, a fifteenth MOS tube PM8, a sixteenth MOS tube NM8, a seventeenth MOS tube NM9, a first resistor R1, a second resistor R2, a third capacitor C3, a fourth inverter INV4, a first bias generator, a second bias generator and a third buffer BUFF3; the twelfth MOS tube PM6 is electrically connected to the first resistor R1 and is used to be electrically connected to the control signal generating circuit, the thirteenth MOS tube NM7 is electrically connected to the second resistor R2 and is used to be electrically connected to the control signal generating circuit, and the fourteenth MOS tube PM 7 are electrically connected to the first bias generator and the fifteenth MOS transistor PM8, respectively. The seventeenth MOS transistor NM9 are electrically connected to the second bias generator and the sixteenth MOS transistor NM8, respectively. The third capacitor C3 is electrically connected to the first resistor R1, the second resistor R2, the fifteenth MOS transistor PM8, the sixteenth MOS transistor NM8, and the fourth inverter INV4, respectively. The first bias generator and the second bias generator are also electrically connected to the charge pump circuit 300. The fourth inverter INV4 is also electrically connected to the first phase detector 100 and the second phase detector 200, respectively. The fourth inverter INV4 is also electrically connected to the second power tube L_MOS through the third buffer BUFF3.

[0049] Further, see Figure 7 The first power tube driving unit 410 includes an eighteenth MOS tube PM9, a nineteenth MOS tube NM10, a third resistor R3, a fourth capacitor C4, a third level conversion circuit and a fourth buffer BUFF4; the source of the eighteenth MOS tube PM9 is electrically connected to the power supply, the gates of the eighteenth MOS tube PM9 and the nineteenth MOS tube NM10 are both used to be electrically connected to the control signal generating circuit, the drain of the eighteenth MOS tube PM9 is electrically connected to one end of the third resistor R3, the other end of the third resistor R3 is respectively electrically connected to the drain of the nineteenth MOS tube NM10, one end of the fourth capacitor C4, and one end of the third level conversion circuit, the source of the nineteenth MOS tube NM10 and the other end of the fourth capacitor C4 are both grounded, the other end of the third level conversion circuit is respectively electrically connected to the second phase detector 200 and one end of the fourth buffer BUFF4, and the other end of the fourth buffer BUFF4 is used to be electrically connected to the first power tube H_MOS.

[0050] For further information, see Figure 8 As shown in the structural schematic diagram of the dead time adjustment circuit, the control signal generating circuit in this embodiment may include a PWM logic control circuit, an oscillator, a comparator and an operational amplifier circuit.

[0051] Specifically, in this embodiment, the driving circuit 400 is used to generate a power level driving signal, and at the same time, the dead time is adjusted by adjusting the transmission delay of the driving signal according to the voltage signals VCTRL1 and VCTRL2 output by the charge pump circuit 300. In the initial stage, the voltage signals VCTRL1 and VCTRL2 are both low, the bias voltage VBIAS1 generated by the first bias generator is very small, and the bias voltage VBIAS2 generated by the second bias generator is also very small, so the current I1 is very large and the current I2 is very small. Fig. 9 As shown in the signal waveform diagram in , when the control signal CTRL is "0" (i.e., a low-level signal), the signal at point A turns to "1" (i.e., a high-level signal) after the delay TDLY1 generated by the resistor R1 and the capacitor C1, and then the signal is converted into a high-voltage domain signal through the high-speed level conversion circuit, and the second drive feedback signal HO_FB corresponding to the first power tube H_MOS is output, and at the same time, the first power tube H_MOS (i.e., the high-side power tube) is driven to turn on after passing through the fourth buffer BUFF4, and the node signal SW is pulled high. The signal at point B turns to "1" after the delay TDLY2, and the signal at point B outputs the first drive feedback signal LO_FB corresponding to the second power tube L_MOS after passing through the third inverter INV3, and at the same time, the second power tube L_MOS (i.e., the low-side power tube) is turned off after passing through the third buffer BUFF3. Initially, the delay TDLY2 is much smaller than the delay TDLY1, so that the second power tube L_MOS is turned off first, and then the first power tube H_MOS is turned on, and the node signal SW is pulled high at the same time; at this time, the phase difference between the falling edge of the first drive feedback signal LO_FB and the rising edge of the node signal SW is the largest, that is, the rising edge dead time is the largest at this time. Afterwards, the first phase detector 100 detects the phase difference between the falling edge of the first drive feedback signal LO_FB and the rising edge of the node signal SW, and then the voltage signal VCTRL1 is increased through the charge pump circuit 300, so that the current I1 decreases, the delay TDLY2 begins to increase, and the difference between the delay TDLY2 and the delay TDLY1 is reduced. The phase difference between the falling edge of the first drive feedback signal LO_FB and the rising edge of the node signal SW gradually decreases until the voltage signal VCTRL1 is stable. At this time, the phase difference between the falling edge of the first drive feedback signal LO_FB and the rising edge of the node signal SW is locked. ; According to the working principle of the first phase detector 100 and the charge pump circuit 300, after the voltage signal VCTRL1 is stable, the phase difference between the detected rising edge of the target node signal SW_SENSE (i.e. the rising edge of the node signal SW) and the falling edge of the second pulse signal LO_SENSE_A (i.e. the falling edge of the first drive feedback signal LO_FB) is VDOWN1_TON. Then, when the voltage signal VCTRL1 is stable, the phase difference between the falling edge of the first drive feedback signal LO_FB and the rising edge of the node signal SW, i.e. the rising edge dead time TDEADTIME_H, is:

[0052]

[0053] Similarly, when the control signal CTRL is "1" (i.e., a high-level signal), the signal at point A turns to "0" (i.e., a low-level signal) after a delay of TDLY3, and then the signal is converted into a high-voltage domain signal through a high-speed level conversion circuit, and then the second drive feedback signal HO_FB corresponding to the first power tube H_MOS is output, and at the same time, the first power tube H_MOS is turned off after passing through the fourth buffer BUFF4. The signal at point B turns to "0" after a delay of TDLY4, and the first drive feedback signal LO_FB corresponding to the second power tube L_MOS is output after passing through the third inverter INV3, and at the same time, the second power tube L_MOS is driven to turn on after passing through the third buffer BUFF3. Initially, the delay TDLY4 is much greater than the delay TDLY3, so that the first power tube H_MOS can be turned off first and then the second power tube L_MOS can be turned on. At this time, the phase difference between the rising edge of the first drive feedback signal LO_FB and the falling edge of the second drive feedback signal HO_FB is the largest, that is, the falling edge dead zone time is the largest. Afterwards, the second phase detector 200 detects the phase difference between the rising edge of the first drive feedback signal LO_FB and the falling edge of the second drive feedback signal HO_FB, and then the voltage signal VCTRL2 is gradually increased through the charge pump circuit 300, so that the current I2 gradually increases, the delay TDLY4 gradually decreases and approaches the delay TDLY3, and the phase difference between the rising edge of the first drive feedback signal LO_FB and the falling edge of the second drive feedback signal HO_FB gradually decreases until the voltage signal VCTRL2 is stable, then the phase difference between the rising edge of the first drive feedback signal LO_FB and the falling edge of the second drive feedback signal HO_FB is Difference lock; According to the working principle of the second phase detector 200 and the charge pump circuit 300, after the voltage signal VCTRL2 is stable, the phase difference between the rising edge of the detected first drive feedback signal LO_FB (i.e., the LO rising edge) and the falling edge of the target drive feedback signal HO_SENSE_A (i.e., the second drive feedback signal HO_FB falling edge) is VDOWN2_TON. Then, when the voltage signal VCTRL2 is stable, the phase difference between the rising edge of the first drive feedback signal LO_FB and the falling edge of the second drive feedback signal HO_FB, i.e., the falling edge dead time TDEADTIME_L, is:

[0054]

[0055] Therefore, this embodiment uses a PLL-like detection method to control and lock the dead time. Compared with the traditional dead time design method, this embodiment uses the feedback adjustment of the phase detector and the charge pump circuit 300 to enable the dead time to be adaptively adjusted, that is, the dead time is reduced from the maximum value to stability, and the dead time when stable is TON2 / 3 and TON1 / 3. By reducing the dead time to a smaller value through detection and feedback, the circuit power consumption can be reduced while ensuring the reliability of circuit conversion.

[0056] The dead time adjustment circuit provided in the embodiment of the present application generates a first pulse control signal by detecting the phase difference between the node signal of the two power tubes and the first drive feedback signal transmitted by the drive circuit through the first phase detector, and generates a second pulse control signal by detecting the phase difference between the first drive feedback signal and the second drive feedback signal through the second phase detector. The charge pump circuit converts the two pulse control signals into a DC voltage signal. The DC voltage signal can change the phase difference between the node signal and the first drive feedback signal, and the phase difference between the first drive feedback signal and the second drive feedback signal by adjusting the transmission delay of the drive signal output from the drive circuit to the second power tube. After detection and feedback by the first phase detector and the second phase detector, when the DC voltage signal output by the charge pump circuit is stable, the phase difference between the switch node and the first drive feedback signal, and the phase difference between the first drive feedback signal and the second drive feedback signal are locked, that is, the dead time of the two stages are locked, thereby completing the adaptive adjustment and stabilization of the dead time through phase detection and signal feedback, ensuring the reliability of circuit conversion while reducing circuit power consumption.

[0057] The embodiment of the present application also provides a dead time adjustment method, which is applied to the above-mentioned dead time adjustment circuit, see Fig.10 The basic flow chart of the dead time adjustment method shown in FIG. 1 includes:

[0058] Step 1001: A first phase detector generates a first pulse control signal according to a node signal and a phase difference between a first drive feedback signal transmitted by a drive circuit;

[0059] Step 1002: The second phase detector generates a second pulse control signal according to the phase difference between the first drive feedback signal and the second drive feedback signal transmitted by the drive circuit;

[0060] Step 1003: the charge pump circuit generates a corresponding voltage signal according to the first pulse control signal and the second pulse control signal;

[0061] Step 1004: The driving circuit generates a driving signal and transmits it to the first power tube and the second power tube, and adjusts the delay time of transmitting the driving signal to the second power tube according to the voltage signal.

[0062] Specifically, Figure 8 As shown, in this embodiment, the first phase detector generates a pulse control signal for controlling the charge pump circuit by detecting the phase difference when the first drive feedback signal LO_FB corresponding to the second power tube turns low and the node signal SW turns high. The second phase detector generates a pulse control signal for the charge pump circuit by detecting the phase difference when the second drive feedback signal HO_FB corresponding to the first power tube turns low and the first drive feedback signal LO_FB turns high. The charge pump circuit converts the pulse control signals output by the two phase detectors into delay control signals through the charge pump principle. The drive circuit adjusts the delay of its own output signal according to the delay control signal to achieve the purpose of adjusting the dead time. Among them, the charge pump circuit converts the two pulse control signals into a DC voltage signal. The DC voltage signal can change the phase difference between the node signal and the first drive feedback signal, and the phase difference between the first drive feedback signal and the second drive feedback signal by adjusting the transmission delay of the drive circuit output to the drive signal of the second power tube. After detection and feedback by the first phase detector and the second phase detector, when the DC voltage signal output by the charge pump circuit is stable, the phase difference between the switch node and the first drive feedback signal, and the phase difference between the first drive feedback signal and the second drive feedback signal are locked, that is, the dead time of the two stages is locked. Therefore, the dead time can be adaptively adjusted and stabilized through phase detection and signal feedback, thereby ensuring the reliability of circuit conversion while reducing circuit power consumption.

[0063] It should be noted that the various embodiments in the present application are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0064] It should also be noted that, in the content of the present application, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" can expressly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "include one..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

[0065] The above description of the disclosed embodiments enables professionals and technicians in the field to implement or use the present application. Various modifications to these embodiments will be apparent to professionals and technicians in the field, and the general principles defined in the present application can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown in the present application, but will conform to the widest range consistent with the principles and novel features disclosed in the present application.

Claims

1. A dead time adjustment circuit, characterized in that: include: A first phase detector, a second phase detector, a charge pump circuit and a driving circuit; The first phase detector is electrically connected to the driving circuit and is used to be electrically connected to the node of the first power tube and the second power tube in the external power-stage switching power supply circuit. The first phase detector is configured to: generate a first pulse control signal according to the node signal and the phase difference of the first driving feedback signal transmitted by the driving circuit; wherein the node signal is a signal at the node of the first power tube and the second power tube; The second phase detector is electrically connected to the driving circuit, and the second phase detector is configured to: generate a second pulse control signal according to a phase difference between the first driving feedback signal and the second driving feedback signal transmitted by the driving circuit; The charge pump circuit is electrically connected to the first phase detector and the second phase detector respectively, and the charge pump circuit is configured to: generate a corresponding voltage signal according to the first pulse control signal and the second pulse control signal; The driving circuit is electrically connected to the charge pump circuit and is used to be electrically connected to the first power tube and the second power tube respectively. The driving circuit is configured to: generate a driving signal to be transmitted to the first power tube and the second power tube, and adjust the delay duration of the driving signal transmitted to the second power tube according to the voltage signal.

2. The dead time adjustment circuit according to claim 1, characterized in that: The first phase detector comprises a first pulse signal generating circuit, a first level conversion circuit, a first buffer, a first NOR gate and a first NAND gate, the first pulse signal generating circuit is electrically connected to the driving circuit, the first NOR gate and the first NAND gate respectively, the first buffer is electrically connected to the first level conversion circuit, the first NOR gate and the first NAND gate respectively, and the first level conversion circuit is also used to be electrically connected to the node; The first pulse signal generating circuit is configured to: generate a first pulse signal and a second pulse signal according to the first drive feedback signal; wherein the high level pulse width of the first pulse signal is equal to the low level pulse width of the second pulse signal, and the rising edge of the first pulse signal, the falling edge of the second pulse signal and the falling edge of the first drive feedback signal occur simultaneously; The first level conversion circuit is configured to: perform level conversion on the node signal in the high voltage domain to obtain a target node signal; The first NOR gate is configured to: generate a first sub-pulse control signal according to a phase difference between a rising edge of the target node signal and a falling edge of the second pulse signal; The first NAND gate is configured to generate a second sub-pulse control signal according to a phase difference between a rising edge of the target node signal and a falling edge of the first pulse signal.

3. The dead time adjustment circuit according to claim 2, characterized in that: The first pulse signal generating circuit includes a first inverter, a second inverter and a first pulse generator; The first inverter is electrically connected to the driving circuit and one end of the first pulse generator respectively, the other end of the first pulse generator is electrically connected to one end of the second inverter and the first NAND gate respectively, and the other end of the second inverter is electrically connected to the first NOR gate.

4. The dead time adjustment circuit according to claim 1, characterized in that: The second phase detector comprises a second pulse signal generating circuit, a second level conversion circuit, a second buffer, a second NOR gate and a second NAND gate, the second buffer is electrically connected to the driving circuit, the second NOR gate and the second NAND gate respectively, the second pulse signal generating circuit is electrically connected to the second level conversion circuit, the second NOR gate and the second NAND gate respectively, and the second level conversion circuit is also electrically connected to the driving circuit; The second level conversion circuit is configured to: perform level conversion on the second drive feedback signal in the high voltage domain to obtain a target drive feedback signal; The second pulse signal generating circuit is configured to: generate a third pulse signal and a fourth pulse signal according to the target drive feedback signal; wherein the high level pulse width of the third pulse signal is equal to the low level pulse width of the fourth pulse signal, and the rising edge of the third pulse signal, the falling edge of the fourth pulse signal, and the falling edge of the target drive feedback signal occur simultaneously; The second NOR gate is configured to: generate a third sub-pulse control signal according to a phase difference between a rising edge of the first driving feedback signal and a falling edge of the fourth pulse signal; The second NAND gate is configured to generate a fourth sub-pulse control signal according to a phase difference between a rising edge of the first drive feedback signal and a falling edge of the third pulse signal.

5. The dead time adjustment circuit according to claim 4, characterized in that: The second pulse signal generating circuit includes a third inverter and a second pulse generator; One end of the second pulse generator is electrically connected to the second level conversion circuit, the other end of the second pulse generator is electrically connected to the second NAND gate and one end of the third inverter respectively, and the other end of the third inverter is electrically connected to the second NOR gate.

6. The dead time adjustment circuit according to claim 1, characterized in that: The charge pump circuit includes a first current mirror, a second current mirror, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a first capacitor and a second capacitor; The sources of the first MOS tube and the third MOS tube are both electrically connected to the first current mirror, the sources of the second MOS tube and the fourth MOS tube are both electrically connected to the second current mirror, the gates of the first MOS tube and the second MOS tube are both electrically connected to the first phase detector, the gates of the third MOS tube and the fourth MOS tube are both electrically connected to the second phase detector, the drain of the first MOS tube is respectively electrically connected to the drain of the second MOS tube and the charge pump circuit, the drain of the third MOS tube is respectively electrically connected to the drain of the fourth MOS tube and the charge pump circuit, the first capacitor is respectively electrically connected to the drain of the first MOS tube and the first current mirror, and the second capacitor is respectively electrically connected to the drain of the third MOS tube and the second current mirror.

7. The dead time adjustment circuit according to claim 6, characterized in that: The first current mirror includes a fifth MOS tube, a sixth MOS tube and a seventh MOS tube; The sources of the fifth MOS tube, the sixth MOS tube and the seventh MOS tube are all electrically connected to the power supply, the gate of the fifth MOS tube is electrically connected to the gate of the sixth MOS tube, the drain of the fifth MOS tube, the gate of the seventh MOS tube and the second current mirror respectively, the drain of the sixth MOS tube is electrically connected to the source of the first MOS tube, and the drain of the seventh MOS tube is electrically connected to the source of the third MOS tube.

8. The dead time adjustment circuit according to claim 6, characterized in that: The second current mirror includes an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube and a constant current source; The gates of the eighth MOS tube, the ninth MOS tube, the tenth MOS tube and the eleventh MOS tube are all electrically connected to one end of the constant current source, the other end of the constant current source is electrically connected to the power supply, the drain of the eighth MOS tube is electrically connected to one end of the constant current source, the drain of the ninth MOS tube is electrically connected to the first current mirror, the drain of the tenth MOS tube is electrically connected to the source of the second MOS tube, the drain of the eleventh MOS tube is electrically connected to the source of the fourth MOS tube, the sources of the eighth MOS tube, the ninth MOS tube, the tenth MOS tube and the eleventh MOS tube are all grounded, the source of the tenth MOS tube is also electrically connected to the first capacitor, and the source of the eleventh MOS tube is also electrically connected to the second capacitor.

9. The dead time adjustment circuit according to claim 1, characterized in that: The driving circuit includes a first power tube driving unit and a second power tube driving unit, the first power tube driving unit is electrically connected to the second phase detector, and the first power tube driving unit is respectively used to be electrically connected to the first power tube and an external control signal generating circuit, the second power tube driving unit is respectively electrically connected to the first phase detector, the second phase detector, and the charge pump circuit, and the second power tube driving unit is respectively used to be electrically connected to the second power tube and the control signal generating circuit; The first power tube driving unit is configured to: generate a corresponding first driving signal to the first power tube according to the control signal transmitted by the control signal generating circuit; The second power tube driving unit is configured to: generate a corresponding second driving signal according to the control signal transmitted by the control signal generating circuit, and adjust the delay time of the second driving signal transmitted to the second power tube according to the voltage signal transmitted by the charge pump circuit.

10. The dead time adjustment circuit according to claim 9, characterized in that: The second power tube driving unit includes a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, a first resistor, a second resistor, a third capacitor, a fourth inverter, a first bias generator, a second bias generator and a third buffer; The twelfth MOS transistor is electrically connected to the first resistor and is used to be electrically connected to the control signal generating circuit. The thirteenth MOS transistor is electrically connected to the second resistor and is used to be electrically connected to the control signal generating circuit. The fourteenth MOS transistor is electrically connected to the first bias generator and the fifteenth MOS transistor respectively. The seventeenth MOS transistor is electrically connected to the second bias generator and the sixteenth MOS transistor respectively. The third capacitor is electrically connected to the first resistor, the second resistor, the fifteenth MOS transistor, the sixteenth MOS transistor, and the fourth inverter respectively. The first bias generator and the second bias generator are also electrically connected to the charge pump circuit. The fourth inverter is also electrically connected to the first phase detector and the second phase detector respectively, and the fourth inverter is also electrically connected to the second power tube through the third buffer.

11. The dead time adjustment circuit according to claim 9, characterized in that: The first power tube driving unit includes an eighteenth MOS tube, a nineteenth MOS tube, a third resistor, a fourth capacitor, a third level conversion circuit and a fourth buffer; The source of the eighteenth MOS tube is electrically connected to the power supply, the gates of the eighteenth MOS tube and the nineteenth MOS tube are both used to be electrically connected to the control signal generating circuit, the drain of the eighteenth MOS tube is electrically connected to one end of the third resistor, the other end of the third resistor is respectively electrically connected to the drain of the nineteenth MOS tube, one end of the fourth capacitor, and one end of the third level conversion circuit, the source of the nineteenth MOS tube and the other end of the fourth capacitor are both grounded, the other end of the third level conversion circuit is respectively electrically connected to the second phase detector and one end of the fourth buffer, and the other end of the fourth buffer is used to be electrically connected to the first power tube.

12. A dead time adjustment method, characterized in that: A dead time adjustment circuit as claimed in any one of claims 1 to 11, comprising: The first phase detector generates a first pulse control signal according to the node signal and the phase difference of the first driving feedback signal transmitted by the driving circuit; wherein the node signal is a signal at the node between the first power tube and the second power tube; A second phase detector generates a second pulse control signal according to a phase difference between the first drive feedback signal and the second drive feedback signal transmitted by the drive circuit; The charge pump circuit generates a corresponding voltage signal according to the first pulse control signal and the second pulse control signal; The driving circuit generates a driving signal to be transmitted to the first power tube and the second power tube, and adjusts the delay time of the driving signal being transmitted to the second power tube according to the voltage signal.

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