Timing circuit

Abstract

The embodiment of the invention provides a timing circuit, which comprises a current generation module, a current output module and a timing module, and is characterized in that the current generation module is configured to generate a first current linearly changing along with frequency through charging and discharging of a switched capacitor; the current output module is configured to output the first current according to the first current mirror to obtain second current, and the second current is equal to the first current; and the timing module is configured to charge the first capacitor according to the second current to generate a slope voltage, and compare the slope voltage with the first voltage to obtain a timing signal which linearly changes along with the frequency. The problem that a timing circuit in an existing BUCKBOOST system is difficult to adapt to a wide-range working frequency is solved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular, to timing circuits. Background Art

[0002] In the system of the buck-boost converter in the average current mode (BUCK_BOOST system), there are a turn-on timing circuit and a turn-off timing circuit. Among them, the turn-on time obtained by the turn-on timing circuit is proportional to the output voltage and inversely proportional to the input voltage; the turn-off time obtained by the turn-off timing circuit is proportional to the input voltage and inversely proportional to the output voltage. Taking the turn-on timing circuit as an example, the turn-on timing circuit compares the ramp voltage Vramp generated by the input voltage with the output voltage superimposed with the compensation voltage Vcomp to determine the turn-on time of the upper power tube in the BUCK (step-down) stage. In practical applications, if the operating frequency of the system changes in a wide range, the ramp voltage Vramp generated by the turn-on timing circuit rises at a fixed slope. In order to obtain different turn-on times of the upper power tube at different frequencies, Vcomp also needs to change in a wide range. Since Vcomp is the output voltage of the operational amplifier, it is difficult to ensure that the operational amplifier is in the high gain amplification area within the entire Vcomp variation range, and the power supply voltage requirements for the operational amplifier are also high, which is not suitable for the design of low power supply voltage operational amplifiers. Similarly, the off-time timing circuit compares the ramp voltage Vramp generated by the output voltage with the input voltage superimposed with the compensation voltage Vcomp to determine the off-time of the power tube in the boost phase. Therefore, the off-time timing circuit also has the aforementioned problem in a wide range of system operating frequencies.

[0003] In summary, it can be seen that the timing circuit in the existing BUCK_BOOST system has the problem of being difficult to adapt to a wide range of operating frequencies. Summary of the invention

[0004] The embodiments described herein provide a timing circuit to solve the problem that the timing circuit in the existing BUCK_BOOST system is difficult to adapt to a wide range of operating frequencies.

[0005] According to a first aspect of the present disclosure, a timing circuit is provided, comprising: a current generating module, a current output module, and a timing module, wherein the current generating module is configured to generate a first current that varies linearly with frequency by charging and discharging a switching capacitor, and the frequency is the switching frequency of the switching capacitor; the current output module is configured to output the first current according to a first current mirror to obtain a second current, and the second current is equal to the first current; the timing module is configured to charge the first capacitor according to the second current to generate a ramp voltage, and compare the ramp voltage with the first voltage to obtain a timing signal that varies linearly with frequency.

[0006] Optionally, the current generating module includes: a first operational amplifier, a first transistor, a second capacitor, and the switching capacitor, wherein the negative input terminal of the first operational amplifier is coupled to the second voltage, the positive input terminal of the first operational amplifier is respectively coupled to the first electrode of the first transistor, one end of the second capacitor, and the switching capacitor, and the output terminal of the first operational amplifier is coupled to the control electrode of the first transistor; the second electrode of the first transistor is coupled to the current output module, and the current flowing through the first transistor is the first current; the other end of the second capacitor is coupled to the ground terminal; the switching capacitor is connected in parallel with the second capacitor, and the switching capacitor is configured to control the charging and discharging of the third capacitor through the first switch and the second switch.

[0007] Optionally, the current generating module includes: a first operational amplifier, a first transistor, a second capacitor, the switching capacitor, a first conversion unit, a filtering unit, and a second conversion unit, wherein the negative input terminal of the first operational amplifier is coupled to the second voltage, the positive input terminal of the first operational amplifier is respectively coupled to the first pole of the first transistor, one end of the second capacitor, and the switching capacitor, and the output terminal of the first operational amplifier is coupled to the control pole of the first transistor; the second pole of the first transistor is coupled to the first conversion unit; the other end of the second capacitor is coupled to the ground terminal; the switching capacitor is connected in parallel with the second capacitor, and the switching capacitor is configured to control the charging and discharging of the third capacitor through the first switch and the second switch; the first conversion unit is configured to convert the current of the second pole of the first transistor into a third voltage through a second current mirror; the filtering unit is configured to filter the third voltage; the second conversion unit is configured to convert the filtered third voltage through the second operational amplifier to obtain the first current.

[0008] Optionally, when the second voltage is the input voltage of the voltage conversion system and the first voltage is the sum of the output voltage of the voltage conversion system and the change in the compensation voltage, the timing circuit is a turn-on timing circuit, and the timing signal indicates the turn-on time of the upper power tube of the voltage conversion system; when the second voltage is the output voltage of the voltage conversion system and the first voltage is the sum of the input voltage of the voltage conversion system and the change in the compensation voltage, the timing circuit is a turn-off timing circuit, and the timing signal indicates the turn-off time of the upper power tube.

[0009] Optionally, the switching capacitor includes: the third capacitor, the first switch, and the second switch, wherein one end of the third capacitor is coupled to one end of the first switch and one end of the second switch, respectively, and the other end of the third capacitor is coupled to the ground, and the capacitance of the first capacitor and the third capacitor are equal; the other end of the first switch is coupled to the first electrode of the first transistor, and the other end of the second switch is coupled to the ground; the first control signal of the first switch and the second control signal of the second switch are generated by the same clock signal, and the first control signal and the second control signal are opposite signals to each other, and the clock frequency of the clock signal is the switching frequency of the switching capacitor.

[0010] Optionally, the current output module includes the first current mirror composed of a second transistor and a third transistor, wherein the control electrode of the second transistor is respectively coupled to the first electrode of the second transistor, the current generating module, and the control electrode of the third transistor, the second electrode of the second transistor and the second electrode of the third transistor are both coupled to the power supply voltage, the first electrode of the third transistor is coupled to the timing module, and outputs the second current; the timing module includes: a comparator and the first capacitor, wherein the positive input terminal of the comparator is respectively coupled to the second current output by the current output module and one end of the first capacitor, the negative input terminal of the comparator is coupled to the first voltage, the output terminal of the comparator outputs the timing signal, and the other end of the first capacitor is coupled to the ground terminal.

[0011] Optionally, the first conversion unit includes: the second current mirror composed of a fourth transistor and a fifth transistor, and a first resistor, wherein the control electrode of the fourth transistor is respectively coupled to the first electrode of the fourth transistor, the second electrode of the first transistor, and the control electrode of the fifth transistor, and the second electrode of the fourth transistor and the second electrode of the fifth transistor are both coupled to the power supply voltage; the first electrode of the fifth transistor is respectively coupled to one end of the first resistor and the filtering unit, and the voltage of one end of the first resistor is the third voltage; the other end of the first resistor is coupled to the ground end.

[0012] Optionally, the filtering unit includes: a second resistor and a fourth capacitor, wherein one end of the second resistor is coupled to the first conversion unit, and the other end of the second resistor is respectively coupled to one end of the fourth capacitor and the second conversion unit; the other end of the fourth capacitor is coupled to the ground end.

[0013] Optionally, the second conversion unit includes: the second operational amplifier, a sixth transistor, and a third resistor, wherein the positive input terminal of the second operational amplifier is coupled to the filtering unit, the negative input terminal of the second operational amplifier is respectively coupled to the second electrode of the sixth transistor and one end of the third resistor, and the output terminal of the second operational amplifier is coupled to the control electrode of the sixth transistor; the first electrode of the sixth transistor is coupled to the current output module and outputs the first current; and the other end of the third resistor is coupled to the ground terminal.

[0014] Optionally, the resistance values ​​of the first resistor and the third resistor are equal.

[0015] In the timing circuit of the embodiment of the present disclosure, a first current that varies linearly with frequency is generated by charging and discharging the switch capacitor, and the current signal is output through the first current mirror to obtain a second current signal, and then the first capacitor is charged according to the second current to generate a ramp voltage, and the ramp voltage is compared with the first voltage to obtain a timing signal that varies with frequency. When the timing circuit is applied to the BUCK_BOOST system, as a turn-on timing circuit or a turn-off timing circuit, the turn-on time and the turn-off time vary linearly with frequency, which can make the change in the compensation voltage zero, and even in a wider frequency range, the compensation voltage can be basically unchanged, so there is no need for high-demand design of the operational amplifier, making the circuit design of the entire system loop simpler. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure, wherein:

[0017] Figure 1 A schematic block diagram of a timing circuit according to an embodiment of the present disclosure is shown;

[0018] Figure 2 An exemplary circuit diagram of a timing circuit according to an embodiment of the present disclosure is shown;

[0019] Figure 3 A schematic diagram of waveforms of charging and discharging of a switch capacitor in a timing circuit according to an embodiment of the present disclosure is shown;

[0020] Figure 4 A schematic block diagram corresponding to a timing circuit according to an embodiment of the present disclosure used in a voltage conversion system is shown;

[0021] Figure 5 A schematic structural diagram of another timing circuit according to an embodiment of the present disclosure is shown;

[0022] Figure 6An exemplary circuit diagram of a first conversion unit, a filtering unit, and a second conversion unit according to an embodiment of the present disclosure is shown;

[0023] The elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0026] In all embodiments of the present disclosure, since the source and drain of a metal oxide semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle terminal (gate or gate terminal) of the MOS transistor is referred to as a control terminal, and the remaining two terminals of the MOS transistor are referred to as a first terminal and a second terminal, respectively. In addition, terms such as "first" and "second" are only used to distinguish one component (or a portion of a component) from another component (or another portion of a component).

[0027] In order to solve the problem that the timing circuit in the existing BUCK_BOOST system is difficult to adapt to a wide range of operating frequencies, a timing circuit that changes linearly with frequency is proposed, and the on-time or off-time changes linearly with the frequency, so that the change in the compensation voltage is zero, and even in a wider operating frequency range, the compensation voltage can be basically unchanged, and there is no need to change with the frequency in a large range, so there is no need to put forward high requirements for the design of the operational amplifier to meet the wide range of operating frequency changes. The timing circuit disclosed in the present invention is described in detail below.

[0028] Figure 1FIG. 1 is a schematic block diagram of a timing circuit 100 according to an embodiment of the present disclosure. Figure 1 As shown, the timing circuit 100 includes: a current generating module 110, a current output module 120, and a timing module 130.

[0029] Among them, the current generating module 110 is configured to generate a first current I1 that varies linearly with frequency through the charge and discharge of the switch capacitor, wherein the frequency is the switching frequency of the switch capacitor. Based on the principle of charge and discharge of the switch capacitor 111 (not shown in the figure), a periodic current signal can be obtained. After eliminating the ripple of the periodic current signal, the first current I1 that varies linearly with frequency can be obtained. The first current I1 that varies linearly with frequency is obtained in order to subsequently obtain a timing signal timer that varies linearly with frequency. Specifically, the voltage signal (corresponding to Figure 1 V2 in the figure is converted into a current signal, and then the obtained current signal is used to charge the switch capacitor 111 to obtain a current signal that changes periodically. At the same time or in steps, the current signal can be filtered to obtain a first current I1 that changes linearly with the frequency.

[0030] The current output module 120 is configured to output the first current I1 according to the first current mirror to obtain the second current I2, and the second current I2 is equal to the first current I1. The current output module 120 is to output the first current I1 obtained by the current generating module 110, which changes linearly with the frequency, in proportion to each other through the current mirror, for use by the subsequent circuit. The mirror ratio of the first current mirror is 1.

[0031] The timing module 130 is configured to charge the first capacitor C1 (not shown in the figure) according to the second current I2 to generate a ramp voltage Vramp (not shown in the figure), and compare the ramp voltage Vramp with the first voltage V1 to obtain a timing signal timer that changes linearly with the frequency. The principle of the timing module 130 is basically consistent with the existing timing principle. By inputting the ramp voltage Vramp and the first voltage V1 into the comparator comp, the timing signal timer is obtained according to the condition of the comparator comp flipping. The ramp voltage Vramp is the voltage on the first capacitor C1 obtained by charging the first capacitor C1 with the second current I2. When the ramp voltage Vramp is charged to be equal to the first voltage V1, the comparator comp flips. Because the second current I2 changes linearly with the frequency, the obtained timing signal timer can be made to change linearly with the frequency.

[0032] Further, such as Figure 2As shown, the current generating module 110 includes: a first operational amplifier OP1, a first transistor M1, a second capacitor C2, and a switch capacitor 111, wherein the negative input terminal of the first operational amplifier OP1 is coupled to the second voltage V2, the positive input terminal of the first operational amplifier OP1 is respectively coupled to the first electrode of the first transistor M1, one end of the second capacitor C2, and the switch capacitor 111, and the output terminal of the first operational amplifier OP1 is coupled to the control electrode of the first transistor M1; the second electrode of the first transistor M1 is coupled to the current output module 120, and the current flowing through the first transistor M1 is the first current I1; the other end of the second capacitor C2 is coupled to the ground terminal; the switch capacitor 111 is connected in parallel with the second capacitor C2, and the switch capacitor 111 is configured to control the charging and discharging of the third capacitor C3 through the first switch S1 and the second switch S2.

[0033] Further, such as Figure 2 As shown, the switch capacitor 111 includes: a third capacitor C3, a first switch S1, and a second switch S2, wherein one end of the third capacitor C3 is coupled to one end of the first switch S1 and one end of the second switch S2 respectively, and the other end of the third capacitor C3 is coupled to the ground end, and the capacitance of the first capacitor C1 and the third capacitor C3 is equal; the other end of the first switch S1 is coupled to the first electrode of the first transistor M1, and the other end of the second switch S2 is coupled to the ground end; the first control signal Ks1 of the first switch S1 and the second control signal Ks2 of the second switch S2 are generated by the same clock signal Clk, and the first control signal Ks1 and the second control signal Ks2 are opposite signals to each other, and the clock frequency of the clock signal Clk is the switching frequency of the switch capacitor 111.

[0034] Further, such as Figure 2 As shown, the first control signal Ks1 and the second control signal Ks2 can be generated by the control signal generating unit 112. Specifically, the control signal generating unit 112 at least includes a first inverter N1 and a second inverter N2. The input end of the first inverter N1 is coupled to the clock signal Clk, the output end of the first inverter N1 is coupled to the input end of the second inverter N2, the signal at the output end of the first inverter N1 is used as the second control signal Ks2, and the signal at the output end of the second inverter N2 is used as the first control signal Ks1.

[0035] Further, such as Figure 2 As shown, the current output module 120 includes a first current mirror composed of a second transistor M2 and a third transistor M3, wherein the control electrode of the second transistor M2 is respectively coupled to the first electrode of the second transistor M2, the current generating module 110, and the control electrode of the third transistor M3, the second electrode of the second transistor M2 and the second electrode of the third transistor M3 are both coupled to the power supply voltage VCC, the first electrode of the third transistor M3 is coupled to the timing module 130, and outputs the second current I2; wherein the second transistor M2 and the third transistor M3 are both P-type MOS tubes.

[0036] Further, such as Figure 2 As shown, the timing module 130 includes: a comparator comp, a first capacitor C1, wherein the positive input terminal of the comparator comp is respectively coupled to the second current I2 output by the current output module 120 and one end of the first capacitor C1, the negative input terminal of the comparator comp is coupled to the first voltage V1, and the output terminal of the comparator comp outputs a timing signal timer; the other end of the first capacitor C1 is coupled to the ground.

[0037] Combine the following Figure 2 The circuit principle of the timing circuit in the embodiment of the present disclosure is explained as follows: when Clk is at a high level, Ks1 is at a high level, S1 is turned on, S2 is turned off, and I1 charges C3. When Clk is at a low level, Ks2 is at a high level, S2 is turned on, S1 is turned off, and the charge on C3 is reduced to 0. C2 is a voltage-stabilizing capacitor, which can prevent the voltage of V4 (V4 is the voltage of the node between the first transistor M1 and the switching capacitor 111) from changing significantly, ensuring that OP1 always works in the small signal amplification area. The average voltage of V4 is V2. Assuming that the switching frequency of Clk is f, the amount of charge provided to C3 in one cycle is: Q = C3 × V2, and the average current of I1 can be expressed as: I1 = V2 × C3 × f. Figure 3 As shown, a waveform diagram of C3 charging and discharging is shown, where Vc3 is the voltage at one end of C3. It can be seen that C3 is periodically charged and discharged. Since C3 is periodically charged and discharged, I1 is also a periodic signal. In order to make the ripple of I1 as small as possible, the bandwidth of OP1 is as small as possible as the clock frequency of Clk. OP1 is equivalent to a low-pass filter to play a filtering role. When the bandwidth of OP1 is small enough, the ripple of I1 can be reduced to I1 is approximately a DC quantity. At this time, I1 can be considered as a signal that changes linearly with frequency. After obtaining I1, I2 is obtained by mirroring I1 through the first current mirror (M2, M3), I2 = I1 = V2 × C3 × f, I2 charges C1, and according to the capacitor charging principle and the flip condition of the comparator comp, the expression of the timing signal timer can be finally obtained as follows:

[0038]

[0039] It can be seen that timer is a signal that changes linearly with frequency f.

[0040] If V2 = Vin, V1 = Vout + dVcomp, where Vin is the input voltage in the voltage conversion system, Vout is the output voltage in the voltage conversion system, and dVcomp is the change in the compensation voltage in the voltage conversion system,

[0041] And C1=C3, then the above expression (1) becomes:

[0042]

[0043] From expression (2), we can see that if the system loop is adjusted to make the upper tube conduction time:

[0044]

[0045] Then dVcomp can be made zero, and Vcomp remains basically unchanged, so that there is no need for a high-demand design of the operational amplifier, and it can adapt to a wider range of operating frequencies.

[0046] It should be noted that the above formulas (2) and (3) are suitable for on-time timing. If it is off-time timing, it is necessary to make V2 = Vout, V1 = Vin + dVcomp,

[0047] Then the above expression (1) becomes:

[0048]

[0049] From expression (4), we can see that if the system loop is adjusted to make the upper tube off time:

[0050]

[0051] Then dVcomp can be made zero, and the above equations (4) and (5) are suitable for turn-off timing.

[0052] According to the above inferences, it can be concluded that when the timing circuit 100 in the embodiment of the present disclosure is used as a voltage conversion system (such as a Buck system, a Boost system, or a BUCK_BOOST system) to turn on and off the timing circuit, dVcomp can be made zero, and Vcomp remains basically unchanged. This does not require a high-demand design of the operational amplifier, and can adapt to a larger range of operating frequencies. Figure 4 The schematic diagram shows the corresponding structure when the timing circuit 100 is applied to a voltage conversion system as a turn-on timing circuit and a turn-off timing circuit.

[0053] Furthermore, the embodiment of the present disclosure provides another implementation of the current generating module, such as Figure 5 As shown, the current generating module includes: a first operational amplifier OP1, a first transistor M1, a second capacitor C2, the switch capacitor 111, a first conversion unit 113, a filtering unit 114, and a second conversion unit 115.

[0054] Among them, the negative input terminal of the first operational amplifier OP1 is coupled to the second voltage V2, the positive input terminal of the first operational amplifier OP1 is respectively coupled to the first electrode of the first transistor M1, one end of the second capacitor C2, and the switch capacitor 111, the output terminal of the first operational amplifier OP1 is coupled to the control electrode of the first transistor M1; the second electrode of the first transistor M1 is coupled to the first conversion unit 113; the other end of the second capacitor C2 is coupled to the ground terminal; the switch capacitor 111 is connected in parallel with the second capacitor C2, and the switch capacitor 111 is configured to control the charging and discharging of the third capacitor C3 through the first switch S1 and the second switch S2. The specific circuit structure of the switch capacitor 111 and the generation and control of the first control signal Ks1 and the second control signal Ks2 for controlling the switches (S1, S2) in the switch capacitor 111 Figure 2 The contents are the same, so I won’t repeat them here.

[0055] The first conversion unit 113 is configured to convert the current of the second electrode of the first transistor M1 into a third voltage V3 through a second current mirror. Figure 6 As shown, an exemplary circuit diagram of a first conversion unit 113 is provided. Figure 6 The first conversion unit 113 includes: a second current mirror composed of a fourth transistor M4 and a fifth transistor M5, and a first resistor R1, wherein the control electrode of the fourth transistor M4 is respectively coupled to the first electrode of the fourth transistor M4, the second electrode of the first transistor M1, and the control electrode of the fifth transistor M5, and the second electrode of the fourth transistor M4 and the second electrode of the fifth transistor M5 are both coupled to the power supply voltage VCC; the first electrode of the fifth transistor M5 is respectively coupled to one end of the first resistor R1 and the filtering unit 114, and the voltage at one end of the first resistor R1 is the third voltage V3; the other end of the first resistor R1 is coupled to the ground end.

[0056] The filtering unit 114 is configured to filter the third voltage V3; further, as Figure 6 As shown, an exemplary circuit diagram of a filtering unit 114 is provided. Figure 6 In the figure, the filtering unit 114 includes: a second resistor R2 and a fourth capacitor C4, wherein one end of the second resistor R2 is coupled to the first conversion unit 113, and the other end of the second resistor R2 is respectively coupled to one end of the fourth capacitor C4 and the second conversion unit 115; the other end of the fourth capacitor C4 is coupled to the ground. Figure 6 The filtering unit 114 in the embodiment is a circuit structure of RC filtering, and can certainly be other filtering structures as long as the filtering of the third voltage V3 can be achieved.

[0057] The second conversion unit 115 is configured to convert the filtered third voltage V3 through the second operational amplifier OP2 to obtain the first current I1. Figure 6As shown, an exemplary circuit diagram of a second conversion unit 115 is provided. Figure 6 In the embodiment, the second conversion unit 115 includes: a second operational amplifier OP2, a sixth transistor M6, and a third resistor R3, wherein the positive input terminal of the second operational amplifier OP2 is coupled to the filtering unit 114, the negative input terminal of the second operational amplifier OP2 is respectively coupled to the second electrode of the sixth transistor M6 and one end of the third resistor R3, and the output terminal of the second operational amplifier OP2 is coupled to the control electrode of the sixth transistor M6; the first electrode of the sixth transistor M6 is coupled to the current output module 120, and outputs the first current I1; the other end of the third resistor R3 is coupled to the ground terminal.

[0058] Figure 5-6 The corresponding timing circuit 100 and Figure 2 The difference lies in the different structure of the current generating module 110. Figure 2 In this case, the periodic current signal is obtained and filtered at the same time, so that I1 that varies linearly with the frequency can be directly obtained. OP1 is used as a filter. In theory, it can make the current output by the second pole of M1 a DC signal that varies linearly with the frequency. However, it requires the bandwidth of OP1 to be small enough, which is difficult to achieve in practical applications. Figure 5-6 In the example, OP1 is used as a filter, and the subsequent filter unit 114 is used for filtering. This is a multi-layer step-by-step filtering structure. Figure 2 , Figure 5-6 The bandwidth requirement of OP1 will be reduced, and it can better ensure that the final I1 is a DC signal that changes linearly with the frequency, thereby improving the overall accuracy of the circuit.

[0059] Combine the following Figure 5 and Figure 6The principle of the timing circuit 100 in the embodiment of the present disclosure is explained in more detail: when Clk is at a high level, Ks1 is at a high level, S1 is turned on, and the current generated on M1 charges C3; when Clk is at a low level, Ks2 is at a high level, S2 is turned on, and the charge on C3 is reduced to 0. C2 is a voltage-stabilizing capacitor, which can prevent the voltage of V4 from changing significantly, ensuring that OP1 always works in the small signal amplification area. The average voltage of V4 is V2. Assuming that the switching frequency of Clk is f, the amount of charge provided to C3 in one cycle is: Q=C3×V2, and the average value of the current generated on M1 can be expressed as: V2×C3×f. The current generated on M1 is a periodic signal. OP1, as a low-pass filter, will perform preliminary filtering on the current generated on M1. Then, the second current mirror M4 and M5 will mirror the current generated on M1 to R1 and convert it into a voltage signal V3. The ripple on V3 will be further reduced by filtering with R2 and C4. Finally, OP2 will convert the filtered V3 into the first current I1 that changes linearly with the frequency. At this time, I1 is already a DC signal. Then, the first current mirror (M2, M3) will mirror I1 to obtain I2. The mirror ratio of the second current mirror is 1, and R1=R3. Then, I2=I1=V2×C3×f can be obtained. I2 charges C1. According to the capacitor charging principle and the flipping condition of the comparator comp, the expression of the timing signal timer can be obtained as follows:

[0060]

[0061] As in the previous embodiment, when V2 = Vin, V1 = Vout + dVcomp,

[0062]

[0063] Through the system loop regulation, the upper tube conduction time is:

[0064] Then dVcomp can be made zero;

[0065] When V2=Vout,V1=Vin+dVcomp,

[0066]

[0067] Through the system loop regulation, the upper tube off time is:

[0068] Then dVcomp can be made zero.

[0069] In summary, the timing circuit in the embodiment of the present disclosure is a timing circuit that changes linearly with the frequency, and the timing signal can change linearly with the frequency. As an on-timing circuit or an off-timing circuit, it can keep the compensation voltage Vcomp in the voltage conversion system basically unchanged, and can adapt well to a wider range of operating frequencies.

[0070] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive, unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is placed after a group of terms, "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0071] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present disclosure can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

[0072] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A timing circuit, characterized in that: The timing circuit includes: a current generating module, a current output module, and a timing module. Wherein, the current generating module is configured to generate a first current that varies linearly with frequency through charging and discharging of the switch capacitor, and the frequency is the switching frequency of the switch capacitor; The current output module is configured to output the first current according to a first current mirror to obtain a second current, wherein the second current is equal to the first current; The timing module is configured to charge the first capacitor according to the second current to generate a ramp voltage, and compare the ramp voltage with the first voltage to obtain a timing signal that changes linearly with the frequency.

2. The timing circuit according to claim 1, characterized in that: The current generating module includes: a first operational amplifier, a first transistor, a second capacitor, and the switch capacitor. Wherein, the negative input terminal of the first operational amplifier is coupled to the second voltage, the positive input terminal of the first operational amplifier is respectively coupled to the first electrode of the first transistor, one end of the second capacitor, and the switch capacitor, and the output terminal of the first operational amplifier is coupled to the control electrode of the first transistor; The second electrode of the first transistor is coupled to the current output module, and the current flowing through the first transistor is the first current; The other end of the second capacitor is coupled to the ground; The switch capacitor is connected in parallel with the second capacitor, and the switch capacitor is configured to control the charging and discharging of the third capacitor through the first switch and the second switch.

3. The timing circuit according to claim 1, characterized in that: The current generating module includes: a first operational amplifier, a first transistor, a second capacitor, the switch capacitor, a first conversion unit, a filtering unit, and a second conversion unit. Wherein, the negative input terminal of the first operational amplifier is coupled to the second voltage, the positive input terminal of the first operational amplifier is respectively coupled to the first electrode of the first transistor, one end of the second capacitor, and the switch capacitor, the output terminal of the first operational amplifier is coupled to the control electrode of the first transistor; the second electrode of the first transistor is coupled to the first conversion unit; the other end of the second capacitor is coupled to the ground terminal; the switch capacitor is connected in parallel with the second capacitor, and the switch capacitor is configured to control the charging and discharging of the third capacitor through the first switch and the second switch; The first conversion unit is configured to convert the current of the second electrode of the first transistor into a third voltage through a second current mirror; The filtering unit is configured to filter the third voltage; The second conversion unit is configured to convert the filtered third voltage through a second operational amplifier to obtain the first current.

4. The timing circuit according to claim 2 or 3, characterized in that: When the second voltage is the input voltage of the voltage conversion system, and the first voltage is the sum of the output voltage of the voltage conversion system and the variation of the compensation voltage, the timing circuit is a conduction timing circuit, and the timing signal indicates the conduction time of the upper power tube of the voltage conversion system; When the second voltage is the output voltage of the voltage conversion system and the first voltage is the sum of the input voltage of the voltage conversion system and the change in the compensation voltage, the timing circuit is a shutdown timing circuit and the timing signal indicates the shutdown time of the upper power tube.

5. The timing circuit according to claim 4, characterized in that: The switch capacitor includes: the third capacitor, the first switch, and the second switch. One end of the third capacitor is respectively coupled to one end of the first switch and one end of the second switch, the other end of the third capacitor is coupled to the ground, and the capacitance of the first capacitor and the third capacitor are equal; The other end of the first switch is coupled to the first electrode of the first transistor, and the other end of the second switch is coupled to the ground end; The first control signal of the first switch and the second control signal of the second switch are generated by the same clock signal, and the first control signal and the second control signal are opposite signals to each other. The clock frequency of the clock signal is the switching frequency of the switch capacitor.

6. The timing circuit according to claim 5, characterized in that: The current output module includes the first current mirror composed of a second transistor and a third transistor, Wherein, the control electrode of the second transistor is respectively coupled to the first electrode of the second transistor, the current generating module, and the control electrode of the third transistor, the second electrode of the second transistor and the second electrode of the third transistor are both coupled to the power supply voltage, and the first electrode of the third transistor is coupled to the timing module and outputs the second current; The timing module includes: a comparator and the first capacitor, wherein the positive input terminal of the comparator is respectively coupled to the second current output by the current output module and one end of the first capacitor, the negative input terminal of the comparator is coupled to the first voltage, the output terminal of the comparator outputs the timing signal, and the other end of the first capacitor is coupled to the ground.

7. The timing circuit according to claim 3, characterized in that: The first conversion unit includes: the second current mirror composed of a fourth transistor and a fifth transistor, a first resistor, The control electrode of the fourth transistor is respectively coupled to the first electrode of the fourth transistor, the second electrode of the first transistor, and the control electrode of the fifth transistor, and the second electrode of the fourth transistor and the second electrode of the fifth transistor are both coupled to a power supply voltage; A first electrode of the fifth transistor is respectively coupled to one end of the first resistor and the filter unit, and a voltage at one end of the first resistor is the third voltage; The other end of the first resistor is coupled to the ground.

8. The timing circuit according to claim 7, characterized in that: The filtering unit includes: a second resistor and a fourth capacitor. Wherein, one end of the second resistor is coupled to the first conversion unit, and the other end of the second resistor is respectively coupled to one end of the fourth capacitor and the second conversion unit; The other end of the fourth capacitor is coupled to the ground.

9. The timing circuit according to claim 8, characterized in that: The second conversion unit includes: the second operational amplifier, a sixth transistor, and a third resistor. Wherein, the positive input terminal of the second operational amplifier is coupled to the filter unit, the negative input terminal of the second operational amplifier is respectively coupled to the second electrode of the sixth transistor and one end of the third resistor, and the output terminal of the second operational amplifier is coupled to the control electrode of the sixth transistor; The first electrode of the sixth transistor is coupled to the current output module and outputs the first current; The other end of the third resistor is coupled to the ground.

10. The timing circuit according to claim 9, characterized in that: The resistance values ​​of the first resistor and the third resistor are equal.

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