High-precision high-frequency adjustable frequency oscillation circuit of integrated circuit chip

Abstract

The invention relates to a high-precision high-frequency adjustable frequency oscillating circuit of an integrated circuit chip. The system comprises a constant reference output module used for providing a reference signal irrelevant to temperature and power supply fluctuation; the voltage-stabilizing internal power supply module is used for converting an external power supply into a voltage-stabilizing power supply by utilizing the reference signal; the high-frequency oscillation generation module is used for receiving the voltage-stabilized power supply and generating a high-frequency oscillation signal; the frequency regulation and control module is coupled with the high-frequency oscillation generation module and is used for regulating the high-frequency oscillation signal; and the logic control module is respectively connected with the constant reference output module, the voltage stabilization internal power supply module, the high-frequency oscillation generation module and the frequency regulation and control module, and is used for receiving an external control signal and outputting instructions including starting, dormancy and frequency output so as to realize high-precision adjustable output of the oscillation circuit in different working modes. According to the invention, high precision and stability can still be maintained in a complex environment.

Description

Technical Field

[0001] The invention relates to the technical field of integrated chips, in particular to a high-precision, high-frequency and frequency-adjustable oscillating circuit of an integrated circuit chip. Background Art

[0002] In the chip design process, high-precision oscillation frequency is often used as a clock signal, and some chips have extremely high requirements for the accuracy and reliability of this frequency. Once the internal frequency deviates, it may cause the chip to operate abnormally or even crash. However, chips usually work in complex environments, such as high / low temperature changes, power surges / sags, insufficient or overvoltage power supply, etc. These factors may affect the stability of the clock circuit. Therefore, it is particularly important to design an oscillation circuit with high precision, strong stability and support for high-frequency regulation. Summary of the invention

[0003] To this end, the present invention provides an integrated circuit chip high-precision high-frequency adjustable frequency oscillation circuit, aiming to solve the deficiencies in the integrated circuit frequency circuit design in the prior art, especially the existing clock circuit is prone to frequency abnormality, frequency interruption and even chip crash when facing complex working environments such as power supply fluctuations or temperature changes. The present invention thus provides an integrated circuit chip high-precision high-frequency adjustable frequency oscillation circuit that can maintain high precision and stability in complex environments.

[0004] In order to solve the above technical problems, the present invention provides an integrated circuit chip high-precision high-frequency adjustable frequency oscillator circuit, comprising: Constant reference output module, used to provide a reference signal independent of temperature and power supply fluctuations; A voltage-stabilized internal power supply module converts an external power supply into a voltage-stabilized power supply using the reference signal; A high-frequency oscillation generating module receives the voltage-stabilized power supply and generates a high-frequency oscillation signal; A frequency control module, coupled to the high-frequency oscillation generating module, for adjusting the high-frequency oscillation signal; The logic control module is respectively connected to the constant reference output module, the voltage-stabilized internal power supply module, the high-frequency oscillation generating module and the frequency regulation module, and is used to receive external control signals and output instructions including startup, sleep and frequency output, so as to realize high-precision adjustable output of the oscillation circuit in different working modes.

[0005] In one embodiment of the present invention, the voltage-stabilized internal power supply module comprises: A reference input unit, used for receiving a reference signal provided by the constant reference output module; A voltage stabilization control unit converts an external power supply into a regulated power supply by using an internal source follower or operational amplifier loop regulation structure; The start / clear control unit is used to receive an external enable signal and a clear signal, and initialize and control the switch of the voltage-regulated internal power supply module when the chip is powered on or restored from a sleep mode.

[0006] In one embodiment of the present invention, the high-frequency oscillation generating module includes a first high-frequency oscillation generating module, which is a ring oscillator or a transistor-capacitor coupled oscillation circuit, and is used to generate an original high-frequency oscillation analog signal under the drive of the regulated internal power supply.

[0007] In one embodiment of the present invention, the high-frequency oscillation generating module includes a second high-frequency oscillation generating module, which performs frequency multiplication, frequency division or shaping processing on the oscillation signal output by the first high-frequency oscillation generating module, and outputs a high-frequency digital signal that can be directly used by a digital circuit.

[0008] In one embodiment of the present invention, the frequency control module includes: Several levels of switchable resistor networks are used to adjust the equivalent resistance of the oscillation circuit, thereby achieving multi-level fine adjustment and coarse adjustment of the output frequency; A temperature coefficient compensation structure for comprehensively compensating the positive and negative temperature coefficients of the resistor network to eliminate oscillation frequency drift caused by temperature changes; Several MOS switch arrays are controlled on and off by external logic signals to select a preset resistance branch, thereby obtaining a desired high-precision output frequency.

[0009] In one embodiment of the present invention, the logic control module includes: A startup control unit, used to activate the constant reference output module, the voltage-stabilized internal power supply module and the high-frequency oscillation generation module in sequence when the chip is powered on; A sleep control unit, used to shut down the constant reference output module, the voltage-stabilized internal power supply module and the high-frequency oscillation generation module when the system is in sleep mode, so as to reduce static power consumption; The frequency instruction output unit is used to provide a plurality of step selection signals to the frequency control module to set or change the fine adjustment gear of the output frequency.

[0010] In one embodiment of the present invention, the logic control module is further configured to switch the oscillation circuit between a startup mode, a working mode and a sleep mode according to an external operation mode selection signal, wherein: In the startup mode, the reference voltage source and the voltage-stabilized power supply module are turned on successively, and then the oscillation generation is started; In the working mode, the high-frequency oscillation generating module continuously outputs a stable high-frequency clock signal; In the sleep mode, the constant reference output module and the voltage-stabilized internal power supply module are turned off, and the high-frequency oscillation output is stopped.

[0011] In one embodiment of the present invention, the oscillation circuit can maintain a stable output frequency when the external power supply is in the range of 2V to 7V, and can still output a normal clock signal with undistorted amplitude and duty cycle when a power surge or sudden drop occurs within 0.1μs.

[0012] In one embodiment of the present invention, the temperature drift of the output frequency of the oscillation circuit does not exceed ±0.3% within the ambient temperature range of -20°C to 140°C, and the output frequency does not jump or interrupt when the temperature changes rapidly.

[0013] The above technical solution of the present invention has the following advantages compared with the prior art: The high-precision, high-frequency, adjustable-frequency oscillator circuit of an integrated circuit chip described in the present invention is composed of multiple functional modules, including a constant reference output module (VBG module), a voltage-stabilized internal power supply module (VREF module), a high-frequency oscillation generation module (OSC module, composed of osc1 and osc2), a frequency control module (res_sel), and a corresponding logic control module. The circuit achieves high-precision, adjustable, high-frequency, and environmentally resistant (including voltage mutations, temperature changes) clock output through a reasonable architecture and signal path. The circuit has a high output frequency, a wide frequency range, and strong adjustability. Its original frequency range can be adjusted between 4MHz-48MHz according to circuit parameters, and its application range is relatively wide.

[0014] The circuit of the present invention has high frequency accuracy, and can perform several levels of fine adjustment on the frequency according to the logic signal, and the final frequency deviates from the required standard frequency by only 0.1%-0.2%.

[0015] The circuit frequency of the present invention is insensitive to power supply, has high power supply rejection ratio and strong impact resistance. Within the integrated circuit limit withstand voltage range of 2 to 7V, the output frequency remains constant. When the power supply voltage surges / drops within 0.1μs, the signal will not have waveform distortion or frequency aberration, and the frequency remains stable.

[0016] The circuit frequency of the present invention is insensitive to ambient temperature and has strong resistance to complex environments. In the ambient temperature range of -20 to 140°C, the frequency temperature drift is controlled within ±0.3%. In the case of a sudden change in temperature, the output frequency does not fluctuate and the circuit works stably.

[0017] The circuit of the present invention uses the conventional 3V / 5V MOS process of the integrated circuit chip and an external VDD power supply as input, thereby solving the problems of frequency instability, failure and crash in the internal clock frequency design of the chip.

[0018] The circuit of the present invention has a highly universal design. The circuit can be used as a high-frequency clock circuit for most chips. The design has a wide adjustable range and can use logic signals to fine-tune the output frequency to several levels (for example, 24M-256 levels of control), which is suitable for high-precision application scenarios.

[0019] The internal power supply voltage output by the circuit of the present invention is adjustable. According to the resistance setting of the voltage-stabilized internal power supply module, the output internal voltage can be flexibly adjusted to meet different product requirements. At the same time, the parameter size of the design element can be adjusted to adapt to different anti-interference-power consumption-start-up speed requirements.

[0020] The circuit of the present invention has good output frequency stability, and the temperature characteristics and power supply rejection ratio of the voltage signal meet the requirements of most circuits for reference, and can be used as a voltage reference signal after power-on. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0022] Figure 1 It is the overall structure diagram of the high-precision high-frequency adjustable frequency oscillator circuit of the integrated circuit chip of the present invention.

[0023] Figure 2 It is a structural diagram of the constant reference output module of the present invention.

[0024] Figure 3 It is a structural diagram of the voltage-stabilized internal power supply module of the present invention.

[0025] Figure 4 It is a structural diagram of the first high-frequency oscillation generating module (osc1) of the present invention.

[0026] Figure 5 It is a structural diagram of the second high-frequency oscillation generating module (osc2) of the present invention.

[0027] Figure 6 It is a structural diagram of the frequency control module of the present invention. DETAILED DESCRIPTION

[0028] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0029] In the present invention, if directions (up, down, left, right, front and back) are described, it is only for the convenience of describing the technical solution of the present invention, and does not indicate or imply that the technical features referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it cannot be understood as a limitation of the present invention.

[0030] In the present invention, "several" means one or more, "multiple" means more than two, "greater than", "less than", "exceed" and the like are understood to exclude the number itself; "above", "below", "within" and the like are understood to include the number itself. In the description of the present invention, if there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0031] In the present invention, unless otherwise clearly defined, the words "set", "install", "connect" and the like should be understood in a broad sense, for example, they can be directly connected or indirectly connected through an intermediate medium; they can be fixedly connected or detachably connected or integrally formed; they can be mechanically connected or electrically connected or able to communicate with each other; they can be the internal connection of two elements or the interaction relationship between two elements. Those skilled in the art can reasonably determine the specific meanings of the above words in the present invention in combination with the specific content of the technical solution.

[0032] Reference Figure 1 As shown, an integrated circuit chip high-precision high-frequency adjustable frequency oscillator circuit of the present invention comprises: The constant reference output module (VBG) is used to provide a reference signal that is independent of temperature and power supply fluctuations. The constant reference output module (VBG) adopts a bandgap reference voltage source structure, uses transistor characteristics to generate a bias that is independent of the power supply, and converts the unstable input power provided by the front port into a VBG reference signal with a good power supply rejection ratio. This part uses the driver provided by the chip power supply voltage as the power supply VDD (which can be turned off in sleep mode). The reference output temperature characteristics need to be adjusted according to the process parameters to achieve a reference temperature offset of -20-140℃ <0.3% and a power supply rejection ratio of more than 60dB.

[0033] The voltage-stabilized internal power supply module (VREF) converts the external power supply into a voltage-stabilized power supply using the reference signal; the voltage-stabilized internal power supply module (VREF) is responsible for generating an internal power supply that can be used to drive the oscillation circuit. In the working mode, the module uses the stable reference voltage vbg (reference signal) as the signal source to convert the chip power supply (external power supply VDD) into a voltage-stabilized power supply vref1 with high stability and high driving capability. The vref1 voltage is provided to the high-frequency oscillation generation module (OSC) and the frequency control module (res_sel). The module has a relatively strong ability to resist power supply interference, and can provide redundancy when the power supply voltage has sudden changes such as jitter and spikes, so as to ensure that the high-frequency oscillation generation module (osc) does not fail. The module can provide adjustment of the MOS tube size and capacitance parameters to further improve the anti-interference ability, but it will also increase the working power consumption / reduce the startup speed accordingly. The actual need is to make a trade-off based on the application end.

[0034] The module uses the IHRC_EN (enable) signal as the start signal and the IHRC_EN_delay signal as the clear signal. The IHRC_EN_delay (clear signal) ensures that the module is in a normal state every time the low voltage is turned on, and that the subsequent circuit does not generate additional power consumption in the sleep mode.

[0035] The high-frequency oscillation generating module (osc) receives the voltage-stabilized power supply and generates a high-frequency oscillation signal. The high-frequency oscillation generating module (osc) includes a first high-frequency oscillation generating module (osc1) and a second high-frequency oscillation generating module (osc2).

[0036] Among them, the first high-frequency oscillation generating module (osc1) is mainly responsible for generating a high-frequency oscillation analog signal of a certain design value. After vref is turned on and the module receives the IHRC frequency start signal, the module starts working and generates an analog oscillation signal. The original value of the analog frequency of this design can be determined by adjusting the parameters according to the actual application. The original value is related to the paired matching capacitors in the circuit. When adjusting the capacitor parameters, it is necessary to ensure that the capacitors are matched in pairs.

[0037] The second high-frequency oscillation generation module (osc2) is mainly responsible for selecting the output frequency. It can freely select 1x / 2x output frequency according to the actual application requirements and the response speed of the logic circuit to expand the applicable range of high-frequency frequency. At the same time, the module also converts the analog oscillation signal of the internal vref as the power supply into a digital signal that can be directly used by the logic circuit, and then can be directly input into the MCU logic circuit as the main frequency or for other uses.

[0038] The frequency control module (res_sel) is coupled to the high-frequency oscillation generating module and is used to adjust the high-frequency oscillation signal. The frequency control module is mainly responsible for fine-tuning the frequency generated by the high-frequency oscillation generating module (osc). Since practical applications have high requirements for frequency accuracy, it is necessary to eliminate the deviation caused by the chip production process through the regulation of this module to achieve high precision and high accuracy requirements. At the same time, this module can also be used in subsequent applications, where there is a need to significantly adjust the frequency, and the frequency can be reset without modifying the chip.

[0039] In the circuit, the number of trimming groups can be determined according to the needs. Figure 6 The design given in the specification is an 8×32 256-level adjustment design, where 8 levels are large levels M that can greatly adjust the frequency, and 32 levels are small levels N that can fine-tune the frequency (the actual number of M×N levels can be freely determined according to the chip, generally an exponential multiple of 2).

[0040] In the circuit, the large-range single-stage resistor res_symbol_A / small-range single-stage resistor res_symbol_B are obtained by connecting two resistors with different temperature coefficients in series / in parallel, respectively. This design is used to cancel the positive and negative temperature coefficients of the resistors and eliminate the frequency drift caused by temperature changes. The resistance value of the large-range single-stage resistor Ra=N×the resistance value of the small-range single-stage resistor Rb.

[0041] The logic control module (MCU) is respectively connected to the constant reference output module, the voltage-stabilized internal power supply module, the high-frequency oscillation generating module and the frequency regulation module, and is used to receive external control signals and output instructions including startup, sleep and frequency output, so as to realize high-precision adjustable output of the oscillation circuit in different working modes.

[0042] Specifically, the working modes include: Startup Mode: When the chip power supply vdd is powered on from 0V, the designed circuit module is in the startup mode. The MUC logic circuit inputs the startup signal, first turning on the reference module vbg, and then turning on the regulated voltage source vref. After the regulated voltage source is ready to start, the OSC oscillation circuit is finally turned on.

[0043] Working Mode: After the chip starts normally, when the non-sleep mode power supply vdd is normal, the circuit is in working mode and outputs a stable frequency.

[0044] Sleep mode (sleep): In sleep mode, the reference module vbg, the voltage regulator circuit vref, and the OSC oscillation circuit are all turned off, and the 5V static power consumption is less than 1nW. When exiting sleep mode, it starts up like the startup mode.

[0045] The circuit structure and working principle are further described below.

[0046] Constant Reference Output Module (VBG Module): Reference Figure 1 As shown, in the overall framework of the circuit shown, the VBG module is a front-end reference generation module. This module uses bandgap reference technology to generate a reference voltage signal vbg that is basically independent of the power supply voltage and temperature. The typical implementation of the VBG module is to form a bandgap reference source by combining transistors and a precisely matched resistor array in the circuit. Through the front-end unstable voltage input, the module outputs the vbg signal to provide a reliable reference for the subsequent voltage-stabilized internal power supply module and the oscillation module. This module includes multiple MOS transistors and a small amount of high-precision resistors in the actual integrated circuit, and is turned on before the subsequent modules are started.

[0047] Regulated internal power supply module (VREF module): Reference Figure 2 As shown in the figure, the module uses the stable reference voltage vbg provided by the VBG module as the input reference, and converts the external power supply VDD into a high-stability, low-noise internally regulated power supply vref1 through an internal MOS tube source follower or op amp control circuit. The vref1 voltage is provided to the high-frequency oscillation generation module (OSC) and the frequency control module (res_sel).

[0048] As can be seen from the circuit diagram, the left input end has the IHRC_EN signal and the related inverter (Inverter) and MOS tube M4. When IHRC_EN is high, the power-on start signal or permission signal is transmitted to the core reference voltage generation part of the circuit through devices such as M4, so that the module enters the working state from the off state.

[0049] The function of the inverter is to perform phase or level shaping on the IHRC_EN signal so that MOS tubes such as M4 can correctly open the internal circuit power path.

[0050] The power supply voltage domain is divided into two voltage domains, namely, vdd1 and vdd2, to improve the power supply rejection capability and optimize the circuit performance.

[0051] Vdd1, vdd2 and the internal node (vbp1) can be connected in order through MOS tubes such as M34 to provide suitable bias and power supply conditions for different parts of the reference circuit.

[0052] MOS tube array (M1_2, M2_6, M2_2, M5_2, M15_2...) and bias node (vbp1) There are a series of MOS tube arrays (such as M1_2, M2_6, M2_2, M5_2, M15_2, etc.) and nodes marked vbp1 and vbg in the middle of the circuit. These MOS tubes and the rear horizontal nodes form a reference voltage that is relatively stable to the power supply voltage and temperature.

[0053] vbp1 is usually an internal bias voltage node, which is used to set the operating point of the MOS tube to ensure that the reference voltage is insensitive to power supply and voltage changes.

[0054] The current / voltage reference unit composed of transistors (Q1, Q24, Q34) and resistors (R0, R33) and other devices, together with precision resistors such as R0 and R33, form the core of the bandgap reference.

[0055] The bandgap reference selects two voltages with temperature complementary characteristics (such as PN junction voltage) and resistor voltage division to offset the positive and negative temperature changes, thereby obtaining a stable reference voltage vbg that does not change significantly with temperature and voltage. Resistors such as R0 and R33 play the role of current, voltage division and temperature coefficient compensation in the circuit. The resistance value and Q tube characteristics are carefully matched to keep the output vbg constant within the process and temperature range.

[0056] Startup and dead zone prevention circuit (M18, M19, M20, M21, M22, M23...), the bandgap reference circuit requires a startup circuit to prevent the circuit from entering a non-conducting dead zone state after power-on.

[0057] Devices such as M18, M19, and M20 form the startup path. When the circuit is just powered on, these MOS tubes provide initial current to the key nodes, allowing the reference branch to enter the normal operating point. The startup circuit can then be turned off to reduce power consumption. MOS tubes such as M21, M22, M23, and M16 are components used for adjustment and stabilization in the circuit to ensure that the vbg output is stable under various working conditions. The node marked with vbg is the final bandgap reference output voltage. This voltage has a strong suppression ability for power supply voltage and temperature, and usually provides a stable and reliable reference reference for circuits such as post-stage voltage regulation, current reference, charge pump, and oscillator. MOS tubes such as M17, M8, M24_4, M25_4, and M29 are combined in the reference output path to buffer and control vbg and ensure that it maintains the design level under various operating conditions.

[0058] Reference Figure 3As shown in the figure, the VREF module includes a MOS transistor array, a voltage regulation reference circuit, and a corresponding start / shutdown signal control unit. In the circuit, IHRC_EN is the start signal of the module. When IHRC_EN is valid, the VREF module starts to work and provides a regulated internal power supply for the OSC module. When IHRC_EN_delay (clear signal) works, it can ensure that the module is in a normal state when it is turned on at low voltage or restarted after sleep.

[0059] In the actual circuit diagram, we can see the MOS devices and control logic connected in series. The gate end of the MOS tube is connected to the reference voltage point, and the drain / source is connected to the subsequent load to achieve a regulated output. VREF can also suppress power surges / sags to avoid oscillation abnormalities caused by interference on the power supply side.

[0060] IHRC_EN and IHRC_EN_delay signals, these control signals affect the startup and shutdown of the entire regulated reference power supply through logic gates (such as I1 marked as nor2d1) and MOS tubes (M14, M5). I0 is an inverter (Inverter), which is used to level-shape the input signal (such as IHRC_EN from the external MCU logic). I1 is a NOR gate, which logically combines the IHRC_EN and IHRC_EN_delay signals. When the two meet specific conditions, the output signal can control the conduction of MOS tubes such as M14. M14 is controlled by the logic gate to determine whether the downstream circuit (such as the reference voltage generation and output stage) enters the working state. M15 is connected to the vdd1 power line, which is used to provide a specific current or pull a node to a suitable level during the startup phase to ensure that the circuit is powered on normally.

[0061] There is a reference voltage input from VBG in the circuit. VBG is a high stability reference voltage source output with temperature and power supply variation immunity.

[0062] Bias and filter network composed of M1, M6, M19, C2 and other components: These MOS tubes (such as M1, M6, M19) and capacitors (C2) form an internal bias loop and compensation network, which are used to further convert the vbg reference signal into a more stable internal bias point (bb node) or provide suitable operating conditions for the generation of vref1. Capacitors such as C2 provide frequency compensation, filtering and suppression of high-frequency noise, making the output smoother and more stable. R0, R1, and R21 are resistor elements, which play a role in setting the output voltage level, limiting current and temperature compensation by distributing and modulating current and voltage.

[0063] The ngate node is a control gate potential, which is used to control the conduction of the MOS tube, thereby refining the regulation of the reference voltage or current.

[0064] M2, M4, C0, C14 are combined in the VBG reference loop to further adjust and stabilize the signal from VBG, suppress low-frequency noise or compensate for temperature characteristics.

[0065] C0 and C14 are filtering or compensation capacitors used to stabilize the output node voltage and suppress oscillation.

[0066] M5 is controlled by IHRC_EN. When the circuit is enabled, M5 is turned on and the stabilized internal voltage node is output as vref1, which becomes the reference power input of the subsequent oscillator or other modules.

[0067] vref1 is a controlled internal regulated reference power supply, which can remain stable under external power supply changes and internal load disturbances, thereby improving the accuracy and reliability of the entire system.

[0068] C11 is used as a filter capacitor at the vref1 end to smooth the final output reference voltage, reduce high-frequency noise, and make vref1 a stable, low-noise reference voltage source.

[0069] High frequency oscillation generation module (OSC module, including osc1 and osc2): Reference Figure 4 , Figure 5 As shown, the OSC module actually has a two-level structure: osc1 and osc2.

[0070] osc1 module: mainly generates an original high-frequency analog oscillation signal. A ring oscillator (RingOscillator) or an oscillation structure composed of a transistor, capacitor, and resistor is usually used here. In the circuit, multiple inverters (INV units composed of MOS tubes) are connected in series to form an oscillation loop. There may also be a current source or a limiting device controlled by a MOS tube to ensure the stability of the oscillation amplitude and frequency. The output of osc1 is an analog waveform, which is used in subsequent links after shaping.

[0071] Reference Figure 4 As shown in the figure, the IHRC_EN signal can be seen in the circuit, which is buffered and delayed by a series of inverters such as I57, I54, and I51. The function of these inverters is to shape and stabilize the IHRC_EN input signal and pass it to the subsequent circuit to control the start and stop of the oscillator. IHRC_EN is the "enable" or "start" signal of the circuit. When IHRC_EN is valid, the circuit enters the working state and provides enabling conditions for the subsequent oscillation loop.

[0072] The circuit is mainly composed of a MOS tube array, a matching capacitor array, an inverter, a logic gate (NOR, NAND) and a control signal interface. The IHRC_EN signal enters oscillation after being stabilized by a series of inverters, so that the MOS tube and the capacitor network work with the voltage-stabilized power supply in vref1. The res_sel module selects the corresponding resistor and capacitor path through the MOS tube switch network to achieve subdivision adjustment of the oscillation frequency. Finally, after being processed by the logic gate circuit, the generated oscillation pre-output signal (osc_pre) is sent to the subsequent osc2 module for the final signal output. This circuit design ensures that the oscillation frequency is stable and adjustable, and has high immunity to changes in power supply and temperature environment.

[0073] osc2 module: used to multiply or divide the output frequency of osc1, and convert the analog waveform into a digitally usable clock signal output. In this module, you can see the gate circuit composed of MOS tubes, the frequency multiplication unit (such as a controlled MOS switch network), and a series of inverters for signal shaping and output drive. osc2 outputs the selected frequency signal to the subsequent logic control module or directly uses it as a clock signal (clkout) for other modules in the system. The osc2 part can also select the output frequency (1x / 2x, etc.) through the internal control signal.

[0074] Reference Figure 5 As shown, the output signal port of the previous stage (osc1) is "osc_pre". The "osc_pre" signal firstly goes through an inverter I20 (Inv1) to shape and buffer the input signal. The inverter is composed of MOS tubes, which can realize level flipping and driving capability enhancement of the "osc_pre" signal.

[0075] The signal output by inverter I20 is fed into a D flip-flop (labeled as "dff1"). The D flip-flop uses vref1 as the internal reference power supply and latches the input signal to convert the original analog oscillation signal into a controlled digital waveform, which is beneficial to subsequent digital circuit processing. The flip-flop plays the role of synchronization and stable output, so that the output pulse has better duty cycle and phase characteristics.

[0076] Multiplexer (MUX) and Transmission Gate (TG) After the dff1 output, there are transmission gates composed of multiple MOS tubes (marked as "tg1" or symbols such as I14 and I15 in the figure), and control signals such as "muxa_" are input. These transmission gates and the selection network controlled by the muxa_ line form a simple multiplexer structure. Through the control signal (muxa_), the circuit can select between different signal sources or bypass / cut off the oscillation signal.

[0077] The transmission gate is usually composed of a pair of complementary MOS tubes (PMOS + NMOS), which can conduct with low resistance when the control signal is valid, allowing the signal to pass without distortion; and disconnect the signal path when the control signal is invalid.

[0078] After the transmission gate, the inverter I13 (Inv1) acts as a buffer and shaping unit to further correct the signal output by the MUX. The inverter can provide a suitable logic level and enhance the driving capability.

[0079] The figure shows the enable signal lines marked as IHRC_EN and IHRC_ENA, as well as the logic network composed of MOS transistors such as M24, M23, M22, M25, M29, and M34. These MOS devices are used to realize the start and stop control of the output clock, mode selection, and power consumption management.

[0080] Through control signals such as IHRC_EN and IHRC_ENA, the circuit can shut down the oscillation output when the chip enters sleep mode, thereby saving power consumption; in normal working mode, these MOS tube networks ensure that the oscillation signal path is opened normally and the output maintains a high-frequency clock signal with high precision.

[0081] On the far right side of the circuit, multiple inverters (such as I138, I140, I142) and additional driver tube M146 are connected in series on the output path. These inverters are cascaded to form an output buffer chain, which drives the stabilized and selected digital oscillation signal "clkout" to the subsequent circuit module. The multiple inverters can ensure that the output has sufficient driving capability and matches the required load.

[0082] The connection between osc1 and osc2 is as follows: the pre oscillation signal (such as osc_pre) output by osc1 enters the osc2 selection path through the cascaded MOS gate circuit, inverter, trigger (DFF) or transmission gate (tg unit).

[0083] In osc2, there are NAND gates, AND gates, or inverter arrays, which are used to adjust and amplify the output signal, so that it can eventually become a digital clock with a stable duty cycle and matching amplitude. It also includes a MOS tube array to form a controlled switch structure, which can determine whether to output an oscillation signal and roughly adjust the frequency according to control signals such as IHRC_ENA.

[0084] Frequency control module (res_sel module): Reference Figure 6 As shown, the res_sel module uses a series of optional resistor arrays and MOS selection switches (M, N hierarchical control network) to accurately adjust the oscillation frequency.

[0085] In the circuit, we can see two basic unit resistor symbols, res_symbol_A and res_symbol_B. These resistors have carefully designed temperature coefficients and are connected in series and parallel to form adjustable resistance values ​​of multiple gears to achieve precise fine-tuning and wide-range coarse-tuning of the oscillation frequency. The 8×32 and other multi-level selection structures are selected through the control words such as selH<7:0> and selL<31:0> output by the logic control module, thereby changing the equivalent resistance of the oscillation circuit, and finally refining the oscillation frequency, so that the final output frequency and the standard frequency deviation are within the range of 0.1%-0.2%.

[0086] At the same time, this module is designed to be corrected through internal logic (such as burning in control words) after chip production to compensate for process deviations and environmental errors, ensuring that the final frequency is stable and reliable.

[0087] Specifically, the original oscillation frequency output by osc1 will be fine-tuned and corrected through the subsequent resistor network and control circuit. The "res_symbol_A" and "res_symbol_B" boxes are standard resistor element units, which are composed of positive and negative temperature coefficient resistors such as R_p and R_n. By combining resistors with positive and negative temperature coefficients, the frequency drift caused by temperature changes can be offset, so that the circuit can maintain frequency stability under different temperature environments. res_symbol_A and res_symbol_B represent the basic units of two types of resistor fine-tuning gears, which can be combined in series and parallel to form multiple selectable resistance value gears. The "total 8", "total 32", etc. in the figure indicate the number of resistor array levels set for coarse and fine frequency adjustment in the frequency control circuit.

[0088] For example, the "symbolA" part can be used to implement 8 large-scale frequency adjustment (corresponding to selH<7:0>). By connecting or disconnecting certain resistors in the circuit, the equivalent resistance value of the oscillator loop is changed, thereby making a larger adjustment (coarse adjustment) to the frequency.

[0089] The "symbolB" part is used for 32 small-speed frequency adjustments (corresponding to selL<31:0>), which is a more precise fine-tuning of the frequency.

[0090] The overall design is similar to a programmable resistor DAC (digitally controlled resistor), which has both coarse and fine adjustment gears, forming 8×32=256 levels of composite adjustable gears (which can be changed according to actual design requirements).

[0091] The MOS tubes (M0, M2, M15, M21, M217, etc.) distributed in the resistor network are controlled by their gate control signals (selH <x>、selL <x>) selectively connects or disconnects the corresponding resistance branch.

[0092] When the control signal is high, the corresponding MOS tube is turned on, and the branch resistor is connected to the main oscillation circuit; when the control signal is low, the corresponding MOS tube is turned off, and the resistor branch does not affect the circuit.

[0093] By digitally controlling the MOS tube array, the required resistance value combination can be flexibly selected to achieve frequency modulation.

[0094] The right side of the figure is the logic control module, which receives control words (such as CAL<7:0>, selH<7:0>, selL<31:0>) from the upper-level circuit or MCU.

[0095] The selH<7:0> signal is used to control the selection of 8-level coarse-tuning resistors, and the selL<31:0> signal is used to control the selection of 32-level fine-tuning resistors, so that in actual applications, the best resistance combination can be set for the oscillator according to measurement results, production correction data, or changes in the operating environment to achieve the required precise frequency. The logic control module distributes the digital control signal to the MOS switch network to achieve online adjustment of the resistance level and frequency fine-tuning and correction.

[0096] Logic control module: In the overall circuit framework, the logic control module receives signal input from the MCU logic circuit, which is used to control IHRC_EN, IHRC_EN_delay, and the gear control signal (selH<7:0>, selL<31:0>) in res_sel. In sleep mode, the MCU logic can shut down the VBG, VREF, and OSC modules to reduce power consumption. When the MCU is powered on, each module is activated in the startup sequence, so that the circuit gradually enters the working state and outputs a stable clock. The connection between the logic control module and OSC and res_sel can be seen as the control signal line input MOS selection array, and the frequency is adjusted by the resistor array and MOS switch combination.

[0097] During operation, an external VDD power supply is provided to the VBG module and the VREF module; the VBG module generates a stable reference vbg signal which is input to the VREF module.

[0098] The VREF module modulates VDD and vbg through internal voltage regulation and outputs vref1 to OSC (osc1+osc2) and res_sel for use, providing them with stable internal working power.

[0099] When the IHRC_EN signal is valid, the OSC module starts, where osc1 generates basic high-frequency oscillation, osc2 multiplies or selects the output frequency according to the control signal, and outputs a high-precision digital clock signal clkout after correction through the logic signal.

[0100] The res_sel module fine-tunes the OSC frequency by selecting different resistor network configurations to compensate for the deviations caused by the process and environment, so that the output frequency meets high-precision requirements.

[0101] The MCU logic circuit is responsible for generating control signals such as IHRC_EN, IHRC_EN_delay, selH, selL, etc. to realize switching between different working modes such as startup, sleep, and frequency modulation.

[0102] In summary, the circuit provides high-stability power supply and reference conditions for the subsequent high-frequency oscillation generation module (OSC) through the VBG module (constant reference output module) and the VREF module (voltage-stabilized internal power supply module). The OSC module (including osc1 and osc2) generates high-precision high-frequency oscillation signals under this internal voltage-stabilized condition. The res_sel module achieves fine correction and adjustment of the frequency through an adjustable resistor network. The logic control module controls the startup, shutdown and frequency modulation mode selection of the circuit according to the external MCU signal. The overall circuit still maintains high accuracy and high stability of frequency output under complex environments such as variable temperature and power supply mutation.

[0103] Finally, it should be noted that the above specific implementation methods are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.< / x> < / x>

Claims

1. An integrated circuit chip high-precision high-frequency adjustable frequency oscillator circuit, characterized in that: include: Constant reference output module, used to provide a reference signal independent of temperature and power supply fluctuations; A voltage-stabilized internal power supply module converts an external power supply into a voltage-stabilized power supply using the reference signal; A high-frequency oscillation generating module receives the voltage-stabilized power supply and generates a high-frequency oscillation signal; A frequency control module, coupled to the high-frequency oscillation generating module, for adjusting the high-frequency oscillation signal; The logic control module is respectively connected to the constant reference output module, the voltage-stabilized internal power supply module, the high-frequency oscillation generating module and the frequency regulation module, and is used to receive external control signals and output instructions including startup, sleep and frequency output, so as to realize high-precision adjustable output of the oscillation circuit in different working modes.

2. The high-precision high-frequency adjustable frequency oscillator circuit of an integrated circuit chip according to claim 1, characterized in that: The voltage-stabilized internal power supply module comprises: A reference input unit, used for receiving a reference signal provided by the constant reference output module; A voltage stabilization control unit converts an external power supply into a regulated power supply by using an internal source follower or operational amplifier loop regulation structure; The start / clear control unit is used to receive an external enable signal and a clear signal, and initialize and control the switch of the voltage-regulated internal power supply module when the chip is powered on or restored from a sleep mode.

3. The high-precision high-frequency adjustable frequency oscillator circuit of an integrated circuit chip according to claim 1, characterized in that: The high-frequency oscillation generating module includes a first high-frequency oscillation generating module, which is a ring oscillator or a transistor-capacitor coupled oscillation circuit, and is used to generate an original high-frequency oscillation analog signal under the drive of the regulated internal power supply.

4. The high-precision high-frequency adjustable frequency oscillator circuit of an integrated circuit chip according to claim 3, characterized in that: The high-frequency oscillation generating module includes a second high-frequency oscillation generating module, which performs frequency multiplication, frequency division or shaping processing on the oscillation signal output by the first high-frequency oscillation generating module, and outputs a high-frequency digital signal that can be directly used by a digital circuit.

5. The high-precision high-frequency adjustable frequency oscillator circuit of an integrated circuit chip according to claim 1, characterized in that: The frequency control module includes: Several levels of switchable resistor networks are used to adjust the equivalent resistance of the oscillation circuit, thereby achieving multi-level fine adjustment and coarse adjustment of the output frequency; A temperature coefficient compensation structure for comprehensively compensating the positive and negative temperature coefficients of the resistor network to eliminate oscillation frequency drift caused by temperature changes; Several MOS switch arrays are controlled on and off by external logic signals to select a preset resistance branch, thereby obtaining a desired high-precision output frequency.

6. The high-precision high-frequency adjustable frequency oscillator circuit of an integrated circuit chip according to claim 1, characterized in that: The logic control module comprises: A startup control unit, used to activate the constant reference output module, the voltage-stabilized internal power supply module and the high-frequency oscillation generation module in sequence when the chip is powered on; A sleep control unit, used to shut down the constant reference output module, the voltage-stabilized internal power supply module and the high-frequency oscillation generation module when the system is in sleep mode, so as to reduce static power consumption; The frequency instruction output unit is used to provide a plurality of step selection signals to the frequency control module to set or change the fine adjustment gear of the output frequency.

7. The high-precision high-frequency adjustable frequency oscillator circuit of an integrated circuit chip according to claim 1, characterized in that: The logic control module is further configured to switch the oscillator circuit between a startup mode, a working mode and a sleep mode according to an external operation mode selection signal, wherein: In the startup mode, the reference voltage source and the voltage-stabilized power supply module are turned on successively, and then the oscillation generation is started; In the working mode, the high-frequency oscillation generating module continuously outputs a stable high-frequency clock signal; In the sleep mode, the constant reference output module and the voltage-stabilized internal power supply module are turned off, and the high-frequency oscillation output is stopped.

8. The high-precision high-frequency adjustable frequency oscillator circuit of an integrated circuit chip according to claim 1, characterized in that: The oscillator circuit can maintain a stable output frequency when the external power supply is in the range of 2V to 7V, and can still output a normal clock signal with undistorted amplitude and duty cycle when a power surge or sudden drop occurs within 0.1μs.

9. The high-precision high-frequency adjustable frequency oscillator circuit of an integrated circuit chip according to claim 1, characterized in that: The temperature drift of the output frequency of the oscillator circuit does not exceed ±0.3% within the ambient temperature range of -20°C to 140°C, and the output frequency does not jump or interrupt when the temperature changes rapidly.

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