Relaxation oscillator, chip and electronic device

Abstract

The invention provides a relaxation oscillator, a chip and an electronic device, the relaxation oscillator comprises a bias module, a first generation module, a first comparator, a second generation module, a second comparator and a control logic module, the first generation module and the second generation module alternately enter a first working mode and a second working mode, in the first working mode, the first comparator is connected with the second comparator, and in the second working mode, the second comparator is connected with the control logic module. The non-inverting input end inputs a reference voltage, when the voltage of the inverting input end rises from a preset initial voltage to the reference voltage, a discharge signal is output, so that the voltage of the inverting input end drops, and when the voltage of the inverting input end drops to the reference voltage, the discharge signal is stopped being output, so that the voltage of the inverting input end is kept as the reference voltage; in the second working mode, the reference voltage is input into the inverted input end, the first comparator or the second comparator is grounded and reset at the non-inverted input end until the voltage of the non-inverted input end reaches the reference voltage, and the first output signal or the second output signal is correspondingly output.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a relaxation oscillator, a chip and an electronic device. Background Art

[0002] Now, ideally, the RC value determines the nominal frequency of the relaxation oscillator. The main problems that arise in relaxation oscillators are offset voltage, delay time, leakage and tunneling currents, and current mismatch. The offset voltage occurs mainly due to the mismatch between the quasi-differential transistors in the comparator. The size of the transistors minimizes the offset voltage. Usually, the offset voltage increases linearly with temperature and varies slightly with changes in the supply voltage. The delay time of the comparator mainly determines the delay time of the entire circuit. The delay time is also sensitive to temperature and power supply changes. It exhibits nonlinear behavior over temperature and is directly related to the bandwidth of the comparator.

[0003] Relaxation oscillators are usually implemented in current mode, exponential RC time mode, or voltage mode. Frequency stability is often affected by process, voltage, and temperature (PVT) variations. Comparator offsets during PVT variations are often the main challenge in achieving stable frequency in ultra-low power relaxation oscillators. Summary of the invention

[0004] The present application provides a relaxation oscillator, a chip and an electronic device for providing an oscillation clock frequency with higher accuracy without increasing power consumption.

[0005] In a first aspect, an embodiment of the present application provides a relaxation oscillator, the relaxation oscillator comprising: Bias module; A first generating module, wherein the first generating module is connected to the bias module to obtain a reference voltage provided by the bias module; A first comparator, wherein an inverting input terminal of the first comparator is connected to a first output terminal of the first generating module, and a non-inverting input terminal of the first comparator is connected to a second output terminal of the first generating module; A second generating module, wherein the second generating module is connected to the bias module to obtain a reference voltage provided by the bias module; A second comparator, wherein an inverting input terminal of the second comparator is connected to a first output terminal of the second generating module, and a non-inverting input terminal of the second comparator is connected to a second output terminal of the second generating module; a control logic module, the control logic module being connected to an output terminal of the first comparator and an output terminal of the second comparator respectively, and the control logic module being used to generate a clock pulse according to a first output signal of the first comparator and a second output signal of the second comparator; Among them, the first generating module and the second generating module alternately enter the first working mode and the second working mode. In the first working mode, the reference voltage is input to the non-inverting input terminal, and the first comparator or the second comparator outputs a discharge signal when the voltage at the inverting input terminal rises from a preset starting voltage to the reference voltage, so that the voltage at the inverting input terminal decreases, and stops outputting the discharge signal when the voltage at the inverting input terminal decreases to the reference voltage, so that the voltage at the inverting input terminal remains at the reference voltage; in the second working mode, the reference voltage is input to the inverting input terminal, and the non-inverting input terminal is grounded and reset, and the first comparator or the second comparator is grounded and reset at the non-inverting input terminal until the voltage at the non-inverting input terminal reaches the reference voltage, and the first output signal or the second output signal is correspondingly output.

[0006] In a second aspect, an embodiment of the present application provides a chip, wherein the chip includes a relaxation oscillator as described in any one of the embodiments of the present application.

[0007] In a third aspect, an embodiment of the present application provides an electronic device, wherein the electronic device comprises a relaxation oscillator as described in any one of the embodiments of the present application.

[0008] The embodiment of the present application provides a relaxation oscillator, including: a bias module, a first generating module, a first comparator, a second generating module, a second comparator and a control logic module, wherein the first generating module is connected to the bias module to obtain a reference voltage provided by the bias module; the inverting input terminal of the first comparator is connected to the first output terminal of the first generating module, and the non-inverting input terminal of the first comparator is connected to the second output terminal of the first generating module; the second generating module is connected to the bias module to obtain the reference voltage provided by the bias module; the inverting input terminal of the second comparator is connected to the first output terminal of the second generating module, and the non-inverting input terminal of the second comparator is connected to the second output terminal of the second generating module; the control logic module is respectively connected to the output terminal of the first comparator and the output terminal of the second comparator, and the control logic module is used to generate a reference voltage according to the first output terminal of the first comparator. The output signal and the second output signal of the second comparator generate a clock pulse; wherein, the first generating module and the second generating module alternately enter the first working mode and the second working mode, in the first working mode, a reference voltage is input to the non-inverting input terminal, and the first comparator or the second comparator outputs a discharge signal when the voltage at the inverting input terminal rises from a preset starting voltage to the reference voltage, so that the voltage at the inverting input terminal decreases, and when the voltage at the inverting input terminal decreases to the reference voltage, the discharge signal is stopped from being output, so that the voltage at the inverting input terminal is maintained at the reference voltage; in the second working mode, a reference voltage is input to the inverting input terminal, the non-inverting input terminal is grounded and reset, and the first comparator or the second comparator is grounded and reset at the non-inverting input terminal until the voltage at the non-inverting input terminal reaches the reference voltage, and the first output signal or the second output signal is output accordingly.Through the relaxation oscillator, the first generating module and the second generating module alternately enter the first working mode and the second working mode. In the first working mode, the first generating module or the second generating module provides a reference voltage to the non-inverting input terminal of the comparator, and increases the voltage of the inverting input terminal of the comparator from a preset starting voltage until the voltage of the inverting input terminal of the comparator reaches the reference voltage. Under the influence of the discharge signal of the comparator, the voltage of the inverting input terminal of the comparator is discharged and reduced until the voltage of the inverting input terminal of the comparator is reduced to the reference voltage, so that the comparator stops outputting the discharge signal. At the moment of starting the discharge, due to the delay, the part of the first actual voltage of the inverting input terminal of the comparator that is greater than the reference voltage is the delay. Delay voltage, at the moment of stopping discharge, the second actual voltage at the inverting input terminal of the comparator is the reference voltage minus the delay voltage, that is, the reference voltage. It can be seen that in the second working mode, the inverting input terminal of the comparator obtains a reference voltage less than the reference voltage. When the comparator generates a clock pulse according to the reference voltage, it starts level reversal when the non-inverting input terminal reaches the reference voltage, and completes the level reversal when the non-inverting input terminal reaches the reference voltage, thereby correcting the delay of the comparator. Since the delay voltage changes with the comparator, it is suitable for different types of comparators to perform delay correction, and is also suitable for a comparator to perform delay correction in different usage situations. At the same time, the reference voltage (V) of the embodiment of the present application. REF -ΔV) can be in a lower range, for example, VDD / 2 ≥ V REF -ΔV≥VDD / 4, in the second working mode, the clock pulse generation time can be reduced, that is, the oscillation frequency of the clock pulse is increased without requiring a larger charging current (I REF ) ensures a higher charging and discharging speed for the oscillation frequency, thereby achieving a higher oscillation frequency without increasing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0010] Figure 1 A circuit diagram of a conventional oscillator provided in an embodiment of the present application; Figure 2 A voltage waveform diagram of a comparison voltage of a conventional relaxation oscillator provided in an embodiment of the present application; Figure 3 A schematic block diagram of a first relaxation oscillator provided in an embodiment of the present application; Figure 4A schematic diagram of a waveform of an input voltage of a first comparator provided in an embodiment of the present application; Figure 5 A schematic diagram of a waveform of a voltage at a VP1 terminal provided in an embodiment of the present application; Figure 6 A schematic diagram of a waveform of an input voltage of a second comparator provided in an embodiment of the present application; Figure 7 A schematic diagram of a clock pulse waveform provided in an embodiment of the present application; Figure 8 A circuit diagram of a second first voltage generating unit provided in an embodiment of the present application; Fig. 9 A circuit diagram of a first voltage generating unit provided in an embodiment of the present application; Fig.10 A circuit diagram of a bias module and a first clock generating unit provided in an embodiment of the present application.

[0011] Figure Number: 100, relaxation oscillator; 11, bias module; 12, first generating module; 121, first voltage generating unit; 122, first clock generating unit; 123, first multiplexing unit; 13, first comparator; 14, second generating module; 141, second voltage generating unit; 142, second clock generating unit; 143, second multiplexing unit; 15, second comparator; 16, control logic module; IS1, first current source; IS2, second current source; Q1, first switch tube; Q2, second switch tube; Q3, third switch tube; Q4, fourth switch tube; Q5, fifth switch tube; Q6, sixth switch tube; Q7, seventh switch tube; R1, first resistor; R2, second resistor; C1, first capacitor; C2, second capacitor. DETAILED DESCRIPTION

[0012] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change according to actual conditions.

[0014] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0015] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0016] See also Figure 1 , Figure 1 is a circuit diagram of a conventional oscillator provided in an embodiment of the present application. Figure 1 As shown in Figure 1, a conventional relaxation oscillator includes two comparators, an RS latch, a bias reference and a timing circuit. The working principle of a conventional relaxation oscillator is realized by charging and discharging a capacitor. The comparator compares the capacitor voltage with the reference voltage V REF When the capacitor voltage reaches the reference voltage V REF When the comparator generates a pulse, the pulse is maintained by the RS-FF latch until the next comparison. The output signal of the RS-FF latch is controlled by the charging or discharging of the capacitor.

[0017] Relaxation oscillators generally use current mode, exponential RC time mode or voltage mode structures. Frequency stability is usually affected by process, voltage and temperature (PVT) variations.

[0018] See also Figure 2 , Figure 2 The voltage waveform diagram of the comparison voltage of a conventional relaxation oscillator provided in the embodiment of the present application is shown. Figure 2 As shown, in a conventional relaxation oscillator, a comparison voltage is input to the non-inverting input terminal of the comparator, and the comparator compares the comparison voltage with a reference voltage. The comparison voltage rises in a ramp and when it reaches the reference voltage When the conventional relaxation oscillator resets the ramp voltage and generates the ramp voltage again. By repeating the charging and discharging operations, the conventional relaxation oscillator generates a clock pulse. The oscillation frequency of the conventional relaxation oscillator The specific calculation formula is: ; in, and They are the boost capacitor and the reference current used to generate the ramp voltage respectively.

[0019] However, if Figure 2As shown, due to the delay time τ of the comparator and the offset voltage , the ramp voltage will not The reset causes the oscillation frequency to change. Rewritten as: ; It can be seen that compensation technology to correct frequency changes is very necessary.

[0020] See also Figure 3 , Figure 3 The schematic block diagram of the first relaxation oscillator provided in the embodiment of the present application is shown. Figure 3 As shown, the relaxation oscillator 100 includes: a bias module 11 , a first generating module 12 , a first comparator 13 , a second generating module 14 , a second comparator 15 and a control logic module 16 .

[0021] The first generating module 12 is connected to the bias module 11 to obtain the reference voltage V provided by the bias module 11. REF The inverting input terminal of the first comparator 13 is connected to the first output terminal of the first generating module 12, and the non-inverting input terminal (VP1 terminal) of the first comparator 13 is connected to the second output terminal of the first generating module 12. The second generating module 14 is connected to the bias module 11 to obtain the reference voltage V provided by the bias module 11. REF The inverting input terminal (VN1 terminal) of the second comparator 15 is connected to the first output terminal of the second generating module 14, and the non-inverting input terminal of the second comparator 15 is connected to the second output terminal of the second generating module 14. The control logic module 16 is connected to the output terminal of the first comparator 13 and the output terminal of the second comparator 15 respectively, and the control logic module 16 is used to generate a clock pulse according to the first output signal (CLK_L) of the first comparator 13 and the second output signal (CLK_H) of the second comparator 15.

[0022] The relaxation oscillator 100 includes a first working mode and a second working mode. The first comparator 13 and the second comparator 15 alternately execute the first working mode and the second working mode. That is, when the first comparator 13 is in the first working mode, the second comparator 15 is in the second working mode. The first working mode is used to generate a reference voltage V REF -ΔV, the second working mode is used to adjust the reference voltage V REF -ΔV is supported by the first comparator 13 generating the first output signal (CLK_L) or the second comparator 15 generating the second output signal (CLK_H). Since both the first output signal (CLK_L) and the second output signal (CLK_H) are low level signals, the control logic module 16 needs to invert one of them when generating the clock pulse.

[0023] The first generating module 12 and the second generating module 14 alternately enter the first working mode and the second working mode. In the first working mode, the non-inverting input terminal (VP1 terminal or VP2 terminal) inputs the reference voltage V REF , the voltage at the inverting input terminal (VN1 terminal or VN2 terminal) of the first comparator 13 or the second comparator 15 rises from the preset starting voltage to the reference voltage V REF When the voltage at the inverting input terminal drops to the reference voltage V REF When the discharge signal is stopped, the voltage at the inverting input terminal is kept at the reference voltage V REF -ΔV. In the second working mode, the reference voltage V is input to the inverting input terminal. REF -ΔV, the non-inverting input terminal is grounded and reset, the first comparator 13 or the second comparator 15 is grounded and reset at the non-inverting input terminal until the voltage at the non-inverting input terminal reaches the reference voltage V REF The -ΔV interval corresponds to outputting the first output signal (CLK_L) or the second output signal (CLK_H).

[0024] It should be noted that, in the embodiment of the present application, the first generating module 12 and the second generating module 14 are the same. For the convenience of explanation, the specific explanation of the first generating module 12 is also applicable to the second generating module 14. Similarly, the first comparator 13 and the second comparator 15 are also the same. The specific explanation of the first comparator 13 is also applicable to the second comparator 15. For example, the explanation of the voltage change of the non-inverting input terminal (VP1) of the first comparator 13 is also applicable to the non-inverting input terminal (VP2) of the second comparator 15.

[0025] It should be noted that, in this embodiment, the VP1 terminal is the non-inverting input terminal of the first comparator, and the VN1 terminal is the inverting input terminal of the first comparator.

[0026] See also Figure 4 , Figure 4 FIG. 1 shows a waveform diagram of an input voltage of a first comparator provided in an embodiment of the present application. Figure 4 As shown, the VP1 terminal is connected to the reference voltage V REF , VN1 terminal is connected to the preset initial voltage V X , initial voltage V X Slightly less than the reference voltage V REF , since the reference voltage V REF Greater than the initial voltage V X , the first comparator 13 outputs a high level. At t 1 At time t, the first generating module 12 charges the VN1 terminal, so that the VN1 terminal is 2 When the reference voltage V REF, due to the delay, the first comparator 13 is 3 At the moment, the output is reversed and the discharge signal is output. The discharge signal is at a low level, so that the first generating module 12 discharges the VN1 terminal, and at t 4 The voltage at the VN1 terminal drops to the reference voltage V REF Due to the delay, the first comparator 13 is 5 The output inversion is completed at the moment, and the output discharge signal stops. The VN1 terminal is at t 5 When the reference voltage V REF -ΔV, and maintain it for a period of time, and maintain it in the second working mode. Through the above technical solution, a voltage lower than the reference voltage V REF The reference voltage V REF -ΔV, for the second working mode.

[0027] In the second working mode, the voltage at the VN1 terminal is maintained at the reference voltage V REF -ΔV. at t 6 At the moment, the VP1 terminal is grounded through the first generating module 12 to achieve voltage reset, that is, the voltage of the VP1 terminal drops to 0, and then the first generating module 12 charges the VP1 terminal, so that the voltage of the VP1 terminal rises in a ramp. 7 When the reference voltage V REF -ΔV, due to the delay, the first comparator 13 is 8 The output is inverted at [t 6 , t 8 ], the first comparator 13 outputs a low level, which is the first output signal (CLK_L).

[0028] V REF -ΔV can be set in a relatively low range, for example, VDD / 2≥V REF -ΔV≥VDD / 4, in the second working mode, the clock pulse generation time can be reduced, that is, shortened [t 6 , t 8 ] interval length, generating a shorter clock pulse, that is, increasing the oscillation frequency of the clock pulse without requiring a larger charging current (I REF ) ensures a higher oscillation frequency charge and discharge speed, thereby achieving a higher oscillation frequency without increasing power consumption It should be noted that V REF >V REF -ΔV≥VDD / 10 is within the protection scope of the embodiments of the present application.

[0029] See also Figure 5 , Figure 5The waveform diagram of the voltage at the VP1 terminal provided in the embodiment of the present application is shown. When the voltage at the VP1 terminal reaches V REF At this moment, VP1 is reset.

[0030] Through the above solution, the first comparator 13 corrects the delay voltage ΔV, because the reference voltage V REF -ΔV is generated in the previous first working mode. The time interval between the first working mode and the second working mode is very short. Therefore, the delay voltage ΔV is not easily affected by external factors and is suitable for a comparator to perform delay correction under different usage conditions. At the same time, the delay voltage ΔV changes with the process variation of the first comparator 13 and is suitable for different types of comparators to perform delay correction.

[0031] Through the above embodiments, the working principles of the first generating module 12 and the first comparator 13 in the first working mode and the second working mode are explained. It should be noted that the above process is also applicable to the second generating module 14 and the second comparator 15, which will not be repeated here.

[0032] In one embodiment, see Figure 6 , Figure 6 FIG. 1 shows a waveform diagram of an input voltage of a second comparator provided by an embodiment of the present application. Figure 6 As shown, in [t 1 , t 6 ], the second comparator 15 is in the second working mode, for generating a second output signal (CLK_H). Figure 6 t in 1 Time, t 6 Time and Figure 4 t in 1 Time, t 6 At corresponding moments, the first comparator 13 and the second comparator 15 enter the first working mode and the second working mode alternately.

[0033] See also Figure 7 , Figure 7 A waveform diagram of a clock pulse provided by an embodiment of the present application is shown. Figure 7 As shown, the control logic module 16 generates a clock pulse according to the first output signal (CLK_L) and the second output signal (CLK_H). It should be noted that: Figure 7 The second output signal (CLK_H) is inverted.

[0034] The embodiment of the present application provides a relaxation oscillator, including: a bias module, a first generating module, a first comparator, a second generating module, a second comparator and a control logic module, wherein the first generating module is connected to the bias module to obtain a reference voltage provided by the bias module; the inverting input terminal of the first comparator is connected to the first output terminal of the first generating module, and the non-inverting input terminal of the first comparator is connected to the second output terminal of the first generating module; the second generating module is connected to the bias module to obtain the reference voltage provided by the bias module; the inverting input terminal of the second comparator is connected to the first output terminal of the second generating module, and the non-inverting input terminal of the second comparator is connected to the second output terminal of the second generating module; the control logic module is respectively connected to the output terminal of the first comparator and the output terminal of the second comparator, and the control logic module is used to generate a reference voltage according to the first output terminal of the first comparator. The output signal and the second output signal of the second comparator generate a clock pulse; wherein, the first generating module and the second generating module alternately enter the first working mode and the second working mode, in the first working mode, a reference voltage is input to the non-inverting input terminal, and the first comparator or the second comparator outputs a discharge signal when the voltage at the inverting input terminal rises from a preset starting voltage to the reference voltage, so that the voltage at the inverting input terminal decreases, and when the voltage at the inverting input terminal decreases to the reference voltage, the discharge signal is stopped from being output, so that the voltage at the inverting input terminal is maintained at the reference voltage; in the second working mode, a reference voltage is input to the inverting input terminal, the non-inverting input terminal is grounded and reset, and the first comparator or the second comparator is grounded and reset at the non-inverting input terminal until the voltage at the non-inverting input terminal reaches the reference voltage, and the first output signal or the second output signal is output accordingly.Through the relaxation oscillator, the first generating module and the second generating module alternately enter the first working mode and the second working mode. In the first working mode, the first generating module or the second generating module provides a reference voltage to the non-inverting input terminal of the comparator, and increases the voltage of the inverting input terminal of the comparator from a preset starting voltage until the voltage of the inverting input terminal of the comparator reaches the reference voltage. Under the influence of the discharge signal of the comparator, the voltage of the inverting input terminal of the comparator is discharged and reduced until the voltage of the inverting input terminal of the comparator is reduced to the reference voltage, so that the comparator stops outputting the discharge signal. At the moment of starting the discharge, due to the delay, the part of the first actual voltage of the inverting input terminal of the comparator that is greater than the reference voltage is the delay. Delay voltage, at the moment of stopping discharge, the second actual voltage at the inverting input terminal of the comparator is the reference voltage minus the delay voltage, that is, the reference voltage. It can be seen that in the second working mode, the inverting input terminal of the comparator obtains a reference voltage less than the reference voltage. When the comparator generates a clock pulse according to the reference voltage, it starts level reversal when the non-inverting input terminal reaches the reference voltage, and completes the level reversal when the non-inverting input terminal reaches the reference voltage, thereby correcting the delay of the comparator. Since the delay voltage changes with the comparator, it is suitable for different types of comparators to perform delay correction, and is also suitable for a comparator to perform delay correction in different usage situations. At the same time, the reference voltage (V) of the embodiment of the present application. REF -ΔV) can be in a lower range, for example, VDD / 2 ≥ V REF -ΔV≥VDD / 4, in the second working mode, the clock pulse generation time can be reduced, that is, the oscillation frequency of the clock pulse is increased without requiring a larger charging current (I REF ) ensures a higher charging and discharging speed for the oscillation frequency, thereby achieving a higher oscillation frequency without increasing power consumption.

[0035] In order to more clearly introduce the technical solution of the present application, the technical solution of the present application will be introduced through specific embodiments below. It should be noted that the specific embodiments are used to expand the technical solution of the present application, but are not intended to limit the present application.

[0036] In some embodiments, see Figure 8 , Figure 8 The circuit diagram of the second first voltage generating unit provided in the embodiment of the present application is shown. Figure 8 As shown, the first generating module 12 includes: a first voltage generating unit 121 , a first clock generating unit 122 and a first multiplexing unit 123 , and the second generating module 14 includes: a second voltage generating unit 141 , a second clock generating unit 142 and a second multiplexing unit 143 .

[0037] The first terminal of the first voltage generating unit 121 is connected to the preset voltage source (VDD), the output terminal of the first voltage generating unit 121 is connected to the inverting input terminal of the first comparator 13, the output terminal of the first voltage generating unit 121 is the first output terminal of the first generating module 12, and the second terminal of the first voltage generating unit 121 is grounded. The first terminal of the first clock generating unit 122 is connected to the preset voltage source, and the second terminal of the first clock generating unit 122 is connected to the reference voltage V REF The output end of the first clock generating unit 122 is connected to the second output end of the first generating module 12, and the output end of the first clock generating unit 122 is connected to the first end of the first multiplexing unit 123. The second end of the first multiplexing unit 123 is connected to the reference voltage V REF , the output end of the first multiplexing unit 123 is connected to the non-inverting input end of the first comparator 13.

[0038] The input end of the second voltage generating unit 141 is connected to the preset voltage source, the output end of the second voltage generating unit 141 is connected to the inverting input end of the second comparator 15, the output end of the second voltage generating unit 141 is the first output end of the second generating module 14, the second end of the first voltage generating unit 121 is grounded, the first end of the second clock generating unit 142 is connected to the preset voltage source, and the second end of the second clock generating unit 142 is connected to the reference voltage V REF The output end of the first clock generating unit 122 is connected to the second output end of the first generating module 12, the output end of the second clock generating unit 142 is connected to the first end of the second multiplexing unit 143, and the second end of the second multiplexing unit 143 is connected to the reference voltage V REF The output end of the second multiplexing unit 143 is connected to the non-inverting input end of the second comparator 15 .

[0039] In some embodiments, in the first working mode, the first multiplexing unit 123 controls the reference voltage V REF The non-inverting input terminal of the first comparator 13 is connected. In the second working mode, the first multiplexing unit 123 controls the output terminal of the first clock generating unit 122 to be connected to the non-inverting input terminal of the first comparator 13, and the non-inverting input terminal is grounded and reset through the first multiplexing unit 123 and the first clock generating unit 122.

[0040] In some embodiments, see Fig. 9 , Fig. 9 The circuit diagram of a first voltage generating unit provided in an embodiment of the present application is shown. Fig. 9 As shown, the first voltage generating unit 121 includes: a first current source IS1, a second current source IS2, a first switch tube Q1, a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4 and a first capacitor C1.

[0041] The input end of the first current source IS1 is connected to a preset voltage source, the control end of the first current source IS1 is connected to the bias module 11, the output end of the first current source IS1 is respectively connected to the first end of the first switch tube Q1 and the first end of the second switch tube Q2, the first end of the first switch tube Q1 is respectively connected to the first end of the third switch tube Q3 and the controlled end of the third switch tube Q3, the second end of the third switch tube Q3 is grounded, the second end of the second switch tube Q2 is respectively connected to the first end of the fourth switch tube Q4, the first end of the first capacitor C1, and the inverting input end of the first comparator 13, the second end of the fourth switch tube Q4 is connected to the input end of the second current source IS2, the output end of the second current source IS2 and the second end of the first capacitor C1 are both grounded, and the controlled ends of the first switch tube Q1, the second switch tube Q2 and the fourth switch tube Q4 are all connected to the control logic module 16.

[0042] Exemplarily, the first switch tube Q1, the second switch tube Q2 and the fourth switch tube Q4 are all switch transistors, for example, triodes or MOS tubes. The third switch tube Q3 is a diode-connected transistor, and the third switch tube Q3 is used to generate the initial voltage V X The first current source IS1 and the second current source IS2 are connected to the bias circuit and are controlled to be turned on by the bias circuit. Figure 4 , Figure 7 and Fig. 9 , turn on the second switch tube Q2, charge the first capacitor C1 through the first current source IS1, so that the voltage across the first capacitor C1 rises, so that the VN1 terminal is 1 The voltage at the moment is V X Increase. At t 3 At time t, based on the discharge signal, the second switch tube Q2 is turned off and the fourth switch tube Q4 is turned on, so that the voltage across the first capacitor C1 drops and the voltage at the VN1 terminal is reduced. 5 At this moment, since the first comparator 13 stops outputting the discharge signal, the second switch tube Q2 and the fourth switch tube Q4 are both in the off state, and the voltage across the first capacitor C1 is the reference voltage V REF -ΔV.

[0043] It should be noted that the circuit of the second voltage generating unit 141 is the same as the circuit of the first voltage generating unit 121 , and will not be described in detail herein.

[0044] In some embodiments, see Fig.10 , Fig.10 The circuit diagram of a bias module and a first clock generating unit provided in an embodiment of the present application is shown. Fig.10 As shown, the bias module 11 includes: a fifth switch tube Q5, a sixth switch tube Q6, a first resistor R1 and a second resistor R2.

[0045] The fifth switch tube Q5 and the sixth switch tube Q6 form a current mirror, the first end of the fifth switch tube Q5 and the first end of the sixth switch tube Q6 are both connected to a preset voltage source, the controlled end of the fifth switch tube Q5 is respectively connected to the controlled end of the sixth switch tube Q6, the second end of the fifth switch tube Q5, and the first end of the first resistor R1, the second end of the first resistor R1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded.

[0046] In some embodiments, the temperature coefficient of the first resistor R1 and the temperature coefficient of the second resistor R2 are opposite, and the resistance value of the first resistor R1 and the second resistor R2 is the output current of the first current source IS1 and the reference voltage V REF Sure.

[0047] Exemplarily, the temperature dependence of ROSC is compensated by using a first resistor R1 and a second resistor R2 with opposite temperature coefficients. The specific calculation formula for the sum of the resistance values ​​of the first resistor R1 and the second resistor R2 is: ; In this way, after the preset voltage source (VDD), the specifications of the fifth switch tube Q5 and the specifications of the sixth switch tube Q6 are determined, the resistance values ​​of the first resistor R1 and the second resistor R2 are determined, and the voltage of the controlled end of the fifth switch tube Q5 and the voltage of the controlled end of the sixth switch tube Q6 are both the reference voltage V REF The current at the second end of the fifth switch tube Q5 and the current at the second end of the sixth switch tube Q6 are both I REF .

[0048] like Fig.10 As shown, the first clock generating unit 122 includes: a seventh switch tube Q7 and a second capacitor C2.

[0049] The first end of the seventh switch tube Q7 is respectively connected to the second end of the sixth switch tube Q6, the first end of the first capacitor C1, and the non-inverting input end of the first comparator 13, and the second end of the seventh switch tube Q7 and the second end of the second capacitor C2 are both grounded. The controlled end of the seventh switch tube Q7 is connected to the control logic module 16.

[0050] Exemplary, combined Figure 4 , Figure 7 and Fig.10 The first end of the seventh switch tube Q7 is connected to the VP1 end through the first multiplexing unit 123. 6 At the moment, the VP1 terminal is grounded and reset by turning off the sixth switch tube Q6 and turning on the seventh switch tube Q7. After the VP1 terminal is grounded and reset, the sixth switch tube Q6 is turned on to charge the second capacitor C2, so that the voltage of the VP1 terminal increases. 7 At this moment, the voltage at the VP1 terminal reaches the reference voltage VREF -ΔV, at time t8, the first comparator 13 starts to output a high level, and the voltage across the second capacitor C2 is the reference voltage V REF , turn off the sixth switch tube Q6 and the seventh switch tube Q7, and enter the next cycle. 1 , t 8 ], the first comparator 13 generates a first output signal (CLK_L).

[0051] In some embodiments, in the second working mode, the non-inverting input terminal is grounded and reset through the seventh switch tube Q7, the first capacitor C1 is charged and boosted by the output current of the sixth switch tube Q6, and the non-inverting input terminal reaches the reference voltage V through the first capacitor C1. REF -ΔV, the current required for charging and voltage boosting of the first capacitor C1 is half of the output current of the sixth switch tube Q6.

[0052] Exemplarily, by changing the current mirror ratio, the charging current of the second capacitor C2 can be set to I REF / 2, thus, the specific calculation formula of the oscillation frequency of the relaxation oscillator 100 in the embodiment of the present application is: ; in, is the oscillation frequency of the relaxation oscillator 100 in the embodiment of the present application, C 2 is the capacitance of the second capacitor.

[0053] The relaxation oscillator 100 proposed in the embodiment of the present application can compensate for the delay time of the comparator and is not affected by the offset voltage.

[0054] The oscillation frequency of the relaxation oscillator 100 in the embodiment of the present application is given by Rewrite as , The specific calculation formula is: ; in, is the capacitance of the second capacitor C2. The temperature coefficient of the second capacitor C2 is very small and can be eliminated by adjusting the temperature coefficient of the first resistor R1 and the temperature coefficient of the second resistor R2.

[0055] An embodiment of the present application provides a chip, and the chip includes a relaxation oscillator as described in any one of the embodiments of the present application.

[0056] An embodiment of the present application provides an electronic device, and the electronic device includes a relaxation oscillator as described in any one of the embodiments of the present application.

[0057] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A relaxation oscillator, characterized in that: The relaxation oscillator comprises: Bias module; A first generating module, wherein the first generating module is connected to the bias module to obtain a reference voltage provided by the bias module; A first comparator, wherein an inverting input terminal of the first comparator is connected to a first output terminal of the first generating module, and a non-inverting input terminal of the first comparator is connected to a second output terminal of the first generating module; A second generating module, wherein the second generating module is connected to the bias module to obtain a reference voltage provided by the bias module; A second comparator, wherein an inverting input terminal of the second comparator is connected to a first output terminal of the second generating module, and a non-inverting input terminal of the second comparator is connected to a second output terminal of the second generating module; a control logic module, the control logic module being connected to an output terminal of the first comparator and an output terminal of the second comparator respectively, and the control logic module being used to generate a clock pulse according to a first output signal of the first comparator and a second output signal of the second comparator; Among them, the first generating module and the second generating module alternately enter the first working mode and the second working mode. In the first working mode, the reference voltage is input to the non-inverting input terminal, and the first comparator or the second comparator outputs a discharge signal when the voltage at the inverting input terminal rises from a preset starting voltage to the reference voltage, so that the voltage at the inverting input terminal decreases, and stops outputting the discharge signal when the voltage at the inverting input terminal decreases to the reference voltage, so that the voltage at the inverting input terminal remains at the reference voltage; in the second working mode, the reference voltage is input to the inverting input terminal, and the non-inverting input terminal is grounded and reset, and the first comparator or the second comparator is grounded and reset at the non-inverting input terminal until the voltage at the non-inverting input terminal reaches the reference voltage, and the first output signal or the second output signal is correspondingly output.

2. The relaxation oscillator according to claim 1, characterized in that The first generating module comprises: a first voltage generating unit, a first clock generating unit and a first multiplexing unit, and the second generating module comprises: a second voltage generating unit, a second clock generating unit and a second multiplexing unit; The first end of the first voltage generating unit is connected to the preset voltage source, the output end of the first voltage generating unit is connected to the inverting input end of the first comparator, the output end of the first voltage generating unit is the first output end of the first generating module, the second end of the first voltage generating unit is grounded, the first end of the first clock generating unit is connected to the preset voltage source, the second end of the first clock generating unit is connected to the reference voltage, the output end of the first clock generating unit is the second output end of the first generating module, the output end of the first clock generating unit is connected to the first end of the first multiplexing unit, the second end of the first multiplexing unit is connected to the reference voltage, and the output end of the first multiplexing unit is connected to the non-inverting input end of the first comparator; The input end of the second voltage generating unit is connected to the preset voltage source, the output end of the second voltage generating unit is connected to the inverting input end of the second comparator, the output end of the second voltage generating unit is the first output end of the second generating module, the second end of the first voltage generating unit is grounded, the first end of the second clock generating unit is connected to the preset voltage source, the second end of the second clock generating unit is connected to the reference voltage, the output end of the first clock generating unit is the second output end of the first generating module, the output end of the second clock generating unit is connected to the first end of the second multiplexing unit, the second end of the second multiplexing unit is connected to the reference voltage, and the output end of the second multiplexing unit is connected to the non-inverting input end of the second comparator.

3. The relaxation oscillator according to claim 2, characterized in that: In the first working mode, the first multiplexing unit controls the reference voltage to be connected to the non-inverting input of the first comparator; in the second working mode, the first multiplexing unit controls the output of the first clock generating unit to be connected to the non-inverting input of the first comparator, and the non-inverting input is grounded and reset through the first multiplexing unit and the first clock generating unit.

4. The relaxation oscillator according to claim 2, characterized in that: The first voltage generating unit includes: a first current source, a second current source, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube and a first capacitor; The input end of the first current source is connected to the preset voltage source, the control end of the first current source is connected to the bias module, the output end of the first current source is respectively connected to the first end of the first switch tube and the first end of the second switch tube, the first end of the first switch tube is respectively connected to the first end of the third switch tube and the controlled end of the third switch tube, the second end of the third switch tube is grounded, the second end of the second switch tube is respectively connected to the first end of the fourth switch tube, the first end of the first capacitor, and the inverting input end of the first comparator, the second end of the fourth switch tube is connected to the input end of the second current source, the output end of the second current source and the second end of the first capacitor are both grounded, and the controlled end of the first switch tube, the controlled end of the second switch tube and the controlled end of the fourth switch tube are all connected to the control logic module.

5. The relaxation oscillator according to claim 4, characterized in that The bias module includes: a fifth switch tube, a sixth switch tube, a first resistor and a second resistor; The fifth switch tube and the sixth switch tube form a current mirror, the first end of the fifth switch tube and the first end of the sixth switch tube are both connected to the preset voltage source, the controlled end of the fifth switch tube is respectively connected to the controlled end of the sixth switch tube, the second end of the fifth switch tube, and the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is grounded.

6. The relaxation oscillator according to claim 5, characterized in that The temperature coefficient of the first resistor and the temperature coefficient of the second resistor are opposite, and the sum of the resistance values ​​of the first resistor and the second resistor is determined according to the output current of the first current source and the reference voltage.

7. The relaxation oscillator according to claim 5, characterized in that The first clock generating unit includes: a seventh switch tube and a second capacitor. The first end of the seventh switch tube is respectively connected to the second end of the sixth switch tube, the first end of the first capacitor, and the non-inverting input end of the first comparator, and the second end of the seventh switch tube and the second end of the second capacitor are both grounded.

8. The relaxation oscillator according to claim 7, characterized in that In the second working mode, the non-inverting input terminal is grounded and reset through the seventh switch tube, the first capacitor is charged and boosted by the output current of the sixth switch tube, the non-inverting input terminal reaches the reference voltage through the first capacitor, and the current required for charging and boosting the first capacitor is half of the output current of the sixth switch tube.

9. A chip, characterized in that: The chip comprises the relaxation oscillator according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device comprises the relaxation oscillator according to any one of claims 1 to 8.

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