Oscillator circuit, corresponding radar sensor, vehicle, and operating method

Abstract

An oscillator circuit, a corresponding radar sensor, a vehicle, and an operating method are disclosed. An oscillator includes a tunable resonant circuit having an inductor and a variable capacitor coupled between a first node and a second node, and a set of capacitors selectively coupled between the first node and the second node. An input control node receiving an input control signal is coupled to the variable capacitor and the set of capacitors. The tunable resonant circuit is tunable based on the input control signal. A biasing circuit biases the tunable resonant circuit to generate a variable frequency output signal between the first node and the second node. A voltage divider generates a set of different voltage thresholds, and a set of comparator circuits having hysteresis compares the input control signal with the set of different voltage thresholds to generate a set of control signals. The capacitors in the set of capacitors are selectively coupled between the first node and the second node according to the control signals in the set of control signals.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to Italian Application No. 102020000019786, filed on Aug. 7, 2020, the content of which is incorporated herein by reference in its entirety to the maximum extent permitted by law. Technical Field

[0003] This description relates to a phase-locked loop (PLL) circuit. For example, embodiments as described herein can be used in radar detection systems, such as those increasingly used in automotive advanced driver assistance systems (ADAS). Background Art

[0004] Short-range radar sensors and / or long-range radar sensors can be placed around a vehicle (e.g., an automobile) to detect objects near and / or around the vehicle. Radar sensor data can be processed (e.g., by a processing unit in the vehicle) to prevent accidents, prepare for vehicle accidents, or take actions to reduce the severity of an accident. By way of example only, possible applications of advanced driver assistance systems are adaptive cruise control, pre-crash safety systems, blind spot detection, lane change assistance, etc.

[0005] Conventional (e.g., standard) specifications for the operating frequency bands of short-range radar sensors and long-range radar sensors are 77 GHz to 81 GHz and 76 GHz to 77 GHz, respectively. These frequency bands correspond to wavelengths on the order of a few millimeters (mm, 1 mm = 10 -3 m).

[0006] A frequency-modulated continuous-wave (FMCW) radar system can be used for such millimeter-wave radar applications in the automotive industry. The operating principle of an FMCW radar is as Figure 1 shown, which is an example diagram of the possible time-frequency relationship of radar signals in an FMCW radar system.

[0007] As Figure 1 shown, an FMCW radar system can transmit (e.g., periodically) a transmit signal TX (as shown by the solid line in Figure 1 ), also referred to as a "chirp", whose frequency (e.g., linearly) sweeps over a certain time interval T m (e.g., whose duration T m is in the range of 10 μs to 40 μs, 1 μs = 10 -6 s) over a frequency range F. For example, for short-range radar, the frequency range F can be a 4-GHz range between 77 GHz and 81 GHz, or for long-range radar, the frequency range F can be a 1-GHz range between 76 GHz and 77 GHz.

[0008] The FMCW radar system can then receive the corresponding echo signal RX generated by the reflection of the transmitted signal TX at the target object (illustrated by the dashed line in Figure 1 ).

[0009] As Figure 1 shown, when the frequency of the transmitted signal TX equals the reference value f1, the FMCW radar system can detect the first time instant t1, where f1 is included in the frequency range F. When the frequency of the echo signal RX equals the reference value f1, the FMCW radar system can then detect the second time instant t2 and detect the frequency f2 of the transmitted signal TX at the second time instant t2. Thus, the FMCW radar system can calculate the frequency value f R as the difference between the frequency f2 and the reference frequency f1.

[0010] The time interval t between the first time instant t1 and the second time instant t2 R is a function of the distance R between the radar sensor and the target object (e.g., proportional to R), according to the following equation, where c is the propagation speed of the radar signals TX and RX:

[0011]

[0012] As Figure 1 shown, the slope of the "chirp" of the radar signal TX can be calculated according to the following equation:

[0013]

[0014] Thus, the distance R between the radar sensor and the target object can be calculated as follows:

[0015]

[0016] A PLL circuit including a voltage-controlled oscillator (VCO) can be used in the FMCW radar detection system to generate a variable frequency signal (e.g., a "chirp" signal).

[0017] It should be noted that the wide tuning range of the voltage-controlled oscillator in the radar sensor can be related to meeting the FMCW standard specifications, e.g., especially for short-range radar sensors with a 4 GHz sweep range.

[0018] On the one hand, as long as there is a proportional relationship between the ranging accuracy and the signal sweep bandwidth F, a larger frequency range F is beneficial to improving the resolution of the FMCW radar system.

[0019] On the other hand, the resolution of the FMCW radar system is limited by phase noise.

[0020] It should be noted that since the varactor diode used in a voltage-controlled oscillator may have a low quality factor (Q) at such high frequencies (e.g., between 76 GHz and 81 GHz), it may be difficult to achieve a wide frequency tuning range and low phase noise in the voltage-controlled oscillator. Using a large-area varactor diode may help meet the requirements of the tuning range, but may result in high phase noise and high power consumption.

[0021] Therefore, an improved tuning strategy for the voltage-controlled oscillator in the PLL circuit may be desirable. Summary of the Invention

[0022] One or more embodiments may relate to a circuit.

[0023] One or more embodiments may relate to a corresponding radar sensor.

[0024] One or more embodiments may relate to a corresponding vehicle.

[0025] One or more embodiments may relate to a corresponding method of operating a circuit.

[0026] According to one or more embodiments, a circuit (e.g., a voltage-controlled oscillator) is provided that may include a tunable resonant circuit having a first node and a second node. The tunable resonant circuit may include an inductor coupled between the first node and the second node, a variable capacitor coupled between the first node and the second node, and a set of capacitors selectively coupled between the first node and the second node. The circuit may include an input control node coupled to the variable capacitor and the set of capacitors. The input control node is configured to receive an input control signal. The tunable resonant circuit may be tunable according to the input control signal. The circuit may include a bias circuit coupled to the tunable resonant circuit and configured to bias the tunable resonant circuit to generate a variable frequency output signal between the first node and the second node.

[0027] According to one or more embodiments, the circuit may further include a voltage divider network configured to generate a set of different voltage thresholds, and a comparator circuit with hysteresis configured to compare the input control signal with the set of different voltage thresholds to generate a corresponding set of control signals. The capacitors in the set of capacitors may be selectively coupled between the first node and the second node according to the corresponding control signals in the set of control signals.

[0028] Thus, one or more embodiments may facilitate fast and continuous coarse tuning of an oscillator circuit applicable to automotive radar sensors, while performing fine tuning using a small varactor diode. Using a small varactor diode can reduce power consumption and phase noise. Brief Description of the Drawings

[0029] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, in which:

[0030] The foregoing Figure 1 is an example diagram of a possible time-frequency relationship of a radar signal in a frequency-modulated continuous-wave (FMCW) radar system,

[0031] Figure 2 is an exemplary circuit diagram of a PLL circuit that may be used in a radar sensor,

[0032] Figure 3 is an exemplary circuit diagram of a voltage-controlled oscillator circuit that may be used in a PLL circuit,

[0033] Figure 4 and Figure 5 is an example diagram of a possible tuning strategy for a voltage-controlled oscillator circuit,

[0034] Figure 6 and Figure 7 is an exemplary circuit diagram of a voltage-controlled oscillator circuit according to one or more embodiments of the present description,

[0035] Figure 8 is a circuit diagram illustrating possible implementation details of one or more embodiments of the present description,

[0036] Figure 9 is an exemplary diagram of a PLL tuning strategy according to one or more embodiments of the present description, and

[0037] Figure 10 is an exemplary circuit diagram of a radar architecture in a vehicle according to one or more embodiments of the present description. Detailed Description

[0038] In the following description, one or more specific details are shown, aimed at providing an in-depth understanding of examples of embodiments of the present description. Embodiments may be obtained without one or more specific details, or by using other methods, components, materials, etc. In other cases, certain structures, materials, or operations are not described in detail so as not to obscure certain aspects of the embodiments.

[0039] References to "an embodiment" or "one embodiment" in the context of the present description are intended to indicate that a particular configuration, structure, or characteristic described with respect to that embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may occur in one or more points of the present description do not necessarily refer to the same embodiment. Moreover, in one or more embodiments, a particular conformation, structure, or characteristic may be combined in any suitable manner.

[0040] The headings / references used in this document are provided for convenience only and thus do not define the scope of protection or the scope of embodiments.

[0041] For simplicity, in the figures attached hereto, similar components or elements are denoted by similar references / numbers. For the sake of brevity, the corresponding descriptions of each figure will not be repeated.

[0042] As an introduction to the detailed description of the exemplary embodiments, reference may first be made to Figure 2 .

[0043] Figure 2 is an exemplary circuit diagram of a phase-locked loop (PLL) circuit 20 that may be used in a radar sensor. The PLL circuit 20 may include: an input node 200 configured to receive an input reference signal f ref ; a phase-frequency detector (PFD) circuit 202 having a first input configured to receive the input reference signal f ref ; a charge pump (CP) circuit 204 coupled to the output of the phase-frequency detector circuit 202; a low-pass filter circuit 206 coupled to the output of the charge pump circuit 204 and configured to generate a control signal V at a corresponding output node 208 C ; a voltage-controlled oscillator (VCO) circuit 210 coupled to node 208 and controlled by the control signal V C , the voltage-controlled oscillator circuit 210 being configured to generate an output signal f at an output node 212 O ; and a feedback loop configured to provide the output signal f at a second input of the phase-frequency detector circuit 202 O .

[0044] The feedback loop optionally includes a frequency divider circuit 214.

[0045] As Figure 2 shown, the voltage-controlled oscillator circuit 210 may include an active core 216 (e.g., a biasing circuit) coupled to an LC resonance circuit 218.

[0046] The active core 216 may include a pair of transistors M1 and M2, e.g., metal-oxide-semiconductor (MOS) field-effect transistors. As Figure 2 shown, the first transistor M1 may have a source terminal coupled to ground GND and a drain terminal coupled to a first terminal 219a of the LC resonance circuit 218, and the second transistor M2 may have a source terminal coupled to ground GND and a drain terminal coupled to a second terminal 219b of the LC resonance circuit 218. The control (gate) terminal of the first transistor M1 may be coupled to the drain terminal of the second transistor M2, and the control (gate) terminal of the second transistor M2 may be coupled to the drain terminal of the first transistor M1.

[0047] As Figure 2 shown, the LC resonant circuit 218 may include an inductive component and a capacitive component coupled between a first terminal 219a and a second terminal 219b of the LC resonant circuit 218.

[0048] As illustrated herein, the inductive component may include an inductor L, and the capacitive component may include one or more (e.g., a pair of) varactors or variable capacitors C coupled in series V , where a control signal V C is applied at a node 224 intermediate the two varactors C V .

[0049] As Figure 2 shown, the LC resonant circuit 218 may further include a capacitor array (or bank) 220 coupled in parallel to the varactor C V . The capacitor array 220 may be configured to receive a set of configuration signals from an analog-to-digital converter circuit 222. The analog-to-digital converter 222 may be coupled to the node 208 to receive the control signal V C . For example, the analog-to-digital converter 222 may be an N-bit ADC, and the capacitor array 220 may include 2 N unit capacitors.

[0050] The configuration signals (e.g., an N-bit binary signal generated by the ADC 222) may be used to activate and deactivate a set of switches respectively coupled to the capacitors in the capacitor array 220, thereby variably changing the total capacitance of the capacitive component of the LC resonant circuit 218 to tune the output frequency of the voltage-controlled oscillator 210.

[0051] In the PLL circuit 20 as Figure 2 shown, the analog-to-digital converter 222 and the capacitor array 220 may be used to perform coarse tuning of the LC resonant circuit 218, and the varactor C V may be used to perform fine tuning of the LC resonant circuit 218. This tuning strategy may advantageously avoid using large varactors that may result in high power consumption and high phase noise.

[0052] As Figure 3 illustrated, the figure is a circuit block diagram exemplifying possible implementation details for the voltage-controlled oscillator circuit 210 in the PLL circuit 20, and the analog-to-digital converter 222 may include a successive approximation analog-to-digital converter (SA-ADC).

[0053] The successive approximation analog-to-digital converter may include a comparator circuit 300 having a first (e.g., non-inverting) input coupled to the node 208 to receive the control signal V C and a second input coupled to the node 302 to receive a reference signal VR second (e.g., inverting) input. For example, the reference signal V R may be equal to the supply voltage V of the PLL circuit 20 CC divided by two (i.e., V R = V CC / 2). The successive approximation analog-to-digital converter may further include a successive approximation register (SAR) 304 configured to receive the output signal from the comparator circuit 300 and provide an N-bit configuration signal to the capacitor array 220.

[0054] As Figure 3 shown, a first switch S V may be provided in the propagation path between the configuration node of the LC resonant circuit 218 (here, the node 224 in the middle of the varactor diode C FT ) and the first input of the comparator circuit 300 (i.e., the node 208), and a second switch S CT may be provided in the propagation path between the configuration node of the LC resonant circuit 218 and the second input of the comparator circuit 300 (i.e., the node 302).

[0055] Thus, as Figure 3 exemplified, the tuning of the voltage-controlled oscillator circuit 210 may be performed in two steps to avoid instability.

[0056] In the first tuning step, the first switch S FT is opened and the second switch S CT is closed. The varactor diode C V provides a constant capacitance value (e.g., an average value), and the ADC converter 222 performs coarse frequency tuning by enabling a selected subset of the capacitors in the capacitor array 220.

[0057] In the second tuning step, the first switch S FT is closed and the second switch S CT is opened. The varactor diode C V is connected to the control voltage V C and changes its capacitance value to provide fine frequency tuning.

[0058] It should be noted that two different tuning strategies may be implemented in the voltage-controlled oscillator circuit 210 including a successive approximation ADC, as Figure 3 shown.

[0059] According to the first tuning strategy as Figure 4 shown, the coarse frequency tuning step sets the output frequency of the PLL circuit to the minimum frequency f min and the maximum frequency f maxThe average value f0* between, while the varactor diode C in the LC resonant circuit 218 V remains at its average value. After the coarse frequency tuning step, the varactor diode CV is used to provide the entire frequency change from f min to f max . In other words, the fine tuning step is responsible for covering the entire frequency range F.

[0060] The advantage of such a first tuning strategy is that the coarse tuning can be performed only once (e.g., when the radar detection system is started), thus facilitating the continuous frequency tuning required for automotive radar sensors. The disadvantage of this first tuning strategy is that it may involve a large varactor diode C V , which may result in high power consumption and high phase noise.

[0061] According to the second tuning strategy as Figure 5 shown, the coarse frequency tuning step sets the output frequency of the PLL circuit to the average value f′0* between the lower frequency f′ min and the higher frequency f′ max defining a sub-range (e.g., 77 GHz to 81 GHz, or 76 GHz to 77 GHz) of the entire sweep range F, while the varactor diode C in the LC resonant circuit 218 V remains at its average value. After the coarse frequency tuning step, the varactor diode is used to provide the (smaller) frequency change from f′ min to f′ max . In other words, the fine tuning step is only responsible for covering a sub-range of the entire frequency range F.

[0062] The advantage of this second tuning strategy is that it can involve a small varactor diode CV, resulting in low power consumption and low phase noise. The disadvantage of this second tuning strategy is that it may involve performing the coarse tuning step multiple times during each frequency scan, resulting in a delay time τ D in the PLL circuit response, and this delay time τ D is equal to N times the settling time τ S of the PLL circuit (i.e., τ D = N·τ S ). Additionally, due to the large delay time and the two-step frequency tuning operation, this second tuning strategy may not be suitable for automotive radar applications.

[0063] The following documents (all incorporated by reference) are examples of possible strategies for tuning the PLL circuit 20 using a successive approximation analog-to-digital converter, as Figure 3Shown: Shi et al., "A dual loop dual VCO CMOS PLL using a novel coarse tuning technique for DTV", 9th International Conference on Solid State and Integrated Circuit Technology, Beijing, 2008, pp. 1597-1600, doi:10.1109 / ICSICT.2008.4734882; and Hou et al., "A 20GHz PLL for 40Gbps SerDes application with 4bit switch-capacitor adaptive controller", IEEE International Conference on Electron Devices and Solid-State Circuits, Chengdu, 2014, pp. 1-2, doi:10.1109 / EDSSC.2014.7061152.

[0064] In both cases, these solutions may not be satisfactory because performing coarse tuning requires additional time and a clock signal is needed (i.e., both solutions are clock-based).

[0065] Accordingly, one or more embodiments may be directed to providing an improved tuning system for a PLL circuit for use, for example, in automotive radar applications.

[0066] Figure 6 is an exemplary circuit diagram of a voltage-controlled oscillator circuit 610 according to one or more embodiments for use in a PLL circuit architecture as Figure 2 illustrated.

[0067] As Figure 6 shown, the voltage-controlled oscillator circuit 610 may include an active core 616 coupled to an LC resonance circuit 618.

[0068] The active core 616 may include a pair of transistors M1 and M2, e.g., MOS field effect transistors. As Figure 6 shown, the first transistor M1 may have a source terminal coupled to ground GND and a drain terminal coupled to a first terminal 619a of the LC resonance circuit 618, and the second transistor M2 may have a source terminal coupled to ground GND and a drain terminal coupled to a second terminal 619B of the LC resonance circuit 618. The control (gate) terminal of the first transistor M1 may be coupled to the drain terminal of the second transistor M2, and the control (gate) terminal of the second transistor M2 may be coupled to the drain terminal of the first transistor M1.

[0069] As shown Figure 6 in FIG. 2, the LC resonant circuit 618 may include an inductance component and a capacitance component coupled between a first terminal 619a and a second terminal 619b of the LC resonant circuit 618.

[0070] As illustrated herein, the inductance component may include an inductor L, and the capacitance component may include one or more (e.g., a pair of) varactors or variable capacitors C coupled in series V , where a control signal VC received from node 608 is set at a node 624 intermediate the two varactors C V .

[0071] As shown Figure 6 in FIG. 3, the LC resonant circuit 618 may further include a capacitor array 620 coupled in parallel to the varactor C V . The capacitor array 620 may be configured to receive a set of configuration signals from an analog-to-digital converter 622 coupled to node 608 to receive a control signal V C . For example, the analog-to-digital converter 622 may be an N-bit ADC, and the capacitor array 620 may include 2 N unit capacitors.

[0072] By way of non-limiting example only, one or more embodiments may rely on a thermometer ADC converter driving 11 unit capacitors.

[0073] The configuration signals may be used to activate and deactivate a set of switches respectively coupled to the capacitors in the capacitor array 620, such that the total capacitance of the capacitance component of the LC resonant circuit 618 may be varied to tune the voltage-controlled oscillator 610.

[0074] In the voltage-controlled oscillator circuit 610 as shown Figure 6 in FIG. 4, the analog-to-digital converter 622 and the capacitor array 620 may be used to perform coarse tuning of the LC resonant circuit 618, and the varactor C V may be used to perform fine tuning of the LC resonant circuit 618.

[0075] In one or more embodiments, the analog-to-digital converter 622 may include a flash-type ADC architecture. Different from a conventional flash ADC, the comparators in the flash ADC 622 may be comparators with hysteresis.

[0076] The hysteretic behavior of the comparators in the flash ADC 622 may advantageously provide stable behavior of a PLL circuit including Figure 6 the VCO circuit 610 as shown in FIG. 5, without requiring a two-step tuning operation. As shown Figure 6 in FIG. 6, one or more embodiments may thus not involve such as Figure 3The switch S shown FT and S CT for use of the switches

[0077] As Figure 7 illustrated Figure 7 is a schematic (e.g., simplified) circuit diagram of a voltage - controlled oscillator 610 according to one or more embodiments, and the operating frequency of the voltage - controlled oscillator 610 can be set by an LC resonant circuit 618 (also referred to as "LC tank" in this description).

[0078] In one or more embodiments, the LC resonant circuit 618 can include an inductor component L with a high quality factor Q (illustrated here by two inductors L / 2 having an intermediate node 624' coupled to node 608) and a capacitor component. The capacitor component of the LC resonant circuit 618 can include one or more (e.g., a pair of) varactor diodes 2C VAR (e.g., small and / or application - optimized varactor diodes) and a capacitor array (capacitor bank) 620 with a high quality factor Q. The capacitors in the capacitor array 620 can be selectively coupled between a first terminal 619a and a second terminal 619b of the LC resonant circuit 618 through corresponding switches.

[0079] As Figure 7 shown, the flash - type ADC 622 can be configured to sense the control voltage V at node 608 C , and enable a plurality of switched capacitors in the array 620 according to the control voltage V C .

[0080] The enabled capacitors in the capacitor array 620 can thus produce a coarse tuning of the frequency of the signal generated by the voltage - controlled oscillator 610. The varactor diodes 2C VAR can be used to achieve a fine tuning of the frequency.

[0081] Figure 8 is an exemplary circuit diagram of possible implementation details of an unconventional flash - type ADC (flash ADC) 622 and a switched - capacitor array 620 according to one or more embodiments.

[0082] As Figure 8 shown, the flash - type ADC 622 can include a voltage divider or "voltage ladder" (e.g., a resistive voltage divider including a plurality of resistors R, e.g., N + 1 resistors having the same resistance value), which is configured to generate N different voltage levels (e.g., voltage thresholds V TH1 、V TH2 、…、V THN) Such voltage levels can be equidistant, for example, between a reference voltage such as a ground voltage (e.g., 0V) and a supply voltage V DD therebetween.

[0083] The N voltage levels generated by the voltage divider can be provided at a second input (e.g., an inverting input) of a corresponding number N of comparators 8001, 8002, …, 800 N (collectively also denoted by reference numeral 800 in this description). The comparator 800 with hysteresis can receive at its first input (e.g., a non-inverting input) a control voltage V from node 608 C . The comparator 800 with hysteresis can be a high-speed, low-power comparator suitable for implementing flash ADC conversion. Thus, the comparators 800 with hysteresis can collectively generate an N-bit output signal S1, S2, …, S N , which is a thermometer code or thermometer representation of the control signal V C .

[0084] In one or more embodiments, the hysteresis width of the comparator 800 can be selected to facilitate varactor diode C V compensation for frequency variations caused by the enabling or disabling of the unit capacitors in the switched capacitor array 620.

[0085] As Figure 8 illustrated, the switched capacitor array 620 can include N high-Q capacitors selectively coupled between a first terminal 619a and a second terminal 619b of the LC resonant circuit 618 (e.g., in parallel with varactor diode 2C VAR ). As illustrated herein, each capacitor can include a pair of capacitors 2C connected in series, and a corresponding switch is disposed between the capacitors 2C.

[0086] Each of the N switches in the capacitor array 620 can be controlled (e.g., opened and closed) according to the output signal of the corresponding comparator 800 with hysteresis (i.e., according to the bits S1, S2, …, S of the thermometer code generated by the comparator 800 N ). Thus, depending on the control voltage V C , a subset of the capacitors 2C in the array 620 can be coupled to the LC resonant circuit 618 (e.g., from no capacitors coupled to all capacitors coupled) to effect coarse frequency tuning.

[0087] Thus, one or more embodiments can rely on coarse quantization tuning and fine continuous tuning of the frequency of the signal generated by the voltage-controlled oscillator 610.

[0088] For example, the coarse frequency tuning can be quantified as M·Δf, where M is an integer value ranging from 0 to N-1, N is the number of intervals into which the operating frequency range (e.g., for a long-range radar sensor, from 76 GHz to 77 GHz, or for a short-range radar sensor, from 77 GHz to 81 GHz) is divided, and Δf is the resulting frequency step size.

[0089] The number M of the N steps can be selected (e.g., instantaneously) by the flash ADC 622. The coarse tuning group including the array 620 of high-Q switched capacitors 2C helps to change the output frequency of the voltage-controlled oscillator 610 in a quantified manner. The flash ADC 622 can enable multiple switched capacitors 2C proportional to the control voltage V C of the PLL circuit.

[0090] The small varactor diodes 2C VAR help with the fine tuning of the output frequency of the voltage-controlled oscillator 610 in order to adjust the operating frequency within the range defined by the coarse tuning, as shown in the following equation:

[0091] f OP = N DIV ·f REF = f MIN + M·Δf + V C ·K VCO

[0092] where, f OP is the output frequency of the voltage-controlled oscillator 610, N DIV is the (optional) division factor of the feedback loop of the PLL circuit (see, e.g., Figure 2 block 214 in), f REF is the frequency of the reference signal f Figure 2 at the input of the PLL circuit (see, e.g., REF node 200 in), f MIN is the fundamental frequency generated by the voltage-controlled oscillator 610, M is the number of capacitors enabled in the array 620 according to the control signal V C , Δf is the coarse tuning frequency step size, K VCO is the tuning proportionality factor of the varactor diodes 2C VAR in the voltage-controlled oscillator 610.

[0093] Figure 9 is an example of the coarse quantization tuning frequency CTF defined by the switched capacitor array 620 and the fine continuous tuning range FTR managed via the varactor diodes 2C VAR .

[0094] Thus, in one or more embodiments, due to the advanced tuning system, rapid selection of the operating frequency can be achieved. The lock time of the PLL circuit can be set by the fine-tuning loop as long as the flash ADC 622 can operate almost instantaneously. Each flash conversion enables specific switched capacitors of the capacitor array 620 through high-speed comparators 800 having different switching threshold voltages.

[0095] It should be noted that throughout this specification, the reference to "flash ADC" collectively designates a voltage divider and comparator 800 that generates a thermometer code indicative of the value of V C Regardless of the use of the name "flash ADC", one or more embodiments may or may not include an encoder circuit configured to convert the thermometer code to a binary signal, depending on whether such conversion may be required or not in different embodiments.

[0096] It should be noted that without departing from the scope of the present disclosure, the inductive and capacitive components in the LC resonant circuit 618 can be arranged according to various arrangements additionally known to those skilled in the art (e.g., comparing the different arrangements illustrated in Figure 6 and Figure 7 For example, one or more embodiments may include one of a Hartley oscillator, a Colpitts oscillator, and a Clapp oscillator.

[0097] Thus, one or more embodiments may provide one or more of the following advantages: rapid coarse tuning suitable for use in automotive radar sensors as long as continuous tuning operation is maintained (no two-step tuning procedure is required); small varactors for fine tuning, which result in low power consumption and low phase noise as long as the coarse tuning results in an output frequency close to the final output frequency; the possibility of eliminating the clock signal; and the possibility of implementing a PLL circuit according to one or more embodiments integrated in 28nm FD-SOI CMOS technology.

[0098] As Figure 10 illustrated, one or more embodiments can be applied to vehicle V. Vehicle V may include a power supply system 1000, a control unit 1002 (e.g., a microcontroller unit, MCU), and a radar sensor 1004.

[0099] The radar sensor 1004 may include a PLL circuit 1006, a transmitter circuit 1008, a receiver circuit 1010, a transmitter antenna 1012, and a receiver antenna 1014.

[0100] The power supply system 1000 can supply a power supply voltage (e.g., equal to 1V or 3.3V) to the radar sensor 1004 and supply a power supply voltage (e.g., equal to 3.3V or 5V) to the control unit 1002.

[0101] The control unit 1002 can provide an input reference signal f ref to control the PLL circuit 1006. The PLL circuit 1006 can provide a variable frequency signal f O to drive the transmitter circuit 1008 (e.g., according to the FMCW driving scheme). The transmitter circuit can bias the transmitter antenna 1012 accordingly to transmit the transmission signal TX.

[0102] The receiver antenna 1014 can receive the echo signal RX and provide it to the receiver circuit 1010, and the receiver circuit 1010 processes the information about the transmitted and received signals to provide information about the distance of the target object.

[0103] As illustrated herein, a circuit such as a voltage controlled oscillator (e.g., 610) can include: a tunable resonant circuit (e.g., 618) having a first node (e.g., 619a) and a second node (e.g., 619b), and including an inductor (e.g., L; L / 2) coupled between the first node and the second node, a variable capacitor (e.g., C V ; 2C VAR ) coupled between the first node and the second node, and a capacitor set (e.g., 620, 2C) selectively coupled between the first node and the second node; an input control node (e.g., 608), coupled to the variable capacitor and the capacitor set, the input control node being configured to receive an input control signal (e.g., V C ), wherein the tunable resonant circuit is tunable according to the input control signal; and a biasing circuit (e.g., 616), coupled to the tunable resonant circuit and configured to bias the tunable resonant circuit to generate a variable frequency output signal (e.g., f O ) between the first node and the second node.

[0104] As illustrated herein, the circuit can further include: a voltage divider network (e.g., V DD ), R), configured to generate a set of different voltage thresholds (e.g., V TH1 、V TH2 、…、V THN ); and a set of comparator circuits with hysteresis (e.g., 8001, 8002, …, 800 N ), configured to compare the input control signal with the set of different voltage thresholds to generate a corresponding set of control signals (e.g., S1, S2, …, SN )。

[0105] As illustrated herein, the capacitances in the capacitance bank can be selectively coupled between the first node and the second node according to corresponding control signals in the control signal bank.

[0106] As illustrated herein, the capacitances in the capacitance bank can be configured to be selectively coupled between the first node and the second node in response to corresponding voltage thresholds in a concentration of corresponding control signals in the control signal bank indicating that the input control signal is higher than different voltage thresholds.

[0107] As illustrated herein, a variable capacitance can include a pair of variable capacitances (e.g., C V ) arranged in series between the first node and the second node. Optionally, the pair of variable capacitors can have a configuration node (e.g., 624) arranged therebetween to receive the input control signal.

[0108] As illustrated herein, an inductor can include a pair of inductors (e.g., L / 2) arranged in series between the first node and the second node. Optionally, the pair of inductors can have a configuration node (e.g., 624') arranged between the pair of inductors to receive the input control signal.

[0109] As illustrated herein, a voltage divider network can be configured to generate equally spaced voltage thresholds.

[0110] As illustrated herein, the circuit can further include: an input node (e.g., 200) configured to receive an input reference signal (e.g., f ref );a phase-frequency detector circuit (e.g., 202) configured to receive the input reference signal and the variable frequency output signal;a charge pump circuit (e.g., 204) configured to receive an output signal from the phase-frequency detector circuit;and a low-pass filter (e.g., 206) configured to receive an output signal from the charge pump circuit and generate the input control signal.

[0111] As illustrated herein, a radar sensor (e.g., 1004) can include a circuit (e.g., 1006) according to one or more embodiments, and a transmitter circuit (e.g., 1008) coupled to an antenna (e.g., 1012). The circuit in the radar sensor can be configured to receive the input reference signal from a microcontroller unit (e.g., 1002) and provide the variable frequency output signal to the transmitter circuit.

[0112] As illustrated herein, a vehicle (e.g., V) may include a radar sensor according to one or more embodiments.

[0113] As illustrated herein, a method of operating a circuit according to one or more embodiments may include: receiving an input control signal at the input control node coupled to the variable capacitor and the capacitor bank, and tuning the tunable resonant circuit according to the input control signal; generating a set of different voltage thresholds; comparing the input control signal with the set of different voltage thresholds to generate a corresponding set of control signals; selectively coupling capacitors in the capacitor bank between the first node and the second node according to the corresponding control signals in the set of control signals; and biasing the tunable resonant circuit to generate a variable frequency output signal between the first node and the second node.

[0114] As illustrated herein, the comparing may include performing a hysteresis comparison of the input control signal with the set of different voltage thresholds.

[0115] Without prejudice to the basic principles, details and embodiments may be changed, even significantly, only by way of example with respect to what is described, without departing from the scope of protection.

[0116] The scope of protection is determined by the appended claims.

Claims

1. A circuit, comprising: A tunable resonant circuit, comprising: A first node; A second node; An inductor coupled between the first node and the second node; wherein the inductor comprises an inductor pair that is serially arranged between the first node and the second node, and the inductor pair has a configuration node that is arranged between the inductor pair to receive an input control signal; A variable capacitor coupled between the first node and the second node; A capacitor set capable of being selectively coupled between the first node and the second node; and An input control node configured to receive the input control signal, wherein the tunable resonant circuit is tunable according to the input control signal; A bias circuit coupled to the tunable resonant circuit and configured to bias the tunable resonant circuit to generate a variable-frequency output signal between the first node and the second node; A voltage divider network configured to generate a set of different voltage thresholds; and A set of comparator circuits with hysteresis configured to compare the input control signal with the set of different voltage thresholds to generate a corresponding set of control signals; and Wherein the capacitance of the capacitor set can be selectively coupled between the first node and the second node according to the corresponding control signal in the set of control signals.

2. The circuit according to claim 1, wherein the capacitance of the capacitor set is configured to be selectively coupled between the first node and the second node in response to the corresponding control signal in the set of control signals indicating that the input control signal is higher than the corresponding voltage threshold in the set of different voltage thresholds.

3. The circuit according to claim 1, wherein the variable capacitor comprises a variable capacitor pair that is serially arranged between the first node and the second node, and the variable capacitor pair has a configuration node that is arranged between the variable capacitor pair to receive the input control signal.

4. The circuit according to claim 1, wherein the voltage divider network is configured to generate equally spaced voltage thresholds.

5. The circuit according to claim 1, further comprising: An input node configured to receive an input reference signal; A phase-frequency detector circuit configured to receive the input reference signal and the variable-frequency output signal; A charge pump circuit configured to receive an output signal from the phase-frequency detector circuit; And A low-pass filter configured to receive an output signal from the charge pump circuit and generate the input control signal received at the input control node.

6. A radar sensor, comprising: A circuit, comprising: A tunable resonant circuit having a first node and a second node, the tunable resonant circuit comprising: An inductor, coupled between the first node and the second node; wherein the inductor includes an inductor pair, the inductor pair being arranged in series between the first node and the second node, the inductor pair having a configuration node, the configuration node being arranged between the inductor pair to receive an input control signal; A variable capacitor, coupled between the first node and the second node; A capacitor set, capable of being selectively coupled between the first node and the second node; and An input control node, configured to receive the input control signal, wherein the tunable resonant circuit is tunable according to the input control signal; A bias circuit, coupled to the tunable resonant circuit and configured to bias the tunable resonant circuit to generate a variable frequency output signal between the first node and the second node; A voltage divider network, configured to generate a set of different voltage thresholds; and A set of comparator circuits with hysteresis, configured to compare the input control signal with the set of different voltage thresholds to generate a corresponding set of control signals; wherein the capacitance of the capacitor set is selectively coupled between the first node and the second node according to the corresponding control signal in the set of control signals; and A transmitter circuit, coupled to an antenna, wherein the circuit is configured to receive an input reference signal from a microcontroller unit and provide the variable frequency output signal to the transmitter circuit.

7. The radar sensor according to claim 6, wherein the capacitance of the capacitor set is configured to be selectively coupled between the first node and the second node in response to the corresponding control signal in the set of control signals indicating that the input control signal is higher than the corresponding voltage threshold in the set of different voltage thresholds.

8. The radar sensor according to claim 6, wherein the variable capacitor includes a variable capacitor pair, the variable capacitor pair being arranged in series between the first node and the second node, the variable capacitor pair having a configuration node, the configuration node being arranged between the variable capacitor pair to receive the input control signal.

9. The radar sensor according to claim 6, wherein the voltage divider network is configured to generate equally spaced voltage thresholds.

10. The radar sensor according to claim 6, further comprising: An input node, configured to receive an input reference signal; A phase-frequency detector circuit, configured to receive the input reference signal and the variable frequency output signal; A charge pump circuit, configured to receive an output signal from the phase-frequency detector circuit; and A low-pass filter, configured to receive an output signal from the charge pump circuit and generate the input control signal received at the input control node.

11. A vehicle, comprising the radar sensor according to claim 6.

12. A method of operating a circuit, comprising: An input control signal is received at an input control node, and a tunable resonant circuit is tuned in accordance with the input control signal. The input control node is coupled to a variable capacitor and a capacitor bank. The input control node is coupled to a tap between a pair of inductors connected in series, and the tunable resonant circuit includes the pair of inductors connected in series; Generate a set of different voltage thresholds; Compare the input control signal with the set of different voltage thresholds to generate a corresponding set of control signals; Selectively couple capacitances of the capacitor bank between a first node and a second node in accordance with corresponding control signals in the set of control signals; And Bias the tunable resonant circuit to generate a variable frequency output signal between the first node and the second node; Wherein the comparison includes performing a hysteresis comparison of the input control signal with the set of different voltage thresholds.

13. The method according to claim 12, wherein in response to a corresponding control signal in the set of control signals indicating that the input control signal is higher than a corresponding voltage threshold in the set of different voltage thresholds, the capacitance of the capacitor bank is selectively coupled between the first node and the second node.

14. The method according to claim 12, further comprising: Receiving an input reference signal; Receiving the input reference signal and the variable frequency output signal at a phase-frequency detector circuit; Receiving an output signal from the phase-frequency detector circuit at a charge pump circuit; And Using a low-pass filter that receives the output signal from the charge pump circuit to generate the input control signal received at the input control node.

Images