High linearity low noise amplifier circuit

Abstract

The invention relates to the technical field of microelectronics, semiconductors and communication technologies, and discloses a high-linearity low-noise amplifier circuit, the circuit comprises an amplification circuit, a compensation circuit and an active bias circuit, the amplification circuit comprises a transistor M3, and the amplification circuit amplifies a radio frequency signal through the transistor M3 and outputs an amplified signal; the compensation circuit comprises a capacitor C3 and a transistor M4, and the compensation circuit is used for performing derivative superposition with a transistor M3 in the amplification circuit by using the capacitor C3 and the transistor M4, so that third-order items in the circuit are mutually offset; and the active bias circuit is used for returning part of the amplification signal to the input end of the amplification circuit. According to the high-linearity low-noise amplifier circuit, derivative superposition is carried out on the capacitor C3, the transistor M4 and the main amplification transistor M3, so that third-order items in the circuit are offset, the linearity of the circuit is improved, and the high-linearity low-noise amplifier circuit has the advantage of being high in linearity.

Description

Technical Field

[0001] The present invention relates to the technical fields of microelectronics, semiconductors and communication technologies, and in particular to a high-linearity low-noise amplifier circuit. Background Art

[0002] With the rapid development of high-tech, RF wireless communication technology is widely used in many fields such as global satellite positioning system (GPS), wireless local area network (WLAN), cellular mobile phone and personal communication service (PCS). The low noise amplifier is located at the front end of the RF receiving system and is required to have a good noise figure and appropriate gain so that the subsequent circuit can process the signal.

[0003] In addition, in order to ensure that the signal received by the receiving system can be transmitted to the subsequent microprocessor for processing without distortion, the entire RF front-end circuit needs to have good linearity. In fact, interference signals generally appear at the input of the low-noise amplifier, which needs to provide higher linearity to prevent intermodulation of interference signals and maintain high sensitivity. Especially in military or special commercial applications, the requirements for the linearity of the receiving system, especially the low-noise amplifier, will be further improved. The gain and noise performance of the low-noise amplifier have been improved with the further reduction of the CMOS process size, and there have been many debates on how to improve its linearity. For example, the feedforward control method is used to offset the third-order component in the circuit. This technology was found in the subsequent verification that the input signal of the gain stage needs to be attenuated and separated, which will greatly affect the stability of the circuit. The optimal bias method and the derivative overlap method can use transistor bias to achieve the cancellation of the third-order current in different working areas, but the existence of the source feedback inductor will weaken the cancellation effect of this method. Summary of the invention

[0004] Based on this, it is necessary to address the technical problem of low linearity of the high linearity low noise amplifier circuit in the prior art, and propose a high linearity low noise amplifier circuit, the circuit comprising: an amplifier circuit, a compensation circuit and an active bias circuit; the amplifier circuit comprises a transistor M3, the amplifier circuit amplifies the radio frequency signal through the transistor M3, and outputs the amplified signal;

[0005] The compensation circuit includes a capacitor C3 and a transistor M4, and the compensation circuit is used to use the capacitor C3 and the transistor M4 to perform derivative superposition with the transistor M3 in the amplifier circuit so that the third-order terms in the circuit cancel each other out;

[0006] The active bias circuit is used to return part of the amplified signal to the input end of the amplifying circuit.

[0007] In one embodiment, the amplifier circuit includes a capacitor C1, a transistor M3, a resistor R6, a resistor R7, an inductor L2, an inductor L1, and a capacitor C2, one end of the capacitor C1 is a radio frequency input end, the other end of the capacitor C1 is connected to the gate of the transistor M3, the source of the transistor M3 is connected to one end of the resistor R6, the other end of the resistor R6 is grounded, one end of the resistor R7 connected in parallel with the inductor L2 is connected to the drain of the transistor M3, the other end of the resistor R7 connected in parallel with the inductor L2 is respectively connected to one end of the inductor L1 and one end of the capacitor C2, the other end of the inductor L1 is connected to the power supply VDD, and the other end of the capacitor C2 is a radio frequency output end.

[0008] In one embodiment, the compensation circuit includes a capacitor C3 and a transistor M4, wherein the drain of the transistor M4 is connected to the drain of the transistor M3, one end of the capacitor C3 is connected to the gate of the transistor M3, the other end is connected to the gate of the transistor M4, and the source of the transistor M4 is grounded.

[0009] In one embodiment, the active bias circuit includes a transistor M1, a transistor M2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, and a resistor R5. One end of the resistor R1 is connected to the drain of the transistor M3, and the other end of the resistor R1 is connected to the gate of the transistor M1. One end of the resistor R2 is connected to the drain of the transistor M1, and the other end of the resistor R2 is connected to the drain of the transistor M3. The gate of the transistor M2 is simultaneously connected to one end of the resistor R4, one end of the resistor R5, and the source of the transistor M1. The other end of the resistor R4 is grounded, and the other end of the resistor R5 is connected to the gate of the transistor M3. The source of the transistor M2 is connected to one end of the resistor R3, and the other end of the resistor R3 is grounded. The drain of the transistor M2 is connected to the gate of the transistor M1.

[0010] The high linearity low noise amplifier circuit proposed in the present invention includes an amplifier circuit, a compensation circuit and an active bias circuit. The amplifier circuit includes a transistor M3. The amplifier circuit amplifies the radio frequency signal through the transistor M3 and outputs the amplified signal. The compensation circuit includes a capacitor C3 and a transistor M4. The compensation circuit is used to use the capacitor C3 and the transistor M4 to perform derivative superposition with the transistor M3 in the amplifier circuit so that the third-order terms in the circuit cancel each other. The active bias circuit is used to return part of the amplified signal to the input end of the amplifier circuit. The high linearity low noise amplifier circuit proposed in the present invention uses the capacitor C3 and the transistor M4 to perform derivative superposition with the main amplifier transistor M3 so that the third-order terms in the circuit cancel each other, thereby improving the linearity of the circuit and having the characteristics of high linearity. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0012] in:

[0013] Figure 1 Schematic diagram of the circuit structure of a high linearity low noise amplifier circuit in one embodiment;

[0014] Figure 2 A compensation circuit diagram of a high linearity low noise amplifier circuit of the present invention;

[0015] Figure 3 The active bias circuit diagram of the high linearity low noise amplifier circuit of the present invention;

[0016] Figure 4 This is a simulation result diagram of the 1dB compression point output of the high linearity low noise amplifier circuit of the present invention;

[0017] Figure 5 This is a simulation result diagram of the output third-order intermodulation point in the high linearity low noise amplifier circuit of the present invention;

[0018] Figure 6 The noise coefficient curve of the high linearity low noise amplifier circuit of the present invention changes with frequency. DETAILED DESCRIPTION

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by technicians in the technical field of the present application; the terms used in the specification of the application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application; the terms "including" and "having" and any variations thereof in the specification and claims of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of the present application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0020] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] See also Figure 1 As shown, Figure 1 A circuit diagram of a high linearity low noise amplifier circuit provided for an embodiment of the present invention includes: a transistor M1, a transistor M2, a transistor M3, a transistor M4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a capacitor C1, a capacitor C2, a capacitor C3, an inductor L1, and an inductor L2.

[0023] Among them, one end of the resistor R1 is connected to the drain of the transistor M3, the other end of the resistor R1 is connected to the gate of the transistor M1, one end of the resistor R2 is connected to the drain of the transistor M1, the other end of the resistor R2 is connected to the drain of the transistor M3, the gate of the transistor M2 is simultaneously connected to one end of the resistor R4, one end of the resistor R5 and the source of the transistor M1, the other end of the resistor R4 is grounded, the other end of the resistor R5 is connected to the source of the transistor M3, the source of the transistor M2 is connected to one end of the resistor R3, the other end of the resistor R3 is grounded, and the drain of the transistor M2 is connected to the gate of the transistor M1;

[0024] One end of the capacitor C1 is the RF input end, the other end of the capacitor C1 is connected to the gate of the transistor M3, the source of the transistor M3 is connected to one end of the resistor R6, the other end of the resistor R6 is grounded, the drain of the transistor M4 is connected to the drain of the transistor M3, one end of the capacitor C3 is connected to the gate of the transistor M3, the other end is connected to the gate of the transistor M4, the source of the transistor M4 is grounded, one end of the resistor R7 connected in parallel with the inductor L2 is connected to the drain of the transistor M3, the other end of the resistor R7 connected in parallel with the inductor L2 is respectively connected to one end of the inductor L1 and one end of the capacitor C2, the other end of the inductor L1 is connected to the power supply VDD, and the other end of the capacitor C2 is the RF output end.

[0025] In this embodiment, the amplifier circuit includes an amplifier circuit, a compensation circuit and an active bias circuit. The RF signal enters from the DC blocking capacitor C1, is amplified by the common source amplifier and the compensation circuit, and is finally output from the DC blocking capacitor C2. During the process, a part of the signal at the output end is returned to the input end through the active bias circuit.

[0026] refer to Figure 2The active bias circuit includes a transistor M1, a transistor M2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, and a resistor R5. One end of the resistor R1 is connected to the drain of the transistor M3, the other end of the resistor R1 is connected to the gate of the transistor M1, one end of the resistor R2 is connected to the drain of the transistor M1, the other end of the resistor R2 is connected to the drain of the transistor M3, the gate of the transistor M2 is simultaneously connected to one end of the resistor R4, one end of the resistor R5, and the source of the transistor M1, the other end of the resistor R4 is grounded, the other end of the resistor R5 is connected to the source of the transistor M3, the source of the transistor M2 is connected to one end of the resistor R3, the other end of the resistor R3 is grounded, and the drain of the transistor M2 is connected to the gate of the transistor M1.

[0027] refer to Figure 3 The compensation circuit includes a capacitor C3 and a transistor M4. The drain of the transistor M4 is connected to the drain of the transistor M3, one end of the capacitor C3 is connected to the gate of the transistor M3, the other end of the capacitor C3 is connected to the gate of the transistor M4, and the source of the transistor M4 is grounded.

[0028] The amplifier circuit includes a capacitor C1, a transistor M3, a resistor R6, a resistor R7, an inductor L2, an inductor L1, and a capacitor C2. One end of the capacitor C1 is a radio frequency input end, the other end of the capacitor C1 is connected to the gate of the transistor M3, the source of the transistor M3 is connected to one end of the resistor R6, the other end of the resistor R6 is grounded, one end of the resistor R7 connected in parallel with the inductor L2 is connected to the drain of the transistor M3, the other end of the resistor R7 connected in parallel with the inductor L2 is respectively connected to one end of the inductor L1 and one end of the capacitor C2, the other end of the inductor L1 is connected to the power supply VDD, and the other end of the capacitor C2 is a radio frequency output end.

[0029] The working principle of the high linearity low noise amplifier circuit proposed in the present invention is as follows: Compared with the common source amplifier of the traditional active bias circuit structure, the present invention has the characteristics of high linearity. The core idea of ​​linearity optimization is to use compensation, and the capacitor C3 and transistor M4 in the circuit are superimposed with the main amplifier transistor M3 to make the third-order terms in the circuit cancel each other, thereby improving the linearity of the circuit. Different from the general derivative overlap method, the source of the compensation transistor and the source of the main amplifier tube of this design are grounded in different ways, so that the source ends of the two transistors can produce a phase difference and perform vector and compensation.

[0030] refer to Figure 4 , 5 , 6, Figure 4 The IP3 value of the high linearity low noise amplifier circuit of the present invention varies with frequency. Figure 5 is the value of OP1 dB of the high linearity low noise amplifier circuit as the frequency changes, Figure 6 It is the noise coefficient of the high linearity low noise amplifier circuit as the frequency changes, revealing that the high linearity low noise amplifier circuit of the present invention has the characteristic of high linearity.

[0031] The above-mentioned embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them. Although the present invention has been described in detail with reference to the above-mentioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above-mentioned embodiments, or replace some of the technical features therein by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention.

Claims

1. A high linearity low noise amplifier circuit, characterized in that: The high linearity low noise amplifier circuit comprises: an amplification circuit, a compensation circuit and an active bias circuit; The amplifier circuit includes a transistor M3, and the amplifier circuit amplifies the radio frequency signal through the transistor M3 and outputs an amplified signal; The compensation circuit includes a capacitor C3 and a transistor M4, and the compensation circuit is used to use the capacitor C3 and the transistor M4 to perform derivative superposition with the transistor M3 in the amplifier circuit so that the third-order terms in the circuit cancel each other out; The active bias circuit is used to return part of the amplified signal to the input end of the amplifying circuit.

2. The high linearity low noise amplifier circuit according to claim 1, characterized in that: The amplifier circuit includes a capacitor C1, a transistor M3, a resistor R6, a resistor R7, an inductor L2, an inductor L1, and a capacitor C2. One end of the capacitor C1 is a radio frequency input end, the other end of the capacitor C1 is connected to the gate of the transistor M3, the source of the transistor M3 is connected to one end of the resistor R6, the other end of the resistor R6 is grounded, one end of the resistor R7 connected in parallel with the inductor L2 is connected to the drain of the transistor M3, the other end of the resistor R7 connected in parallel with the inductor L2 is respectively connected to one end of the inductor L1 and one end of the capacitor C2, the other end of the inductor L1 is connected to the power supply VDD, and the other end of the capacitor C2 is a radio frequency output end.

3. The high linearity low noise amplifier circuit according to claim 2, characterized in that: The compensation circuit includes a capacitor C3 and a transistor M4, wherein the drain of the transistor M4 is connected to the drain of the transistor M3, one end of the capacitor C3 is connected to the gate of the transistor M3, the other end of the capacitor C3 is connected to the gate of the transistor M4, and the source of the transistor M4 is grounded.

4. The high linearity low noise amplifier circuit according to claim 3, characterized in that: The active bias circuit includes a transistor M1, a transistor M2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, and a resistor R5. One end of the resistor R1 is connected to the drain of the transistor M3, and the other end of the resistor R1 is connected to the gate of the transistor M1. One end of the resistor R2 is connected to the drain of the transistor M1, and the other end of the resistor R2 is connected to the drain of the transistor M3. The gate of the transistor M2 is simultaneously connected to one end of the resistor R4, one end of the resistor R5, and the source of the transistor M1. The other end of the resistor R4 is grounded, and the other end of the resistor R5 is connected to the gate of the transistor M3. The source of the transistor M2 is connected to one end of the resistor R3, and the other end of the resistor R3 is grounded. The drain of the transistor M2 is connected to the gate of the transistor M1.

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