Differential low noise amplifier and radio frequency chip

Abstract

The invention is suitable for the technical field of communication, and particularly relates to a differential low-noise amplifier and a radio frequency chip. The differential low-noise amplifier comprises a first low-noise amplification unit and a second low-noise amplification unit; the first low-noise amplification unit is used for counteracting noise generated by the differential low-noise amplifier; the output end of the second low-noise amplification unit serves as the output end of the differential low-noise amplifier and is used for outputting signals, and the second low-noise amplification unit is used for conducting input matching on the broadband of the differential low-noise amplifier. Compared with the prior art, a two-stage cascade structure formed by the first low-noise amplification unit and the second low-noise amplification unit is adopted, the first low-noise amplification unit counteracts noise by utilizing transistor characteristics, and the second low-noise amplification unit enhances isolation between input and output while enhancing gain, so that the noise is reduced, and the noise is reduced. Finally, broadband input matching, noise cancellation and single-end-to-differential conversion of the whole differential low-noise amplifier are achieved, and the differential low-noise amplifier is suitable for a radio frequency front-end circuit.

Description

Technical Field

[0001] The present invention is applicable to the field of communication technology, and in particular relates to a differential low noise amplifier and a radio frequency chip. Background Art

[0002] With the development of wireless communication technology, RF front-end circuits have always been one of the key areas of research and innovation. As the starting part of the receiving link, the differential low-noise amplifier's ability to process weak signals directly determines the performance of the entire communication system. In recent years, with the continuous updating of communication standards and the increasing richness of application scenarios, such as the rise of smart homes and smart transportation, the adaptability and performance requirements of RF front-end circuits have become increasingly stringent.

[0003] However, in the face of these new demands, existing single-ended low-noise amplifiers have gradually shown their shortcomings in noise suppression, bandwidth expansion, and signal processing flexibility. They have problems such as poor noise suppression, low gain, and poor linearity, and are unable to meet the performance requirements of existing RF front-end circuits.

[0004] Therefore, there is an urgent need for a new differential low noise amplifier and RF chip to solve the above technical problems. Summary of the invention

[0005] The present invention provides a differential low noise amplifier and a radio frequency chip, aiming to improve the bandwidth and linearity of the differential low noise amplifier and reduce the noise coefficient.

[0006] In a first aspect, the present invention provides a differential low noise amplifier, the differential low noise amplifier comprising a first low noise amplifying unit and a second low noise amplifying unit; The input end of the first low-noise amplifying unit is used as the input end of the differential low-noise amplifier to receive an input signal, the first output end of the first low-noise amplifying unit is connected to the first input end of the second low-noise amplifying unit, the second output end of the first low-noise amplifying unit is connected to the second input end of the second low-noise amplifying unit, and the first low-noise amplifying unit is used to cancel the noise generated by the differential low-noise amplifier and realize the conversion of the single-ended input signal to the differential output signal; The output end of the second low-noise amplifier unit serves as the output end of the differential low-noise amplifier and is used to output a signal. The second low-noise amplifier unit is used to match and optimize the gain and bandwidth of the differential low-noise amplifier. The first low-noise amplifying unit includes an input matching circuit, a first amplifying circuit and a first output matching circuit; the input end of the input matching circuit serves as the input end of the first low-noise amplifying unit, the output end of the input matching circuit is connected to the input end of the first amplifying circuit, the first output end of the first amplifying circuit is connected to the first input end of the first output matching circuit, the second output end of the first amplifying circuit is connected to the second input end of the first output matching circuit, the first output end of the first output matching circuit serves as the first output end of the first low-noise amplifying unit, and the second output end of the first output matching circuit serves as the second output end of the first low-noise amplifying unit; wherein the first amplifying circuit is a noise cancellation amplifying circuit based on a common gate-common source structure composed of MOS tubes; The second low-noise amplifying unit includes a second amplifying circuit, a third amplifying circuit and a second output matching circuit; the input end of the second amplifying circuit serves as the first input end of the second low-noise amplifying unit, the output end of the second amplifying circuit is connected to the first input end of the second output matching circuit, the input end of the third amplifying circuit serves as the second input end of the second low-noise amplifying unit, the output end of the third amplifying circuit is connected to the second input end of the second output matching circuit, and the output end of the second output matching circuit serves as the output end of the second low-noise amplifying unit; wherein the second amplifying circuit is a common-source and common-gate structure amplifying circuit composed of MOS tubes.

[0007] The first amplifier circuit includes a first inductor, a second inductor, a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube; the source of the first MOS tube serves as an input end of the first amplifier circuit, the gate of the first MOS tube is used to connect a first external bias voltage, and the drain of the first MOS tube is connected to the source of the second MOS tube; the first end of the first inductor is connected to the source of the first MOS tube, and the second end of the first inductor is grounded; the gate of the second MOS tube is connected to the gate of the fourth MOS tube, and the drain of the second MOS tube serves as a second output end of the first amplifier circuit; the gate of the third MOS tube is connected to the source of the first MOS tube, the source of the third MOS tube is connected to the first end of the second inductor, the second end of the second inductor is grounded, the drain of the third MOS tube is connected to the source of the fourth MOS tube, and the drain of the fourth MOS tube serves as a first output end of the first amplifier circuit.

[0008] Preferably, the input matching circuit comprises a first capacitor; the first end of the first capacitor serves as the input end of the input matching circuit, and the second end of the first capacitor serves as the output end of the input matching circuit.

[0009] Preferably, the first output matching circuit includes a third inductor, a fourth inductor, a second capacitor and a third capacitor; the first end of the third inductor serves as the second input end of the first output matching circuit, the second end of the third inductor is connected to the external power supply voltage, the first end of the fourth inductor serves as the first input end of the first output matching circuit, the second end of the fourth inductor is connected to the external power supply voltage, the first end of the second capacitor is connected to the first end of the third inductor, the second end of the second capacitor serves as the second output end of the first output matching circuit, the first end of the third capacitor is connected to the first end of the fourth inductor, and the second end of the third capacitor serves as the first output end of the first output matching circuit.

[0010] Preferably, the second amplifier circuit includes a fifth inductor, a sixth inductor, a seventh inductor, a fifth MOS tube and a sixth MOS tube; the gate of the fifth MOS tube serves as the input end of the second amplifier circuit, the source of the fifth MOS tube is connected to the first end of the fifth inductor, the second end of the fifth inductor is grounded, the drain of the fifth MOS tube is connected to the first end of the sixth inductor, the second end of the sixth inductor is connected to the source of the sixth MOS tube, the drain of the sixth MOS tube serves as the output end of the second amplifier circuit, the gate of the sixth MOS tube is connected to the first end of the seventh inductor, and the second end of the seventh inductor is connected to the second external bias voltage.

[0011] Preferably, the third amplifier circuit includes an eighth inductor, a ninth inductor, a tenth inductor, a seventh MOS tube and an eighth MOS tube; the gate of the seventh MOS tube serves as the input end of the third amplifier circuit, the source of the seventh MOS tube is connected to the first end of the eighth inductor, the second end of the eighth inductor is grounded, the drain of the seventh MOS tube is connected to the first end of the ninth inductor, the second end of the ninth inductor is connected to the source of the eighth MOS tube, the drain of the eighth MOS tube serves as the output end of the third amplifier circuit, the gate of the eighth MOS tube is connected to the first end of the tenth inductor, and the second end of the tenth inductor is connected to the second external bias voltage.

[0012] Preferably, the second output matching circuit includes a fourth capacitor, a fifth capacitor, an eleventh inductor and a twelfth inductor; one end of the eleventh inductor serves as the first input end of the second output matching circuit, the second end of the eleventh inductor is connected to an external power supply voltage, the first end of the fourth capacitor is connected to the first end of the eleventh inductor, the second end of the fourth capacitor serves as the first output end of the second output matching circuit, the first end of the twelfth inductor serves as the second input end of the second output matching circuit, the second end of the twelfth inductor is connected to the external power supply voltage, the first end of the fifth capacitor is connected to the first end of the twelfth inductor, and the second end of the fifth capacitor serves as the second output end of the second output matching circuit.

[0013] In a second aspect, the present invention further provides a radio frequency chip, comprising a differential low noise amplifier as described in any one of the above embodiments.

[0014] Compared with the prior art, the present invention adopts a two-stage cascade structure consisting of a first low-noise amplifier unit and a second low-noise amplifier unit. The first low-noise amplifier unit cancels noise by utilizing the characteristics of transistors, and the second low-noise amplifier unit enhances the isolation between input and output while enhancing the gain, ultimately achieving broadband input matching, noise cancellation and single-ended to differential conversion of the entire differential low-noise amplifier, which is suitable for RF front-end circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings: Figure 1 The circuit structure of the differential low noise amplifier provided by the embodiment of the present invention is shown in FIG. Figure 1 ; Figure 2 The circuit structure of the differential low noise amplifier provided by the embodiment of the present invention is shown in FIG. Figure 2 .

[0016] In the figure, 100 is a differential low-noise amplifier, 10 is a first low-noise amplifier unit, 11 is an input matching circuit, 12 is a first amplifier circuit, 13 is a first output matching circuit, 20 is a second low-noise amplifier unit, 21 is a second amplifier circuit, 22 is a third amplifier circuit, and 23 is a second output matching circuit. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0018] Embodiment 1 Please refer to Figure 1-Figure 2 , the present invention provides a differential low noise amplifier 100, the differential low noise amplifier 100 comprises a first low noise amplifying unit 10 and a second low noise amplifying unit 20; The input end of the first low-noise amplifying unit 10 is used as the input end of the differential low-noise amplifier 100 to receive an input signal. The first output end of the first low-noise amplifying unit 10 is connected to the first input end of the second low-noise amplifying unit 20. The second output end of the first low-noise amplifying unit 10 is connected to the second input end of the second low-noise amplifying unit 20. The first low-noise amplifying unit 10 is used to cancel the noise generated by the differential low-noise amplifier 100 and realize the conversion of the single-ended input signal to the differential output signal. The output end of the second low-noise amplifier unit 20 serves as the output end of the differential low-noise amplifier 100 and is used to output a signal. The second low-noise amplifier unit 20 is used to match and optimize the gain and bandwidth of the differential low-noise amplifier 100. The first low-noise amplifying unit 10 includes an input matching circuit 11, a first amplifying circuit 12 and a first output matching circuit 13; the input end of the input matching circuit 11 serves as the input end of the first low-noise amplifying unit 10, the output end of the input matching circuit 11 is connected to the input end of the first amplifying circuit 12, the first output end of the first amplifying circuit 12 is connected to the first input end of the first output matching circuit 13, the second output end of the first amplifying circuit 12 is connected to the second input end of the first output matching circuit 13, the first output end of the first output matching circuit 13 serves as the first output end of the first low-noise amplifying unit 10, and the second output end of the first output matching circuit 13 serves as the second output end of the first low-noise amplifying unit 10; wherein the first amplifying circuit 12 is a noise canceling amplifying circuit based on a common gate-common source structure composed of MOS tubes; The second low-noise amplifying unit 20 includes a second amplifying circuit 21, a third amplifying circuit 22 and a second output matching circuit 23; the input end of the second amplifying circuit 21 serves as the first input end of the second low-noise amplifying unit 20, the output end of the second amplifying circuit 21 is connected to the first input end of the second output matching circuit 23, the input end of the third amplifying circuit 22 serves as the second input end of the second low-noise amplifying unit 20, the output end of the third amplifying circuit 22 is connected to the second input end of the second output matching circuit 23, and the output end of the second output matching circuit 23 serves as the output end of the second low-noise amplifying unit 20; wherein the second amplifying circuit 21 is a common-source and common-gate structure amplifying circuit composed of a MOS tube.

[0019] In the embodiment of the present invention, the first amplifier circuit 12 includes a first inductor L1, a second inductor L2, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3 and a fourth MOS transistor M4; the source of the first MOS transistor M1 serves as the input end of the first amplifier circuit 12, the gate of the first MOS transistor M1 is connected to the first external bias voltage VBIAS1, the drain of the first MOS transistor M1 is connected to the source of the second MOS transistor M2, the first end of the first inductor L1 is connected to the source of the first MOS transistor M1, the second end of the first inductor L1 is grounded, the gate of the second MOS transistor M2 is connected to the gate of the fourth MOS transistor M4, the drain of the second MOS transistor M2 serves as the second output end of the first amplifier circuit 12, the gate of the third MOS transistor M3 is connected to the source of the first MOS transistor M1, the source of the third MOS transistor M3 is connected to the first end of the second inductor L2, the second end of the second inductor L2 is grounded, the drain of the third MOS transistor M3 is connected to the source of the fourth MOS transistor M4, and the drain of the fourth MOS transistor M4 serves as the first output end of the first amplifier circuit 12.

[0020] Specifically, Figure 1-Figure 2 K1-K6 in the figure represent different coupling coefficients, and the specific value of the coupling coefficient is adjusted according to the actual simulation results. The first inductor L1 and the second inductor L2 are coupled to each other and the coupling coefficient is K1; the third inductor L3 and the fourth inductor L4 are coupled to each other and the coupling coefficient is K2; the eleventh inductor L11 and the twelfth inductor L12 are coupled to each other and the coupling coefficient is K3; the sixth inductor L6 and the seventh inductor L7 are coupled to each other and the coupling coefficient is K4; the ninth inductor L9 and the tenth inductor L10 are coupled to each other and the coupling coefficient is K5; the fifth inductor L5 and the eighth inductor L8 are coupled to each other and the coupling coefficient is K6. The present invention adopts a two-stage amplifier circuit cascade structure composed of a first low-noise amplifier unit 10 and a second low-noise amplifier unit 20 for the differential low-noise amplifier 100, and realizes noise cancellation and single-ended to differential conversion through the two-stage circuit cascade.

[0021] When input noise acts on the gate of the first MOS tube M1 of the first low-noise amplifier unit 10, the noise current will generate voltage changes at the drain and source of the first MOS tube M1. Due to the particularity of the circuit structure, the voltage generated by the drain noise current of the first MOS tube M1 at the differential output end is correlated with the noise voltage output by the second MOS tube M2. By reasonably designing the circuit parameters according to the actual situation, the two noise voltages can be equal in magnitude and polarity, so as to cancel each other at the differential output end. The second low-noise amplifier unit 20 further optimizes the gain and bandwidth of the overall circuit of the differential low-noise amplifier 100, and enhances the isolation between the input and the output. The circuit not only realizes broadband input matching and noise cancellation, but also completes the single-ended to differential conversion, effectively improves the linearity, gain and bandwidth of the differential low-noise amplifier 100, not only enhances the isolation between the input and the output, but also cancels the noise of the first amplifier circuit 12, so that the performance of the differential low-noise amplifier 100 is better.

[0022] In the embodiment of the present invention, the input matching circuit 11 includes a first capacitor C1; a first end of the first capacitor C1 serves as an input end of the input matching circuit 11, and a second end of the first capacitor C1 serves as an output end of the input matching circuit 11. The first capacitor C1 is an input DC blocking capacitor.

[0023] In the embodiment of the present invention, the first output matching circuit 13 includes a third inductor L3, a fourth inductor L4, a second capacitor C2 and a third capacitor C3, wherein the second capacitor C2 and the third capacitor C3 are inter-stage capacitors; a first end of the third inductor L3 serves as a second input end of the first output matching circuit 13, a second end of the third inductor L3 is connected to an external power supply voltage VDD, a first end of the fourth inductor L4 serves as a first input end of the first output matching circuit 13, a second end of the fourth inductor L4 is connected to an external power supply voltage VDD, a first end of the second capacitor C2 is connected to a first end of the third inductor L3, a second end of the second capacitor C2 serves as a second output end of the first output matching circuit 13, a first end of the third capacitor C3 is connected to a first end of the fourth inductor L4, and a second end of the third capacitor C3 serves as a first output end of the first output matching circuit 13.

[0024] In the embodiment of the present invention, the second amplifier circuit 21 includes a fifth inductor L5, a sixth inductor L6, a seventh inductor L7, a fifth MOS transistor M5 and a sixth MOS transistor M6; the gate of the fifth MOS transistor M5 serves as the input end of the second amplifier circuit 21, the source of the fifth MOS transistor M5 is connected to the first end of the fifth inductor L5, the second end of the fifth inductor L5 is grounded, the drain of the fifth MOS transistor M5 is connected to the first end of the sixth inductor L6, the second end of the sixth inductor L6 is connected to the source of the sixth MOS transistor M6, the drain of the sixth MOS transistor M6 serves as the output end of the second amplifier circuit 21, the gate of the sixth MOS transistor M6 is connected to the first end of the seventh inductor L7, and the second end of the seventh inductor L7 is connected to the second external bias voltage VBIAS2. It should be noted that the specific values ​​of the first external bias voltage VBIAS1 and the second external bias voltage VBIAS2 can be set according to actual conditions, and the values ​​of the first external bias voltage VBIAS1 and the second external bias voltage VBIAS2 can be the same or different.

[0025] In the embodiment of the present invention, the third amplifier circuit 22 includes an eighth inductor L8, a ninth inductor L9, a tenth inductor L10, a seventh MOS tube M7 and an eighth MOS tube M8; the gate of the seventh MOS tube M7 serves as the input end of the third amplifier circuit 22, the source of the seventh MOS tube M7 is connected to the first end of the eighth inductor L8, the second end of the eighth inductor L8 is grounded, the drain of the seventh MOS tube M7 is connected to the first end of the ninth inductor L9, the second end of the ninth inductor L9 is connected to the source of the eighth MOS tube M8, the drain of the eighth MOS tube M8 serves as the output end of the third amplifier circuit 22, the gate of the eighth MOS tube is connected to the first end of the tenth inductor L10, and the second end of the tenth inductor L10 is connected to the second external bias voltage VBIAS2.

[0026] In the embodiment of the present invention, the second output matching circuit 23 includes a fourth capacitor C4, a fifth capacitor C5, an eleventh inductor L11 and a twelfth inductor L12; one end of the eleventh inductor L11 serves as a first input end of the second output matching circuit 23, a second end of the eleventh inductor L11 is connected to an external power supply voltage VDD, a first end of the fourth capacitor C4 is connected to a first end of the eleventh inductor L11, a second end of the fourth capacitor C4 serves as a first output end (i.e., Vout1) of the second output matching circuit 23, a first end of the twelfth inductor L12 serves as a second input end of the second output matching circuit 23, a second end of the twelfth inductor L12 is connected to an external power supply voltage VDD, a first end of the fifth capacitor C5 is connected to a first end of the twelfth inductor L12, and a second end of the fifth capacitor C5 serves as a second output end (i.e., Vout2) of the second output matching circuit 23.

[0027] Compared with the prior art, the present invention adopts a two-stage cascade structure consisting of a first low-noise amplifier unit and a second low-noise amplifier unit. The first low-noise amplifier unit cancels noise by utilizing the characteristics of transistors, and the second low-noise amplifier unit enhances the isolation between input and output while enhancing the gain, ultimately achieving broadband input matching, noise cancellation and single-ended to differential conversion of the entire differential low-noise amplifier, which is suitable for RF front-end circuits.

[0028] Embodiment 2 An embodiment of the present invention further provides a radio frequency chip, which includes the differential low noise amplifier 100 as described in the above embodiment and can achieve the same technical effect. Please refer to the description in the above embodiment and will not be repeated here.

[0029] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0030] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A differential low noise amplifier, characterized in that: The differential low noise amplifier comprises a first low noise amplifying unit and a second low noise amplifying unit; The input end of the first low-noise amplifying unit is used as the input end of the differential low-noise amplifier to receive an input signal, the first output end of the first low-noise amplifying unit is connected to the first input end of the second low-noise amplifying unit, the second output end of the first low-noise amplifying unit is connected to the second input end of the second low-noise amplifying unit, and the first low-noise amplifying unit is used to cancel the noise generated by the differential low-noise amplifier and realize the conversion of the single-ended input signal to the differential output signal; The output end of the second low-noise amplifier unit serves as the output end of the differential low-noise amplifier and is used to output a signal. The second low-noise amplifier unit is used to match and optimize the gain and bandwidth of the differential low-noise amplifier. The first low noise amplifying unit comprises an input matching circuit, a first amplifying circuit and a first output matching circuit; The input end of the input matching circuit serves as the input end of the first low-noise amplifying unit, the output end of the input matching circuit is connected to the input end of the first amplifying circuit, the first output end of the first amplifying circuit is connected to the first input end of the first output matching circuit, the second output end of the first amplifying circuit is connected to the second input end of the first output matching circuit, the first output end of the first output matching circuit serves as the first output end of the first low-noise amplifying unit, and the second output end of the first output matching circuit serves as the second output end of the first low-noise amplifying unit; wherein the first amplifying circuit is a noise canceling amplifying circuit based on a common gate-common source structure composed of MOS tubes; The second low-noise amplifying unit includes a second amplifying circuit, a third amplifying circuit and a second output matching circuit; the input end of the second amplifying circuit serves as the first input end of the second low-noise amplifying unit, the output end of the second amplifying circuit is connected to the first input end of the second output matching circuit, the input end of the third amplifying circuit serves as the second input end of the second low-noise amplifying unit, the output end of the third amplifying circuit is connected to the second input end of the second output matching circuit, and the output end of the second output matching circuit serves as the output end of the second low-noise amplifying unit; wherein the second amplifying circuit is a common-source and common-gate structure amplifying circuit composed of MOS tubes.

2. The differential low noise amplifier according to claim 1, wherein: The first amplifier circuit includes a first inductor, a second inductor, a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor; the source of the first MOS transistor serves as the input end of the first amplifier circuit, the gate of the first MOS transistor is used to connect a first external bias voltage, and the drain of the first MOS transistor is connected to the source of the second MOS transistor; The first end of the first inductor is connected to the source of the first MOS tube, and the second end of the first inductor is grounded; the gate of the second MOS tube is connected to the gate of the fourth MOS tube, and the drain of the second MOS tube serves as the second output end of the first amplifier circuit; the gate of the third MOS tube is connected to the source of the first MOS tube, the source of the third MOS tube is connected to the first end of the second inductor, the second end of the second inductor is grounded, the drain of the third MOS tube is connected to the source of the fourth MOS tube, and the drain of the fourth MOS tube serves as the first output end of the first amplifier circuit.

3. The differential low noise amplifier according to claim 1, wherein: The input matching circuit includes a first capacitor; a first end of the first capacitor serves as an input end of the input matching circuit, and a second end of the first capacitor serves as an output end of the input matching circuit.

4. The differential low noise amplifier according to claim 1, wherein: The first output matching circuit includes a third inductor, a fourth inductor, a second capacitor and a third capacitor; the first end of the third inductor serves as the second input end of the first output matching circuit, the second end of the third inductor is used to connect to an external power supply voltage, the first end of the fourth inductor serves as the first input end of the first output matching circuit, and the second end of the fourth inductor is used to connect to an external power supply voltage; the first end of the second capacitor is connected to the first end of the third inductor, the second end of the second capacitor serves as the second output end of the first output matching circuit, the first end of the third capacitor is connected to the first end of the fourth inductor, and the second end of the third capacitor serves as the first output end of the first output matching circuit.

5. The differential low noise amplifier according to claim 1, wherein: The second amplifier circuit includes a fifth inductor, a sixth inductor, a seventh inductor, a fifth MOS tube and a sixth MOS tube; the gate of the fifth MOS tube serves as an input end of the second amplifier circuit, the source of the fifth MOS tube is connected to the first end of the fifth inductor, the second end of the fifth inductor is grounded, and the drain of the fifth MOS tube is connected to the first end of the sixth inductor; the second end of the sixth inductor is connected to the source of the sixth MOS tube, the drain of the sixth MOS tube serves as an output end of the second amplifier circuit, the gate of the sixth MOS tube is connected to the first end of the seventh inductor, and the second end of the seventh inductor is used to connect a second external bias voltage.

6. The differential low noise amplifier according to claim 1, wherein: The third amplifier circuit includes an eighth inductor, a ninth inductor, a tenth inductor, a seventh MOS tube and an eighth MOS tube; the gate of the seventh MOS tube serves as the input end of the third amplifier circuit, the source of the seventh MOS tube is connected to the first end of the eighth inductor, the second end of the eighth inductor is grounded, and the drain of the seventh MOS tube is connected to the first end of the ninth inductor; the second end of the ninth inductor is connected to the source of the eighth MOS tube, the drain of the eighth MOS tube serves as the output end of the third amplifier circuit, the gate of the eighth MOS tube is connected to the first end of the tenth inductor, and the second end of the tenth inductor is used to connect to the second external bias voltage.

7. The differential low noise amplifier according to claim 1, wherein: The second output matching circuit includes a fourth capacitor, a fifth capacitor, an eleventh inductor and a twelfth inductor; one end of the eleventh inductor serves as a first input end of the second output matching circuit, and a second end of the eleventh inductor is used to connect an external power supply voltage; a first end of the fourth capacitor is connected to a first end of the eleventh inductor, and a second end of the fourth capacitor serves as a first output end of the second output matching circuit; a first end of the twelfth inductor serves as a second input end of the second output matching circuit, and a second end of the twelfth inductor is used to connect an external power supply voltage; a first end of the fifth capacitor is connected to a first end of the twelfth inductor, and a second end of the fifth capacitor serves as a second output end of the second output matching circuit.

8. A radio frequency chip, characterized in that: The radio frequency chip includes the differential low noise amplifier as described in claims 1-7.

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