Semiconductor cascade structure and electronic equipment

Abstract

The invention provides a semiconductor cascade structure and electronic equipment, and relates to the technical field of semiconductors, the semiconductor cascade structure comprises an enhancement mode transistor, a first depletion mode transistor, a second depletion mode transistor and a diode, the source electrode of the first depletion mode transistor is connected to the drain electrode of the enhancement mode transistor, and the source electrode of the second depletion mode transistor is connected to the drain electrode of the second depletion mode transistor; a stray capacitor Cgs is arranged between the source electrode and the grid electrode of the first depletion type transistor; the source electrode of the second depletion mode transistor is connected to the drain electrode of the first depletion mode transistor, and the grid electrode of the second depletion mode transistor is connected to the source electrode of the enhancement mode transistor; the anode of the diode is connected to the grid electrode of the first depletion mode transistor, and the cathode is connected to the source electrode of the enhancement mode transistor. Compared with the prior art, the cascade structure has the advantages that the saturation current of cascade can be reduced, the short-circuit capability of the cascade structure is improved, and meanwhile, due to the fact that the depletion transistors are connected in series and the diodes are additionally arranged, the reliability of the whole device cannot be deteriorated, the on-resistance is basically unchanged, and the performance of the device cannot be affected.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor cascade structure and an electronic device. Background Art

[0002] The cascode device composed of a depletion-mode GaN high electron mobility transistor (D-HEMT) and an enhancement-mode low-voltage MOS is a common normally-off GaN device on the market. In order to reduce the leakage current of the device, the gate generally uses a MIS (metal-insulator-barrier) structure. Since the saturation current of the cascode is very large, its short-circuit capability is very poor, which is disadvantageous for some application scenarios.

[0003] Currently, the short-circuit capability of the cascode is mainly improved by reducing the saturation current. However, the current method of reducing the saturation current will inevitably increase the on-resistance of the device and reduce the reliability of the device. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor cascade structure and an electronic device, which can reduce the saturation current of the cascode and improve its short-circuit capability, while the device reliability will not be deteriorated, the on-resistance remains basically unchanged, and the device performance will not be affected.

[0005] In a first aspect, the present invention provides a semiconductor cascade structure, comprising:

[0006] Enhancement mode transistor;

[0007] a first depletion-mode transistor, wherein a source of the first depletion-mode transistor is connected to a drain of the enhancement-mode transistor, wherein a parasitic capacitance Cgs is provided between the source and the gate of the first depletion-mode transistor;

[0008] a second depletion-mode transistor, wherein a source of the second depletion-mode transistor is connected to a drain of the first depletion-mode transistor, and a gate of the second depletion-mode transistor is connected to a source of the enhancement-mode transistor;

[0009] A diode, wherein an anode of the diode is connected to the gate of the first depletion-mode transistor, and a cathode of the diode is connected to the source of the enhancement-mode transistor.

[0010] In an optional implementation, the first depletion-mode transistor and the second depletion-mode transistor are integrated in the same depletion-mode device.

[0011] In an optional embodiment, the depletion-mode device includes:

[0012] substrate;

[0013] a channel layer, wherein the channel layer is disposed on the substrate;

[0014] a barrier layer, the barrier layer being disposed on the channel layer;

[0015] a dielectric layer, wherein the dielectric layer is disposed on the barrier layer;

[0016] A source electrode and a drain electrode, wherein the source electrode and the drain electrode are arranged in the dielectric layer at intervals and contact the channel layer;

[0017] A first gate electrode and a second gate electrode, wherein the first gate electrode and the second gate electrode are spaced apart in the dielectric layer and located between the source electrode and the drain electrode, the first gate electrode is close to the source electrode, and the second gate electrode is close to the drain electrode.

[0018] In an optional embodiment, the depletion-mode device further includes a gate field plate, which is disposed on the dielectric layer and covers a side of the second gate electrode away from the substrate.

[0019] In an optional embodiment, the semiconductor cascade structure further includes a first capacitor, one end of the first capacitor is connected to the source of the first depletion-mode transistor, and the other end of the first capacitor is connected to the gate of the first depletion-mode transistor.

[0020] In an optional embodiment, the semiconductor cascade structure further includes a second capacitor, one end of the second capacitor is connected to the anode of the diode, and the other end of the second capacitor is connected to the cathode of the diode, so that the second capacitor is connected in parallel with the diode.

[0021] In an optional embodiment, the diode is a Zener diode.

[0022] In an optional embodiment, the semiconductor cascade structure further includes a first resistor, one end of which is connected to the cathode of the diode, and the other end of which is connected to the source of the enhancement transistor, so that the first resistor and the diode are connected in series.

[0023] In an optional embodiment, the semiconductor cascade structure further includes a second resistor and a third capacitor, one end of the second resistor is connected to the drain of the enhancement mode transistor, the other end of the second resistor is connected to the source of the enhancement mode transistor, one end of the third capacitor is connected to the drain of the enhancement mode transistor, and the other end of the third capacitor is connected to the source of the enhancement mode transistor, so that the second resistor, the third capacitor and the enhancement mode transistor are connected in parallel; and / or;

[0024] The semiconductor cascade structure further includes a third resistor, one end of which is connected to the gate of the second depletion-mode transistor, and the other end of which is connected to the source of the enhancement-mode transistor.

[0025] In a second aspect, the present invention provides an electronic device comprising a semiconductor cascade structure as described in any one of the aforementioned embodiments.

[0026] The beneficial effects of the embodiments of the present invention are:

[0027] The semiconductor cascade structure and electronic device provided by the embodiment of the present invention connect the source of the first depletion-mode transistor to the drain of the enhancement-mode transistor, connect the source of the second depletion-mode transistor to the drain of the first depletion-mode transistor, realize series connection, connect the gate of the second depletion-mode transistor to the source of the enhancement-mode transistor, and connect the anode of the diode to the gate of the first depletion-mode transistor, and connect the cathode of the diode to the source of the enhancement-mode transistor, thereby forming a cascode circuit. Since there is a parasitic capacitance Cgs between the source and the gate of the first depletion-mode transistor, when the device is turned off, the drain of the second depletion-mode transistor and the source of the enhancement-mode transistor are connected. The voltage will increase, so that there will also be a voltage difference between the source of the first depletion transistor and the source of the enhancement transistor. At this time, Cgs will be charged through the diode, and the gate of the first depletion transistor is also grounded through the diode. In the subsequent opening process, the voltage between the source of the first depletion transistor and the source of the enhancement transistor decreases. Since the diode is in a reverse state, the charge on Cgs cannot be released, which will cause a relatively high positive voltage between the source and the gate of the first depletion transistor, that is, there is a negative voltage between the gate and the source of the first depletion transistor, thereby reducing the saturation current of the cascode and improving the short-circuit capability of the device. Compared with the prior art, the semiconductor cascade structure and electronic device provided by the embodiment of the present invention can reduce the saturation current of the cascode and improve its short-circuit capability. At the same time, due to the use of depletion transistors in series and the addition of diodes, the overall device reliability will not deteriorate, and the on-resistance is basically unchanged compared with the conventional cascade resistance, which will not affect the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0029] Figure 1A circuit diagram of a first semiconductor cascade structure provided by an embodiment of the present invention;

[0030] Figure 2 for Figure 1 A schematic diagram of an integrated structure of a first depletion-mode transistor and a second depletion-mode transistor;

[0031] Figure 3 A circuit diagram of a second semiconductor cascade structure provided by an embodiment of the present invention;

[0032] Figure 4 A circuit diagram of a third semiconductor cascade structure provided by an embodiment of the present invention;

[0033] Figure 5 A circuit diagram of a fourth semiconductor cascade structure provided by an embodiment of the present invention;

[0034] Figure 6 A circuit diagram of a fifth semiconductor cascade structure provided by an embodiment of the present invention;

[0035] Figure 7 A circuit diagram of a sixth semiconductor cascade structure provided in an embodiment of the present invention.

[0036] icon:

[0037] 100-semiconductor cascade structure; 110-enhancement mode transistor; 120-first depletion mode transistor; 130-second depletion mode transistor; 131-third resistor; 140-diode; 150-depletion mode device; 151-substrate; 152-channel layer; 153-barrier layer; 154-dielectric layer; 155-source electrode; 156-drain electrode; 157-first gate electrode; 158-second gate electrode; 159-gate field plate; 160-first capacitor; 170-second capacitor; 180-first resistor; 190-second resistor; 191-third capacitor. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0039] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0041] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0042] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0043] As disclosed in the background technology, the existing cascode GaN (gallium nitride) device is composed of a low-voltage Si-MOSFET and a high-voltage depletion-type GaN HEMT in a cascode manner. The drain of the high-voltage depletion-type GaN HEMT is the drain of the cascade structure, and the gate of the low-voltage Si-MOSFET is the gate of the cascade structure, which ultimately realizes the enhanced function. The cascode GaN device of the cascode GaN device needs to package GaN HEMT, MOSFET and other components together in a certain connection method. HEMT is the main voltage-resistant device with a high saturation current density and low on-resistance, but it is difficult for the existing HEMT device to have a suitable saturation current density while ensuring low on-resistance, and the short-circuit capability is poor.

[0044] In order to solve the above problems, an embodiment of the present invention provides a novel semiconductor cascade structure. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.

[0045] See also Figure 1The embodiment of the present invention provides a semiconductor cascade structure 100 and an electronic device, which can reduce the saturation current of the cascode and improve its short-circuit capability, while the device reliability will not be deteriorated, the on-resistance remains basically unchanged, and the device performance will not be affected. In addition, no additional preparation process steps are required, no additional device cost is required, and the reliability of the device is further increased.

[0046] The semiconductor cascade structure 100 provided in an embodiment of the present invention includes an enhancement transistor 110, a first depletion transistor 120, a second depletion transistor 130 and a diode 140, wherein the source of the first depletion transistor 120 is connected to the drain of the enhancement transistor 110, wherein a parasitic capacitance Cgs is provided between the source and the gate of the first depletion transistor 120; the source of the second depletion transistor 130 is connected to the drain of the first depletion transistor 120, and the gate of the second depletion transistor 130 is connected to the source of the enhancement transistor 110; the anode of the diode 140 is connected to the gate of the first depletion transistor 120, and the cathode of the diode 140 is connected to the source of the enhancement transistor 110.

[0047] In some embodiments, the source of the enhancement mode transistor 110 is grounded, wherein the first depletion mode transistor 120, the second depletion mode transistor 130 and the enhancement mode transistor 110 can form a cascode circuit. In addition, the enhancement mode transistor 110 is an enhancement mode low voltage MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and its basic structure and working principle can refer to the existing MOSFET. At the same time, the first depletion mode transistor 120 and the second depletion mode transistor 130 can both be depletion mode gallium nitride high electron mobility transistors (d-HEMT).

[0048] It should be noted that the source of the first depletion-mode transistor 120 is set to S1, and the gate is set to G1; the drain of the second depletion-mode transistor 130 is set to D, and the gate is set to G2, and the source of the enhancement-mode transistor 110 is set to S0. Since there is a parasitic capacitance Cgs between the source S1 and the gate G1 of the first depletion-mode transistor 120, when the device is turned off, the voltage between the drain D of the second depletion-mode transistor 130 and the source S0 of the enhancement-mode transistor 110 will increase, so that there will also be a voltage difference between the source S1 of the first depletion-mode transistor and the source S0 of the enhancement-mode transistor 110. When Cgs is turned on, it will be charged through the diode 140, and the gate G1 of the first depletion-mode transistor 120 is also grounded through the diode 140. In the subsequent turn-on process, the voltage between the source S1 of the first depletion-mode transistor 120 and the source S0 of the enhancement-mode transistor 110 decreases. Since the diode 140 is in a reverse state, the charge on Cgs cannot be released, which will cause a relatively high positive voltage between the source S1 and the gate G1 of the first depletion-mode transistor 120, that is, the Vgs of the first depletion-mode transistor 120 is less than 0, thereby reducing the saturation current of the cascode and improving the short-circuit capability of the device.

[0049] See also Figure 2 In some embodiments, the first depletion-mode transistor 120 and the second depletion-mode transistor 130 are integrated in the same depletion-mode device 150. Specifically, the first depletion-mode transistor 120 and the second depletion-mode transistor 130 can be formed by the same d-HEMT, that is, through the reasonable distribution and preparation of the electrodes, the electrodes of the two depletion-mode transistors can be formed on the same substrate 151, so that the same depletion-mode device 150 constitutes the first depletion-mode transistor 120 and the second depletion-mode transistor 130. This arrangement allows the first depletion-mode transistor 120 and the second depletion-mode transistor 130 to be prepared at the same time without the need for separate additional preparation, so there is no need to increase the device cost, and the reliability of the device is further increased.

[0050] Of course, in other preferred embodiments of the present invention, the first depletion-mode transistor 120 and the second depletion-mode transistor 130 may also be prepared separately to form two independent transistors, and the two independent transistors are connected in series.

[0051] Furthermore, in some embodiments, the depletion-mode device 150 includes a substrate 151, a channel layer 152, a barrier layer 153, a dielectric layer 154, a source electrode 155, a drain electrode 156, a first gate electrode 157, and a second gate electrode 158. The substrate 151 may be silicon carbide (SiC), silicon (Si), sapphire, and gallium nitride (GaN), etc. The channel layer 152 is disposed on the substrate 151. In order to improve the crystal quality of the channel layer 152, a dielectric layer 154 may be formed between the substrate 151 and the channel layer 157. A nucleation layer and a buffer layer are arranged between the layers 152, and the channel layer 152 can be gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (AlInGaN), indium gallium nitride (InGaN), etc. At the same time, a barrier layer 153 is arranged on the channel layer 152, and the barrier layer 153 can be aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (AlInGaN), indium gallium nitride (InGaN), etc. The dielectric layer 154 can be silicon nitride (SiN) or silicon oxide (SiO 2 ) or a composite layer of the two, the dielectric layer 154 is arranged on the semiconductor, wherein the materials and preparation process of the channel layer 152, the barrier layer 153 and the dielectric layer 154 can refer to the existing HEMT structure. The source electrode 155 and the drain electrode 156 are spaced apart in the dielectric layer 154 and contact the channel layer 152, wherein the channel layer 152 forms a two-dimensional electron gas (2DEG) at the interface close to the barrier layer 153, the first gate electrode 157 and the second gate electrode 158 are spaced apart in the dielectric layer 154 and are located between the source electrode 155 and the drain electrode 156, the first gate electrode 157 is close to the source electrode 155, and together with the source electrode 155 and the 2DEG between the first gate electrode 157 and the second gate electrode 158 constitute a first depletion-mode transistor 120, the second gate electrode 158 is close to the drain electrode 156, and together with the drain electrode 156 and the 2DEG between the first gate electrode 157 and the second gate electrode 158 constitute a second depletion-mode transistor 130, thereby forming the structure of the first depletion-mode transistor 120 and the second depletion-mode transistor 130 in the same HEMT structure.

[0052] It should be noted that in this embodiment, the first gate electrode 157 and the second gate electrode 158 are spaced apart from the barrier layer 153. Under the action of the two-dimensional electron gas, the equivalent drain of the first depletion-mode transistor 120 is directly connected to the equivalent source of the second depletion-mode transistor 130. Therefore, the preparation of the metal electrode between the first gate electrode 157 and the second gate electrode 158 can be omitted, simplifying the structure and process steps. In some embodiments, the depletion-mode device 150 in this embodiment can also be used in a direct drive circuit, and its specific structure is not described in detail here.

[0053] In some embodiments, the depletion-mode device 150 further includes a gate field plate 159, which is disposed on the dielectric layer 154 and covers the side of the second gate electrode 158 away from the substrate 151. Specifically, the breakdown voltage of the first depletion-mode transistor 120 is less than that of the second depletion-mode transistor 130. For example, the breakdown voltage of the first depletion-mode transistor 120 is 50V, and the breakdown voltage of the second depletion-mode transistor 130 is greater than 650V. The first depletion-mode transistor 120 and the second depletion-mode transistor 130 are connected in series. Therefore, the breakdown voltage of the second depletion-mode transistor 130 can be increased by adding the structure of the gate field plate 159. The breakdown voltage requirement of the first depletion-mode transistor 120 is relatively low, so a field plate is not required. Of course, in some preferred embodiments, in order to optimize the local electric field or improve manufacturability, the first gate electrode 157 can also appropriately use a field plate structure.

[0054] See also Figure 3 In some embodiments, the semiconductor cascade structure 100 further includes a first capacitor 160 (C1 in the figure), one end of the first capacitor 160 is connected to the source of the first depletion-mode transistor 120, and the other end of the first capacitor 160 is connected to the gate of the first depletion-mode transistor 120. Specifically, the first capacitor 160 can affect the saturation current, and the saturation current can be reduced in a wide range by increasing the first capacitor 160, that is, the capacitance value of the first capacitor 160 and the saturation current can be negatively correlated, thereby further improving the short-circuit capability.

[0055] See also Figure 4 In some embodiments, the semiconductor cascade structure 100 further includes a second capacitor 170 (C2 in the figure), one end of the second capacitor 170 is connected to the anode of the diode 140, and the other end of the second capacitor 170 is connected to the cathode of the diode 140, so that the second capacitor 170 is connected in parallel with the diode 140. Specifically, the second capacitor 170 can also adjust the saturation current, and its adjustment function is opposite to that of the first capacitor 160. Generally, while reducing the saturation current, the on-resistance of the device will also increase to a certain extent. The second capacitor 170 can optimize the on-resistance of the device while maintaining an appropriate saturation current.

[0056] It should be noted that, in some embodiments, the first capacitor 160 and the second capacitor 170 may also exist at the same time, so that the first capacitor 160 and the second capacitor 170 can affect the size of the saturation current within different adjustment ranges, thereby achieving better adjustability.

[0057] In some embodiments, the diode 140 is a voltage regulator diode 140. Specifically, the diode 140 can be a 12V voltage regulator. When the voltage regulator is used, the Vgs of the first depletion-mode transistor 120 when turned on can be kept constant and will not be affected by capacitance or voltage, thereby making the performance of the entire device more stable. The voltage regulator voltage of the voltage regulator can be selected according to the threshold voltage of the first depletion-mode transistor. Generally speaking, the more positive the threshold voltage of the first depletion-mode transistor is (the smaller the absolute value is), the lower the voltage regulator voltage selected by the voltage regulator is, and vice versa.

[0058] See also Figure 5 In some embodiments, the semiconductor cascade structure 100 further includes a first resistor 180, one end of the first resistor 180 is connected to the cathode of the diode 140, and the other end of the first resistor 180 is connected to the source of the enhancement mode transistor 110, so that the first resistor 180 and the diode 140 are connected in series. Specifically, the first resistor 180 is arranged between the cathode of the diode 140 and the source of the enhancement mode transistor 110, and the first resistor 180 is connected in series with the diode 140 and in parallel with the second depletion mode transistor 130. By setting a damping circuit, it is possible to suppress oscillation and improve the stability of the device.

[0059] See also Figure 6 In some embodiments, the semiconductor cascade structure 100 further includes a second resistor 190 and a third capacitor 191, one end of the second resistor 190 is connected to the drain of the enhancement transistor 110, the other end of the second resistor 190 is connected to the source of the enhancement transistor 110, one end of the third capacitor 191 is connected to the drain of the enhancement transistor 110, and the other end of the third capacitor 191 is connected to the source of the enhancement transistor 110, so that the second resistor 190, the third capacitor 191 and the enhancement transistor 110 are connected in parallel. Specifically, by additionally providing the second resistor 190 and the third capacitor 191, the oscillation can be stabilized and the reliability of the device can be improved.

[0060] See also Figure 7 In some embodiments, the semiconductor cascade structure 100 further includes a third resistor 131, one end of the third resistor 131 is connected to the gate of the second depletion-mode transistor 130, and the other end is connected to the source of the enhancement-mode transistor 110. By setting the third resistor 131, the switching speed of the device can be controlled and oscillation can be suppressed.

[0061] It should be noted that the semiconductor cascade structure 100 provided in this embodiment, such as Figure 1As shown, in an actual device, since the device has parasitic capacitance, there will be a parasitic capacitance Cgs between the source S1 and the gate G1 of the first depletion-mode transistor 120. When the device is turned off, the voltage between the drain D of the second depletion-mode transistor 130 and the source S0 of the enhancement-mode transistor 110 will increase, which will cause a voltage difference between S1 and S0. At this time, Cgs will be charged through the diode 140 (the diode 140 is forward-conducted), and G1 is also grounded through the diode 140. In the subsequent opening process, the voltage between S1 and S0 of the device decreases. Since the diode 140 is in a reverse state, the charge on Cgs cannot be released, which will cause a relatively high positive voltage between S1 and G1, that is, Vgs of the first depletion-mode transistor 120 is less than 0, so that the saturation current of the first depletion-mode transistor 120 and the entire cascode will decrease, and the short-circuit capability of the device will be improved.

[0062] An embodiment of the present invention also provides an electronic device, including the aforementioned semiconductor cascade structure 100. The electronic device can be a high-voltage device, for example, an electronic device including a Cascode common-source and common-gate power device. In an embodiment of an application, the electronic device adopts the aforementioned semiconductor cascade structure 100 during packaging. The semiconductor cascade structure 100 includes an enhancement transistor 110, a first depletion transistor 120, a second depletion transistor 130 and a diode 140. The source of the first depletion transistor 120 is connected to the drain of the enhancement transistor 110, wherein a parasitic capacitance Cgs is provided between the source and the gate of the first depletion transistor 120; the source of the second depletion transistor 130 is connected to the drain of the first depletion transistor 120, and the gate of the second depletion transistor 130 is connected to the source of the enhancement transistor 110; the anode of the diode 140 is connected to the gate of the first depletion transistor 120, and the cathode of the diode 140 is connected to the source of the enhancement transistor 110.

[0063] In summary, the semiconductor cascade structure 100 and the electronic device provided in the embodiment of the present invention connect the source of the first depletion-mode transistor 120 to the drain of the enhancement-mode transistor 110, connect the source of the second depletion-mode transistor 130 to the drain of the first depletion-mode transistor 120, and realize series connection. The gate of the second depletion-mode transistor 130 is connected to the source of the enhancement-mode transistor 110, and the anode of the diode 140 is connected to the gate of the first depletion-mode transistor 120, and the cathode of the diode 140 is connected to the source of the enhancement-mode transistor 110, thereby forming a cascode circuit. Since there is a parasitic capacitance Cgs between the source and the gate of the first depletion-mode transistor 120, when the device is turned off, the second depletion-mode transistor 130 is connected to the source of the enhancement-mode transistor 110. The voltage between the drain of transistor 130 and the source of enhancement transistor 110 will increase, so that there will also be a voltage difference between the source of the first depletion transistor and the source of enhancement transistor 110. At this time, Cgs will be charged through diode 140, and the gate of the first depletion transistor 120 is also grounded through diode 140. In the subsequent opening process, the voltage between the source of the first depletion transistor 120 and the source of the enhancement transistor 110 decreases. Since diode 140 is in a reverse state, the charge on Cgs cannot be released, which will cause a relatively high positive voltage between the source and gate of the first depletion transistor 120, thereby reducing the saturation current of the cascode and improving the short-circuit capability of the device. Compared with the prior art, the semiconductor cascade structure 100 and the electronic device provided in the embodiment of the present invention can reduce the saturation current of the cascode and improve its short-circuit capability. At the same time, due to the use of depletion transistors in series and the addition of the diode 140, the overall device reliability will not be deteriorated, and the on-resistance is basically unchanged compared with the conventional cascade resistance, which will not affect the device performance.

[0064] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor cascade structure, characterized in that: include: Enhancement mode transistor; a first depletion-mode transistor, wherein a source of the first depletion-mode transistor is connected to a drain of the enhancement-mode transistor, wherein a parasitic capacitance Cgs is provided between the source and the gate of the first depletion-mode transistor; a second depletion-mode transistor, wherein a source of the second depletion-mode transistor is connected to a drain of the first depletion-mode transistor, and a gate of the second depletion-mode transistor is connected to a source of the enhancement-mode transistor; A diode, wherein an anode of the diode is connected to the gate of the first depletion-mode transistor, and a cathode of the diode is connected to the source of the enhancement-mode transistor.

2. The semiconductor cascade structure according to claim 1, characterized in that: The first depletion-mode transistor and the second depletion-mode transistor are integrated in the same depletion-mode device.

3. The semiconductor cascade structure according to claim 2, characterized in that: The depletion mode device comprises: substrate; a channel layer, wherein the channel layer is disposed on the substrate; a barrier layer, the barrier layer being disposed on the channel layer; a dielectric layer, wherein the dielectric layer is disposed on the barrier layer; A source electrode and a drain electrode, wherein the source electrode and the drain electrode are arranged in the dielectric layer at intervals and contact the channel layer; A first gate electrode and a second gate electrode, wherein the first gate electrode and the second gate electrode are spaced apart in the dielectric layer and located between the source electrode and the drain electrode, the first gate electrode is close to the source electrode, and the second gate electrode is close to the drain electrode.

4. The semiconductor cascade structure according to claim 3, characterized in that: The depletion-mode device further comprises a gate field plate, which is disposed on the dielectric layer and covers a side of the second gate electrode away from the substrate.

5. The semiconductor cascade structure according to claim 1, characterized in that: The semiconductor cascade structure further includes a first capacitor, one end of which is connected to the source of the first depletion-mode transistor, and the other end of which is connected to the gate of the first depletion-mode transistor.

6. The semiconductor cascade structure according to claim 1 or 5, characterized in that: The semiconductor cascade structure further includes a second capacitor, one end of the second capacitor is connected to the anode of the diode, and the other end of the second capacitor is connected to the cathode of the diode, so that the second capacitor is connected in parallel with the diode.

7. The semiconductor cascade structure according to claim 1, characterized in that: The diode is a voltage stabilizing diode.

8. The semiconductor cascade structure according to claim 1, characterized in that: The semiconductor cascade structure further includes a first resistor, one end of which is connected to the cathode of the diode, and the other end of which is connected to the source of the enhancement transistor, so that the first resistor and the diode are connected in series.

9. The semiconductor cascade structure according to claim 1, characterized in that: The semiconductor cascade structure further includes a second resistor and a third capacitor, one end of the second resistor is connected to the drain of the enhancement transistor, the other end of the second resistor is connected to the source of the enhancement transistor, one end of the third capacitor is connected to the drain of the enhancement transistor, and the other end of the third capacitor is connected to the source of the enhancement transistor, so that the second resistor, the third capacitor and the enhancement transistor are connected in parallel; and / or, The semiconductor cascade structure further includes a third resistor, one end of which is connected to the gate of the second depletion-mode transistor, and the other end of which is connected to the source of the enhancement-mode transistor.

10. An electronic device, characterized in that: Comprising the semiconductor cascade structure as claimed in any one of claims 1 to 9.

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