A gate control circuit and a motor control system

Abstract

The present application provides a gate control circuit and a motor control system, relating to the technical field of motor drive. The gate control circuit includes a power-on / off control unit, a logic control unit, a power management unit, and a gate drive unit; the power supply terminal of the power-on / off control unit is used to connect to a preset high-voltage power supply, and the first output terminal of the power-on / off control unit is connected to the enable terminal of the power management unit to enable the power-on / off control unit to output an enable current based on a key signal; the second output terminal of the power-on / off control unit is connected to the input terminal of the logic control unit, so that the logic control unit generates a logic signal of the power-on / off state based on the key signal, and the output terminal of the logic control unit is connected to the gate drive unit, so that the gate drive unit generates and outputs a corresponding gate drive signal based on the logic signal of the logic control unit. The gate control circuit of the present application can achieve zero current during shutdown.

Description

Technical Field

[0001] The present application relates to the technical field of motor drive, and more particularly, to a gate control circuit and a motor control system. Background Art

[0002] In the power management system of modern electronic devices, the gate drive circuit plays a crucial role. In the traditional gate drive architecture, generally, a logic control unit is directly connected to the gate drive unit, and the working state of the gate drive unit is directly controlled by the signal generated by the logic control unit, so as to effectively drive the gate of the power device, and then control the conduction and cut-off of the power device to meet the requirements of the circuit for power conversion and control.

[0003] However, currently, the power consumption requirements for electronic devices in the shutdown state are becoming increasingly stringent. The gate drive circuit usually directly controls the gate drive unit through the logic control unit. Some methods rely on the logic controller software to always keep running. Even when the device is in the shutdown state, the logic controller software continuously monitors and processes relevant signals to quickly control the gate drive unit to achieve zero current consumption when needed. However, this method will inevitably consume a certain amount of electric energy and cannot truly achieve zero current consumption in the shutdown state. Another method is that the user toggles the switch to cut off the power supply of the entire system to achieve zero current, but the operation is inconvenient and the control method is not flexible. Summary of the Invention

[0004] In view of the above deficiencies in the prior art, the present application provides a gate control circuit and a motor control system to solve the problems existing in the prior art.

[0005] The technical solutions adopted in the embodiments of the present application are as follows:

[0006] In a first aspect, an embodiment of the present application provides a gate control circuit, including: a power-on / off control unit, a logic control unit, a power management unit, and a gate drive unit;

[0007] The power supply terminal of the power-on / off control unit is used to connect to a preset high-voltage power supply, and the first output terminal of the power-on / off control unit is connected to the enable terminal of the power management unit to enable the power-on / off control unit to output an enable current based on a key signal;

[0008] The first output terminal of the power management unit is connected to the power supply terminal of the logic control unit to provide a power supply, and the second output terminal of the power management unit is connected to the drive terminal of the gate drive unit to provide a drive power supply;

[0009] The second output terminal of the power-on / off control unit is connected to the input terminal of the logic control unit, so that the logic control unit generates a logic signal of the power-on / off state based on the key signal, and the output terminal of the logic control unit is connected to the gate drive unit, so that the gate drive unit generates and outputs a corresponding gate drive signal based on the logic signal of the logic control unit.

[0010] In one embodiment, the power-on / off control unit includes: a key control circuit, a power-on / off detection circuit, a bias current generation circuit, and an enable current output circuit;

[0011] The first terminal of the key control circuit is the power supply terminal of the power-on / off control unit for connecting to the preset high-voltage power supply. The second terminal of the key control circuit is connected to the input terminal of the power-on / off detection circuit, so that the power-on / off detection circuit generates a detection current based on the key signal output by the key control circuit. The output terminal of the power-on / off detection circuit is connected to the input terminal of the bias current generation circuit, so that the bias current generation circuit generates a bias current based on the detection current. The output terminal of the bias current generation circuit is connected to the enable current output circuit, so that the enable current output circuit generates and outputs the enable current based on the bias current;

[0012] The third terminal of the key control circuit is the second output terminal of the power-on / off control unit for connecting to the input terminal of the logic control unit.

[0013] In one embodiment, the key control circuit includes: a first resistor, a second resistor, and a single-key switch;

[0014] One end of the first resistor is the first terminal of the key control circuit. The other end of the first resistor is connected to one end of the single-key switch. The other end of the single-key switch is the second terminal of the key control circuit for connecting to the input terminal of the power-on / off detection circuit. The other end of the single-key switch is also connected to the input terminal of the logic control unit through the second resistor.

[0015] In one embodiment, the power-on / off detection circuit includes: a first current mirror unit, a second current mirror unit, a voltage regulator diode, and a third resistor;

[0016] The power supply terminal of the first current mirror unit is the input terminal of the power-on / off detection circuit. The current input terminal of the first current mirror unit is grounded through the third resistor. The current output terminal of the first current mirror unit is the output terminal of the power-on / off detection circuit. The power supply terminal of the first current mirror unit is connected to the cathode of the zener diode, and the anode of the zener diode is grounded. The power supply terminal of the first current mirror unit is also connected to the current output terminal of the second current mirror unit, and the current input terminal of the second current mirror unit is connected to the output terminal of the bias current generation circuit.

[0017] In one embodiment, the first current mirror unit is a P-type current mirror unit composed of P-type triodes or a P-type current mirror unit composed of PMOS transistors;

[0018] The second current mirror unit is a P-type current mirror unit composed of P-type triodes or a P-type current mirror unit composed of PMOS transistors.

[0019] In one embodiment, the bias current generation circuit includes: a first N-type triode, a second N-type triode, a third N-type triode, a fourth N-type triode, and a fourth resistor;

[0020] One end of the fourth resistor is connected to the emitter of the second N-type triode, the other end of the fourth resistor is grounded, the base of the second N-type triode is connected to the collector of the first N-type triode and the emitter of the third N-type triode, and the collector of the second N-type triode is connected to the base of the first N-type triode and the emitter of the fourth N-type triode;

[0021] The emitter of the first N-type triode is grounded, the collector, the base of the third N-type triode, and the base of the fourth N-type triode are connected, and the collector of the third N-type triode is the input terminal of the bias current generation circuit;

[0022] The collector of the fourth N-type triode is connected to the current input terminal of the second current mirror unit.

[0023] In one embodiment, the enable current output circuit includes: a P-type switch transistor;

[0024] The control terminal of the P-type switch transistor is the input terminal of the enable current output circuit. One end of the P-type switch transistor is used to connect to the preset high-voltage power supply, and the other end of the P-type switch transistor is the output terminal of the enable current output circuit.

[0025] In one embodiment, the gate control circuit further includes: a state monitoring unit;

[0026] The state monitoring unit is connected to the power management unit and the gate drive unit.

[0027] In one embodiment, the power-on / off control unit, the logic control unit, the power management unit, the gate drive unit, and the status monitoring unit are integrated on a single chip.

[0028] In a second aspect, an embodiment of the present application further provides a motor control system, which at least includes the gate control circuit described in any one of the above embodiments.

[0029] The beneficial effects of the present application are as follows: The present application provides a gate control circuit, which includes a power-on / off control unit, a logic control unit, a power management unit, and a gate drive unit; the power supply terminal of the power-on / off control unit is used to connect to a preset high-voltage power supply, and the first output terminal of the power-on / off control unit is connected to the enable terminal of the power management unit, so as to enable the power-on / off control unit to output an enable current based on a key signal; the first output terminal of the power management unit is connected to the power supply terminal of the logic control unit to provide a power supply, and the second output terminal of the power management unit is connected to the drive terminal of the gate drive unit to provide a drive power supply; the second output terminal of the power-on / off control unit is connected to the input terminal of the logic control unit, so that the logic control unit generates a logic signal of the power-on / off state based on the key signal, and the output terminal of the logic control unit is connected to the gate drive unit, so that the gate drive unit generates and outputs a corresponding gate drive signal based on the logic signal of the logic control unit.

[0030] Among them, the power-on / off control unit outputs an enable current to the power management unit based on the key signal. When the enable current is zero, the power management unit will be disabled, the power output will be turned off, and the system will not consume current, achieving the purpose of zero current during shutdown. Moreover, there is no need for the user to manually toggle the switch to cut off the power, effectively solving the problems of inconvenient operation and insufficient control flexibility of the traditional power-off method. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0032] Figure 1 One of the structural schematic diagrams of the gate control circuit provided by the embodiment of the present application;

[0033] Figure 2 The structural schematic diagram of the power-on / off control unit provided by the embodiment of the present application;

[0034] Figure 3 The circuit principle schematic diagram of the gate control circuit provided by the embodiment of the present application;

[0035] Figure 4 This is the second schematic diagram of the gate control circuit provided by the embodiment of the present application;

[0036] Figure 5 This is a simplified flowchart of the on / off state of the gate control circuit;

[0037] Figure 6 These are the waveforms of the key node voltages and the power supply current during the operation of the gate control circuit;

[0038] Figure 7 This is the third schematic diagram of the gate control circuit provided by the embodiment of the present application. Detailed implementation manners

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some but not all of the embodiments of the present application.

[0040] Therefore, the detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.

[0041] In the description of the present application, it should be noted that if terms such as "upper", "lower", etc. are used to indicate the orientation or positional relationship, it is based on the orientation or positional relationship shown in the accompanying drawings or the orientation or positional relationship in which the product of this application is usually placed during use. This is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0042] In addition, terms such as "first", "second", etc. in the description and claims of the present application and the above accompanying drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application described here can be implemented in an order different from those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0043] In the description of the present application, it should also be noted that, unless otherwise clearly specified and limited, the terms "arrangement" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the communication inside two components. For those skilled in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0044] It should be noted that, without conflict, the features in the embodiments of the present application can be combined with each other.

[0045] In the power management system of modern electronic devices, the gate drive circuit plays a crucial role. In the traditional gate drive architecture, generally, a mode of directly connecting a logic control unit and a gate drive unit is adopted, and the working state of the gate drive unit is directly controlled by the signal generated by the logic control unit, so as to effectively drive the gate of a power device (such as a MOSFET, etc.), and then control the on and off of the power device to meet the requirements of the circuit for power conversion and control.

[0046] However, with the increasing popularity of the concept of energy efficiency, the power consumption requirements for electronic devices in the shutdown state are becoming more and more stringent. Under the framework of the existing technology, there are many challenges in achieving the goal of zero current consumption during shutdown. On the one hand, some methods rely on the logic controller software to always keep running. Even when the device is in the shutdown state, the logic controller software continuously monitors and processes relevant signals so as to quickly control the gate drive unit to achieve zero current consumption when needed. However, this method will inevitably consume a certain amount of electric energy, and cannot truly achieve zero current consumption during shutdown. At the same time, it increases the complexity of software design and the instability of the system, and the continuously running software may also bring potential security risks. On the other hand, some solutions attempt to achieve this through designing extremely complex power-on and -off hardware circuits. Such designs often require introducing a large number of additional electronic components, such as special switch circuits, energy storage components, and complex signal detection and switching circuits, etc. This not only greatly increases the complexity of the circuit, cost, and the occupied space of the circuit board, but also reduces the system reliability due to the increase in the number of components. The failure of any newly added component may cause the abnormality of the entire system.

[0047] Therefore, the present application provides a gate control circuit, which can solve the above technical problems. The following will specifically illustrate the gate control circuit provided by the present application through multiple examples in combination with the accompanying drawings.

[0048] Figure 1 is one of the structural schematic diagrams of the gate control circuit provided by the embodiments of the present application, as Figure 1As shown, the gate control circuit includes a power-on / off control unit, a logic control unit, a power management unit, and a gate drive unit.

[0049] Among them, the power supply terminal of the power-on / off control unit is used to connect to a preset high-voltage power supply V M , the first output terminal of the power-on / off control unit is connected to the enable terminal of the power management unit, and is used to enable the power-on / off control unit to output an enable current I EN based on the key signal. After the power management unit receives the enable current I EN , it starts to work. Specifically, the work of the power management unit includes: the first output terminal of the power management unit is connected to the power supply terminal of the logic control unit to provide a power supply V DD to the logic control unit, and the second output terminal of the power management unit is connected to the drive terminal of the gate drive unit to provide a drive power supply V CC to the gate drive unit.

[0050] The second output terminal of the power-on / off control unit is connected to the input terminal of the logic control unit, so that the logic control unit generates a logic signal of the power-on / off state based on the key signal. The output terminal of the logic control unit is connected to the gate drive unit, so that the gate drive unit generates and outputs a corresponding gate drive signal based on the logic signal of the logic control unit.

[0051] In the shutdown state, the current consumed by the power-on / off control unit is zero, and the enable current I EN is zero, which will turn off the power management unit and disconnect the system power supply, and the current consumed by the entire system is zero; when the power-on state is triggered by the key signal, the power-on / off control unit will automatically lock the power-on state, and the enable current I EN will remain valid, and the power management unit will remain working until the shutdown signal output by the logic control unit is detected. It should be noted that according to the design structure of the power management unit, the enable current I EN can also be converted into a voltage signal and sent to the power management unit to enable it.

[0052] In summary, the embodiment of the present application provides a gate control circuit. The power-on / off control unit outputs an enable current I EN to the power management unit based on the key signal. When the enable current I EN is zero, the power management unit will be disabled, the power output will be turned off, and the system will not consume current, achieving the purpose of zero current in shutdown. Moreover, there is no need for the user to manually toggle the switch to cut off the power, effectively solving the problems of inconvenient operation and insufficient control flexibility of the traditional power-off method.

[0053] Figure 2 is a schematic structural diagram of the power-on / off control unit provided by the embodiment of the present application. As shown in Figure 2As shown, in one embodiment, the power-on / off control unit includes a key control circuit, a power-on / off detection circuit, a bias current generation circuit, and an enable current output circuit.

[0054] Among them, the first end of the key control circuit is the power supply end of the power-on / off control unit, which is used to connect to a preset high-voltage power supply V M , the second end of the key control circuit is connected to the input end of the power-on / off detection circuit, so that the power-on / off detection circuit generates a detection current based on the key signal output by the key control circuit. The output end of the power-on / off detection circuit is connected to the input end of the bias current generation circuit, so that the bias current generation circuit generates a bias current based on the detection current; the output end of the bias current generation circuit is connected to the enable current output circuit, so that the enable current output circuit generates and outputs an enable current based on the bias current. The third end of the key control circuit is the second output end of the power-on / off control unit, which is used to connect to the input end of the logic control unit.

[0055] Figure 3 It is a schematic circuit diagram of the gate control circuit provided by the embodiment of the present application. As Figure 3 shown, the key control circuit includes a first resistor R1, a second resistor R2, and a single-key switch S1. Among them, the first resistor R1 is a current-limiting resistor between the preset high-voltage power supply V M and the power-on / off control unit, which can prevent excessive current from damaging the components in the circuit; the second resistor R2 is a protection resistor between the power-on / off control unit and the logic control unit, which plays a role in protecting the components; the single-key switch refers to a switch with only one operation button, and its structure is relatively simple. It mainly consists of components such as a button, a housing, a contact, and a spring. When the button is pressed, the internal contact will close or open, thereby realizing the on / off control of the circuit. The single-key switch has the advantage of simple operation. The user only needs to press or release the button to complete the control of the circuit without complex operation procedures.

[0056] One end of the first resistor R1 is the first end of the key control circuit, which is used to connect to the preset high-voltage power supply V M , the other end of the first resistor R1 is connected to one end of the single-key switch S1. The other end of the single-key switch is the second end of the key control circuit, which is used to connect to the input end of the power-on / off detection circuit. The other end of the single-key switch is also connected to the input end of the logic control unit through the second resistor R2. That is, one end of the second resistor R2 is the third end of the key control circuit.

[0057] Assume that the initial state of the gate control circuit is the shutdown state. The power-on / off control unit and the logic control unit work together to flexibly implement multiple power-on / off methods for the gate control circuit, including but not limited to the following: a. The user presses the single-key switch S1 to turn on the machine, and presses S1 again to turn off the machine; b. The user presses the single-key switch S1 to turn on the machine, and the logic control unit independently controls the shutdown; c. The user presses the single-key switch S1 to turn on the machine, and after pressing S1 again, the logic control unit controls the delayed shutdown; d. The user presses the single-key switch S1 to turn on the machine, and presses the key S1 multiple times to turn off the machine. The single-key switch S1 is set in the power-on / off control unit. The advantage is that only one external pin needs to be reserved after the chip integration to achieve the flexible power-on / off function.

[0058] Continue to refer to Figure 3 , the power-on / off detection circuit includes a first current mirror unit, a second current mirror unit, a zener diode V Z and a third resistor R EN . Among them, the first current mirror unit is a P-type current mirror unit composed of P-type triodes or a P-type current mirror unit composed of PMOS transistors. The second current mirror unit can also be a P-type current mirror unit composed of P-type triodes or a P-type current mirror unit composed of PMOS transistors.

[0059] Figure 3 The first current mirror unit shown includes P-type triodes Q P1 and P-type triodes Q P2 , the second current mirror unit includes P-type triodes Q P3 and P-type triodes Q P4 , the power supply terminal of the first current mirror unit (i.e., the emitters of Q P1 and Q P2 ) is the input terminal of the power-on / off detection circuit. The current input terminal of the first current mirror unit (i.e., the collector of Q P1 ) is grounded through the third resistor R EN . The current output terminal of the first current mirror unit (i.e., the collector of Q P2 ) is the output terminal of the power-on / off detection circuit. The power supply terminal of the first current mirror unit (i.e., the emitters of Q P1 and Q P2 ) is connected to the cathode of the zener diode V Z . The anode of the zener diode V Z is grounded. The power supply terminal of the first current mirror unit (the emitters of Q P1 and Q P2 ) is also connected to the current output terminal of the second current mirror unit (the collector of Q P3 ). The current input terminal of the second current mirror unit (the collector of Q P4 ) is connected to the output terminal of the bias current generation circuit.

[0060] The bias current generation circuit includes a first N-type triode Q N1 and a second N-type triode Q N2 and a third N-type triode Q N3 and a fourth N-type triode Q N4 and a fourth resistor R B . One end of the fourth resistor R B is connected to the emitter of the second N-type triode Q N2 , and the other end of the fourth resistor R B is grounded. The base of the second N-type triode Q N2 is connected to the collector of the first N-type triode Q N1 and the emitter of the third N-type triode Q N3 . The collector of the second N-type triode Q N2 is connected to the base of the first N-type triode Q N1 and the emitter of the fourth N-type triode Q N4 ; The emitter of the first N-type triode Q N1 is grounded. The collector of the third N-type triode Q N3 , the base of the third N-type triode Q N3 and the base of the fourth N-type triode Q N4 are connected. The collector of the third N-type triode Q N3 is the input end of the bias current generation circuit; The collector of the fourth N-type triode Q N4 is connected to the current input end of the second current mirror unit.

[0061] The enable current output circuit includes a P-type switch tube. The control end of the P-type switch tube is the input end of the enable current output circuit. One end of the P-type switch tube is used to connect to a preset high-voltage power supply, and the other end of the P-type switch tube is the output end of the enable current output circuit.

[0062] Among them, the P-type switch tube can be Figure 3 the P-type triode Q P5 shown, or it can also be a P-type MOS tube (not shown in the figure).

[0063] Figure 4 FIG. is the second structural schematic diagram of the gate control circuit provided by the embodiment of the present application. As Figure 4 shown, the gate control circuit may further include a status monitoring unit. The status monitoring unit is connected to the power management unit and the gate driving unit to monitor the system operation status. When the system is abnormal, the power management unit or the gate driving unit is turned off. The monitored abnormal statuses include but are not limited to system over-temperature, over-current, over-voltage, under-voltage, etc.

[0064] The status monitoring unit improves the reliability of the system, plays a role in protecting the safety of the equipment, and also ensures the safety of the staff.

[0065] The working principle of the entire gate control circuit is as follows: In the shutdown state, all units do not work. At this time, Q P3 , Q P4 , Q P5 are all in the cut-off state, and the current consumption of the on-off control unit is zero. Since the current of Q P5 is zero, the power management unit does not work either, and the output voltages of V CC and V DD are both zero. The gate drive unit, the status monitoring unit, and the logic control unit do not work, and the entire system does not consume current. When starting up, press S1, and the preset high-voltage power supply V M generates current, which flows through the resistor R1 and S1 into the V EN node. When the voltage of V EN reaches the conduction voltage V P1 of the PNP transistor Q BEP , the branch of Q P1 and the resistor R EN will conduct, and at the same time, mirror the current to the Q P2 transistor. The current of the Q P2 transistor is injected into the Q N3 transistor as the startup current. When V EN continues to rise to be greater than 2×V BEN , it will cause the bias current generation circuit composed of Q N1 , Q N2 , Q N3 , Q N4 and R B to conduct. The current I B in the R RB branch is: , where V T is the thermoelectric potential, N is the emitter area ratio of Q N2 and Q N4 . This current is mirrored by the Q P4 transistor to the Q P3 and Q P5 transistors. The Q P5 transistor delivers the enable current I EN to the power management unit, enabling the power management unit to work, and outputting the power supplies V CC and V DD to make the entire gate control circuit start running.

[0066] Since there is a zener diode V EN at the V Z node, after pressing S1, the highest voltage of V EN will reach the clamping voltage V1 of the V Z transistor. At this time, if S1 is released, the path from the power supply V M to V EN is cut off. However, due to QP3 The tube has been turned on, generating a pull-up current injected into V EN node, making V EN node maintained at the turn-on voltage of 2×V BEN or above. The entire gate control circuit still works properly, and the power-on state is locked.

[0067] Among them, the locking voltage of V EN is determined by the current of Q P3 tube and the resistance value of resistor R EN . The locking voltage V0 of the locking state V EN should be between the start-up voltage of 2×V BEP and the zener diode clamping voltage V1. After the gate control circuit is powered on, the logic control unit works, outputs a logic signal to the gate drive unit according to the user's instruction to make it operate as required, and outputs a converted gate drive signal.

[0068] The control of the gate control circuit to shut down can be flexibly implemented in multiple ways. One is the direct control of the logic control unit. When the user has not operated for a long time, the pin of the logic control unit connected to R2 can directly output a low level to discharge the V EN node. When the V EN voltage is less than the start-up voltage of 2×V BEP , both the Q P2 branch and the Q N2 branch are cut off, making the pull-up current of Q P3 and the enable current of Q P5 both zero. The power management unit will turn off the output of V CC and V DD . The entire gate drive unit does not work and returns to the shutdown state. At this time, even if the low level of the pin of the logic control unit connected to R2 fails, since there is no pull-up branch for V EN , V EN still remains low.

[0069] Another way is that after the single-key switch S1 is pressed again, the logic control unit decides when to shut down the system. At this time, the logic control unit needs to detect the V EN level. Specifically: after power-on self-locking, the V EN voltage is the locking voltage V0. After the logic control unit is powered on and starts, it begins to monitor the V EN voltage. When the single-key switch S1 is pressed again, V EN will be pulled up again by resistor R1 to the clamping voltage V1. The logic control unit detects the level flip from V0 to V1, indicating that the single-key switch S1 has been pressed, but it needs to continue to monitor the V EN voltage until after the single-key switch S1 is released and V EN becomes the locking voltage V0. The logic control unit detects V ENAfter the change from V1 to V0, it means that the single - key switch S1 is released. After detecting this key operation, the logic control unit then decides when to shut down the system. When shutting down, the I / O port of the logic control unit connected to R2 only needs to output a low level to pull down V EN to make the gate control circuit enter the off state. Figure 5 It is a simplified flowchart of the above - mentioned power - on and power - off states.

[0070] Figure 6 They are the waveforms of the key - node voltage and the power - supply current when the gate control circuit is running. From top to bottom, they are the state of the single - key switch S1 (high level represents pressed, low level represents released), V EN node voltage, V CC power - supply voltage, V DD power - supply voltage, and the overall system current I Q waveform. It can be seen that initially the gate control circuit is in the off state, the V EN voltage is 0.4V (the startup voltage is 1.4V), the power - on and power - off control unit is in the off state, V CC and V DD both output 0V, and the total current of the gate control circuit is 10nA, which can be basically ignored. When the single - key switch S1 is pressed for the first time, the V EN voltage is pulled up to 5V (the clamping voltage of the V Z tube is 5V), the gate control circuit starts to start, V CC and V DD output 12V and 5V voltages respectively, and the stable operating current consumption of the gate control circuit when powered on is 30mA. After the single - key switch S1 is released, the V EN voltage is locked at 3V. When the single - key switch S1 is pressed again, V EN is pulled up to 5V again. After the logic control unit detects the rising edge from 3V to 5V, it continuously monitors the key state. When the single - key switch S1 is released, the V EN voltage will drop. After the logic control unit detects the falling edge of V EN , it will output a low level to directly pull V EN to 0V. At this time, V CC and V DD are turned off, and the current of the gate control circuit decreases to 10nA and is in the off state again.

[0071] It should also be noted that the gate - drive signal output by the gate - drive unit can be single - channel or multi - channel. Whether it is single - channel or multi - channel is determined by the number of gate - drive units. For example, Figure 1 as shown, when there is only one gate - drive unit, a single - channel gate - drive signal is output, which can be used to drive a single - phase motor; for another example, Figure 7As shown, when there are three gate drive units, a three-channel gate drive signal is output, which can be used to drive a three-phase motor.

[0072] In one embodiment, the power-on / off control unit, logic control unit, power management unit, gate drive unit, and status monitoring unit described in the above embodiments of the present application are all integrated on a single chip, and have the following functions:

[0073] 1. Volume reduction: Integrating multiple units on a single chip eliminates the need to use multiple discrete components and circuit boards as in traditional circuits to implement these functions, greatly reducing the volume of the entire system and facilitating the miniaturization and thinness of the device.

[0074] 2. Cost reduction: The integrated design reduces the number of discrete components used, as well as the corresponding circuit board area, packaging materials, etc., reducing the raw material cost. At the same time, the assembly, testing, and other processes during production are also simpler and more efficient, reducing labor costs and time costs, improving production efficiency, and thus reducing the overall production cost.

[0075] 3. Performance improvement: Each unit is connected and communicates through a high-speed, low-latency internal bus or circuit inside the chip, with fast signal transmission speed and better realization of collaborative work and precise synchronization between units. For example, the logic control unit and the gate drive unit can quickly transmit control signals to achieve precise control of power devices, improving the response speed and stability of the system; the power management unit can quickly adjust the supply voltage and current according to the actual needs of the system, providing a stable and efficient power supply for other units, helping to improve the performance of the entire system.

[0076] 4. Power consumption reduction: The integrated chip can adopt more advanced low-power design technologies and processes to optimize the power consumption management of each unit. For example, the power management unit can dynamically adjust the power supply according to the working state of the system, enabling the chip to maintain a low power consumption under different load conditions; the status monitoring unit can monitor the working state of the chip in real time, and when it finds that some units are in an idle state, it notifies the power management unit to reduce the power consumption of this part, thereby effectively reducing the energy consumption of the entire chip and extending the usage time of battery-powered devices.

[0077] 5. Improve reliability: The connection lines and interfaces between discrete components are reduced, lowering the probability of failures caused by poor connections, line interference, etc. Moreover, during the design and production processes, chip manufacturers can conduct overall reliability design and testing on integrated chips to ensure the compatibility and stability between individual units, enhancing the reliability and anti-interference ability of the chips in various working environments. For example, the status monitoring unit can monitor key parameters such as the temperature and voltage of the chip in real time, and take protective measures promptly when abnormalities are detected to prevent the chip from being damaged due to overheating, overvoltage, etc.

[0078] 6. Simplify the design and production processes: For equipment manufacturers, using a chip that integrates multiple functional units simplifies the circuit design process, reducing the complexity and workload of the design. At the same time, it also reduces the difficulty of quality management and control during the production process because only a single chip needs to be purchased, inspected, and assembled instead of managing multiple discrete components, which helps improve the product consistency and production efficiency.

[0079] Based on the gate control circuit provided in the above embodiments, the present application also provides a motor control system, which at least includes the gate control circuit described in any of the above embodiments.

[0080] Optionally, the motor control system may further include a power drive circuit and a motor. Among them, the gate control circuit is mainly used to control the gate voltage of power switching devices (such as MOSFETs, IGBTs, etc.), thereby controlling the conduction and turn-off of the power switching devices to achieve precise control of the current in the motor winding. It can generate appropriate pulse width modulation (PWM) signals according to the requirements of motor control to drive the power switching devices, and then adjust parameters such as the speed and torque of the motor; the power drive circuit is connected between the gate control circuit and the motor, converting the weak electrical signals output by the gate control circuit into strong electrical signals capable of driving the motor, providing sufficient power for the motor. It usually includes components such as power amplifiers and freewheeling diodes to ensure that the motor can operate normally under various working conditions; the motor, as the execution component of the system, converts electrical energy into mechanical energy to achieve rotational or linear motion to drive the load. Different types of motors, such as DC motors, AC induction motors, and permanent magnet synchronous motors, can be selected according to different application scenarios.

[0081] The above are only the specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A gate control circuit, characterized in that: include: Switch control unit, logic control unit, power management unit and gate drive unit; The power supply terminal of the power on / off control unit is used to connect to a preset high voltage power supply, and the first output terminal of the power on / off control unit is connected to the enable terminal of the power management unit, so that the power on / off control unit outputs an enable current based on a key signal; The first output end of the power management unit is connected to the power supply end of the logic control unit to provide power supply, and the second output end of the power management unit is connected to the driving end of the gate driving unit to provide driving power; The second output terminal of the power on / off control unit is connected to the input terminal of the logic control unit, so that the logic control unit generates a logic signal of the power on / off state based on the key signal, and the output terminal of the logic control unit is connected to the gate driving unit, so that the gate driving unit generates and outputs a corresponding gate driving signal based on the logic signal of the logic control unit; The power on / off control unit includes: a key control circuit, a power on / off detection circuit, a bias current generating circuit, and an enabling current output circuit; The first end of the key control circuit is the power supply end of the power on / off control unit, and is used to connect the preset high-voltage power supply. The second end of the key control circuit is connected to the input end of the power on / off detection circuit, so that the power on / off detection circuit generates a detection current based on the key signal output by the key control circuit. The output end of the power on / off detection circuit is connected to the input end of the bias current generating circuit, so that the bias current generating circuit generates a bias current based on the detection current. The output end of the bias current generating circuit is connected to the enable current output circuit, so that the enable current output circuit generates and outputs the enable current based on the bias current. The third terminal of the button control circuit is the second output terminal of the power on / off control unit, and is used to connect to the input terminal of the logic control unit; The power on / off detection circuit comprises: a first current mirror unit, a second current mirror unit, a voltage regulator tube and a third resistor; The power supply end of the first current mirror unit is the input end of the power on / off detection circuit, the current input end of the first current mirror unit is grounded through the third resistor, the current output end of the first current mirror unit is the output end of the power on / off detection circuit, the power supply end of the first current mirror unit is connected to the cathode of the voltage regulator tube, the anode of the voltage regulator tube is grounded, the power supply end of the first current mirror unit is also connected to the current output end of the second current mirror unit, and the current input end of the second current mirror unit is connected to the output end of the bias current generating circuit; The first current mirror unit includes: a first P-type transistor and a second P-type transistor; the second current mirror unit includes: a third P-type transistor and a fourth P-type transistor; the base of the first P-type transistor is connected to the base of the second P-type transistor, the emitter of the first P-type transistor is connected to the emitter of the second P-type transistor, and the collector of the first P-type transistor is connected to the base of the second P-type transistor; the base of the third P-type transistor is connected to the base of the fourth P-type transistor, the emitter of the third P-type transistor is connected to the emitter of the fourth P-type transistor, the emitter of the third P-type transistor is also used to connect to the preset high-voltage power supply, and the base of the third P-type transistor is connected to the collector of the fourth P-type transistor; The emitter of the first P-type transistor and the emitter of the second P-type transistor are the power supply terminals of the first current mirror unit, the collector of the first P-type transistor is the current input terminal of the first current mirror unit, and the collector of the second P-type transistor is the current output terminal of the first current mirror unit; the collector of the third P-type transistor is the current output terminal of the second current mirror unit, and the collector of the fourth P-type transistor is the current input terminal of the second current mirror unit; the emitter of the first P-type transistor is grounded through the voltage regulator, and the collector of the first P-type transistor is grounded through the third resistor.

2. The gate control circuit according to claim 1, characterized in that: The key control circuit comprises: a first resistor, a second resistor and a single-key switch; One end of the first resistor is the first end of the button control circuit, the other end of the first resistor is connected to one end of the single-key switch, the other end of the single-key switch is the second end of the button control circuit, and is used to connect the input end of the power on / off detection circuit, and the other end of the single-key switch is also connected to the input end of the logic control unit through the second resistor.

3. The gate control circuit according to claim 1, characterized in that: The bias current generating circuit comprises: a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor and a fourth resistor; One end of the fourth resistor is connected to the emitter of the second N-type transistor, the other end of the fourth resistor is grounded, the base of the second N-type transistor is connected to the collector of the first N-type transistor and the emitter of the third N-type transistor, and the collector of the second N-type transistor is connected to the base of the first N-type transistor and the emitter of the fourth N-type transistor; The emitter of the first N-type transistor is grounded, the collector of the third N-type transistor, the base of the third N-type transistor and the base of the fourth N-type transistor are connected, and the collector of the third N-type transistor is the input end of the bias current generating circuit; The collector of the fourth N-type transistor is connected to the current input end of the second current mirror unit.

4. The gate control circuit according to claim 1, characterized in that: The enabling current output circuit comprises: a P-type switch tube; The control end of the P-type switch tube is the input end of the enable current output circuit, one end of the P-type switch tube is used to connect to the preset high voltage power supply, and the other end of the P-type switch tube is the output end of the enable current output circuit.

5. The gate control circuit according to claim 1, characterized in that: The gate control circuit further includes: a state monitoring unit; The state monitoring unit is connected to the power management unit and the gate driving unit.

6. The gate control circuit according to claim 5, characterized in that: The on / off control unit, the logic control unit, the power management unit, the gate driving unit and the state monitoring unit are integrated on one chip.

7. A motor control system, characterized in that: At least: The gate control circuit according to any one of claims 1 to 6.

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