Power supply selection switch circuit and power amplifier module with power supply selection switch circuit

Abstract

The present disclosure provides a power selection switch circuit configured to select any one of a first power supply voltage and a second power supply voltage and supply the selected power supply voltage to a power amplifier, and a power amplifier module having the same, the power selection switch circuit configured to select any one of the first power supply voltage and the second power supply voltage, and to supply the selected power supply voltage to the power amplifier. The power supply selection switch circuit includes: a first n-type transistor configured to be turned on in response to a first switch control signal having a first voltage generated by charge pumping the first power supply voltage, and to supply the first power supply voltage to a power supply terminal of the power amplifier when turned on; and a second n-type transistor configured to be turned on in response to a second switching control signal having a second voltage generated by charge-pumping the second power supply voltage, and to supply the second power supply voltage to the power supply terminal of the power amplifier when turned on.

Description

Technical Field

[0001] The invention relates to a power selection switch circuit and a power amplifier module having the power selection switch circuit. Background Art

[0002] The fifth generation cellular communication technology can coexist with the fourth generation cellular communication technology and the Long Term Evolution (LTE) technology, requiring different communication methods and corresponding power amplifiers in one communication terminal system.

[0003] A typical communication terminal system may use one power management integrated circuit (PMIC) and one power amplifier. In order to support various communication methods in one communication terminal system, a large number of PMICs may be desired, thereby increasing the manufacturing cost of the communication terminal system.

[0004] By using the power selection switch, a small number of PMICs can be used to drive a plurality of power amplifiers; therefore, the number of power supply components can be reduced, and the manufacturing cost of the communication terminal can be reduced.

[0005] When implementing a power selection switch, if a pair of n-type transistors and p-type transistors are used as a switch core, the size of the p-type transistor may be designed to be larger to reduce the on-resistance of the transistor for a high direct current (DC) input voltage. As the size of the p-type transistor increases, when the power selection switch is installed in a power amplifier module, the area occupied by the p-type transistor may increase. Therefore, the size and price of the power amplifier module may increase.

[0006] The above information is presented only as background information to help understand the present disclosure. The above description should not be interpreted as these contents belonging to the prior art of the present disclosure. Summary of the invention

[0007] This summary is provided to introduce selected concepts in a simplified form, and these concepts are further described in the following detailed description. This summary is neither intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0008] In a general aspect, a power selection switch circuit is configured to select either a first power supply voltage and a second power supply voltage and supply the selected power supply voltage to a power amplifier, the power selection switch circuit comprising: a first n-type transistor configured to be turned on in response to a first switch control signal and to supply the first power supply voltage to a power supply terminal of the power amplifier when turned on, the first switch control signal having a first voltage generated by charge pumping the first power supply voltage; and a second n-type transistor configured to be turned on in response to a second switch control signal and to supply the second power supply voltage to the power supply terminal of the power amplifier when turned on, the second switch control signal having a second voltage generated by charge pumping the second power supply voltage.

[0009] The power selection switch circuit may further include: a switch controller configured to generate the first switch control signal and the second switch control signal using a first bit signal and a second bit signal input from the outside, so that the transistor to be turned on from the off state of the first n-type transistor and the second n-type transistor is turned on after a predetermined delay, and the transistor to be turned off from the on state of the first n-type transistor and the second n-type transistor is immediately turned off. The first n-type transistor may be configured to be turned off in response to the first switch control signal having a third voltage lower than the first voltage, and the second n-type transistor may be configured to be turned off in response to the second switch control signal having a fourth voltage lower than the second voltage.

[0010] The switch controller may include: a logic circuit configured to generate a first logic signal for generating the first switch control signal and a second logic signal for generating the second switch control signal by combining the first bit signal and the second bit signal; a first delay circuit configured to delay the first logic signal to generate a first delayed signal; a second delay circuit configured to delay the second logic signal to generate a second delayed signal; a first buffer control circuit configured to supply the first voltage or the third voltage as the first switch control signal to the control terminal of the first n-type transistor in response to the first delayed signal; and a second buffer control circuit configured to supply the second voltage or the fourth voltage as the second switch control signal to the control terminal of the second n-type transistor in response to the second delayed signal.

[0011] The first bit signal and the second bit signal may have a value of 0 or 1. The logic circuit may be configured to: when the first bit signal and the second bit signal are both 1 or both 0, set both the first logic signal and the second logic signal to a low level so that both the first n-type transistor and the second n-type transistor are turned off.

[0012] The switch controller may also include: a first clock generator configured to operate in response to the first logic signal and generate a first clock signal having a fifth voltage and a sixth voltage lower than the fifth voltage; a second clock generator configured to operate in response to the second logic signal and generate a second clock signal having the fifth voltage and the sixth voltage; a first charge pump circuit configured to generate the first voltage by charge pumping the first power supply voltage with the fifth voltage in response to the first clock signal, and provide the first voltage to the first buffer control circuit; and a second charge pump circuit configured to generate the second voltage by charge pumping the second power supply voltage with the fifth voltage in response to the second clock signal, and provide the second voltage to the second buffer control circuit.

[0013] The first logic signal and the second logic signal may have a high level and a low level, respectively. The first clock generator and the second clock generator may operate at a high level of the first logic signal and a high level of the second logic signal, respectively, and not operate at a low level.

[0014] The logic circuit may include: a NAND gate configured to receive the first bit signal and the second bit signal; a first AND gate configured to receive the first bit signal and the output of the NAND gate, and output the first logic signal; and a second AND gate configured to receive the second bit signal and the output of the NAND gate, and output the second logic signal.

[0015] The first delay circuit may include: a first delay unit configured to delay the first logic signal; and a first AND gate configured to receive the first logic signal and a signal delayed by the first delay unit. The second delay circuit may include: a second delay unit configured to delay the second logic signal; and a second AND gate configured to receive the second logic signal and a signal delayed by the second delay unit.

[0016] In another general aspect, a power amplifier module comprises: the power amplifier as described above and the power supply selection switch circuit.

[0017] In another general aspect, a power amplifier module includes: a power amplifier configured to receive a power supply voltage from a power supply terminal, and to amplify an input signal and output the amplified signal; and a power supply selection switch circuit configured to provide the power supply terminal with any one of a first power supply voltage supplied from a first power management integrated circuit (IC) and a second power supply voltage supplied from a second power management IC. The power supply selection switch circuit may include: a first n-type transistor configured to have a first terminal connected to the first power management IC, a second terminal connected to the power supply terminal, and a control terminal receiving a first switch control signal, the first switch control signal having a first voltage generated by charge pumping the first power supply voltage; and a second n-type transistor configured to have a first terminal connected to the second power management IC, a second terminal connected to the power supply terminal, and a control terminal receiving a second switch control signal, the second switch control signal having a second voltage generated by charge pumping the second power supply voltage.

[0018] The power selection switch circuit may also include: a switch controller, configured to generate the first switch control signal and the second switch control signal, so that the first n-type transistor is turned on after a predetermined delay when it is about to change from an off state to an on state, and the second n-type transistor is turned on after a predetermined delay when it is about to change from an off state to an on state.

[0019] The first n-type transistor may be configured to be turned off in response to the first switch control signal having a third voltage lower than the first voltage, and the second n-type transistor may be configured to be turned off in response to the second switch control signal having a fourth voltage lower than the second voltage.

[0020] The switch controller may include: a logic circuit configured to generate a first logic signal for generating the first switch control signal and a second logic signal for generating the second switch control signal by combining a first bit signal and a second bit signal input from the outside; a first delay circuit configured to delay the first logic signal to generate a first delayed signal; a second delay circuit configured to delay the second logic signal to generate a second delayed signal; a first buffer control circuit configured to supply the first voltage or the third voltage as the first switch control signal to the control terminal of the first n-type transistor in response to the first delayed signal; and a second buffer control circuit configured to supply the second voltage or the fourth voltage as the second switch control signal to the control terminal of the second n-type transistor in response to the second delayed signal.

[0021] The first bit signal and the second bit signal may have a value of 0 or 1. The logic circuit is configured to, when the first bit signal and the second bit signal are both 1 or both 0, set both the first logic signal and the second logic signal to a low level so that both the first n-type transistor and the second n-type transistor are turned off.

[0022] The switch controller may include: a first clock generator configured to operate in response to the first logic signal and generate a first clock signal having a fifth voltage and a sixth voltage lower than the fifth voltage; a second clock generator configured to operate in response to the second logic signal and generate a second clock signal having the fifth voltage and the sixth voltage; a first charge pump circuit configured to generate the first voltage by charge pumping the first power supply voltage with the fifth voltage in response to the first clock signal and provide the first voltage to the first buffer control circuit; and a second charge pump circuit configured to generate the second voltage by charge pumping the second power supply voltage with the fifth voltage in response to the second clock signal and provide the second voltage to the second buffer control circuit.

[0023] The first n-type transistor may include a plurality of third transistors connected in parallel, the second n-type transistor may include a plurality of fourth transistors connected in parallel, and the plurality of third transistors and the plurality of fourth transistors may be n-type transistors.

[0024] Other features and aspects will be readily apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a diagram schematically showing a power selection switch circuit according to an embodiment.

[0026] Figure 2 It is shown Figure 1 A diagram of a power selection switch circuit 100 is shown.

[0027] Figure 3 It is shown Figure 2 A diagram of a switch controller 110 is shown.

[0028] Figure 4 is a diagram showing a logic circuit 111 according to one embodiment.

[0029] Figure 5 It is shown Figure 4 A diagram of a logic table for the logic circuit shown.

[0030] Figure 6 It is shown Figure 4 Schematic diagram of the first delay circuit 112 is shown.

[0031] Figure 7 It is shown Figure 4 Schematic diagram of the second delay circuit 113 shown.

[0032] Figure 8 It is shown Figure 6 A diagram showing the relationship between the input signal and the output signal of the delay circuit shown.

[0033] Fig. 9 is a diagram showing an operation timing of a power selection switch circuit according to one embodiment.

[0034] Fig.10 is a diagram showing a detailed composition of a switch controller according to an embodiment.

[0035] Fig.11 It is shown Fig.10 A diagram of an example of a charge pump circuit 125 is shown.

[0036] Fig.12 is a diagram showing an operating state of the charge pump circuit 125 in the first operating section.

[0037] Fig.13 is a diagram showing an operating state of the charge pump circuit 125 in the second operating section.

[0038] Fig.14 It shows that the application Figure 1 FIG. 1 is a diagram of an example of a communication terminal system of a power selection switch circuit shown.

[0039] Fig.15 It shows that the application Figure 1 FIG. 2 is a diagram of another example of a communication terminal system of the power selection switch circuit shown.

[0040] Throughout the drawings and detailed description, like reference numerals denote like elements unless otherwise described. The drawings may not be drawn to scale, and the relative size, proportion, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0041] Hereinafter, although examples of the present disclosure will be described in detail with reference to the accompanying drawings, it is noted that the examples are not limited thereto.

[0042] The following specific embodiments are provided to help the reader gain a comprehensive understanding of the methods, devices and / or systems described herein. However, various changes, modifications and equivalents of the methods, devices and / or systems described herein will be readily understood after understanding the present disclosure. For example, the order of operations described herein is merely an example and is not limited to those set forth herein, but may be changed as will be readily understood after understanding the present disclosure, except for operations that must occur in a particular order. In addition, descriptions of features known in the art may be omitted for increased clarity and brevity.

[0043] The features described herein may be implemented in different forms and shall not be construed as being limited to the examples described herein. Rather, the examples described herein are provided only to illustrate some of the many possible ways to implement the methods, devices and / or systems described herein, which will be readily understood after understanding the present disclosure.

[0044] Throughout the specification, when an element such as a layer, a region or a substrate is described as being “on”, “connected to” or “coupled to” another element, it may be directly “on”, directly “connected to” or directly “coupled to” another element, or one or more intervening elements may be present. In contrast, when an element is described as being “directly on”, “directly connected to” or “directly coupled to” another element, there are no other elements between them.

[0045] As used herein, the term “and / or” includes any one or any combination of any two or more of the associated listed items; similarly, “at least one of” includes any one or any combination of any two or more of the associated listed items.

[0046] Although terms such as "first", "second" and "third" may be used herein to describe various members, components, regions, layers or parts, these members, components, regions, layers or parts are not limited by these terms. Rather, these terms are only used to distinguish one member, component, region, layer or part from another member, component, region, layer or part. Therefore, without departing from the teachings of the examples described herein, the first member, first component, first region, first layer or first part mentioned in the examples may also be referred to as the second member, second component, second region, second layer or second part.

[0047] For ease of description, spatially relative terms such as "above", "upper", "below", "lower", etc. may be used herein to describe the relationship of one element to another element as shown in the drawings. Such spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, an element described as being "above" or "upper" relative to another element will be "below" or "lower" relative to the other element. Therefore, the term "above" includes both upper and lower orientations depending on the spatial orientation of the device. The device may also be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative terms used herein will be interpreted accordingly.

[0048] The terms used herein are only used to describe various examples and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. The terms "include", "comprising", and "having" specify the presence of the stated features, quantities, operations, components, elements, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof.

[0049] Variations in the shapes shown in the drawings may occur due to manufacturing techniques and / or tolerances. Therefore, the examples described herein are not limited to the specific shapes shown in the drawings but include variations in shapes that occur during manufacturing.

[0050] Here, it is noted that use of the term “may” with respect to examples (eg, with respect to what an example may include or implement) means that there is at least one example that includes or implements such features, but is not limited to all examples including or implementing such features.

[0051] As will be readily understood after understanding the present disclosure, the features of the examples described herein may be combined in various ways. In addition, although the examples described herein have various configurations, other configurations are feasible as will be readily understood after understanding the present disclosure.

[0052] Throughout the specification, RF signals have (but are not limited to) the following formats: Wi-Fi (IEEE 802.11 series, etc.), WiMAX (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), Enhanced High-Speed ​​Packet Access (HSPA+), Enhanced High-Speed ​​Downlink Packet Access (HSDPA+), Enhanced High-Speed ​​Uplink Packet Access (HSUPA+), Enhanced Data Rates for GSM Evolution (EDGE), Global System for Mobile Communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Enhanced Digital Cordless Telecommunications (DECT), Bluetooth, third generation mobile communication technology (3G), fourth generation mobile communication technology (4G), fifth generation mobile communication technology (5G), and any other wireless protocols and wired protocols specified later.

[0053] Figure 1 is a diagram schematically showing a power selection switch circuit according to an embodiment.

[0054] Reference Figure 1 The power selection switch circuit 100 may receive a power voltage VCC1 from a power management integrated circuit (PMIC) 200_1 , receive a power voltage VCC2 from a PMIC 200_2 , select one of the power voltages VCC1 and VCC2 based on an input control signal CTRL, and output the selected power voltage to a power terminal T_VCC of the power amplifier 300 .

[0055] The PMIC 200_1 may generate a power supply voltage VCC1 from a main power supply.

[0056] The PMIC 200_2 may generate a power supply voltage VCC2 from a main power supply.

[0057] The capacitor Ca may be connected between the PMIC 200_1 and the ground, filter noise of the power voltage VCC1 input from the PMIC 200_1, and stabilize the power voltage VCC1.

[0058] The capacitor Cb may be connected between the PMIC 200_2 and the ground, filter noise of the power voltage VCC2 input from the PMIC 200_2, and stabilize the power voltage VCC2.

[0059] The power amplifier 300 may include an input terminal T_IN, an output terminal T_OUT, and a power terminal T_VCC. The power amplifier 300 may operate by receiving a power voltage selected by the power selection switch circuit 100 via the power terminal T_VCC, amplify an RF signal input to the input terminal T_IN, and output the amplified RF signal from the output terminal T_OUT.

[0060] The power selection switch circuit 100 and the power amplifier 300 may be integrated and implemented as a single power amplifier module 400 .

[0061] Figure 2 It is shown Figure 1 A diagram of a power selection switch circuit 100 is shown.

[0062] Reference Figure 2 The power selection switch circuit 100 may include a transistor SW1 , a transistor SW2 , and a switch controller 110 .

[0063] The transistor SW1 may be connected between the PMIC 200_1 and the power supply terminal T_VCC of the power amplifier 300. The transistor SW1 may be turned on according to the first switch control signal SCS1 of the switch controller 110 input through the gate to supply the power supply voltage VCC1 to the power amplifier ( Figure 2 The power supply terminal T_VCC of the PA) 300 is shown in FIG.

[0064] The transistor SW2 may be connected between the PMIC 200_2 and the power terminal T_VCC of the power amplifier 300. The transistor SW2 may be turned on according to the second switch control signal SCS2 of the switch controller 110 input through the gate to supply the power voltage VCC2 to the power terminal T_VCC of the power amplifier 300.

[0065] According to an embodiment, transistors SW1 and SW2 may be n-type transistors. Transistor SW1 may be implemented as a single n-type transistor, or may be implemented by connecting a plurality of n-type transistors in parallel. Transistor SW2 may also be implemented as a single n-type transistor, or may be implemented by connecting a plurality of n-type transistors in parallel.

[0066] In addition, unlike the embodiment, both transistor SW1 and transistor SW2 can be implemented by connecting at least one n-type transistor and at least one p-type transistor in parallel. The on-resistance of transistors SW1 and SW2 can be reduced by setting the chip size of transistors SW1 and SW2 larger. When transistors SW1 and SW2 can be implemented by connecting at least one n-type transistor and at least one p-type transistor in parallel, the chip size of the p-type transistors of transistors SW1 and SW2 can be increased to reduce the on-resistance of transistors SW1 and SW2 for high input voltage, and thus the overall size of transistors SW1 and SW2 can be increased respectively. For this reason, when the power supply selection switch circuit 100 is configured using transistors SW1 and SW2 implemented by connecting at least one n-type transistor and at least one p-type transistor in parallel, the mounting area of ​​transistors SW1 and SW2 in the power amplifier module 400 can be increased.

[0067] However, if the power selection switch circuit 100 is configured with a transistor SW1 consisting only of n-type transistors and a transistor SW2 consisting only of n-type transistors as in the embodiment, since p-type transistors requiring a larger chip size are not used, the mounting area of ​​the transistor SW1 and the transistor SW2 within the power amplifier module 400 can be reduced.

[0068] The switch controller 110 may receive a control signal CTRL from the outside, and generate a first switch control signal SCS1 for controlling the transistor SW1 and a second switch control signal SCS2 for controlling the transistor SW2 in response to the control signal CTRL. The switch controller 110 may output the first switch control signal SCS1 to the gate of the transistor SW1, and output the second switch control signal SCS2 to the gate of the transistor SW2.

[0069] The control signal CTRL may have a 2-bit value, 1 of the 2 bits may be used to generate the first switch control signal SCS1, and the remaining 1 of the 2 bits may be used to generate the second switch control signal SCS2.

[0070] When the first switch control signal SCS1 is an on control signal and the second switch control signal SCS2 is an off control signal, the transistor SW1 may be turned on and the transistor SW2 may be turned off. Therefore, the power supply voltage VCC1 may be applied to the power supply terminal T_VCC of the power amplifier 300 through the transistor SW1.

[0071] When the first switch control signal SCS1 is a turn-off control signal and the second switch control signal SCS2 is a turn-on control signal, the transistor SW1 may be turned off and the transistor SW2 may be turned on. Therefore, the power supply voltage VCC2 may be applied to the power supply terminal T_VCC of the power amplifier 300 through the transistor SW2.

[0072] The switch control signals SCS1 and SCS2 may have a high level voltage and a low level voltage, respectively. Since the transistors SW1 and SW2 are n-type transistors, the turn-on control signal may be a high level voltage, and the turn-off control signal may be a low level voltage.

[0073] The switch controller 110 may generate a voltage higher than the input voltage to reduce the on-resistance of the n-type transistor SW1 or SW2 , and use the generated voltage as a high level voltage of the first switch control signal SCS1 and the second switch control signal SCS2 .

[0074] Figure 3 It is shown Figure 2 A diagram of a switch controller 110 is shown.

[0075] Reference Figure 3 The switch controller 110 may include a logic circuit 111 , a first delay circuit 112 , a second delay circuit 113 , a first buffer circuit 114 , a second buffer circuit 115 , a first buffer gate 116 , and a second buffer gate 117 .

[0076] The first delay circuit 112 , the first buffer circuit 114 , and the first buffer gate 116 are operable to generate a first switch control signal SCS1 for controlling the transistor SW1 .

[0077] The second delay circuit 113 , the second buffer circuit 115 , and the second buffer gate 117 are operable to generate a second switch control signal SCS2 for controlling the transistor SW2 .

[0078] The logic circuit 111 may receive bit signals B1 and B2 as external control signals, and may generate and output logic signals VLOG1 and VLOG2 in response to the bit signals B1 and B2. The bit signal B1 and the logic signal VLOG1 may be used to control the transistor SW1, and the bit signal B2 and the logic signal VLOG2 may be used to control the transistor SW2. The bit signal B1 may correspond to one of the two bits of the control signal CTRL, and the bit signal B2 may correspond to the remaining one of the two bits of the control signal CTRL.

[0079] Figure 4 is a diagram showing a logic circuit 111 according to one embodiment.

[0080] like Figure 4 As shown, the logic circuit 111 may include a NAND gate 410 , an AND gate 420 , and an AND gate 430 .

[0081] The NAND gate 410 may receive the bit signal B1 and the bit signal B2 , perform a NAND operation on the bit signal B1 and the bit signal B2 , and output a result of the NAND operation to the AND gates 420 and 430 .

[0082] The AND gate 420 may receive the bit signal B1 and the output signal of the NAND gate 410 , generate a logic signal VLOG1 by logically multiplying the bit signal B1 and the output signal of the NAND gate 410 , and output the logic signal VLOG1 .

[0083] The AND gate 430 may receive the bit signal B2 and the output signal of the NAND gate 410 , generate a logic signal VLOG2 by logically multiplying the bit signal B2 and the output signal of the NAND gate 410 , and output the logic signal VLOG2 .

[0084] Figure 5 It is shown Figure 4 A diagram of a logic table for the logic circuit shown.

[0085] Reference Figure 5 , the logic circuit 111 can have four states corresponding to the bit signals B1 and B2.

[0086] If the bit signals B1 and B2 are both low level L, both logic signals VLOG1 and VLOG2 may have low level L. If the bit signals B1 and B2 are both high level H, both logic signals VLOG1 and VLOG2 may have low level L. If the bit signal B1 is low level L and the bit signal B2 is high level H, the logic signal VLOG1 may have low level L and the logic signal VLOG2 may have high level H. If the bit signal B1 is high level H and the bit signal B2 is low level L, the logic signal VLOG1 may have high level H and the logic signal VLOG2 may have low level L.

[0087] When the logic signal VLOG1 is at a high level H, the transistor SW1 may be turned on, and when the logic signal VLOG1 is at a low level L, the transistor SW1 may be turned off.

[0088] When the logic signal VLOG2 is at a high level H, the transistor SW2 may be turned on, and when the logic signal VLOG2 is at a low level L, the transistor SW2 may be turned off.

[0089] Figure 6 It is shown Figure 4 A diagram of the first delay circuit 112 is shown, and Figure 7 It is shown Figure 4 Schematic diagram of the second delay circuit 113 shown.

[0090] Reference Figure 6 , the first delay circuit 112 may include an AND gate 610 and a delay unit 620 .

[0091] The AND gate 610 and the delay unit 620 may generate a delayed signal VDEL1 (hereinafter may also be referred to as a signal VDEL1 or an output signal VDEL1 ) by delaying the logic signal VLOG1 . The delay unit 620 may include a resistor R1 and a capacitor C1 .

[0092] The logic signal VLOG1 may be input to the input terminal A of the AND gate 610. The capacitor C1 may be connected between the input terminal B of the AND gate 610 and the ground. The logic signal VLOG1 may be input to one end of the resistor R1, and the other end of the resistor R1 may be connected to the input terminal B of the AND gate 610. Here, the delay unit 620 may delay the logic signal VLOG1 by a predetermined time and then output it to the input terminal B of the AND gate 610. The RC time constant value may be determined by the value of the resistor R1 and the value of the capacitor C1, and the logic signal VLOG1 may be delayed by the RC time constant value. In addition, the delay unit 620 is an element that delays a signal, and may be implemented using other methods such as the resistor R1 and the capacitor C1. The AND gate 610 may generate a signal VDEL1 by logically multiplying the signals input to the input terminal A and the input terminal B, and output the signal VDEL1.

[0093] Reference Figure 7 , the second delay circuit 113 may include an AND gate 630 and a delay unit 640 .

[0094] The AND gate 630 and the delay unit 640 may generate a delayed signal VDEL2 (hereinafter may also be referred to as a signal VDEL2 or an output signal VDEL2 ) by delaying the logic signal VLOG2 . The delay unit 640 may include a resistor R2 and a capacitor C2 .

[0095] The logic signal VLOG2 may be input to the input terminal A of the AND gate 630. The capacitor C2 may be connected between the input terminal B of the AND gate 630 and the ground. The logic signal VLOG2 may be input to one end of the resistor R2, and the other end of the resistor R2 may be connected to the input terminal B of the AND gate 630. Here, the delay unit 640 may delay the logic signal VLOG2 by a predetermined time and then output it to the input terminal B of the AND gate 630. The RC time constant value may be determined by the value of the resistor R2 and the value of the capacitor C2, and the logic signal VLOG2 may be delayed by the RC time constant value. In addition, the delay unit 640 is an element that delays a signal, and may be implemented using other methods such as a resistor R2 and a capacitor C2. The AND gate 630 may generate a signal VDEL2 by logically multiplying the signals input to the input terminal A and the input terminal B, and output the signal VDEL2.

[0096] Figure 8 It is shown Figure 6A diagram showing the relationship between the input signal and the output signal of the delay circuit shown in FIG. Figure 8 In the description, the AND gate 610 and the delay unit 620 are used, but Figure 7 The AND gate 630 and delay unit 640 shown can also be used.

[0097] Reference Figure 8 , at time t1, the logic signal VLOG1 may change from a low level to a high level.

[0098] At time t1, the signal input to the input terminal A may change from a low level to a high level immediately, but the signal input to the input terminal B may be delayed by a predetermined delay time Δt through the delay unit 620 and then change from a low level to a high level. After the predetermined delay time Δt, due to the operation characteristics of the AND gate 610, at time t2 when both the signal input to the input terminal A and the signal input to the input terminal B become high levels, the signal output from the output terminal Y of the AND gate 610 may change from a low level to a high level. Therefore, when the transistor SW1 changes from an off state to an on state, the turn-off of the transistor SW1 may be delayed by a predetermined delay time Δt.

[0099] Furthermore, at time t3 , the logic signal VLOG1 may change from a high level to a low level.

[0100] At time t3, the signal input to the input terminal A may be immediately changed from a high level to a low level, but the signal input to the input terminal B may be delayed for a predetermined time by the delay unit 620 and then changed from a high level to a low level. Due to the operation characteristics of the AND gate, the signal output from the output terminal Y of the AND gate 610 may be immediately changed from a high level to a low level without a delay time.

[0101] In other words, the first delay circuit 112 may also delay the output signal VDEL1 only when the logic signal VLOG1 changes from a low level to a high level, and may not delay the output signal VDEL1 when the logic signal VLOG1 changes from a high level to a low level. When the logic signal VLOG1 changes from a low level to a high level, the transistor SW1 may change from an off state to an on state, and the transistor SW1 may be turned on after a predetermined delay time. When the logic signal VLOG1 changes from a high level to a low level, the transistor SW1 may change from an on state to an off state, and the transistor SW1 may be turned on immediately without a delay time.

[0102] These delay circuits 112 and 113 can be used to prevent transistors SW1 and SW2 from being turned on at the same time, which will refer to Fig. 9 Further detailed explanation.

[0103] Refer again Figure 3, the first buffer circuit 114 may receive the delay signal VDEL1 output from the first delay circuit 112 and output the buffer signal VBUF1. The first buffer circuit 114 may convert the delay signal VDEL1 into the buffer signal VBUF1. Since the delay signal VDEL1 output from the first delay circuit 112 is a logic signal with a low current level, the first buffer circuit 114 may convert the delay signal VDEL1 output from the first delay circuit 112 into the buffer signal VBUF1 with a high current level.

[0104] The second buffer circuit 115 may receive the delay signal VDEL2 output from the second delay circuit 113 and output a buffer signal VBUF2. The second buffer circuit 115 may convert the delay signal VDEL2 into a buffer signal VBUF2.

[0105] Since specific configurations and operations of the first buffer circuit 114 and the second buffer circuit 115 may be known to those skilled in the art, further detailed description of the buffer circuits 114 and 115 will be omitted.

[0106] The first buffer gate 116 may receive the buffer signal VBUF1 and output the first switch control signal SCS1. The first buffer gate 116 may include an even number of inverter gates connected in series. Since the first buffer gate 116 has a structure in which an even number of inverters are connected in series, the first buffer gate 116 may output the buffer signal VBUF1 as is, and the first switch control signal SCS1 may be the buffer signal VBUF1.

[0107] The second buffer gate 117 may receive the buffer signal VBUF2 and output the second switch control signal SCS2. The second buffer gate 117 may include an even number of inverter gates connected in series. Since the second buffer gate 117 has a structure in which an even number of inverters are connected in series, the second buffer gate 117 may output the buffer signal VBUF2 as is, and the second switch control signal SCS2 may be the buffer signal VBUF2.

[0108] These buffer gates 116 and 117 can set the voltage levels of the input terminal and the output terminal to be the same.

[0109] Fig. 9 is a diagram showing an operation timing of a power selection switch circuit according to one embodiment. Fig. 9 Logic signals VLOG1 and VLOG2 , buffer signals VBUF1 and VBUF2 , and a power supply terminal voltage VOUT depending on bit signals B1 and B2 are shown.

[0110] Reference Fig. 9When the bit signal B1 and the bit signal B2 are input, the logic circuit 111 can output logic signals VLOG1 and VLOG2 according to the bit value of the bit signal B1 and the bit value of the bit signal B2.

[0111] In the period TD1, the logic signal VLOG1 is at a low level, and the logic signal VLOG2 is also at a low level. In this case, both the buffer signals VBUF1 and VBUF2 are low voltages, and both the transistors SW1 and SW2 are in an off state. Therefore, neither of the power supply voltages VCC1 and VCC2 is output.

[0112] In the time period TD2, the logic signal VLOG1 is at a high level, and the logic signal VLOG2 is at a low level. In this case, the buffer signal VBUF1 is a high voltage, and the buffer signal VBUF2 is a low voltage. Considering the time periods TD1 and TD2 together, the logic signal VLOG1 may change from a low level to a high level. Figure 7 and Figure 8 As explained in , when the logic signal changes from a low level to a high level (from 0 to 1), the first delay circuit 112 generates a delay in the output signal. Therefore, since the buffer signal VBUF1 changes from a low voltage to a high voltage after a predetermined delay time Δt, the turn-on of the transistor SW1 can be delayed. That is, the transistor SW1 may not be turned on immediately when the logic signal VLOG1 changes from a low level to a high level, but may be turned on after a predetermined delay time Δt. The transistor SW2 may remain in an off state. Therefore, the power supply selection switch circuit 100 may output the power supply voltage VCC1, and the power supply terminal voltage VOUT may be the power supply voltage VCC1.

[0113] In the time period TD3, the logic signal VLOG1 is at a low level, and the logic signal VLOG2 is at a high level. Considering the time periods TD2 and TD3 together, the logic signal VLOG1 changes from a high level to a low level, and the logic signal VLOG2 changes from a low level to a high level. Figure 7 and Figure 8 As explained in , when the logic signal VLOG2 changes from a low level to a high level (from 0 to 1), the second delay circuit 113 may generate a delay in the output signal. Therefore, since the buffer signal VBUF2 changes from a low voltage to a high voltage after a predetermined delay time Δt, the turn-on of the transistor SW2 may be delayed. In addition, in the time period TD3, the buffer signal VBUF1 immediately changes from a high voltage to a low voltage without a delay time, so the transistor SW1 may be immediately turned off. That is, in the time period TD3, an overlapping turn-off time period ① in which both the transistor SW1 and the transistor SW2 are in the turn-off state may occur.

[0114] When the levels of the logic signals VLOG1 and VLOG2 change, the transistor SW1 and the transistor SW2 may be turned on at the same time. When the transistors SW1 and SW2 are turned on at the same time, a current path is formed along the transistors SW1 and SW2 in the PMICs 200_1 and 200_2, so an overcurrent may be generated. According to an embodiment, the turn-on of the transistor SW2 is delayed by the second delay circuit 113, and the overlapping off time period ① of the transistors SW1 and SW2 can be set, so that the transistors SW1 and SW2 can be prevented from being turned on at the same time.

[0115] Therefore, in the period TD3 , the transistor SW1 may be immediately turned off and the transistor SW2 may be turned on after a predetermined delay time Δt, the power selection switch circuit 100 may output the power voltage VCC2 , and the power terminal voltage VOUT may be the power voltage VCC2 .

[0116] In the time period TD4, the logic signal VLOG1 is at a low level, and the logic signal VLOG2 is also at a low level. Considering the time periods TD3 and TD4 together, the logic signal VLOG2 may change from a high level to a low level. When the logic signal VLOG2 changes from a high level to a low level, the buffer signal VBUF2 may immediately change from a high voltage to a low voltage without a delay time, and thus the transistor SW2 may be immediately turned off. The transistor SW1 may maintain an off state. Therefore, in the time period TD4, the power selection switch circuit 100 does not output any of the power supply voltage VCC1 and the power supply voltage VCC2.

[0117] In the time period TD5, the logic signal VLOG1 is at a low level, and the logic signal VLOG2 is also at a low level. Considering the time periods TD4 and TD5 together, the logic signals VLOG1 and VLOG2 are both kept at a low level, so the buffer signals VBUF1 and VBUF2 can also be kept at a low voltage. Therefore, in the time period TD5, the power selection switch circuit 100 does not output any of the power supply voltage VCC1 and the power supply voltage VCC2.

[0118] In time period TD6, logic signal VLOG1 is at a low level, and logic signal VLOG2 is at a high level. Considering time periods TD5 and TD6 together, logic signal VLOG2 may change from a low level to a high level. Figure 7 and Figure 8As explained in , when the logic signal VLOG2 changes from a low level to a high level, the second delay circuit 113 may generate a delay in the output signal. Therefore, since the buffer signal VBUF2 changes from a low voltage to a high voltage after a predetermined delay time Δt, the turn-on of the transistor SW2 may be delayed. In addition, in the time period TD6, the buffer signal VBUF1 maintains a low voltage, so the transistor SW1 may remain turned off. Therefore, in the time period TD6, the transistor SW2 may be turned on after a predetermined delay time Δt, the power selection switch circuit 100 may output the power supply voltage VCC2, and the power supply terminal voltage VOUT may be the power supply voltage VCC2.

[0119] In time period TD7, logic signal VLOG1 is at a high level, and logic signal VLOG2 is at a low level. Considering time periods TD6 and TD7 together, logic signal VLOG1 may change from a low level to a high level, and logic signal VLOG2 may change from a high level to a low level. Figure 7 and Figure 8 As described in the foregoing, when the logic signal VLOG1 changes from a low level to a high level, the first delay circuit 112 may generate a delay in the output signal. Therefore, since the buffer signal VBUF1 changes from a low voltage to a high voltage after a predetermined delay time Δt, the turn-on of the transistor SW1 may be delayed. In addition, in the time period TD7, the buffer signal VBUF2 immediately changes from a high voltage to a low voltage without a delay time, so the transistor SW2 may be immediately turned off. That is, in the time period TD7, when the logic signal VLOG1 changes from a low level to a high level and the logic signal VLOG2 changes from a high level to a low level, an overlapping turn-off time period ② in which both the transistor SW1 and the transistor SW2 are turned off may occur, so the transistors SW1 and SW2 may be prevented from being turned on at the same time due to the overlapping turn-off time period ②.

[0120] Therefore, in the period TD7 , the transistor SW2 may be immediately turned off and the transistor SW1 may be turned on after a predetermined delay time Δt, the power selection switch circuit 100 may output the power voltage VCC1 , and the power terminal voltage VOUT may be the power voltage VCC1 .

[0121] In the time period TD8, the logic signal VLOG1 is at a low level, and the logic signal VLOG2 is at a low level. Considering the time periods TD7 and TD8 together, the logic signal VLOG1 may change from a high level to a low level. When the logic signal VLOG1 changes from a high level to a low level, the buffer signal VBUF1 may immediately change from a high voltage to a low voltage without a delay time, and thus the transistor SW1 may be immediately turned off. The transistor SW2 may maintain an off state. Therefore, in the time period TD8, the power selection switch circuit 100 does not output any of the power supply voltage VCC1 and the power supply voltage VCC2.

[0122] In this way, when either of the buffer signal VBUF1 and the buffer signal VBUF2 changes from a low voltage to a high voltage, the power selection switch circuit 100 according to the embodiment can change the low voltage to a high voltage after a predetermined delay time. Therefore, when the voltage levels of the buffer signals VBUF1 and VBUF2 change, the transistors SW1 and SW2 can be prevented from being turned on at the same time, and the power amplifier 300 can be protected from the influence of overcurrent.

[0123] In addition, when the bit signal B1 and the bit signal B2 input from the outside are at a low level or a high level at the same time (for example, in time period TD1, time period TD4, time period TD5 or time period TD8), the power selection switch circuit 100 according to the embodiment can turn off the transistor SW1 and the transistor SW2 at the same time, thereby preventing the transistor SW1 and the transistor SW2 from being turned on at the same time, and protecting the power amplifier 300 from the influence of overcurrent.

[0124] Fig.10 is a diagram showing a detailed composition of a switch controller according to an embodiment.

[0125] Reference Fig.10 , the switch controller 110 may further include a control voltage generator 120 .

[0126] exist Fig.10 middle, Figure 3 The first buffer circuit 114 and the first buffer gate 116 are shown as being integrated into the buffer control circuit 130 . Figure 3 The second buffer circuit 115 and the second buffer gate 117 are shown to be integrated into the buffer control circuit 140, and the logic circuit 111, the first delay circuit 112, and the second delay circuit 113 are omitted.

[0127] As described above, both transistors SW1 and SW2 are n-type transistors, and therefore in order to reduce the on-resistance of transistors SW1 and SW2 to a high input voltage, transistors SW1 and SW2 must be controlled with a voltage higher than the input power supply voltage VCC1 or VCC2.

[0128] The control voltage generator 120 may generate a voltage higher than the power supply voltage VCC1 or VCC2 , and the voltage may be used to control the transistors SW1 and SW2 .

[0129] The control voltage generator 120 may include a bandgap reference (BGR) circuit 121 , a low dropout (LDO) circuit 122 , a clock generator 123 , a clock generator 124 , a charge pump circuit 125 , and a charge pump circuit 126 .

[0130] The BGR circuit 121 may generate a reference voltage VBGR from a battery voltage VBAT supplied by a battery power source. The BGR circuit 121 may generate a reference voltage VBGR whose voltage level does not change according to temperature and external environment.

[0131] The LDO circuit 122 can generate a positive voltage VLDO (hereinafter also referred to as voltage VLDO) lower than the battery voltage VBAT from the battery voltage VBAT supplied by the battery power source. The LDO circuit 122 can generate a positive voltage VLDO having a level corresponding to the reference voltage VBGR generated by the BGR circuit 121 using the battery voltage VBAT.

[0132] The voltage V LDO generated by the LDO circuit 122 may be provided to the clock generator 123 and the clock generator 124 .

[0133] The clock generator 123 and the charge pump circuit 125 may be used to generate a gate control voltage for controlling the transistor SW1 .

[0134] The clock generator 124 and the charge pump circuit 126 may be used to generate a gate control voltage for controlling the transistor SW2 .

[0135] The clock generator 123 may operate based on the enable signal EN_CP1 and output a clock signal CLK1 having a voltage VLDO and a ground voltage and an inverted clock signal CLK1' according to a signal V_OSC input from an oscillator. The inverted clock signal CLK1' may be a signal obtained by inverting the clock signal CLK1.

[0136] The clock generator 124 may operate based on the enable signal EN_CP2 and output a clock signal CLK2 having a voltage VLDO and a ground voltage and an inverted clock signal CLK2' according to a signal V_OSC input from an oscillator. The inverted clock signal CLK2' may be a signal obtained by inverting the clock signal CLK2.

[0137] According to an embodiment, Figure 3 The logic signal VLOG1 of the logic circuit 111 shown may be used as the enable signal EN_CP1 . Figure 3 The logic signal VLOG2 of the logic circuit 111 shown can be used as the enable signal EN_CP2. Fig. 9 As shown, in the time period TD2, the logic signal VLOG1 is at a high level, so the clock generator 123 can operate. In this case, the logic signal VLOG2 is at a low level, so the clock generator 124 may not operate. In addition, in the time period TD3, the logic signal VLOG2 is at a high level, so the clock generator 124 can operate, and the logic signal VLOG1 is at a low level, so the clock generator 123 may not operate.

[0138] The charge pump circuit 125 may charge pump the power voltage VCC1 (eg, charge pump the power voltage VCC1 with the voltage VLDO) according to the clock signal CLK1 and the inverted clock signal CLK1 ′ to generate a positive voltage V_OUT_CP1 higher than the power voltage VCC1 , and provide the positive voltage V_OUT_CP1 to the buffer control circuit 130 .

[0139] The charge pump circuit 126 may charge pump the power voltage VCC2 (eg, charge pump the power voltage VCC1 with the voltage VLDO) according to the clock signal CLK2 and the inverted clock signal CLK2 ′ to generate a positive voltage V_OUT_CP2 higher than the power voltage VCC2 , and provide the positive voltage V_OUT_CP2 to the buffer control circuit 140 .

[0140] The buffer control circuit 130 may provide a conduction control voltage corresponding to the conduction control signal to the gate of the transistor SW1 based on the control signal SW1_CONT. The buffer control circuit 130 may provide a cut-off control voltage corresponding to the cut-off control signal to the gate of the transistor SW1 based on the control signal SW1_CONT. Here, the conduction control voltage may be a positive voltage V_OUT_CP1, and the cut-off control voltage may be a ground voltage. Alternatively, the cut-off control voltage may be a negative voltage.

[0141] The buffer control circuit 140 may provide a conduction control voltage corresponding to the conduction control signal to the gate of the transistor SW2 based on the control signal SW2_CONT. The buffer control circuit 140 may provide a cut-off control voltage corresponding to the cut-off control signal to the gate of the transistor SW2 based on the control signal SW2_CONT. Here, the conduction control voltage may be a positive voltage V_OUT_CP2, and the cut-off control voltage may be a ground voltage. Alternatively, the cut-off control voltage may be a negative voltage.

[0142] When the cut-off control voltage is a negative voltage, an additional charge pump circuit may be used to generate a negative voltage from the voltage VLDO generated by the LDO circuit 122 .

[0143] According to an embodiment, Figure 3 The delayed signal VDEL1 of the first delay circuit 112 is shown to be usable as the control signal SW1_CONT. Figure 3The delay signal VDEL2 of the second delay circuit 113 shown can be used as the control signal SW2_CONT. Therefore, when the logic signal VLOG1 changes from a low level to a high level, the buffer control circuit 130 can turn on the transistor SW1 after a predetermined delay time Δt, and when the logic signal VLOG2 changes from a low level to a high level, the buffer control circuit 140 can turn on the transistor SW2 after a predetermined delay time Δt. Thus, it is possible to prevent the transistor SW1 and the transistor SW2 from being turned on at the same time.

[0144] Fig.11 It is shown Fig.10 A diagram of an example of a charge pump circuit 125 is shown.

[0145] Reference Fig.11 , the charge pump circuit 125 may include a pump capacitor C3, a pump capacitor C4, an inverter 1251 and an inverter 1252.

[0146] The clock signal CLK1 may be input to one end of the pump capacitor C3, and the other end of the pump capacitor C3 may be connected to the input terminal IN1 of the inverter 1251. In addition, the other end of the pump capacitor C3 may be connected to the output terminal OUT2 of the inverter 1252.

[0147] The inverted clock signal CLK1′ may be input to one end of the pump capacitor C4, and the other end of the pump capacitor C4 may be connected to the input terminal IN2 of the inverter 1252. In addition, the other end of the pump capacitor C4 may be connected to the output terminal OUT1 of the inverter 1251.

[0148] The inverter 1251 may include a p-type transistor M1 and an n-type transistor M2. The source of the p-type transistor M1 is a power supply terminal and may be connected to the node N1, and the source of the n-type transistor M2 is a power supply terminal and may be connected to the node N2. The drain of the p-type transistor M1 and the drain of the n-type transistor M2 may be the output terminal OUT1 of the inverter 1251, and the gate of the p-type transistor M1 and the gate of the n-type transistor M2 may be the input terminal IN1 of the inverter 1251.

[0149] The inverter 1252 may include a p-type transistor M3 and an n-type transistor M4. The source of the p-type transistor M3 is a power supply terminal and may be connected to the node N1, and the source of the n-type transistor M4 is a power supply terminal and may be connected to the node N2. The drain of the p-type transistor M3 and the drain of the n-type transistor M4 may be the output terminal OUT2 of the inverter 1252, and the gate of the p-type transistor M3 and the gate of the n-type transistor M4 may be the input terminal IN2 of the inverter 1252.

[0150] The charge pump circuit 125 may generate a positive voltage V_OUT_CP1 as an output voltage from an input voltage in which the voltage VLDO and the ground voltage are alternately input according to the clock signal CLK1 and the inverted clock signal CLK1 ′.

[0151] Then, refer to Fig.12 and Fig.13 A method of generating the positive voltage V_OUT_CP1 as the output voltage in the charge pump circuit 125 is described.

[0152] Fig.12 is a diagram showing an operating state of the charge pump circuit 125 in the first operating section, and Fig.13 is a diagram showing an operating state of the charge pump circuit 125 in the second operating section.

[0153] Reference Fig.12 , the clock signal CLK1 and the inverted clock signal CLK1 ′ may have a voltage VLDO as a high level and 0V as a low level.

[0154] In the first operation section, the clock signal CLK1 may have a high level, and the inverted clock signal CLK1' may have a low level. The voltage VLDO may be applied to the pump capacitor C3 by the clock signal CLK1 having a high level, and 0V may be output to the pump capacitor C4 by the inverted clock signal CLK1' having a low level. Therefore, the n-type transistor M2 of the inverter 1251 may be turned on, so the inverter 1251 may output the power supply voltage VCC1 through the output terminal OUT1 of the inverter 1251, the pump capacitor C4 may be charged with the power supply voltage VCC1, and the pump capacitor C3 may be charged with the voltage VLDO. In addition, the p-type transistor M3 of the inverter 1252 may be turned on, and the voltage VLDO charged in the pump capacitor C3 may be transmitted to the node N1 through the output terminal OUT2 of the inverter 1252 and the p-type transistor M3 of the inverter 1252.

[0155] Next, refer to Fig.13, in the second operation section, the clock signal CLK1 may have a low level, and the inverted clock signal CLK1' may have a high level. In the first operation section, the pump capacitor C3 is charged with the voltage VLDO, and the pump capacitor C4 is charged with the power supply voltage VCC1. In the second operation section, 0V is applied to the pump capacitor C3 by the clock signal CLK1 having 0V, and the voltage VLDO is applied to the pump capacitor C4 by the inverted clock signal CLK1' having a high level. Therefore, the pump capacitor C4 may be charged with the voltage VLDO+VCC1, the p-type transistor M1 of the inverter 1251 may be turned on, and the voltage VLDO+VCC1 charged in the pump capacitor C4 may be transmitted to the node N1 through the output terminal OUT1 of the inverter 1251 and the p-type transistor M1 of the inverter 1251. Furthermore, the n-type transistor M4 of the inverter 1252 may be turned on, so the inverter 1252 may output the power supply voltage VCC1 through the output terminal OUT2 through the n-type transistor M4 , and the pump capacitor C3 may be charged with the voltage VLDO+VCC1 .

[0156] According to the clock signal CLK1 and the inverted clock signal CLK1', the Fig.12 The first operating section shown and Fig.13 The second operation section is shown, and the voltage of the node N1 can gradually increase and eventually become the voltage VLDO+VCC1. That is, the charge pump circuit 125 can output the positive voltage VLDO+VCC1 as the output voltage V_OUT_CP1.

[0157] In this way, the charge pump circuit 125 can provide the voltage VLDO+VCC1 higher than the power supply voltage VCC1 as the turn-on control signal of the transistor SW1 .

[0158] The charge pump circuit 126 may also be configured similarly or identically to the charge pump circuit 125. The charge pump circuit 126 may provide a voltage VLDO+VCC1 higher than the power supply voltage VCC1 as a turn-on control signal of the transistor SW2.

[0159] Fig.14 It shows that the application Figure 1 FIG. 1 is a diagram of an example of a communication terminal system of a power selection switch circuit shown.

[0160] Reference Fig.14 , the communication terminal system 1400 may include a plurality of power amplifiers 300_1 , 300_2 , 300_3 , and 300_4 , power selection switch circuits 100_1 and 100_2 , and PMICs 200_1 and 200_2 .

[0161] The power amplifier 300_1 may operate by receiving the power supply voltage VCC1 from the PMIC 200_1, amplify an input RF signal, and output the amplified RF signal.

[0162] The power amplifier 300_4 may operate by receiving the power supply voltage VCC2 from the PMIC 200_2 , amplify an input RF signal, and output the amplified RF signal.

[0163] The power amplifier 300_2 may operate by receiving a power supply voltage selected by the power supply selection switch circuit 100_1 , amplify an input RF signal, and output the amplified RF signal.

[0164] The power amplifier 300_3 may operate by receiving the power supply voltage selected by the power supply selection switch circuit 100_2 , amplify the input RF signal, and output the amplified RF signal.

[0165] The power selection switch circuit 100_1 may select one of the power supply voltages VCC1 and VCC2 and provide the selected power supply voltage to the power amplifier 300_2 .

[0166] The power selection switch circuit 100_2 may select one of the power supply voltages VCC1 and VCC2 and provide the selected power supply voltage to the power amplifier 300_3 .

[0167] The PMIC 200_1 may generate a power supply voltage VCC1 from a main power supply.

[0168] The PMIC 200_2 may generate a power supply voltage VCC2 from a main power supply.

[0169] Generally, four PMICs are required to operate four power amplifiers, but by using a power selection switch circuit, the number of PMICs can be reduced and the cost of the communication terminal system can be reduced.

[0170] Furthermore, as described above, in the power selection switch circuits 100_1 and 100_2 , the two transistors SW1 and SW2 may be configured as n-type transistors, respectively, thereby reducing the size of the power amplifier module when the power amplifier module is implemented.

[0171] Fig.15 It shows that the application Figure 1 FIG. 2 is a diagram of another example of a communication terminal system of the power selection switch circuit shown.

[0172] Reference Fig.15 ,and Fig.14 Differently, the power amplifier 300_3 of the communication terminal system 1500 can receive the power supply voltage from the power supply selection switch circuit 100_1.

[0173] In this way, with Fig.14 In comparison, the number of power selection switches can be reduced.

[0174] According to at least one embodiment, by selectively providing a power supply voltage to a power amplifier via a power supply selection switch circuit, the number of power supply integrated circuits (ICs) can be reduced.

[0175] According to at least one embodiment, two transistors in a power selection switch circuit can be prevented from being turned on at the same time, thereby protecting a power amplifier from overcurrent.

[0176] According to at least one embodiment, two transistors in a power selection switch circuit are configured as n-type transistors so that the mounting area of ​​the two transistors in a power amplifier module can be reduced compared to a case where each transistor in the power selection switch circuit is configured by a p-type transistor and an n-type transistor.

[0177] At least one embodiment may provide a power selection switch circuit that may reduce the size of a power amplifier module.

[0178] At least one embodiment may provide a power selection switch circuit capable of providing a gate control voltage at a voltage level sufficiently higher than an input DC power supply voltage.

[0179] Although specific examples have been shown and described above, it will be readily understood after understanding the present disclosure that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein will be considered as descriptive only, and not for limiting purposes. The description of the features or aspects in each example will be considered applicable to similar features or aspects in other examples. If the described techniques are performed in a different order, and / or if the components in the described system, architecture, device, or circuit are combined in a different manner and / or replaced or supplemented by other components or their equivalents, the components in the described system, architecture, device, or circuit can be obtained. Appropriate results can be obtained. Therefore, the scope of the present disclosure is not limited by specific embodiments, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents will be interpreted as included in the present disclosure.

Claims

1. A power selection switch circuit, configured to select any one of a first power supply voltage and a second power supply voltage and supply the selected power supply voltage to a power amplifier, the power selection switch circuit comprising: a first n-type transistor configured to be turned on in response to a first switch control signal having a first voltage generated by charge pumping the first supply voltage and supplying the first supply voltage to a power supply terminal of the power amplifier when turned on; as well as The second n-type transistor is configured to be turned on in response to a second switch control signal having a second voltage generated by charge pumping the second power supply voltage and supply the second power supply voltage to the power supply terminal of the power amplifier when turned on.

2. The power selection switch circuit according to claim 1, further comprising: a switch controller configured to generate the first switch control signal and the second switch control signal using a first bit signal and a second bit signal input from an external source, so that the transistor to be turned on from the off state of the first n-type transistor and the second n-type transistor is turned on after a delay of a predetermined time, and the transistor to be turned off from the on state of the first n-type transistor and the second n-type transistor is turned off immediately, The first n-type transistor is configured to be turned off in response to the first switch control signal having a third voltage lower than the first voltage, and the second n-type transistor is configured to be turned off in response to the second switch control signal having a fourth voltage lower than the second voltage.

3. The power selection switch circuit according to claim 2, wherein: The switch controller comprises: a logic circuit configured to generate a first logic signal for generating the first switch control signal and a second logic signal for generating the second switch control signal by combining the first bit signal and the second bit signal; a first delay circuit configured to delay the first logic signal to generate a first delayed signal; a second delay circuit configured to delay the second logic signal to generate a second delayed signal; a first buffer control circuit configured to supply the first voltage or the third voltage as the first switch control signal to a control terminal of the first n-type transistor in response to the first delay signal; and The second buffer control circuit is configured to supply the second voltage or the fourth voltage as the second switch control signal to the control terminal of the second n-type transistor in response to the second delay signal.

4. The power selection switch circuit according to claim 3, wherein: The first bit signal and the second bit signal have a value of 0 or 1, and The logic circuit is configured to set both the first logic signal and the second logic signal to a low level when the first bit signal and the second bit signal are both 1 or both 0, so that both the first n-type transistor and the second n-type transistor are turned off.

5. The power selection switch circuit according to claim 4, wherein: The switch controller further comprises: a first clock generator configured to: operate in response to the first logic signal and generate a first clock signal having a fifth voltage and a sixth voltage lower than the fifth voltage; a second clock generator configured to: operate in response to the second logic signal and generate a second clock signal having the fifth voltage and the sixth voltage; a first charge pump circuit configured to generate the first voltage by charge pumping the first power supply voltage with the fifth voltage in response to the first clock signal, and provide the first voltage to the first buffer control circuit; and The second charge pump circuit is configured to generate the second voltage by charge pumping the second power supply voltage with the fifth voltage in response to the second clock signal, and provide the second voltage to the second buffer control circuit.

6. The power selection switch circuit according to claim 5, wherein: The first logic signal and the second logic signal have a high level and a low level, respectively, and The first clock generator and the second clock generator operate at a high level of the first logic signal and a high level of the second logic signal, respectively, and do not operate at a low level.

7. The power selection switch circuit according to claim 3, wherein: The logic circuit comprises: A NAND gate configured to receive the first bit signal and the second bit signal; a first AND gate configured to receive the first bit signal and the output of the NAND gate, and output the first logic signal; and The second AND gate is configured to receive the second bit signal and the output of the NAND gate, and output the second logic signal.

8. The power selection switch circuit according to claim 3, wherein: The first delay circuit comprises: A first delay unit configured to delay the first logic signal; and a first AND gate configured to receive the first logic signal and a signal delayed by the first delay unit, and Wherein, the second delay circuit comprises: A second delay unit configured to delay the second logic signal; and The second AND gate is configured to receive the second logic signal and the signal delayed by the second delay unit.

9. A power amplifier module, comprising: The power amplifier and the power selection switch circuit of claim 1.

10. A power amplifier module, comprising: a power amplifier configured to receive a power supply voltage from a power supply terminal, and to amplify an input signal and output an amplified signal; as well as A power selection switch circuit is configured to provide any one of a first power supply voltage supplied from a first power management integrated circuit and a second power supply voltage supplied from a second power management integrated circuit to the power terminal, wherein: The power selection switch circuit comprises: a first n-type transistor configured to have a first terminal connected to the first power management integrated circuit, a second terminal connected to the power supply terminal, and a control terminal receiving a first switch control signal having a first voltage generated by charge pumping the first power supply voltage; and A second n-type transistor is configured to have a first terminal connected to the second power management integrated circuit, a second terminal connected to the power terminal, and a control terminal receiving a second switch control signal, the second switch control signal having a second voltage generated by charge pumping the second power supply voltage.

11. The power amplifier module according to claim 10, wherein: The power selection switch circuit also includes: A switch controller is configured to generate the first switch control signal and the second switch control signal so that the first n-type transistor is turned on after a predetermined delay when the first n-type transistor is about to change from an off state to an on state, and the second n-type transistor is turned on after a predetermined delay when the second n-type transistor is about to change from an off state to an on state.

12. The power amplifier module according to claim 11, wherein: The first n-type transistor is configured to be turned off in response to the first switch control signal having a third voltage lower than the first voltage, and the second n-type transistor is configured to be turned off in response to the second switch control signal having a fourth voltage lower than the second voltage.

13. The power amplifier module according to claim 12, wherein: The switch controller comprises: a logic circuit configured to generate a first logic signal for generating the first switch control signal and a second logic signal for generating the second switch control signal by combining a first bit signal and a second bit signal input from the outside; a first delay circuit configured to delay the first logic signal to generate a first delayed signal; a second delay circuit configured to delay the second logic signal to generate a second delayed signal; a first buffer control circuit configured to supply the first voltage or the third voltage as the first switch control signal to a control terminal of the first n-type transistor in response to the first delay signal; and The second buffer control circuit is configured to supply the second voltage or the fourth voltage as the second switch control signal to the control terminal of the second n-type transistor in response to the second delay signal.

14. The power amplifier module according to claim 13, wherein: The first bit signal and the second bit signal have a value of 0 or 1, and The logic circuit is configured to set both the first logic signal and the second logic signal to a low level when the first bit signal and the second bit signal are both 1 or both 0, so that both the first n-type transistor and the second n-type transistor are turned off.

15. The power amplifier module according to claim 14, wherein: The switch controller comprises: a first clock generator configured to: operate in response to the first logic signal and generate a first clock signal having a fifth voltage and a sixth voltage lower than the fifth voltage; a second clock generator configured to: operate in response to the second logic signal and generate a second clock signal having the fifth voltage and the sixth voltage; a first charge pump circuit configured to generate the first voltage by charge pumping the first power supply voltage with the fifth voltage in response to the first clock signal, and provide the first voltage to the first buffer control circuit; and The second charge pump circuit is configured to generate the second voltage by charge pumping the second power supply voltage with the fifth voltage in response to the second clock signal, and provide the second voltage to the second buffer control circuit.

16. The power amplifier module according to claim 10, wherein: The first n-type transistor includes a plurality of third transistors connected in parallel, The second n-type transistor includes a plurality of fourth transistors connected in parallel, and The plurality of third transistors and the plurality of fourth transistors are n-type transistors.

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