Phase-locked loop applied to CMOS (complementary metal oxide semiconductor) image sensor during VBlank period

Abstract

The invention discloses a phase-locked loop applied to a CMOS (complementary metal oxide semiconductor) image sensor during a Vbank period, which comprises a phase frequency detector, a charge pump, a low-pass filter, an oscillator, a loop frequency divider and a rear frequency divider, and is characterized in that the phase frequency detector carries out phase frequency detection on an input reference clock and a feedback clock to obtain a pulse signal to control the output current of the charge pump; the output of the charge pump is processed by the low-pass filter to obtain a voltage value to control the frequency of the oscillator; two switches are arranged between the low-pass filter and the charge pump, and rapid locking of the phase-locked loop is realized through the two switches; the output of the oscillator is subjected to frequency division by the loop frequency divider to obtain a feedback clock, and the feedback clock is input to the phase frequency detector; and the final loop output is a locked clock, and a clock signal required by a post-stage circuit is obtained after the loop output is subjected to frequency division processing by a post frequency divider. The phase-locked loop with the structure can realize quick locking, effectively shorten the locking time and reduce the power consumption of the CMOS image sensor.

Description

Technical Field

[0001] The present invention relates to the technical field of CMOS image sensors, and in particular to a phase-locked loop applied to a CMOS image sensor during a Vblank period. Background Art

[0002] At present, with the development of CMOS image sensors, the demand for low power consumption is increasing day by day. As an important functional module of CMOS image sensors, the phase-locked loop (PLL) provides a working clock for them. If the phase-locked loop PLL is turned off during the Vblank period of the CMOS image sensor and turned on during the normal working period of the CMOS image sensor, the power consumption can be reduced. However, in the existing solution, it takes a long time for the phase-locked loop PLL to enter the locked state after it is turned off, which affects the performance of the image sensor. Summary of the invention

[0003] The purpose of the present invention is to provide a phase-locked loop applied to a CMOS image sensor during Vblank. The phase-locked loop with this structure can achieve fast locking and effectively shorten the locking time, thereby reducing the power consumption of the CMOS image sensor.

[0004] The objective of the present invention is achieved through the following technical solutions:

[0005] A phase-locked loop applied to a CMOS image sensor during Vblank, the phase-locked loop comprising a frequency detector, a charge pump, a low-pass filter, an oscillator, a loop divider and a post divider, wherein:

[0006] The frequency detector and phase detector perform frequency detection and phase detection on the input reference clock and the feedback clock, and the obtained pulse signal controls the output current of the charge pump;

[0007] The output of the charge pump is processed by a low-pass filter to obtain a voltage value to control the frequency of the oscillator;

[0008] Two CMOS switches are arranged between the low-pass filter and the charge pump, and the fast locking of the phase-locked loop is achieved through the two CMOS switches;

[0009] The output of the oscillator is divided by the loop frequency divider to obtain a feedback clock, which is input into the frequency and phase detector;

[0010] The final loop output is a locked clock, and the post-frequency divider performs frequency division processing on the loop output to obtain a clock signal required by the subsequent circuit.

[0011] The fast locking of the phase-locked loop is achieved by setting two CMOS switches, and the specific process is as follows:

[0012] SW and SWb are switch on / off control signals, and VCT is the control voltage of the oscillator;

[0013] Assuming that when the phase-locked loop is locked, VCT is voltage V1, when SW is 0 and SWb is 1, the first CMOS switch is turned off and VCT remains near voltage V1;

[0014] A second CMOS switch is connected between the drain end of the MOS tube P1 in the oscillator and the oscillation ring. When SW is 0 and SWb is 1, the second CMOS switch is disconnected, the output of the oscillator is 0, and therefore the output of the phase-locked loop is 0, achieving low power consumption.

[0015] When SW is 1 and SWb is 0, both the first CMOS switch and the second CMOS switch are turned on, and the oscillator starts to oscillate. Because VCT remains near the voltage V1, the phase-locked loop gradually locks from a frequency close to the locked state, achieving rapid locking of the phase-locked loop and enabling low power consumption of CMOS image sensing.

[0016] It can be seen from the technical solution provided by the present invention that the phase-locked loop with the above structure can achieve fast locking and effectively shorten the locking time, thereby reducing the power consumption of the CMOS image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0018] Figure 1 A schematic diagram of the structure of a phase-locked loop applied to a CMOS image sensor during the Vblank period provided by an embodiment of the present invention;

[0019] Figure 2 The figure is a schematic diagram of the structure of the oscillator after adding a switch according to the embodiment of the present invention. DETAILED DESCRIPTION

[0020] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments, which does not constitute a limitation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] The following will further describe the embodiments of the present invention in detail in conjunction with the accompanying drawings. The contents not described in detail in the embodiments of the present invention belong to the prior art known to professionals in the field. In the embodiments of the present invention, if specific conditions are not specified, they are carried out according to the conditions of normal conditions in the field or the manufacturer's recommendations. If the manufacturer is not specified in the reagents or instruments in the embodiments of the present invention, they are all conventional products that can be purchased commercially.

[0022] like Figure 1 FIG. 1 is a schematic diagram of the structure of a phase-locked loop applied to a CMOS image sensor during the Vblank period provided by an embodiment of the present invention, wherein the phase-locked loop includes a frequency detector, a charge pump, a low-pass filter, an oscillator, a loop divider, and a post-divider, wherein:

[0023] The frequency detector and phase detector perform frequency detection and phase detection on the input reference clock and the feedback clock, and the obtained pulse signal controls the output current of the charge pump;

[0024] The output of the charge pump is processed by a low-pass filter to obtain a voltage value to control the frequency of the oscillator;

[0025] Two CMOS switches are arranged between the low-pass filter and the charge pump, and the fast locking of the phase-locked loop is achieved through the two CMOS switches;

[0026] The output of the oscillator is divided by the loop frequency divider to obtain a feedback clock, which is input into the frequency and phase detector;

[0027] The final loop output is a locked clock, and the post-frequency divider performs frequency division processing on the loop output to obtain a clock signal required by the subsequent circuit.

[0028] In a specific implementation, the specific process of realizing fast locking of the phase-locked loop by setting two CMOS switches is as follows:

[0029] SW and SWb are switch on / off control signals, and VCT is the control voltage of the oscillator;

[0030] Assuming that when the phase-locked loop is locked, VCT is voltage V1, when SW is 0 and SWb is 1, the first CMOS switch 1 is disconnected and VCT remains near voltage V1;

[0031] like Figure 2 FIG. 1 is a schematic diagram of the structure of an oscillator after adding a switch according to an embodiment of the present invention. Figure 2 A second CMOS switch 2 is connected between the drain end of the MOS tube P1 in the oscillator and the oscillation ring. When SW is 0 and SWb is 1, the second CMOS switch 2 is disconnected, the output of the oscillator is 0, and therefore the output of the phase-locked loop is 0, achieving low power consumption.

[0032] When SW is 1 and SWb is 0, both the first CMOS switch 1 and the second CMOS switch 2 are turned on, and the oscillator starts to oscillate. Because VCT is kept near the voltage V1, the phase-locked loop gradually locks from a frequency close to the locked state, thereby achieving rapid locking of the phase-locked loop and enabling low power consumption of CMOS image sensing.

[0033] It is worth noting that the contents not described in detail in the embodiments of the present invention belong to the prior art known to professional and technical personnel in the field.

[0034] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or in any form that the information constitutes prior art known to those skilled in the art.

Claims

1. A phase-locked loop applied to a CMOS image sensor during Vblank, characterized in that: The phase-locked loop includes a phase frequency detector, a charge pump, a low-pass filter, an oscillator, a loop frequency divider and a post frequency divider, wherein: The frequency detector and phase detector perform frequency detection and phase detection on the input reference clock and the feedback clock, and the obtained pulse signal controls the output current of the charge pump; The output of the charge pump is processed by a low-pass filter to obtain a voltage value to control the frequency of the oscillator; Two CMOS switches are arranged between the low-pass filter and the charge pump, and the fast locking of the phase-locked loop is achieved through the two CMOS switches; The output of the oscillator is divided by the loop frequency divider to obtain a feedback clock, which is then input into the frequency and phase detector; The final loop output is a locked clock, and the post-frequency divider performs frequency division processing on the loop output to obtain a clock signal required by the subsequent circuit.

2. The phase-locked loop used in the Vblank period of a CMOS image sensor according to claim 1, characterized in that: The fast locking of the phase-locked loop is achieved by setting two CMOS switches, and the specific process is as follows: SW and SWb are switch on / off control signals, and VCT is the control voltage of the oscillator; Assuming that when the phase-locked loop is locked, VCT is voltage V1, when SW is 0 and SWb is 1, the first CMOS switch is turned off and VCT remains near voltage V1; A second CMOS switch is connected between the drain end of the MOS tube P1 in the oscillator and the oscillation ring. When SW is 0 and SWb is 1, the second CMOS switch is disconnected, the output of the oscillator is 0, and therefore the output of the phase-locked loop is 0, achieving low power consumption. When SW is 1 and SWb is 0, both the first CMOS switch and the second CMOS switch are turned on, and the oscillator starts to oscillate. Because VCT remains near the voltage V1, the phase-locked loop gradually locks from a frequency close to the locked state, achieving rapid locking of the phase-locked loop and enabling low power consumption of CMOS image sensing.

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