Offset voltage background calibration method for double-margin pipelined analog-to-digital converter

Abstract

The invention discloses an offset voltage background calibration method for a double-margin pipelined analog-to-digital converter. The offset voltage of the double-margin signal path seriously deteriorates the linearity of the analog-to-digital converter, and the differential-mode offset component and the common-mode offset component of the double-margin signal path are respectively obtained by counting and calculating the digital output standard deviation and the average value of the post-stage analog-to-digital converter, and the differential-mode offset component and the common-mode offset component are calibrated. A traditional amplifier-oriented offset voltage calibration method is mainly divided into two types, namely foreground calibration and background calibration, maladjustment caused by changes of external factors such as a power supply and temperature is generally difficult to track at any time, the calibration range is relatively limited, or extra time cost and hardware overhead are needed in the calibration process, and the working speed of an analog-digital converter is reduced. According to the invention, the offset of the margin amplifier can be calibrated in real time, extra time is not required to be occupied in the process of introducing offset by tracking the change of factors such as temperature and power supply, and the working speed of the analog-to-digital converter is ensured.

Description

Technical Field

[0001] The invention relates to the field of analog-to-digital conversion, and in particular to a background calibration method for an offset voltage of a dual-redundancy pipeline analog-to-digital converter. Background Art

[0002] The pipelined ADC with dual-residue structure is different from the traditional pipelined ADC with a single residue signal. After amplifying two adjacent residue signals, it serves as the reference voltage of the next-stage analog-to-digital converter to quantize the input zero signal. It does not require precise inter-stage gain, thus greatly reducing the accuracy and speed requirements for the inter-stage amplifier, and can achieve high-speed and high-precision conversion at a lower power consumption cost.

[0003] However, the offset introduced by the remainder amplifier in the signal path can affect the linearity of the ADC. Figure 2 Figure 1 shows the mismatch in the differential pair, which can introduce an offset voltage into the amplifier, thus reducing the accuracy of the dual-redundancy ADC. First, there is a mismatch in the resistors acting as the differential pair loads, ΔR L When the voltage V od1 =ΔR L I SS / 2, the offset voltage equivalent to the input terminal is:

[0004]

[0005] When there is a mismatch in the threshold voltage of the input pair, ΔV T When V od2 =ΔI·R L , the offset voltage equivalent to the input terminal is:

[0006]

[0007] Similarly, the offset voltage caused by the MOS tube parameter β is:

[0008] These three mismatches are independent of each other, so the total offset voltage equivalent to the input is:

[0009]

[0010] It can be seen from this that in order to reduce the amplifier offset voltage, V GS -V TSmall enough, the input pair size needs to be increased while ensuring that the tail current remains unchanged, but this method is too expensive and will introduce other nonlinear parasitics. If a foreground calibration of the offset voltage is performed before the analog-to-digital converter starts working, this method can eliminate the fixed offset caused by process errors during the manufacturing process, but it is difficult to ensure the stability of the working environment during the operation of the analog-to-digital converter. For example, when the temperature changes, a new ΔR will appear. L , ΔV T The offset voltage introduced by these mismatches is continuously changing and there is no redundant calibration to eliminate it, which reduces the linearity of the analog-to-digital converter. In 1999, Hendrik van der Ploeg et al. proposed a background calibration that can track the offset voltage introduced by the working environment changes in the circuit in real time. It takes extra time in the calibration process and reduces the conversion speed of the analog-to-digital converter. In 2006, Pedro M. Figueiredo et al. proposed to offset the delay caused by calibration by alternating the two sub-analog-to-digital converters. This method ensures the conversion speed of the analog-to-digital converter, but also leads to an increase in area and power consumption. Summary of the invention

[0011] The technical problem to be solved by the present invention is to provide a background calibration method for the offset voltage of a dual-redundancy pipeline analog-to-digital converter in view of the defects involved in the background technology.

[0012] The present invention adopts the following technical solutions to solve the above technical problems:

[0013] A method for background calibration of offset voltage of a dual-redundancy pipeline analog-to-digital converter comprises the following steps:

[0014] Step 1) Set the offset voltage V of the two residual amplifiers OS1 and V OS2 Converted to differential mode component V OSD and the common mode component V OSC Indicates that V OS1 =V OSC -V OSD / 2,V OS2 =V OSC +V OSD / 2;

[0015] Step 2), based on the margin V of the two signal paths of the analog-to-digital converter res1 and V res2 , combining the offset voltages of the two margin amplifiers V OS1 and V OS2 , the quantization result of the second stage of the analog-to-digital converter is Where N is the number of quantization bits in the second stage of the analog-to-digital converter;

[0016] Step 3), perform gain error calibration on the quantization result of the second stage of the analog-to-digital converter and multiply it by Get the quantization result after eliminating the gain error

[0017] Step 4) Perform offset calibration on the quantization result after eliminating the gain error and subtract it from Get the final calibration result

[0018] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0019] The present invention can track the offset voltage introduced by changing factors such as power supply and temperature and calibrate it in real time, expand the application scenarios of the analog-to-digital converter, avoid adding additional working phases, and ensure the original working speed of the analog-to-digital converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of the background calibration of the offset voltage of the dual-margin pipeline analog-to-digital converter

[0021] Figure 2 This is a schematic diagram of the cause of amplifier offset voltage;

[0022] Figure 3 (a) is a schematic diagram showing the effect of the offset common mode component on the dual-residue signal;

[0023] Figure 3 (b) is a schematic diagram showing the effect of the offset differential mode component on the dual-residue signal;

[0024] Figure 3 (c) is a schematic diagram showing the influence of the offset common mode component and the differential mode component on the dual-residue signal;

[0025] Figure 4 (a) is a schematic diagram of the logic of first offset and then gain error calibration;

[0026] Figure 4 (b) is a schematic diagram of the logic of first gain error and then offset calibration;

[0027] Figure 5 This is the flow chart of the background calibration of the offset voltage;

[0028] Figure 6 (a) is a schematic diagram of the convergence curve of the gain error calibration factor;

[0029] Figure 6 (b) is a schematic diagram of the convergence curve of the offset calibration factor;

[0030] Figure 7 (a) is a schematic diagram showing the effect of offset voltage on dual-residue signal;

[0031] Figure 7 (b) is a schematic diagram of the calibrable offset voltage range. DETAILED DESCRIPTION

[0032] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings:

[0033] The present invention can be implemented in many different forms and should not be considered to be limited to the embodiments described herein. On the contrary, these embodiments are provided to make this disclosure thorough and complete, and will fully express the scope of the present invention to those skilled in the art. In the accompanying drawings, components are enlarged for clarity.

[0034] The present invention introduces a background offset calibration scheme for a low-power, high-speed, high-precision dual-residue pipelined ADC. After the differential input signal enters the first stage of the analog-to-digital converter, the two residual signals of the last conversion cycle are sampled to the residual amplifier and amplified by the same multiple, which is used as the reference voltage of the second stage of the analog-to-digital converter to quantize the 0 input signal of the second stage. The second stage can be a flash analog-to-digital converter (flash ADC) or a successive approximation analog-to-digital converter (SAR ADC). When the two residual signals are amplified, the offset of the residual amplifier will affect the linearity of the analog-to-digital converter. During the manufacturing process, the offset is inevitably introduced due to the process error. In order to eliminate the influence of the error, a foreground calibration is performed at power-on, but the calibration only eliminates the fixed offset. During the operation of the analog-to-digital converter, a random offset is generated due to the change of the working environment. The offset introduces nonlinearity and determines the performance of the circuit. The present invention introduces an algorithm that can always track and calibrate the random offset introduced by factors such as temperature and power supply changes. After calibration, the performance of the circuit is guaranteed.

[0035] The dual-residue signal path contains two residue amplifiers, each of which corresponds to a random offset voltage. These two unrelated offset voltages are converted into a differential component V OSD and the common mode component V OSC The offset voltage of the residual amplifier 1 equivalent to the input terminal is V OSC +V OSD / 2, the offset voltage of the residual amplifier 2 equivalent to the input terminal is V OSC -V OSD / 2. The two residual signals are amplified as the positive and negative reference voltages of the second stage of the analog-to-digital converter to quantize the input differential zero signal. In essence, the absolute value of one reference voltage is compared with the sum of the absolute values ​​of the two reference voltages, and then multiplied by the quantization level of the second stage (2 N , N is the number of second-level quantization bits).

[0036] The offset voltage of the two residual signal paths is considered to be composed of common-mode and differential-mode components. The two offset components have different effects on the analog-to-digital converter. Figure 3 As shown in (a), V OSC Causes the double margin signal to shift up or down, from V res1 and V res2 becomes V res1 -V OSC and V res2 +V OSC , where V res1 and V res2 is the absolute value of the margin voltage of the two signal paths. It can be seen that V OSC The sum of the two residual voltages under the action is still V res1 +V res2 , has not changed, but the quantitative results have changed from becomes Generates offset voltage Although V OSC It does not affect the dynamic performance of the analog-to-digital converter and is reflected as a DC component in the spectrum. However, there are usually redundant bits between the first and second stages of the pipelined analog-to-digital converter, and the offset common-mode component will occupy part of the redundant space. Assuming that the offset occupies all the redundant space in the extreme case, the quantization of the first stage of the analog-to-digital converter will not be allowed to make mistakes, otherwise it will exceed the redundant range, resulting in all 0s or all 1s in the second stage quantization. Therefore, the offset voltage common-mode component should be calibrated if it can be calibrated. Figure 3 As shown in (b), V OSD The quantization range of the subsequent analog-to-digital converter changes from V res1 +V res2 becomes V res1 +V res2 +V OSD , the 0 input position also changes from V res1 becomes V res1 +V OSD / 2, the quantitative results are becomes The change of quantization range will introduce a gain error, and the change of 0 input position will introduce an offset voltage. Compared with the offset, the gain error will cause serious nonlinearity and have a greater impact on the performance of the analog-to-digital converter. OSC and V OSD When Figure 3 (c) shows the quantization result is the same as that of the case with only V OSD The results obtained are similar to There are two forms of mismatch involved, offset and gain error.

[0037] The two mode components of the offset will be reflected in the final quantized results as offset and gain errors, which means that the two mismatches can be calibrated independently point-to-point. Figure 4 (a) Figure 4 (b) shows the logic diagram of the two calibration sequences. Figure 4 The calibration sequence in (a) is to first perform the offset calibration and then subtract the calibration factor Afterwards, the calibrated data Multiply by the gain error calibration factor Theoretically, this calibration sequence is feasible, but the offset calibration factor Cal.O in the first step contains not only the offset voltage to be calibrated, but also the gain error, which goes against the original intention of calibrating the two mismatches independently, and the calibration is more complicated to implement. Figure 4 The calibration sequence in (b) is to first calibrate the gain error and then multiply by the calibration factor After getting After that, the offset voltage calibration is performed. Although the offset calibration factor is V OSC and V OSD , but it can be considered as a DC offset and calibrated together. Figure 4 The calibration sequence in (b) realizes independent calibration of gain error and offset, and calibrates gain error by standard deviation and offset by mean, which is relatively easy to implement.

[0038] Figure 5 A flowchart is given for first performing gain error calibration and then offset calibration. During the calibration process, mean and standard deviation operations are required. In addition, reference standard deviation Ref.σ and reference mean Ref.μ are also required. When the dual-residue Pipelined ADC starts to power on, the two residue amplifiers can be calibrated in sequence through the foreground calibration in Jin Xin's 2021 paper to eliminate the fixed offset caused by process errors during the manufacturing process. The quantization results of the second stage of the analog-to-digital converter within a certain period of time after the foreground calibration are taken to obtain Ref.σ and Ref.μ through calculation. During the background calibration process, the ratio of the real-time standard deviation to Ref.σ is used as the gain error calibration factor Cal.G and the quantization output D OUT2 'Multiply to get D OUT2 ”, for D OUT2 "The average value is subtracted from Ref.μ to obtain the offset voltage that needs to be calibrated, D OUT2 Subtract the offset calibration factor Cal.O to get the final output D OUT2 , the calibration is completed.

[0039] Figure 6(a) and (b) show the convergence curves of the gain error calibration factor Cal.G and the offset calibration factor Cal.O. It can be seen from the figure that after 10,000 sample calibrations, both calibration factors have achieved convergence. Assuming that the sampling rate of the analog-to-digital converter in the actual circuit is 1GS / s, the time corresponding to 10,000 samples is 10us, the working environment remains basically unchanged in a short period of time, and the offset voltage is fixed. During the time when the offset voltage remains unchanged, the calibration is completed in a relatively short time, ensuring that the analog-to-digital converter maintains a high linearity for most of the time.

[0040] The behavioral level simulation verification is carried out for the background calibration algorithm mentioned above. The model is a two-stage pipelined ADC. Taking the analog-to-digital converter with an 8-bit dual-redundancy architecture in the first stage, a 6-bit split capacitor architecture in the second stage, and 2-bit redundancy between stages as an example, the present invention is also applicable to all analog-to-digital converters with dual-redundancy structures. In the ideal quantization case, the margin of the first stage of the analog-to-digital converter should be concentrated at Figure 7 (a) In the black area on the left, the range is 16LSB, the LSB size is 1200mV / 2^12, and the upper and lower red areas are the margins brought by the 2-bit redundancy. The total range is 64LSB, corresponding to the 6-bit quantization of the second stage of the analog-to-digital converter. Figure 7 (a) As can be seen in the right figure, when there is an offset voltage, the margin brought by the redundant bit will change with the offset size. When the margin is greater than or equal to 0, the second stage of the analog-to-digital converter can be quantized normally. When the margin is less than 0, the second stage quantization result will be all 0 or all 1. For the background calibration algorithm mentioned above, the prerequisite is that the second stage can be quantized normally. Based on this, the following requirements are imposed on the two components of the offset voltage:

[0041]

[0042] According to the above formula, we can get Figure 7 (b) shows the range of the background calibration algorithm, when the offset common mode and differential mode components are within the gray area.

[0043] The following table compares the performance of the analog-to-digital converter before and after calibration for different common-mode and differential-mode offset voltage components.

[0044]

[0045] It can be seen from the table that when the offset voltage is Figure 7In the gray area of ​​(b), the common-mode component of the offset voltage does not affect the dynamic performance of the ADC. Regardless of whether background calibration is performed, the effective number of bits (ENOB) and spurious-free dynamic range (SFDR) of the ADC remain at 11.9 bits and 90 dB. The performance of the ADC deteriorates as the differential-mode component of the offset voltage increases, but after background calibration, the ENOB of the ADC is above 11.5 bits and the SFDR is above 85 dB. In addition, when the offset voltage exceeds Figure 7 In the gray area of ​​(b), regardless of whether calibration is performed, the ENOB of the ADC remains around 8 bits, which means that the second-level quantization of the ADC fails. The amplifier offset voltage caused by changes in the working environment is controllable, ensuring the normal operation of the background calibration algorithm in most cases.

[0046] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless defined as herein.

[0047] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A background calibration method for offset voltage of a dual-redundancy pipeline analog-to-digital converter, characterized in that: The following steps are involved: Step 1) Set the offset voltage V of the two residual amplifiers OS1 and V OS2 Converted to differential mode component V OSD and the common mode component V OSC Indicates that V OS1 =V OSC -V OSD / 2,V OS2 =V OSC +V OSD / 2; Step 2), based on the margin V of the two signal paths of the analog-to-digital converter res1 and V res2 , combining the offset voltages of the two margin amplifiers V OS1 and V OS2 , the quantization result of the second stage of the analog-to-digital converter is Where N is the number of quantization bits in the second stage of the analog-to-digital converter; Step 3), perform gain error calibration on the quantization result of the second stage of the analog-to-digital converter and multiply it by Get the quantization result after eliminating the gain error Step 4) Perform offset calibration on the quantization result after eliminating the gain error and subtract it from Get the final calibration result

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