High-precision dynamic comparator with automatic offset voltage calibration circuit

Abstract

The present invention relates to a high-precision dynamic comparator with an offset voltage automatic calibration circuit. A switched-capacitor preamplifier is adopted, so that the comparators applied in FLASH ADCs will not have different DC parameters due to different common-mode voltages, thereby reducing the offset voltage between different comparators. Moreover, a substrate voltage biasing technique is adopted to make the sampling switch have a smaller resistance when conducting and a larger resistance when cutoff. The offset voltage automatic calibration circuit ACC enables the circuit to adaptively adjust the offset voltage according to the process errors during the manufacturing process. Compared with traditional comparators, the design form of a switched-capacitor comparator is adopted, so that the input signal of the comparator is near the common-mode voltage VCM, ensuring that each comparator will not have an offset voltage error caused by different DC parameters due to different common-mode voltages, and the offset voltage automatic calibration circuit ACC makes the offset voltage of the comparator even smaller.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuit design, and relates to a high-precision dynamic comparator with an offset voltage automatic calibration circuit. Background Art

[0002] A dynamic high-precision comparator is a key component in modern electronic technology, especially playing a crucial role in an ADC (Analog-to-Digital Converter). A dynamic comparator is a circuit for comparing the magnitudes of voltages. When the input signals are different, the discharge speed of the output stage circuit is made different, and a positive feedback is introduced to further accelerate the discharge speed so as to achieve the comparison effect. However, due to the mismatches existing in the manufacturing process, there will inevitably be a problem that the comparison threshold of the comparator deviates. This is unacceptable in high-precision comparators. Therefore, how to implement a dynamic comparator with high precision and an offset voltage self-calibration function has become a technical problem to be solved. Summary of the Invention

[0003] In view of the problems existing in the above-mentioned traditional technologies, the present invention proposes a high-precision dynamic comparator with an offset voltage automatic calibration circuit, which can implement a dynamic comparator with high precision and an offset voltage self-calibration function.

[0004] To achieve the above object, the embodiments of the present invention adopt the following technical solutions:

[0005] Provide a high-precision dynamic comparator with an offset voltage automatic calibration circuit, including a signal sampling circuit, a preamplifier, and a dynamic latch. The signal sampling circuit is designed based on a bootstrapped transistor source follower (BTSP) circuit and uses a substrate voltage biasing technique. The dynamic latch includes a latch (LAT), an offset voltage automatic calibration circuit (ACC), and a dynamic comparator;

[0006] The sampling input terminal of the signal sampling circuit is used to access the input signal and the reference signal to be sampled. The output terminal of the signal sampling circuit is connected to the input terminal of the preamplifier. The output terminal of the preamplifier is connected to the input terminal of the dynamic comparator. The output terminal of the dynamic comparator is respectively connected to the input terminal of the latch (LAT) and the input terminal of the offset voltage automatic calibration circuit (ACC). The output terminal of the offset voltage automatic calibration circuit (ACC) is connected to the calibration input terminal of the dynamic comparator;

[0007] The signal sampling circuit is used to sample the input signal and the reference signal. The preamplifier is used to pre-amplify the sampling output of the signal sampling circuit. The offset voltage automatic calibration circuit (ACC) is used to adaptively reduce the offset voltage of the dynamic comparator according to the process errors in the manufacturing process. The dynamic comparator is used to perform data comparison. The latch (LAT) is used to control whether the output signal of the dynamic comparator changes with the change of the input signal.

[0008] In one embodiment, the signal sampling circuit includes an inverter INV0, an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, a bootstrapping circuit BTSP, transistors NMOS0, NMOS1, NMOS2, NMOS3, NMOS4, NMOS5, NMOS6, NMOS7, a transistor PMOS0, a capacitor C0, and a capacitor C1;

[0009] The PHI terminal of the bootstrapping circuit BTSP is used to access the control signal VSAMP through the inverter INV0, the PHIB terminal of the bootstrapping circuit BTSP is used to access the control signal VSAMP, the VIN terminal of the bootstrapping circuit BTSP is used to access the input signal VSIG, and the OUT terminal of the bootstrapping circuit BTSP is respectively connected to the gates of the transistor NMOS0 and the transistor NMOS1;

[0010] The drains of the transistor NMOS0 and the transistor NMOS1 are connected and used to access the input signal VSIG. The substrate terminal of the transistor NMOS0 is respectively connected to the source of the transistor NMOS1 and the drain of the transistor NMOS2. The source of the transistor NMOS0 is connected to one end of the capacitor C0. The gate of the transistor NMOS2 is used to access the control signal VSAMP. The source of the transistor NMOS2 is grounded. The drain of the transistor NMOS3 and the drain of the transistor PMOS0 are connected and used to access the reference signal VREF. The source of the transistor NMOS3 and the source of the transistor PMOS0 are connected and connected to one end of the capacitor C0. The other end of the capacitor C0 is connected to the first input terminal of the preamplifier. The inverters INV1, INV2, and INV3 are connected in series in sequence. The input terminal of the inverter INV1 is used to access the input signal PHIB. The output terminal of the inverter INV3 is connected to the gate of the transistor PMOS0. The gate of the transistor NMOS3 is connected to the output terminal of the inverter INV2;

[0011] Inverter INV4 and inverter INV5 are connected in series. The input terminal of inverter INV4 is used to receive the input signal NCON2. The output terminal of inverter INV5 is connected to the gate of transistor NMOS5. The drains of transistor NMOS4 and transistor NMOS5 are both connected to one end of capacitor C1. The drain of transistor NMOS6 is connected to the other end of capacitor C1. The other end of capacitor C1 is connected to the second input terminal of the preamplifier. The gate of transistor NMOS4 is connected to the output terminal of inverter INV0. The source of transistor NMOS4 is used to receive the signal VSS. The source of transistor NMOS5 is used to receive the reference signal VREFN. The gate of transistor NMOS6 is used to receive the input signal PHIB. The substrate of transistor NMOS6 is used to receive the signal VSS. The sources of transistor NMOS6 and transistor NMOS7 are both used to receive the signal VCM. The drain of transistor NMOS7 is connected to the other end of capacitor C0. The substrate of transistor NMOS7 is used to receive the signal VSS. The gate of transistor NMOS7 is used to receive the input signal NCON2.

[0012] In one embodiment, the preamplifier includes transistor NMOS8, transistor NMOS9, transistor NMOS10, transistor NMOS11, and transistor NMOS12;

[0013] The gate of transistor NMOS8 is used to receive the bias voltage VBIAS. The source of transistor NMOS8 is grounded. The drain of transistor NMOS8 is respectively connected to the source of transistor NMOS9 and the source of transistor NMOS10. The substrate of transistor NMOS9 is connected to the substrate of transistor NMOS10 and is used to receive the signal VSS. The gate of transistor NMOS9 is connected to the first output terminal of the signal sampling circuit. The gate of transistor NMOS10 is connected to the second output terminal of the signal sampling circuit. The drain of transistor NMOS9 is connected to the drain of transistor NMOS11 and is connected to the first input terminal of the dynamic comparator. The drain of transistor NMOS10 is connected to the drain of transistor NMOS12 and is connected to the second input terminal of the dynamic comparator. The sources of transistor NMOS11 and transistor NMOS12 are connected and are used to receive the power supply voltage VDD. The gates of transistor NMOS11 and transistor NMOS12 are connected and are used to receive the power supply voltage VDD.

[0014] In one embodiment, the dynamic comparator in the dynamic latch includes an inverter INV6, an inverter INV7, a NOR gate NOR1, a NOR gate NOR2, a transistor NMOS13, a transistor NMOS14, a transistor NMOS15, a transistor NMOS16, a transistor NMOS17, a transistor PMOS1, a transistor PMOS2, a transistor PMOS3, a transistor PMOS4, a transistor PMOS5, a transistor PMOS6, a transistor PMOS7, a transistor PMOS8, a transistor PMOS9, a transistor PMOS10, a transistor PMOS11, a transistor PMOS12, a transistor PMOS13, and a transistor PMOS14;

[0015] The gate of the transistor NMOS17 is used to access the clock signal CLK, the source of the transistor NMOS17 is grounded, the drain of the transistor NMOS17 is respectively connected to the source of the transistor NMOS13 and the source of the transistor NMOS14, the gate of the transistor NMOS13 is connected to the second output terminal of the preamplifier, the gate of the transistor NMOS14 is connected to the first output terminal of the preamplifier, the substrate electrodes of the transistor NMOS13 and the transistor NMOS14 are both used to access the signal VSS, the drain of the transistor NMOS13 is connected to the drain of the transistor NMOS15, the drain of the transistor NMOS14 is connected to the drain of the transistor NMOS16, and the substrate electrodes of the transistor NMOS15 and the transistor NMOS16 are both used to access the signal VSS;

[0016] The source of the transistor NMOS15, the drain of the transistor PMOS2, the drain of the transistor PMOS1, the gate of the transistor PMOS3, and the gate of the transistor NMOS16 are connected together. The source of the transistor NMOS16, the drain of the transistor PMOS3, the drain of the transistor PMOS4, the gate of the transistor PMOS2, and the gate of the transistor NMOS15 are connected together. The sources of the transistor PMOS1, the transistor PMOS2, the transistor PMOS3, and the transistor PMOS4 are all used to access the power supply voltage VDD. The gates of the transistor PMOS1 and the transistor PMOS4 are both used to access the clock signal CLK. The input terminal of the inverter INV6 is connected to the drain of the transistor PMOS2, the input terminal of the inverter INV7 is connected to the drain of the transistor PMOS3. The output terminal of the inverter INV6 is connected to the first input terminal of the NOR gate NOR1, the output terminal of the inverter INV7 is connected to the second input terminal of the NOR gate NOR2. The output terminal of the NOR gate NOR1 is connected to the first input terminal of the NOR gate NOR2. The output terminal of the NOR gate NOR2 is respectively connected to the second input terminal of the NOR gate NOR1, the input terminal of the latch LAT, and the input terminal of the offset voltage automatic calibration circuit ACC;

[0017] The gates of transistors PMOS5 to PMOS9 are connected together and connected to the drain of transistor NMOS15. The gates of transistors PMOS10 to PMOS14 are connected together and connected to the drain of transistor NMOS16. The substrate electrodes of transistors PMOS5 to PMOS14 are all used to access the power supply voltage VDD. The source and drain of transistor PMOS5 are connected together. The source and drain of transistor PMOS6 are connected together. The source and drain of transistor PMOS7 are connected together. The source and drain of transistor PMOS9 are connected together. The sources of transistors PMOS5 to PMOS9 are respectively connected to the right output terminal of the offset voltage automatic calibration circuit ACC. The source and drain of transistor PMOS10 are connected together. The source and drain of transistor PMOS11 are connected together. The source and drain of transistor PMOS12 are connected together. The source and drain of transistor PMOS13 are connected together. The source and drain of transistor PMOS14 are connected together. The sources of transistors PMOS10 to PMOS14 are respectively connected to the left output terminal of the offset voltage automatic calibration circuit ACC.

[0018] In one embodiment, the offset voltage automatic calibration circuit ACC includes INCNDEC units 0 to 9, D flip - flops 0 to 9, a left output gate circuit, and a right output gate circuit. The INCNDEC units and D flip - flops 9 are in one - to - one correspondence;

[0019] The clock terminals of each D flip - flop are all used to access the offset voltage calibration clock signal. The reset terminals of each D flip - flop are all used to access the offset voltage automatic calibration reset signal. The D terminal of each D flip - flop is connected to the S terminal of the corresponding INCNDEC unit. The Q terminal of each D flip - flop is connected to the B terminal of the corresponding INCNDEC unit. The DEC terminals of INCNDEC units 0 to 4 are all connected to the output terminal of NOR gate NOR2. INCNDEC units 0 to 4 are cascaded in sequence through the CB terminal and Cin terminal. The CB terminal of INCNDEC unit 4 is floating;

[0020] The DEC terminals of INCNDEC units 5 to 9 are all connected to the output terminal of NOR gate NOR2 through inverter INV12. INCNDEC units 5 to 9 are cascaded in sequence through the CB terminal and Cin terminal. The CB terminal of INCNDEC unit 9 is floating;

[0021] The output terminal of the left output gate circuit is connected to the Cin terminal of the INCNDEC unit 0, and the input terminals of the left output gate circuit are respectively connected to the sources of the transistors PMOS10, PMOS11, PMOS12, PMOS13, and PMOS14. The output terminal of the right output gate circuit is connected to the Cin terminal of the INCNDEC unit 5, and the input terminals of the right output gate circuit are respectively connected to the drains of the transistors PMOS5, PMOS6, PMOS7, PMOS8, and PMOS9.

[0022] In one embodiment, the right output gate circuit includes inverters INV8, INV9, NAND gates NAND1, NAND2, NAND3, NAND4, NAND5, NAND6, NOR gates NOR3, NOR4, NOR5, and NOR6, and the left output gate circuit includes inverters INV10, INV11, NAND gates NAND7, NAND8, NAND9, NAND10, NAND11, NAND12, NOR gates NOR7, NOR8, NOR9, and NOR10;

[0023] The input terminals of the NAND gates NAND1, NAND2, NOR gates NOR3, and NOR4 serve as the input terminals of the right output gate circuit. The two input terminals of the NOR gate NOR5 are respectively connected to the output terminals of the NAND gates NAND1 and NAND2. The output terminal of the NOR gate NOR5 is connected to the first input terminal of the NAND gate NAND4. The two input terminals of the NAND gate NAND3 are respectively connected to the output terminals of the NOR gates NOR3 and NOR4. Another input terminal of the NAND gate NAND3 is connected to the Q-bar terminal of the D flip-flop 9. The output terminal of the NAND gate NAND3 is respectively connected to one input terminal of the NOR gate NOR6 and one input terminal of the NAND gate NAND11. The other input terminal of the NOR gate NOR6 is connected to the output terminal of the NOR gate NOR2. The output terminal of the NOR gate NOR6 is connected to the input terminal of the inverter INV8. One input terminal of the NAND gate NAND5 is connected to the output terminal of the NOR gate NOR2. Another input terminal of the NAND gate NAND5 is connected to the output terminal of the NAND gate NAND9. The second input terminal of the NAND gate NAND4 is connected to the Q terminal of the D flip-flop 9. The third input terminal of the NAND gate NAND4 is connected to the output terminal of the NOR gate NOR2. The three input terminals of the NAND gate NAND6 are respectively connected to the output terminals of the NAND gates NAND4, NAND5, and inverter INV8. The output terminal of the NAND gate NAND6 is connected to the Cin terminal of the INCNDEC unit 5 through the inverter INV9;

[0024] The input terminals of NAND gate NAND7, NAND gate NAND8, NOR gate NOR7, and NOR gate NOR8 serve as the input terminals of the left output gate circuit. The two input terminals of NOR gate NOR9 are respectively connected to the output terminals of NAND gate NAND7 and NAND gate NAND8. The output terminal of NOR gate NOR9 is connected to the first input terminal of NAND gate NAND10. The two input terminals of NAND gate NAND9 are respectively connected to the output terminals of NOR gate NOR7 and NOR gate NOR8. Another input terminal of NAND gate NAND9 is connected to the Q-bar terminal of D flip-flop 4. The output terminal of NAND gate NAND9 is respectively connected to one input terminal of NOR gate NOR10. The other input terminal of NOR gate NOR10 is connected to the output terminal of inverter INV12. The output terminal of NOR gate NOR10 is connected to the input terminal of inverter INV10. Another input terminal of NAND gate NAND11 is connected to the output terminal of inverter INV12. The second input terminal of NAND gate NAND10 is connected to the Q terminal of D flip-flop 4. The third input terminal of NAND gate NAND10 is connected to the output terminal of inverter INV12. The three input terminals of NAND gate NAND12 are respectively connected to the output terminals of NAND gate NAND10, NAND gate NAND11, and inverter INV10. The output terminal of NAND gate NAND12 is connected to the Cin terminal of INCNDEC unit 0 through inverter INV11.

[0025] In one of the embodiments, the INCNDEC unit includes exclusive-OR gate XOR0, exclusive-OR gate XOR1, NAND gate NAND13, and inverter INV13. The first input terminal of exclusive-OR gate XOR0 is used as the DEC terminal. The second input terminal of exclusive-OR gate XOR0 and the second input terminal of exclusive-OR gate XOR1 are connected together as the B terminal. The output terminal of exclusive-OR gate XOR0 is connected to the first input terminal of NAND gate NAND13. The second input terminal of NAND gate NAND13 and the first input terminal of exclusive-OR gate XOR1 are connected together as the Cin terminal. The output terminal of NAND gate NAND13 is connected to the input terminal of inverter INV13. The output terminal of inverter INV13 serves as the CB terminal. The output terminal of exclusive-OR gate XOR1 serves as the S terminal.

[0026] One of the technical solutions in the above technical solutions has the following advantages and beneficial effects:

[0027] The above high-precision dynamic comparator with an offset voltage automatic calibration circuit uses a switched-capacitor preamplifier, so that when applied to a comparator in a FLASH (flash memory) ADC, the DC parameters will not be different due to different common-mode voltages, thereby reducing the offset voltage between different comparators; and a substrate voltage biasing technique is adopted, so that the sampling switch has a smaller resistance when conducting and a larger resistance when cutoff. The offset voltage automatic calibration circuit ACC is adopted to enable the circuit to adaptively adjust the offset voltage according to the process errors in the manufacturing process. Compared with traditional comparators, the switched-capacitor comparator design form is adopted, so that the comparator input signal is near the common-mode voltage VCM, ensuring that the offset voltage error caused by different DC parameters due to different common-mode voltages does not occur in each comparator, and the offset voltage automatic calibration circuit ACC is adopted to make the offset voltage of the comparator even smaller. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0029] Figure 1 It is a schematic diagram of the module structure of a high-precision dynamic comparator with an offset voltage automatic calibration circuit in an embodiment;

[0030] Figure 2 It is a schematic diagram of the first part of the circuit structure of a high-precision dynamic comparator with an offset voltage automatic calibration circuit in an embodiment;

[0031] Figure 3 It is a schematic diagram of the second part of the circuit structure of a high-precision dynamic comparator with an offset voltage automatic calibration circuit in an embodiment;

[0032] Figure 4 It is a schematic diagram of the third part of the circuit structure of a high-precision dynamic comparator with an offset voltage automatic calibration circuit in an embodiment;

[0033] Figure 5 It is a schematic diagram of the first part of the structure of the offset voltage automatic calibration circuit ACC in an embodiment;

[0034] Figure 6 It is a schematic diagram of the second part of the structure of the offset voltage automatic calibration circuit ACC in an embodiment;

[0035] Figure 7It is a schematic structural diagram of the INCDEC unit in the automatic offset voltage calibration circuit ACC in an embodiment. Detailed implementation manners

[0036] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0037] It should be noted that referring to "embodiment" herein means that a specific feature, structure or characteristic described in connection with the embodiment may be included in at least one embodiment of the present invention. Displaying this phrase at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments. The term "and / or" used in the description and appended claims of the present invention refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0038] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0039] In one embodiment, as Figure 1As shown, a high-precision dynamic comparator with an offset voltage automatic calibration circuit is provided, including a signal sampling circuit 11, a preamplifier 13, and a dynamic latch 15. The signal sampling circuit 11 is designed based on a bootstrapped gate voltage circuit BTSP and adopts a substrate voltage biasing technique. The dynamic latch 15 includes a latch LAT, an offset voltage automatic calibration circuit ACC, and a dynamic comparator. The sampling input terminal of the signal sampling circuit 11 is used to access the input signal and the reference signal to be sampled. The output terminal of the signal sampling circuit 11 is connected to the input terminal of the preamplifier 13. The output terminal of the preamplifier 13 is connected to the input terminal of the dynamic comparator. The output terminal of the dynamic comparator is respectively connected to the input terminal of the latch LAT and the input terminal of the offset voltage automatic calibration circuit ACC. The output terminal of the offset voltage automatic calibration circuit ACC is connected to the calibration input terminal of the dynamic comparator. The signal sampling circuit 11 is used to sample the input signal and the reference signal. The preamplifier 13 is used to perform pre-amplification on the sampling output of the signal sampling circuit 11. The offset voltage automatic calibration circuit ACC is used to adaptively reduce the offset voltage of the dynamic comparator according to the process error in the manufacturing process. The dynamic comparator is used to perform data comparison. The latch LAT is used to control whether the output signal of the dynamic comparator changes with the change of the input signal.

[0040] It can be understood that in this embodiment, the signal sampling circuit 11 is mainly used to sample and output various input signals (such as the common ground voltage signal VSS, the input signal VSIG, and the common mode voltage signal VCM in the art) and reference signals (such as the reference voltage VREF and the reference signal VREFN in the art). It uses a bootstrapped gate voltage circuit BTSP to perform sampling control and a substrate voltage biasing technique, so that the sampling switch in the signal sampling circuit 11 has a smaller resistance when conducting and a larger resistance when cutoff. For this purpose, those skilled in the art can use MOS transistor devices in combination with inverters and a bootstrapped gate voltage circuit BTSP to design and obtain the required signal sampling circuit 11. Its specific circuit structure form can be various as long as it can be used to provide the required function.

[0041] The preamplifier 13 can adopt the structure design of a switched-capacitor preamplifier 13 to achieve precise amplification of the sampling output. The dynamic latch 15 is designed with a latch LAT, an offset voltage automatic calibration circuit ACC, and a dynamic comparator. The input signal CLK (clock) is used to control the reset and comparison of the dynamic comparator. However, before data comparison, the offset voltage automatic calibration circuit ACC provides the same input voltage for the core transistors in the dynamic comparator, and then adaptively reduces the offset voltage of the dynamic comparator caused by the process error in the manufacturing process according to the comparison result. Finally, the latch LAT controls whether the output signal of the dynamic comparator changes with the change of the input signal.

[0042] The above-mentioned high-precision dynamic comparator with an offset voltage automatic calibration circuit uses a switched-capacitor preamplifier 13, so that when applied to the comparator in a FLASH ADC, the DC parameters will not be different due to different common-mode voltages, thereby reducing the offset voltage between different comparators. In addition, the substrate voltage biasing technique is adopted, so that the sampling switch has a smaller resistance when conducting and a larger resistance when cutoff. The offset voltage automatic calibration circuit ACC is used to enable the circuit to adaptively adjust the offset voltage according to the process errors during the manufacturing process. Compared with traditional comparators, the switched-capacitor comparator design form is adopted, so that the input signal of the comparator is near the common-mode voltage VCM, ensuring that the offset voltage error caused by different DC parameters due to different common-mode voltages in each comparator is avoided. In addition, the offset voltage automatic calibration circuit ACC is adopted to make the offset voltage of the comparator smaller.

[0043] In one embodiment, as Figure 2 shown, the signal sampling circuit 11 includes an inverter INV0, an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, a bootstrapping circuit BTSP, transistors NMOS0, NMOS1, NMOS2, NMOS3, NMOS4, NMOS5, NMOS6, NMOS7, a transistor PMOS0, a capacitor C0, and a capacitor C1. The PHI terminal of the bootstrapping circuit BTSP is used to access the control signal VSAMP through the inverter INV0, the PHIB terminal of the bootstrapping circuit BTSP is used to access the control signal VSAMP, the VIN terminal of the bootstrapping circuit BTSP is used to access the input signal VSIG, and the OUT terminal of the bootstrapping circuit BTSP is respectively connected to the gates of the transistor NMOS0 and the transistor NMOS1.

[0044] The drain of transistor NMOS0 is connected to the drain of transistor NMOS1 and is used to access the input signal VSIG. The substrate of transistor NMOS0 is connected to the source of transistor NMOS1 and the drain of transistor NMOS2 respectively. The source of transistor NMOS0 is connected to one end of capacitor C0. The gate of transistor NMOS2 is used to access the control signal VSAMP. The source of transistor NMOS2 is grounded. The drain of transistor NMOS3 is connected to the drain of transistor PMOS0 and is used to access the reference signal VREF. The source of transistor NMOS3 is connected to the source of transistor PMOS0 and is connected to one end of capacitor C0. The other end of capacitor C0 is connected to the first input terminal of preamplifier 13. Inverters INV1, INV2 and INV3 are connected in series in turn. The input terminal of inverter INV1 is used to access the input signal PHIB. The output terminal of inverter INV3 is connected to the gate of transistor PMOS0. The gate of transistor NMOS3 is connected to the output terminal of inverter INV2.

[0045] Inverters INV4 and INV5 are connected in series. The input terminal of inverter INV4 is used to access the input signal NCON2. The output terminal of inverter INV5 is connected to the gate of transistor NMOS5. The drains of transistors NMOS4 and NMOS5 are both connected to one end of capacitor C1. The drain of transistor NMOS6 is connected to the other end of capacitor C1. The other end of capacitor C1 is connected to the second input terminal of preamplifier 13. The gate of transistor NMOS4 is connected to the output terminal of inverter INV0. The source of transistor NMOS4 is used to access the signal VSS. The source of transistor NMOS5 is used to access the reference signal VREFN. The gate of transistor NMOS6 is used to access the input signal PHIB. The substrate of transistor NMOS6 is used to access the signal VSS. The sources of transistors NMOS6 and NMOS7 are both used to access the signal VCM. The drain of transistor NMOS7 is connected to the other end of capacitor C0. The substrate of transistor NMOS7 is used to access the signal VSS. The gate of transistor NMOS7 is used to access the input signal NCON2.

[0046] It can be understood that in this specification, NMOS refers to an N-type MOS transistor, and PMOS refers to a P-type MOS transistor. The input signal VSAMP controls whether the transistor NMOS0 samples the input signal through the inverter INV0 and the bootstrapping circuit BTSP. The signal VSAMP is the control signal of the bootstrapping circuit BTSP. When the signal VSAMP is at a high level, VSAMB is at a low level, the bootstrapping circuit BTSP enters the reset state, the transistor NMOS0 is cut off, the transistor NMOS1 is cut off, the transistor NMOS2 is turned on, so that the substrate electrode of the transistor NMOS0 is connected to GND (ground), the transistor NMOS4 is cut off, and the sampling of the signal VSS stops. At this time, since the transistor NMOS0 is in the cut-off state, when its substrate is grounded, the equivalent PN junction between the source and drain and the substrate is more reverse-biased, so that its cut-off resistance is larger.

[0047] When the signal VSAMP is at a low level, VSAMPB is at a high level, the bootstrapping circuit BTSP enters the working state, the transistor NMOS0 is turned on, the transistor NMOS1 is turned on, so that the substrate electrode of the transistor NMOS0 is connected to the input signal VSIG, the transistor NMOS2 is cut off, the transistor NMOS4 is turned on. At this time, the transistor NMOS0 samples the input signal VSIG and stores the input signal VSIG in the capacitor C0. The transistor NMOS4 is turned on, and the signal VSS is saved in the capacitor C1. At this time, the source electrode and the substrate electrode of the transistor NMOS0 are short-circuited, which can reduce the threshold voltage change with the input and can reduce its threshold voltage, so that its on-resistance is smaller when it is turned on. In this way, the substrate voltage biasing technology is formed, making the sampling switch have a smaller resistance when turned on and a larger resistance when cut off.

[0048] The input signal PHIB is used to control whether the transistors NMOS3 and PMOS0 sample the reference voltage VREF. Specifically, the input signal PHIB is the control signal for sampling the reference signal VREF. When the input signal PHIB is at a high level, through the action of the inverter INV1, the inverter INV2, and the inverter INV3, the potential at point A is at a high level and the potential at point B is at a low level, so that the transistors NMOS3, NMOS6, and PMOS0 are turned on, and thus the reference signal VREF is stored in the capacitor C0 and the signal VCM is stored in the capacitor C1. When the input signal PHIB is at a low level, through the action of the inverter INV1, the inverter INV2, and the inverter INV3, the potential at point A is at a low level and the potential at point B is at a high level, so that the transistors NMOS3 and PMOS0 are cut off, and at this time, the reference signal VREF and the signal VCM are not sampled.

[0049] The input signal NCON2 controls whether the transistors NMOS5 and NMOS7 sample the common-mode voltage VCM and the reference voltage VREFN through the inverter INV4 and the inverter INV5. Specifically, when the signal NCON2 is at a high level, through the inverter INV4 and the inverter INV5, the signal NCON2LATE becomes high, so that the transistor NMOS7 is turned on, and the common-mode voltage signal VCM and the reference signal VREFN are stored in the capacitor C1; when the signal NCON2 is at a low level, through the inverter INV4 and the inverter INV5, the signal NCON2LATE becomes low, so that the transistor NMOS7 is turned off, and the sampling of the signals VCM and VREFN stops.

[0050] In one embodiment, as Figure 3 shown, the preamplifier 13 includes the transistors NMOS8, NMOS9, NMOS10, NMOS11, and NMOS12. The gate of the transistor NMOS8 is used to access the bias voltage VBIAS, and the source of the transistor NMOS8 is grounded. The drain of the transistor NMOS8 is respectively connected to the sources of the transistors NMOS9 and NMOS10. The substrate of the transistor NMOS9 is connected to the substrate of the transistor NMOS10 and is used to access the signal VSS. The gate of the transistor NMOS9 is connected to the first output terminal of the signal sampling circuit 11. The gate of the transistor NMOS10 is connected to the second output terminal of the signal sampling circuit 11. The drain of the transistor NMOS9 is connected to the drain of the transistor NMOS11 and is connected to the first input terminal of the dynamic comparator. The drain of the transistor NMOS10 is connected to the drain of the transistor NMOS12 and is connected to the second input terminal of the dynamic comparator. The sources of the transistors NMOS11 and NMOS12 are connected together and are used to access the power supply voltage VDD. The gates of the transistors NMOS11 and NMOS12 are connected together and are used to access the power supply voltage VDD.

[0051] It can be understood that the input signal VBIAS gives a bias voltage to the pre-comparator current source. Specifically, the pre-comparator current source is composed of the transistor NMOS8. When the input signal VBIAS is at a high level, the transistor NMOS8 is turned on, and at this time, the preamplifier 13 enters the working state, and the current flows from the transistors NMOS9 and NMOS10 into the transistor NMOS8; when the input signal VBIAS is at a low level, the transistor NMOS8 is turned off, and no current flows into the entire preamplifier 13, so it stops working.

[0052] In one embodiment, as Figure 4As shown, the dynamic comparator in the dynamic latch 15 includes inverter INV6, inverter INV7, NOR gate NOR1, NOR gate NOR2, transistor NMOS13, transistor NMOS14, transistor NMOS15, transistor NMOS16, transistor NMOS17, transistor PMOS1, transistor PMOS2, transistor PMOS3, transistor PMOS4, transistor PMOS5, transistor PMOS6, transistor PMOS7, transistor PMOS8, transistor PMOS9, transistor PMOS10, transistor PMOS11, transistor PMOS12, transistor PMOS13, and transistor PMOS14.

[0053] The gate of transistor NMOS17 is used to access the clock signal CLK. The source of transistor NMOS17 is grounded. The drain of transistor NMOS17 is connected to the sources of transistor NMOS13 and transistor NMOS14 respectively. The gate of transistor NMOS13 is connected to the second output terminal of the preamplifier 13. The gate of transistor NMOS14 is connected to the first output terminal of the preamplifier 13. The substrates of transistor NMOS13 and transistor NMOS14 are both used to access the signal VSS. The drain of transistor NMOS13 is connected to the drain of transistor NMOS15. The drain of transistor NMOS14 is connected to the drain of transistor NMOS16. The substrates of transistor NMOS15 and transistor NMOS16 are both used to access the signal VSS.

[0054] The source of transistor NMOS15, the drain of transistor PMOS2, the drain of transistor PMOS1, the gate of transistor PMOS3, and the gate of transistor NMOS16 are connected together. The source of transistor NMOS16, the drain of transistor PMOS3, the drain of transistor PMOS4, the gate of transistor PMOS2, and the gate of transistor NMOS15 are connected together. The sources of transistor PMOS1, transistor PMOS2, transistor PMOS3, and transistor PMOS4 are all used to access the power supply voltage VDD. The gates of transistor PMOS1 and transistor PMOS4 are both used to access the clock signal CLK. The input terminal of inverter INV6 is connected to the drain of transistor PMOS2. The input terminal of inverter INV7 is connected to the drain of transistor PMOS3. The output terminal of inverter INV6 is connected to the first input terminal of NOR gate NOR1. The output terminal of inverter INV7 is connected to the second input terminal of NOR gate NOR2. The output terminal of NOR gate NOR1 is connected to the first input terminal of NOR gate NOR2. The output terminal of NOR gate NOR2 is connected to the second input terminal of NOR gate NOR1, the input terminal of the latch LAT, and the input terminal of the offset voltage automatic calibration circuit ACC respectively.

[0055] The gates of transistors PMOS5 to PMOS9 are connected together and connected to the drain of transistor NMOS15. The gates of transistors PMOS10 to PMOS14 are connected together and connected to the drain of transistor NMOS16. The substrate electrodes of transistors PMOS5 to PMOS14 are all used to access the power supply voltage VDD. The source and drain of transistor PMOS5 are connected together. The source and drain of transistor PMOS6 are connected together. The source and drain of transistor PMOS7 are connected together. The source and drain of transistor PMOS6 are connected together. The source and drain of transistor PMOS9 are connected together. The sources of transistors PMOS5 to PMOS9 are respectively connected to the right output terminal of the offset voltage automatic calibration circuit ACC. The source and drain of transistor PMOS10 are connected together. The source and drain of transistor PMOS11 are connected together. The source and drain of transistor PMOS12 are connected together. The source and drain of transistor PMOS13 are connected together. The source and drain of transistor PMOS14 are connected together. The sources of transistors PMOS10 to PMOS14 are respectively connected to the left output terminal of the offset voltage automatic calibration circuit ACC.

[0056] It can be understood that the right output terminal of the offset voltage automatic calibration circuit ACC in this embodiment is Figure 4 R<4:0> in Figure 4 and the left output terminal of the offset voltage automatic calibration circuit ACC is L<4:0> in Figures 2 to 4 . The input signal CLK is used to control the reset and comparison of the dynamic comparator. Specifically, when the input signal CLK is at a high level, transistor NMOS17 is turned on, and transistors PMOS1 and PMOS4 are turned off, so that the entire dynamic comparator enters the working state. When the input signal CLK is at a low level, transistor NMOS17 is turned off, and transistors PMOS1 and PMOS4 are turned on, so as to charge the output terminals ON and OP to a high level, thus entering the reset state. Among them, Figures 2 to 4 The circuit terminal labels 01 to 04 in are connected to the circuit terminals with the same labels in each part of the circuit structure diagram. The same applies to Figure 5 and Figure 6 below.

[0057] In one embodiment, as shown in Figure 4 , Figure 5 and Figure 6 , the offset voltage automatic calibration circuit ACC includes INCNDEC units 0 to 9 (i.e., INC0 to INC9), D flip-flops 0 to 9 (i.e., D0 to D9), a left output gate circuit, and a right output gate circuit. The INCNDEC units and D flip-flops 9 correspond one by one. The clock terminals ( CLK ) of each D flip-flop are all used to access the offset voltage calibration clock signal ACC_CLK. The reset terminals ( Rt)(All are used to access the offset voltage automatic calibration reset signal RST. The D terminal of each D flip-flop is connected to the S terminal of the corresponding INCNDEC unit, and the Q terminal of each D flip-flop is connected to the B terminal of the corresponding INCNDEC unit. The DEC terminals of INCNDEC unit 0 to INCNDEC unit 4 are all connected to the output terminal of the NOR gate NOR2. INCNDEC unit 0 to INCNDEC unit 4 are cascaded in sequence through the CB terminal and the Cin terminal, and the CB terminal of INCNDEC unit 4 is floating.)

[0058] )(The DEC terminals of INCNDEC unit 5 to INCNDEC unit 9 are all connected to the output terminal of the NOR gate NOR2 through the inverter INV12. INCNDEC unit 5 to INCNDEC unit 9 are cascaded in sequence through the CB terminal and the Cin terminal, and the CB terminal of INCNDEC unit 9 is floating. The output terminal of the left output gate circuit is connected to the Cin terminal of INCNDEC unit 0, and the input terminals of the left output gate circuit are respectively connected to the source electrodes of the transistor PMOS10, the transistor PMOS11, the transistor PMOS12, the transistor PMOS13 and the transistor PMOS14. The output terminal of the right output gate circuit is connected to the Cin terminal of INCNDEC unit 5, and the input terminals of the right output gate circuit are respectively connected to the drain electrodes of the transistor PMOS5, the transistor PMOS6, the transistor PMOS7, the transistor PMOS8 and the transistor PMOS9.)

[0059] )(It can be understood that the offset voltage calibration clock signal ACC_CLK is used to provide a clock signal for the offset voltage automatic calibration circuit ACC. Among them, the offset voltage calibration clock signal ACC_CLK is also an input signal provided by the outside world and is only used to provide a clock signal for the offset voltage automatic calibration circuit ACC. The offset voltage automatic calibration reset signal RST is the reset signal of the offset voltage automatic calibration circuit ACC. The offset voltage automatic calibration reset signal RST is also an input signal provided by the outside world, and this signal is only used to reset the offset voltage automatic calibration circuit ACC.)

[0060] )(The flash memory lock signal FLASH_LOCK is used to control whether the output signal of the comparator changes. Specifically, the flash memory lock signal FLASH_LOCK is an input signal used to control whether the output of the latch LAT changes with the input. When the FLASH_LOCK signal is a valid signal, as the input signal changes, the output result of the comparator also changes accordingly, and thus the output signal of the latch LAT also changes accordingly. When the FLASH_LOCK signal is an invalid signal, as the input signal changes, the output result of the comparator also changes accordingly, but the output signal of the latch LAT only outputs the signal at the moment when the FLASH_LOCK signal changes from a valid signal to an invalid signal.)

[0061] In one embodiment, as Figure 6 shown, the right output gate circuit includes inverter INV8, inverter INV9, NAND gate NAND1, NAND gate NAND2, NAND gate NAND3, NAND gate NAND4, NAND gate NAND5, NAND gate NAND6, NOR gate NOR3, NOR gate NOR4, NOR gate NOR5, and NOR gate NOR6, and the left output gate circuit includes inverter INV10, inverter INV11, NAND gate NAND7, NAND gate NAND8, NAND gate NAND9, NAND gate NAND10, NAND gate NAND11, NAND gate NAND12, NOR gate NOR7, NOR gate NOR8, NOR gate NOR9, and NOR gate NOR10.

[0062] The input terminals of NAND gate NAND1, NAND gate NAND2, NOR gate NOR3, and NOR gate NOR4 serve as the input terminals of the right output gate circuit. The two input terminals of NOR gate NOR5 are respectively connected to the output terminals of NAND gate NAND1 and NAND gate NAND2. The output terminal of NOR gate NOR5 is connected to the first input terminal of NAND gate NAND4. The two input terminals of NAND gate NAND3 are respectively connected to the output terminals of NOR gate NOR3 and NOR gate NOR4. Another input terminal of NAND gate NAND3 is connected to the Q bar terminal of D flip-flop 9. The output terminal of NAND gate NAND3 is respectively connected to one input terminal of NOR gate NOR6 and one input terminal of NAND gate NAND11. Another input terminal of NOR gate NOR6 is connected to the output terminal of NOR gate NOR2. The output terminal of NOR gate NOR6 is connected to the input terminal of inverter INV8. One input terminal of NAND gate NAND5 is connected to the output terminal of NOR gate NOR2. Another input terminal of NAND gate NAND5 is connected to the output terminal of NAND gate NAND9. The second input terminal of NAND gate NAND4 is connected to the Q terminal of D flip-flop 9. The third input terminal of NAND gate NAND4 is connected to the output terminal of NOR gate NOR2. The three input terminals of NAND gate NAND6 are respectively connected to the output terminals of NAND gate NAND4, NAND gate NAND5, and inverter INV8. The output terminal of NAND gate NAND6 is connected to the Cin terminal of INCNDEC unit 5 through inverter INV9.

[0063] The input terminals of NAND gate NAND7, NAND gate NAND8, NOR gate NOR7 and NOR gate NOR8 serve as the input terminals of the left output gate circuit. The two input terminals of NOR gate NOR9 are respectively connected to the output terminal of NAND gate NAND7 and the output terminal of NAND gate NAND8. The output terminal of NOR gate NOR9 is connected to the first input terminal of NAND gate NAND10. The two input terminals of NAND gate NAND9 are respectively connected to the output terminals of NOR gate NOR7 and NOR gate NOR8. Another input terminal of NAND gate NAND9 is connected to the Q-bar terminal of D flip-flop 4. The output terminal of NAND gate NAND9 is respectively connected to one input terminal of NOR gate NOR10. The other input terminal of NOR gate NOR10 is connected to the output terminal of inverter INV12. The output terminal of NOR gate NOR10 is connected to the input terminal of inverter INV10. Another input terminal of NAND gate NAND11 is connected to the output terminal of inverter INV12. The second input terminal of NAND gate NAND10 is connected to the Q terminal of D flip-flop 4. The third input terminal of NAND gate NAND10 is connected to the output terminal of inverter INV12. The three input terminals of NAND gate NAND12 are respectively connected to the output terminals of NAND gate NAND10, NAND gate NAND11 and inverter INV10. The output terminal of NAND gate NAND12 is connected to the Cin terminal of INCNDEC unit 0 through inverter INV11.

[0064] In one embodiment, as Figure 7 shown, the INCNDEC unit includes exclusive-OR gate XOR0, exclusive-OR gate XOR1, NAND gate NAND13, and inverter INV13. The first input terminal of exclusive-OR gate XOR0 is used as the DEC terminal. The second input terminal of exclusive-OR gate XOR0 and the second input terminal of exclusive-OR gate XOR1 are connected together as the B terminal. The output terminal of exclusive-OR gate XOR0 is connected to the first input terminal of NAND gate NAND13. The second input terminal of NAND gate NAND13 and the first input terminal of exclusive-OR gate XOR1 are connected together as the Cin terminal. The output terminal of NAND gate NAND13 is connected to the input terminal of inverter INV13. The output terminal of inverter INV13 serves as the CB terminal. The output terminal of exclusive-OR gate XOR1 serves as the S terminal.

[0065] Compared with traditional comparators, the entire circuit adopts the design structure of a switched-capacitor comparator, which makes the comparator input signal near the common-mode voltage VCM, ensuring that each comparator does not have an offset voltage error caused by different DC parameters due to different common-mode voltages. Moreover, an automatic offset voltage calibration circuit ACC is adopted to make the offset voltage of the comparator even smaller. During the chip manufacturing process, some devices with the same requirements will not be exactly the same after being actually produced. Therefore, the drain discharge speeds of transistor NMOS15 and transistor NMOS16 are different, introducing an offset voltage. This will lead to misjudgment when the comparator input signals are not very different. The principle of this automatic offset voltage calibration circuit ACC is to first give the same input voltage to transistor NMOS13 and transistor NMOS14 before data comparison, and then, according to the comparison result, adaptively add capacitors to the drains of transistor NMOS15 and transistor NMOS16 through the automatic offset voltage calibration circuit ACC, so that the discharge speeds of the two points tend to be consistent, thereby reducing the offset voltage.

[0066] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0067] The above embodiments only represent several implementation manners of the present invention, and the description is relatively specific and detailed, but it should not be understood as a limitation on the protection scope of the invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several deformations and improvements can still be made, which all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims

1. A high-precision dynamic comparator with an automatic offset voltage calibration circuit, characterized in that: A signal sampling circuit is provided, which is based on a gate voltage bootstrap circuit BTSP and is designed using a substrate voltage biasing technique. The signal sampling circuit is used to sample an input signal to be sampled and a reference signal. The signal sampling circuit includes an inverter INV0, an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, a gate voltage bootstrap circuit BTSP, a transistor NMOS0, a transistor NMOS1, a transistor NMOS2, a transistor NMOS3, a transistor NMOS4, a transistor NMOS5, a transistor NMOS6, a transistor NMOS7, a transistor PMOS0, a capacitor C0, and a capacitor C1. The PHI terminal of the gate voltage bootstrap circuit BTSP is used to access the control signal VSAMP through the inverter INV0, the PHIB terminal of the gate voltage bootstrap circuit BTSP is used to access the control signal VSAMP, the VIN terminal of the gate voltage bootstrap circuit BTSP is used to access the input signal VSIG, and the OUT terminal of the gate voltage bootstrap circuit BTSP is respectively connected to the gate of the transistor NMOS0 and the gate of the transistor NMOS1; The drain of the transistor NMOS0 is connected to the drain of the transistor NMOS1 and is used to access the input signal VSIG, the substrate of the transistor NMOS0 is respectively connected to the source of the transistor NMOS1 and the drain of the transistor NMOS2, the source of the transistor NMOS0 is connected to one end of the capacitor C0, the gate of the transistor NMOS2 is used to access the control signal VSAMP, the source of the transistor NMOS2 is grounded, the drain of the transistor NMOS3 is connected to the drain of the transistor PMOS0 and is used to access the reference signal VREF, the source of the transistor NMOS3 is connected to the source of the transistor PMOS0 and connected to one end of the capacitor C0, the inverter INV1, the inverter INV2 and the inverter INV3 are connected in series in sequence, the input end of the inverter INV1 is used to access the input signal PHIB, the output end of the inverter INV3 is connected to the gate of the transistor PMOS0, and the gate of the transistor NMOS3 is connected to the output end of the inverter INV2; The inverter INV4 and the inverter INV5 are connected in series, the input end of the inverter INV4 is used to access the input signal NCON2, the output end of the inverter INV5 is connected to the gate of the transistor NMOS5, the drain of the transistor NMOS4 and the drain of the transistor NMOS5 are both connected to one end of the capacitor C1, the drain of the transistor NMOS6 is connected to the other end of the capacitor C1, the other end of the capacitor C1 and the other end of the capacitor C0 are used to generate a sampling output, the gate of the transistor NMOS4 is connected to the output end of the inverter INV0, and the transistor N The source of MOS4 is used to access the signal VSS, the source of the transistor NMOS5 is used to access the reference signal VREFN, the gate of the transistor NMOS6 is used to access the input signal PHIB, the substrate of the transistor NMOS6 is used to access the signal VSS, the source of the transistor NMOS6 and the source of the transistor NMOS7 are both used to access the signal VCM, the drain of the transistor NMOS7 is connected to the other end of the capacitor C0, the substrate of the transistor NMOS7 is used to access the signal VSS, and the gate of the transistor NMOS7 is used to access the input signal NCON2.

2. The high-precision dynamic comparator with an automatic offset voltage calibration circuit according to claim 1, characterized in that: It also includes a preamplifier and a dynamic latch, wherein the dynamic latch includes a latch LAT, an offset voltage automatic calibration circuit ACC and a dynamic comparator; The input end of the preamplifier is respectively connected to the other end of the capacitor C1 and the other end of the capacitor C0, the output end of the preamplifier is connected to the input end of the dynamic comparator, the output end of the dynamic comparator is respectively connected to the input end of the latch LAT and the input end of the offset voltage automatic calibration circuit ACC, and the output end of the offset voltage automatic calibration circuit ACC is connected to the calibration input end of the dynamic comparator; The preamplifier is used to preamplify the sampling output of the signal sampling circuit, the offset voltage automatic calibration circuit ACC is used to adaptively reduce the offset voltage of the dynamic comparator according to the process error in the manufacturing process, the dynamic comparator is used to perform data comparison, and the latch LAT is used to control whether the output signal of the dynamic comparator changes with the change of the input signal.

3. The high-precision dynamic comparator with an automatic offset voltage calibration circuit according to claim 2, characterized in that: The preamplifier includes a transistor NMOS8, a transistor NMOS9, a transistor NMOS10, a transistor NMOS11 and a transistor NMOS12; The gate of the transistor NMOS8 is used to access the bias voltage VBIAS, the source of the transistor NMOS8 is grounded, the drain of the transistor NMOS8 is respectively connected to the source of the transistor NMOS9 and the source of the transistor NMOS10, the substrate of the transistor NMOS9 is connected to the substrate of the transistor NMOS10 and is used to access the signal VSS, the gate of the transistor NMOS9 is connected to the other end of the capacitor C0, the gate of the transistor NMOS10 is connected to the other end of the capacitor C1, the drain of the transistor NMOS9 is connected to the drain of the transistor NMOS11 and is connected to the first input end of the dynamic comparator, the drain of the transistor NMOS10 is connected to the drain of the transistor NMOS12 and is connected to the second input end of the dynamic comparator, the source of the transistor NMOS11 is connected to the source of the transistor NMOS12 and is used to access the power supply voltage VDD, and the gate of the transistor NMOS11 is connected to the gate of the transistor NMOS12 and is used to access the power supply voltage VDD.

4. The high-precision dynamic comparator with an offset voltage automatic calibration circuit according to claim 2 or 3, characterized in that: The dynamic comparator includes an inverter INV6, an inverter INV7, a NOR gate NOR1, a NOR gate NOR2, a transistor NMOS13, a transistor NMOS14, a transistor NMOS15, a transistor NMOS16, a transistor NMOS17, a transistor PMOS1, a transistor PMOS2, a transistor PMOS3, a transistor PMOS4, a transistor PMOS5, a transistor PMOS6, a transistor PMOS7, a transistor PMOS8, a transistor PMOS9, a transistor PMOS10, a transistor PMOS11, a transistor PMOS12, a transistor PMOS13 and a transistor PMOS14; The gate of the transistor NMOS17 is used to access the clock signal CLK, the source of the transistor NMOS17 is grounded, the drain of the transistor NMOS17 is respectively connected to the source of the transistor NMOS13 and the source of the transistor NMOS14, the gate of the transistor NMOS13 is connected to the second output terminal of the preamplifier, the gate of the transistor NMOS14 is connected to the first output terminal of the preamplifier, the substrate of the transistor NMOS13 and the substrate of the transistor NMOS14 are both used to access the signal VSS, the drain of the transistor NMOS13 is connected to the drain of the transistor NMOS15, the drain of the transistor NMOS14 is connected to the drain of the transistor NMOS16, and the substrate of the transistor NMOS15 and the substrate of the transistor NMOS16 are both used to access the signal VSS; The source of the transistor NMOS15, the drain of the transistor PMOS2, the drain of the transistor PMOS1, the gate of the transistor PMOS3 and the gate of the transistor NMOS16 are connected, the source of the transistor NMOS16, the drain of the transistor PMOS3, the drain of the transistor PMOS4, the gate of the transistor PMOS2 and the gate of the transistor NMOS15 are connected, the source of the transistor PMOS1, the source of the transistor PMOS2, the source of the transistor PMOS3 and the source of the transistor PMOS4 are all used to access the power supply voltage VDD, the gate of the transistor PMOS1 and the gate of the transistor PMOS4 are connected. The gates of MOS4 are all used to access the clock signal CLK, the input end of the inverter INV6 is connected to the drain of the transistor PMOS2, the input end of the inverter INV7 is connected to the drain of the transistor PMOS3, the output end of the inverter INV6 is connected to the first input end of the NOR gate NOR1, the output end of the inverter INV7 is connected to the second input end of the NOR gate NOR2, the output end of the NOR gate NOR1 is connected to the first input end of the NOR gate NOR2, and the output end of the NOR gate NOR2 is respectively connected to the second input end of the NOR gate NOR1, the input end of the latch LAT and the input end of the offset voltage automatic calibration circuit ACC; The gates of the transistors PMOS5 to PMOS9 are connected to the drain of the transistor NMOS15, the gates of the transistors PMOS10 to PMOS14 are connected to the drain of the transistor NMOS16, the substrates of the transistors PMOS5 to PMOS14 are connected to the power supply voltage VDD, the source and drain of the transistor PMOS5 are connected, the source and drain of the transistor PMOS6 are connected, the source and drain of the transistor PMOS7 are connected, the source and drain of the transistor PMOS9 are connected. The sources of the transistors PMOS5 to PMOS9 are respectively connected to the right output terminal of the automatic offset voltage calibration circuit ACC, the source and drain of the transistor PMOS10 are connected, the source and drain of the transistor PMOS11 are connected, the source and drain of the transistor PMOS12 are connected, the source and drain of the transistor PMOS13 are connected, the source and drain of the transistor PMOS14 are connected, and the sources of the transistors PMOS10 to PMOS14 are respectively connected to the left output terminal of the automatic offset voltage calibration circuit ACC.

5. The high-precision dynamic comparator with an automatic offset voltage calibration circuit according to claim 4, characterized in that: The offset voltage automatic calibration circuit ACC includes INCNDEC units 0 to INCNDEC units 9, D flip-flops 0 to D flip-flops 9, a left output gate circuit and a right output gate circuit, and the INCNDEC units correspond to the D flip-flops 9 one by one; The clock end of each D flip-flop is used to access the offset voltage calibration clock signal, the reset end of each D flip-flop is used to access the offset voltage automatic calibration reset signal, the D end of each D flip-flop is connected to the S end of the corresponding INCNDEC unit, the Q end of each D flip-flop is connected to the B end of the corresponding INCNDEC unit, the DEC end of INCNDEC unit 0 to INCNDEC unit 4 is connected to the output end of the NOR gate NOR2, INCNDEC unit 0 to INCNDEC unit 4 are cascaded with the Cin end through the CB end in turn, and the CB end of INCNDEC unit 4 is left floating; The DEC terminals of INCNDEC units 5 to INCNDEC units 9 are all connected to the output terminal of NOR gate NOR2 through inverter INV12, and INCNDEC units 5 to INCNDEC units 9 are cascaded with Cin terminals through CB terminals in sequence, and the CB terminal of INCNDEC unit 9 is suspended; The output end of the left output gate circuit is connected to the Cin end of the INCNDEC unit 0, and the input end of the left output gate circuit is respectively connected to the source of the transistor PMOS10, the transistor PMOS11, the transistor PMOS12, the transistor PMOS13 and the transistor PMOS14. The output end of the right output gate circuit is connected to the Cin end of the INCNDEC unit 5, and the input end of the right output gate circuit is respectively connected to the drain of the transistor PMOS5, the transistor PMOS6, the transistor PMOS7, the transistor PMOS8 and the transistor PMOS9.

6. The high-precision dynamic comparator with an automatic offset voltage calibration circuit according to claim 5, characterized in that: The right output gate circuit includes an inverter INV8, an inverter INV9, a NAND gate NAND1, a NAND gate NAND2, a NAND gate NAND3, a NAND gate NAND4, a NAND gate NAND5, a NAND gate NAND6, a NOR gate NOR3, a NOR gate NOR4, a NOR gate NOR5 and a NOR gate NOR6; the left output gate circuit includes an inverter INV10, an inverter INV11, a NAND gate NAND7, a NAND gate NAND8, a NAND gate NAND9, a NAND gate NAND10, a NAND gate NAND11, a NAND gate NAND12, a NOR gate NOR7, a NOR gate NOR8, a NOR gate NOR9 and a NOR gate NOR10; The input ends of the NAND gate NAND1, the NAND gate NAND2, the NOR gate NOR3 and the NOR gate NOR4 serve as the input ends of the right output gate circuit, the two input ends of the NOR gate NOR5 are respectively connected to the output end of the NAND gate NAND1 and the output end of the NAND gate NAND2, the output end of the NOR gate NOR5 is connected to the first input end of the NAND gate NAND4, the two input ends of the NAND gate NAND3 are respectively connected to the output ends of the NOR gate NOR3 and the NOR gate NOR4, the other input end of the NAND gate NAND3 is connected to the Q inverting end of the D flip-flop 9, the output end of the NAND gate NAND3 is respectively connected to one input end of the NOR gate NOR6 and one input end of the NAND gate NAND11, the NOR gate NOR6 The other input end of is connected to the output end of the NOR gate NOR2, the output end of the NOR gate NOR6 is connected to the input end of the inverter INV8, one input end of the NAND gate NAND5 is connected to the output end of the NOR gate NOR2, the other input end of the NAND gate NAND5 is connected to the output end of the NAND gate NAND9, the second input end of the NAND gate NAND4 is connected to the Q end of the D flip-flop 9, the third input end of the NAND gate NAND4 is connected to the output end of the NOR gate NOR2, the three input ends of the NAND gate NAND6 are respectively connected to the output ends of the NAND gate NAND4, the NAND gate NAND5 and the inverter INV8, and the output end of the NAND gate NAND6 is connected to the Cin end of the INCNDEC unit 5 through the inverter INV9; The input ends of the NAND gate NAND7, the NAND gate NAND8, the NOR gate NOR7 and the NOR gate NOR8 serve as the input ends of the left output gate circuit, the two input ends of the NOR gate NOR9 are respectively connected to the output end of the NAND gate NAND7 and the output end of the NAND gate NAND8, the output end of the NOR gate NOR9 is connected to the first input end of the NAND gate NAND10, the two input ends of the NAND gate NAND9 are respectively connected to the output ends of the NOR gate NOR7 and the NOR gate NOR8, the other input end of the NAND gate NAND9 is connected to the Q inverting end of the D flip-flop 4, the output ends of the NAND gate NAND9 are respectively connected to one input end of the NOR gate NOR10, the Another input end is connected to the output end of the inverter INV12, the output end of the NOR gate NOR10 is connected to the input end of the inverter INV10, another input end of the NAND gate NAND11 is connected to the output end of the inverter INV12, the second input end of the NAND gate NAND10 is connected to the Q end of the D flip-flop 4, the third input end of the NAND gate NAND10 is connected to the output end of the inverter INV12, the three input ends of the NAND gate NAND12 are respectively connected to the output ends of the NAND gate NAND10, the NAND gate NAND11 and the inverter INV10, and the output end of the NAND gate NAND12 is connected to the Cin end of the INCNDEC unit 0 through the inverter INV11.

7. The high-precision dynamic comparator with an automatic offset voltage calibration circuit according to claim 5, characterized in that: The INCNDEC unit includes an XOR gate XOR0, an XOR gate XOR1, a NAND gate NAND13, and an inverter INV13. The first input end of the XOR gate XOR0 is used as a DEC end, the second input end of the XOR gate XOR0 is connected to the second input end of the XOR gate XOR1 as a B end, the output end of the XOR gate XOR0 is connected to the first input end of the NAND gate NAND13, the second input end of the NAND gate NAND13 is connected to the first input end of the XOR gate XOR1 as a Cin end, the output end of the NAND gate NAND13 is connected to the input end of the inverter INV13, the output end of the inverter INV13 is used as a CB end, and the output end of the XOR gate XOR1 is used as an S end.

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