PLL (Phase Locked Loop) adaptive trimming circuit

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a PLL (Phase Locked Loop) adaptive trimming circuit. Comprising a sampling analog-to-digital conversion module, the sampling analog-to-digital conversion module comprises three sampling analog-to-digital conversion units, the in-phase input ends of the three sampling analog-to-digital conversion units are connected with voltage division nodes N1-N3 on a voltage division network respectively, the inverted input ends of the three sampling analog-to-digital conversion units are connected with control voltage VCTRL, and the output ends of the three sampling analog-to-digital conversion units output a control signal B, a control signal E and a control signal A respectively; wherein each sampling analog-to-digital conversion unit is composed of a hysteresis comparator COMP1, a comparator COMP2 and a phase inverter INV1 which are sequentially connected in series; the digital trimming state machine is composed of a first gate circuit, an N-stage locking loop and a second gate circuit which are sequentially connected in series; the problem that the working characteristic of the PLL is obviously reduced after the PLL is influenced by the PVT is solved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a PLL adaptive trimming circuit. Background Art

[0002] In the design of PLL (Phase Lock Loop), there are two commonly used ones. One is the LC phase-locked loop. Because of the presence of inductor L in this phase-locked loop, it is more commonly used for PLL systems with higher precision. However, the inductor L occupies a large area and involves noise problems in this area, which requires special treatment. The other is a loop design using an analog voltage-controlled unit. The relative accuracy of this circuit structure is lower than that of the LC delay unit, but its design requirements for the layout are relatively low, and the area used is relatively small. For some non-RF systems, this structure is more popular, but this structure is more obviously affected by PVT. From pre-imitation to post-imitation and even to the finished product stage, its locking frequency range is affected by PVT and may be reduced to 50% of the original design. The general design method is to add a large number of trimming designs to the periphery for trimming, thereby reducing the impact of process and voltage on PLL, but this will increase the workload and increase the difficulty of circuit trimming to a certain extent. Summary of the invention

[0003] The object of the present invention is to provide a PLL adaptive adjustment circuit to solve the problem that the working characteristics of the voltage-controlled phase-locked loop (PLL) are significantly reduced after being affected by PVT.

[0004] In order to solve the above technical problems, the present invention provides a PLL adaptive trimming circuit, comprising: The sampling analog-to-digital conversion module comprises three sampling analog-to-digital conversion units, wherein the in-phase input terminals of the three sampling analog-to-digital conversion units are respectively connected to the voltage-dividing nodes N1-N3 on the voltage-dividing network, the inverting input terminals are all connected to the control voltage VCTRL, and the output terminals respectively output a control signal B, a control signal E and a control signal A; wherein each sampling analog-to-digital conversion unit is composed of a hysteresis comparator COMP1, a comparator COMP2 and an inverter INV1 connected in series in sequence; A digital trimming state machine, comprising a first gate circuit, an N-stage locked loop, and a second gate circuit connected in series in sequence; wherein the input end of the first gate circuit is used to input a control signal A and a control signal B, and the output end outputs a control signal CON; the input end of the N-stage locked loop is used to input a control signal CON, an enable signal EN, a control signal A_Z, and a control signal E_Z, and the output end is used to output a digital signal Auto_Trim[N+1:0]; the input end of the second gate circuit is used to input a power supply voltage VS, an enable signal EN, and an output signal of the N-stage locked loop, and the output end is used to output a digital signal Auto_Trim[N]; The reference signal generating module is composed of a resistor array RES_ARRAY, a plurality of resistors R1 and a transistor Q; the control end of the resistor array RES_ARRAY is used to input a digital signal Auto_Trim[N:0], the power supply end is connected to the power supply voltage VS, the ground end is respectively connected to the reference voltage VREF and the ground voltage VG through a plurality of resistors R1 connected in series, the reference voltage VREF is connected to the gate end of the transistor Q, and the substrate end, source end and drain end of the transistor Q are all connected to the ground voltage VG.

[0005] Preferably, the voltage divider network is composed of a plurality of resistors R2 connected in series, wherein the resistor R2 at the head end is connected to the power supply voltage VS, and the resistor R2 at the tail end is connected to the ground voltage VG, and voltage divider nodes N1 to N3 are generated in sequence between every two adjacent resistors R2 from bottom to top.

[0006] Preferably, the three sampling analog-to-digital conversion units specifically include: a first sampling analog-to-digital conversion unit, a second sampling analog-to-digital conversion unit and a third sampling analog-to-digital conversion unit; Wherein, in the first sampling analog-to-digital conversion unit, the non-inverting input terminal and the inverting input terminal of the hysteresis comparator COMP1 are respectively connected to the voltage dividing node N1 and the control voltage VCTRL, the non-inverting output terminal and the inverting output terminal of the hysteresis comparator COMP1 respectively output control signals A1 and A2 to the inverting input terminal and the non-inverting input terminal of the comparator COMP2, the output terminal of the comparator COMP2 outputs the control signal B_Z to the input terminal of the inverter INV1, and the output terminal of the inverter INV1 outputs the control signal B; Wherein, in the second sampling analog-to-digital conversion unit, the non-inverting input terminal and the inverting input terminal of the hysteresis comparator COMP1 are respectively connected to the voltage dividing node N2 and the control voltage VCTRL, the non-inverting output terminal and the inverting output terminal of the hysteresis comparator COMP1 are respectively connected to the non-inverting input terminal and the inverting input terminal of the comparator COMP2, the output terminal of the comparator COMP2 outputs the control signal E_Z to the input terminal of the inverter INV1, and the output terminal of the inverter INV1 outputs the control signal E; In the third sampling analog-to-digital conversion unit, the non-inverting input terminal and the inverting input terminal of the hysteresis comparator COMP1 are respectively connected to the voltage dividing node N3 and the control voltage VCTRL, the non-inverting output terminal and the inverting output terminal of the hysteresis comparator COMP1 are respectively connected to the non-inverting input terminal and the inverting input terminal of the comparator COMP2, the output terminal of the comparator COMP2 outputs the control signal A_Z to the input terminal of the inverter INV1, and the output terminal of the inverter INV1 outputs the control signal A.

[0007] Preferably, the first gate circuit is composed of NOR gates NOR1~NOR2, NAND gates NAND1~NAND2 and inverter INV2; the control signal A and the control signal B are respectively connected to the two input ends of the NOR gate NOR1, the output end of the NOR gate NOR1 is connected to the input end of the inverter INV2, the output end of the inverter INV2 and the output end of the NAND gate NAND1 are respectively connected to the two input ends of the NAND gate NAND2, the control signal A and the control signal B are respectively connected to the two input ends of the NAND gate NAND1, the output end of the NAND gate NAND2 and the control signal A are respectively connected to the two input ends of the NOR gate NOR2, and the output end of the NOR gate NOR2 outputs the control signal CON.

[0008] Preferably, the N-level locked loop includes a first-level locked loop, a second-level locked loop and a third-level locked loop; wherein each level of the locked loop is composed of a NAND gate NAND3, an inverter INV3, a trigger DFF and an inverter INV4; the output end of the NAND gate NAND3 is connected to the input end of the inverter INV3, the output end of the inverter INV3 is connected to the clock end of the trigger DFF, the power supply end of the trigger DFF is connected to the power supply voltage VS, the output end of the trigger DFF outputs a feedback signal by connecting to the inverter INV4, and is connected to the input end of the NAND gate NAND3.

[0009] Preferably, in the first-stage locking loop, the input end of the NAND gate NAND3 also includes the input control signal CON and the enable signal EN, the output end of the inverter INV3 outputs the digital signal Auto_Trim[0], and the output end of the trigger DFF is connected to the input end of the NAND gate NAND3 in the second-stage locking loop.

[0010] Preferably, in the second-stage locking loop, the input end of the NAND gate NAND3 also includes the input control signal E_Z and the enable signal EN, the output end of the inverter INV3 outputs the digital signal Auto_Trim[1], and the output end of the trigger DFF is connected to the input end of the NAND gate NAND3 in the third-stage locking loop.

[0011] Preferably, in the third-level locked loop, the input end of the NAND gate NAND3 also includes the input control signal A_Z and the enable signal EN, the output end of the inverter INV3 outputs the digital signal Auto_Trim[2], and the output end of the trigger DFF is connected to the input end of the NAND gate NAND4 in the second gate circuit.

[0012] Preferably, the second gate circuit is composed of a NAND gate NAND4 and an inverter INV5 connected in series in sequence; the input end of the NAND gate NAND4 also includes an input enable signal EN and a power supply voltage VS, and the output end of the inverter INV5 outputs a digital signal Auto_Trim[3].

[0013] Preferably, the resistor array RES_ARRAY is composed of a plurality of resistors R3 connected in series and a plurality of transmission gate switches T connected in parallel; the power supply end of each transmission gate switch T is connected to an arbitrary number of resistors R3, the ground end is connected to a reference voltage VREF, and the control end is connected to a digital signal Auto_Trim[3:0].

[0014] Compared with the prior art, the present invention has the following beneficial effects: The PLL adaptive adjustment circuit structure of the present invention can reduce the reduction of PLL operating frequency and abnormal working conditions caused by different system voltages, different process angles and temperature deviations, and can reduce the difficulty of manual adjustment. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is the basic structure circuit diagram of the PLL of the present invention.

[0016] Figure 2 It is the structural circuit diagram of the VCO of the present invention.

[0017] Figure 3 It is a circuit diagram of the basic ring oscillator unit structure of the present invention.

[0018] Figure 4 It is a circuit diagram of the sampling analog-to-digital conversion module of the present invention.

[0019] Figure 5 The present invention Figure 4 An enlarged view of the local structure; (a) and (b) are the connection port circuit diagrams of the hysteresis comparator COMP1 and the comparator COMP2 respectively.

[0020] Figure 6 It is a circuit diagram of a digital trimming state machine of the present invention.

[0021] Figure 7 The present invention Figure 6 Circuit diagram of the output control signal CON.

[0022] Figure 8 It is a circuit diagram of a reference signal generating module of the present invention.

[0023] Fig. 9 It is the resistor array circuit diagram of the present invention.

[0024] Fig.10 It is the high and low frequency locking curve diagram of the present invention. DETAILED DESCRIPTION

[0025] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0026] like Figure 1 The figure shows the basic PLL structure, which controls the oscillation frequency of the VCO through VCTRL. The bias current Ibias is generated by VCTRL to achieve VCO frequency control, where PD is used to distinguish the phase frequency difference between the external reference clock and the clock generated inside the VCO, thereby generating charging control for the charge pump, integrating through the capacitor of the LPF to generate the VCTRL voltage, and controlling the VCO to change the frequency / phase, thereby achieving matching with the reference frequency (the frequency and phase are the same as the reference clock). Therefore, this VCTRL is the main reference signal for the PLL circuit.

[0027] like Figure 2 As shown in Figure 1, the VCO consists of multiple amplifiers connected in series and a D2S differential to single-ended converter. Figure 3 As shown in the figure, this circuit is a delay unit of a basic ring oscillator. In order to achieve different oscillation frequencies, this structure uses the size of the Ibias current to change the oscillation frequency. The most fundamental principle is RC delay, where the capacitor C is shown in the circuit, and the resistor R is a variable resistor controlled by the Ibias current. This is achieved by adjusting the conduction state of the transistor through the Ibias current. Because there is a clamp amplifier (i.e. Figure 2The amplifier structure in the circuit), so the Vcalmp potential is the same as the VREF potential, so the corresponding PM1 resistance is (VS-Vclamp) / Ibias. When the current changes, the PM1 resistance changes accordingly. Therefore, the gate potential of PM1 can control the resistance of PM2 and PM3, thereby achieving the delay effect. The oscillation frequency of the delay unit loop is f=1 / (2NTd), and the resistance R is significantly affected by the power supply voltage VS. For example, the nominal value of VS is 1.1, and the deviation may be 1 or 1.2, which will cause the frequency to change. Similarly, temperature and process will also cause Td to change. This situation is objective and cannot be avoided. Generally, when the chip is manufactured, factors such as process deviation are basically fixed. In order to achieve the optimal working condition of the chip / module, the circuit will be manually tested for performance and optimized. However, PLL generally works in different frequency ranges, especially in the case of a larger frequency range. Because of different frequency conditions, the optimal adjustment is feasible at one frequency, but may not be ideal in another case, so it will increase the difficulty of manual adjustment.

[0028] From the above analysis, we can also know that Figure 1 If VREF in the circuit shown is reduced, the equivalent resistance of PM2 and PM3 will be larger, Td will be larger, and the frequency will be smaller; similarly, if VREF is increased, the equivalent resistance of PM2 and PM3 will be smaller, Td will be smaller, and the frequency will be larger. The essence of VREF change is to change the lockable range. For example, in the design of SS process corner, 600M may not be locked under the TT 600M lock (due to the process deviation causing the RC value to be too large, so that the lock frequency cannot be reached). In this case, the bias current Ibias can be manually controlled for optimization to achieve lock, but manual correction is required. With this design, a reference voltage can be set at a higher VREF value. When VCTRL is greater than the reference voltage VNX, the circuit will expand the high-frequency range, so that the SS process angle locking can be achieved without adjusting the current. Similarly, in the case of the SS process angle, artificial correction of the lock will increase the current value. Although this can achieve 600M locking, if the SS is to be locked at a low frequency of 150M, for example, it cannot be locked at a low frequency of 150M because the current value is increased and solidified. Therefore, the locking range of the circuit is limited (even if it can be adjusted).

[0029] Therefore, if the VCTRL signal and VREF signal in the circuit can produce a certain functional relationship, the frequency of the circuit can be changed accordingly with the change of the input reference frequency, and at the same time, related stability or other parts of the adjustment can be performed.

[0030] Therefore, the present invention adopts Figure 4The circuit structure shown is used to distinguish the voltage VCTRL generated by the current generated by the charge pump in the LPF (low-pass filter circuit) and compare it with the distribution of the resistor voltage generated by the power supply voltage VS in the branch. It can be designed artificially to confirm the voltages of nodes N1, N2, and N3. When VCTRL changes to be greater than VN1, VN2, and VN3, the corresponding control signals A, E, and B are generated to become high levels. Since there is ripple in VCTRL, its ripple may be higher than VN1~NV3 (comparison value), but its RMS value is not higher than VNX (RMS is the abbreviation of root mean square, that is, root mean square, which means that VCTRL can be considered as an upward sawtooth wave. When this waveform is compared with a stable VNX, if there is no hysteresis comparator, once the sawtooth wave is greater than VNX, it will output a high level, but the actual waveform may not want it to be so sensitive, thereby causing VREF to change), so a hysteresis comparator COMP1 is added to realize delayed comparison and avoid misjudgment.

[0031] When the control signals A, E, B and E_Z change due to VCTRL, these signals are added to the state machine for analysis and the Auto_Trim[3:0] signal is generated accordingly, which can control Figure 8 The VREF value generated in the reference signal generation module in the control circuit can automatically control the corresponding frequency range change.

[0032] Please refer to the following for details: Figures 4 to 9 As shown, the embodiment of the present invention specifically provides a PLL adaptive trimming circuit, including: The sampling analog-to-digital conversion module comprises three sampling analog-to-digital conversion units, wherein the in-phase input terminals of the three sampling analog-to-digital conversion units are respectively connected to the voltage-dividing nodes N1-N3 on the voltage-dividing network, the inverting input terminals are all connected to the control voltage VCTRL, and the output terminals respectively output a control signal B, a control signal E and a control signal A; wherein each sampling analog-to-digital conversion unit is composed of a hysteresis comparator COMP1, a comparator COMP2 and an inverter INV1 connected in series in sequence; A digital trimming state machine, comprising a first gate circuit, an N-stage locked loop, and a second gate circuit connected in series in sequence; wherein the input end of the first gate circuit is used to input a control signal A and a control signal B, and the output end outputs a control signal CON; the input end of the N-stage locked loop is used to input a control signal CON, an enable signal EN, a control signal A_Z, and a control signal E_Z, and the output end is used to output a digital signal Auto_Trim[N+1:0]; the input end of the second gate circuit is used to input a power supply voltage VS, an enable signal EN, and an output signal of the N-stage locked loop, and the output end is used to output a digital signal Auto_Trim[N]; The reference signal generating module is composed of a resistor array RES_ARRAY, a plurality of resistors R1 and a transistor Q; the control end of the resistor array RES_ARRAY is used to input a digital signal Auto_Trim[N:0], the power supply end is connected to the power supply voltage VS, the ground end is respectively connected to the reference voltage VREF and the ground voltage VG through a plurality of resistors R1 connected in series, the reference voltage VREF is connected to the gate end of the transistor Q, and the substrate end, source end and drain end of the transistor Q are all connected to the ground voltage VG.

[0033] The voltage divider network is composed of a plurality of resistors R2 connected in series, wherein the resistor R2 at the head end is connected to the power supply voltage VS, and the resistor R2 at the tail end is connected to the ground voltage VG, and voltage divider nodes N1 to N3 are generated in sequence between every two adjacent resistors R2 from bottom to top.

[0034] The three sampling analog-to-digital conversion units specifically include: a first sampling analog-to-digital conversion unit, a second sampling analog-to-digital conversion unit and a third sampling analog-to-digital conversion unit; Wherein, in the first sampling analog-to-digital conversion unit, the non-inverting input terminal and the inverting input terminal of the hysteresis comparator COMP1 are respectively connected to the voltage dividing node N1 and the control voltage VCTRL, the non-inverting output terminal and the inverting output terminal of the hysteresis comparator COMP1 respectively output control signals A1 and A2 to the inverting input terminal and the non-inverting input terminal of the comparator COMP2, the output terminal of the comparator COMP2 outputs the control signal B_Z to the input terminal of the inverter INV1, and the output terminal of the inverter INV1 outputs the control signal B; Wherein, in the second sampling analog-to-digital conversion unit, the non-inverting input terminal and the inverting input terminal of the hysteresis comparator COMP1 are respectively connected to the voltage dividing node N2 and the control voltage VCTRL, the non-inverting output terminal and the inverting output terminal of the hysteresis comparator COMP1 are respectively connected to the non-inverting input terminal and the inverting input terminal of the comparator COMP2, the output terminal of the comparator COMP2 outputs the control signal E_Z to the input terminal of the inverter INV1, and the output terminal of the inverter INV1 outputs the control signal E; In the third sampling analog-to-digital conversion unit, the non-inverting input terminal and the inverting input terminal of the hysteresis comparator COMP1 are respectively connected to the voltage dividing node N3 and the control voltage VCTRL, the non-inverting output terminal and the inverting output terminal of the hysteresis comparator COMP1 are respectively connected to the non-inverting input terminal and the inverting input terminal of the comparator COMP2, the output terminal of the comparator COMP2 outputs the control signal A_Z to the input terminal of the inverter INV1, and the output terminal of the inverter INV1 outputs the control signal A.

[0035] like Figure 4As shown, when VCTRL>VN1, B outputs a low level; on the contrary, when VCTRL<VN1, B outputs a high level. The function of the hysteresis comparator COMP1 is that when VN1>VCTRL about 50mV, B will jump from H to L. In other words, for A or E, it is just the opposite, that is, when VCTRL changes to be greater than VN2, E jumps from L to H (because the connection method of A1 and A2 is opposite to that of A and E branches).

[0036] The first gate circuit is composed of NOR gates NOR1~NOR2, NAND gates NAND1~NAND2 and inverter INV2; the control signal A and the control signal B are respectively connected to the two input ends of the NOR gate NOR1, the output end of the NOR gate NOR1 is connected to the input end of the inverter INV2, the output end of the inverter INV2 and the output end of the NAND gate NAND1 are respectively connected to the two input ends of the NAND gate NAND2, the control signal A and the control signal B are respectively connected to the two input ends of the NAND gate NAND1, the output end of the NAND gate NAND2 and the control signal A are respectively connected to the two input ends of the NOR gate NOR2, and the output end of the NOR gate NOR2 outputs the control signal CON.

[0037] The N-level locked loop includes a first-level locked loop, a second-level locked loop and a third-level locked loop; each level of the locked loop is composed of a NAND gate NAND3, an inverter INV3, a trigger DFF and an inverter INV4; the output end of the NAND gate NAND3 is connected to the input end of the inverter INV3, the output end of the inverter INV3 is connected to the clock end of the trigger DFF, the power supply end of the trigger DFF is connected to the power supply voltage VS, the output end of the trigger DFF outputs a feedback signal by connecting to the inverter INV4, and is connected to the input end of the NAND gate NAND3.

[0038] In the first-stage locked loop, the input end of the NAND gate NAND3 also includes the input control signal CON and the enable signal EN, the output end of the inverter INV3 outputs the digital signal Auto_Trim[0], and the output end of the trigger DFF is connected to the input end of the NAND gate NAND3 in the second-stage locked loop.

[0039] In the second-stage locked loop, the input end of the NAND gate NAND3 also includes the input control signal E_Z and the enable signal EN, the output end of the inverter INV3 outputs the digital signal Auto_Trim[1], and the output end of the trigger DFF is connected to the input end of the NAND gate NAND3 in the third-stage locked loop.

[0040] In the third-level locked loop, the input end of the NAND gate NAND3 also includes the input control signal A_Z and the enable signal EN, the output end of the inverter INV3 outputs the digital signal Auto_Trim[2], and the output end of the trigger DFF is connected to the input end of the NAND gate NAND4 in the second gate circuit.

[0041] The second gate circuit is composed of a NAND gate NAND4 and an inverter INV5 connected in series in sequence; the input end of the NAND gate NAND4 also includes an input enable signal EN and a power supply voltage VS, and the output end of the inverter INV5 outputs a digital signal Auto_Trim[3].

[0042] like Figure 6 and Figure 7 As shown, taking the input point of NAND3 as Y, if A is H, Y=L; if A is L and B is H, Y=H; if A is L and B is L, Y=L.

[0043] like Fig. 9 As shown, the resistor array RES_ARRAY is composed of a number of resistors R3 connected in series and a number of transmission gate switches T connected in parallel; the power supply end of each transmission gate switch T is connected to an arbitrary number of resistors R3, the ground end is connected to a reference voltage VREF, and the control end is connected to a digital signal Auto_Trim[3:0].

[0044] Specific implementation example: First, Figure 6 The RST bit in the trigger is set to a high level, which resets the trigger. The default output of the trigger is a low level. When VCTRL is at a low level, Figure 4If VN1 = (VS - VG) × 0.25, VN2 = (VS - VG) × 0.5, and VN3 = (VS - VG) × 0.75, then when VCTRL is low, i.e., VCTRL < VN1, for the input of NAND3 in branch B, since B = H and A = L, the output of NOR2 (the input of NAND3) is H (Y = H). At this time, Auto_Trim[0] will output a high level, thus controlling the reference signal generation module to output VREF0 = (VS - VG) × 4R1 / (6 × R3 + 4 × R1). Then, as the PLL operates, VCTRL will continuously increase until the circuit stabilizes. It is possible that VCTRL at the locked frequency will not be higher than VN1, in which case only Auto_Trim[0] in the circuit outputs a high level, and the other Auto_Trim[3:1] will continue to maintain the low level after being set by RST. It is also possible that due to the action of the charge pump and integration on the capacitor of the LPF, the voltage of VCTRL increases, which may then lead to VN2 > VCTRL > VN1. In this case, first, B will change from high level H to low level L, causing the D flip - flop to be valid at the falling edge, outputting the VS level from the D terminal to the Q terminal, so that the output of the first - stage DFF is H, and Auto_Trim[0] becomes low and remains so, thus locking the first stage (the loop composed of NAND3, INV3, DFF, and INV4), keeping Auto_Trim[0] low all the time. Looking at the second stage, since the first - stage outputs H to NAND3 and the EN enable is set to H (set to H from the beginning of this module), and the output level of the feedback loop INV4 in the second stage is high, the decision is then left to E_Z. When VCTRL < VN2, E_Z is high (E is low), so at this time Auto_Trim[1] is high, and thus VREF changes to VREF1 = (VS - VG) × 4R1 / (5 × R3 + 4 × R1), that is, VREF1 > VREF0. Since increasing VREF will increase the oscillation frequency range of the VCO, such a change can increase the locked frequency range.

[0045] Furthermore, the embodiments of the present invention are elaborated in detail as follows in the implementation process: 1) Taking FF_-55 at a low frequency of 100M as an example Compared with the TT_25 process corner, FF_-55 has a larger current, a smaller threshold, and a relatively smaller resistance value. This will cause the frequency of the VCO to be higher than that of TT_25 under the same configuration. Relatively speaking, there may be problems with locking at low frequencies for FF_-55. If a lower VREF can be provided to the Figure 3 ring - type oscillator circuit in, then the overall frequency of the ring oscillator will decrease (without changing the tail current). For example, Figure 4The resistor is designed, and the VS voltage is 1.1V. Then VN1, VN2, and VN3 are set to 400m, 600m, and 850m. When FF_-55 is locked at 100M, VCTRL will increase first. However, since the frequency corresponding to FF_-55 is higher, VCTRL increases, but it does not reach 400m. When VIN is L and VIP is H, the hysteresis comparator COMP1 has VON and VOP. For the comparator COMP2, when VIN is L, the output is L, and when VIN is H, the output is H. Therefore, the sampling ADC output is B_Z=L, B=H, A_Z=H, A=L, E_Z=H, and E=L; first, the RST reset signal of the state machine is used to reset the circuit. By default, Auto_Trim[3:0] is all low, thereby resetting VREF to low level 0. When the PLL starts working, the VCTRL voltage increases. Looking at the trim bit state machine, A=H and B=L at this time, the corresponding state machine Auto_Trim[0] is high, while Auto_Trim[3:1] are all low. Therefore, the reference voltage VREF generated by the reference signal generation module is determined by VS-VS / (Rvar+Rcom)×Rvar=VS×Rcom / (Rvar+Rcom) (Rvar represents the resistor R3 in the trim array. As the transmission gate connects and disconnects the circuit, a variable resistor structure is realized; Rcom represents Figure 8 The four resistors R1 in the figure). The corresponding Rvar resistor is larger and the corresponding VREF is smaller.

[0046] 2) Take SS_125 high frequency 600M as an example Compared with TT_25 process corner, SS_125 has smaller current, larger threshold and larger resistance. This will cause the VCO frequency to be higher than TT_25 under the same configuration. Relatively speaking, SS_125 may have problems locking at high frequencies. If a higher VREF can be provided at high frequencies, Figure 3In the ring oscillator circuit, the overall frequency of the ring oscillation will increase (without changing the tail current). Assume that VCTRL gradually increases, and when it is higher than the potential of N3, B=L, B_Z=H, E_Z=L, E=H, A=H, A_Z=L. However, before VCTRL is higher than N3, VCTRL is higher than N2 and lower than N3 voltage. In this case, B=L, B_Z=H, E_Z=L, E=H, A_Z=H, A=L. In this case, TT2 is high. When it is greater than N3, A_Z=H→L occurs. At this time, TT2 changes from high level to low level. The following DFF captures the falling edge, thereby changing the DFF output to high level, so that the Auto_Trim[3] output is high level, thereby controlling the trimming resistor RES of the reference output circuit to change to Rvar. The corresponding voltage is smaller, and the related VREF is still VS×Rcom / (Rvar+Rcom), but the Rvar resistance decreases, so that VREF becomes larger, thereby increasing the circuit frequency. The DFF feedback loop is designed as a one-time locking design, which can ensure that it is always locked after power-on.

[0047] Table 1, Table 2 and Table 3 below are tables of hysteresis amplifier logic (analog), comparator logic (analog) and sampling analog-to-digital conversion module ADC output logic, respectively.

[0048] Table 1 VIN H L VIP L H VON L H VOP H L Table 2 VIN H L VIP L H VON H L Table 3 Road B A1 (Analog) A2 (Analog) B (number) B_Z (number) VCTRL>VREF L H L H VCTRL<VREF H L H L E, A road / / A / E (digital) A / E (digital) VCTRL>VREF L H H L VCTRL<VREF H L L H like Fig.10 As shown, VR1~VR4 represent VREF0~VREF3. A brief explanation is as follows: look at the green curve (both together), that is, when Auto_Trim[0] is turned on, VREF1 outputs, and the corresponding lock curve is green; look at the red curve, when VCTRL is greater than VN1 (about tens of millivolts), Auto_Trim[0] is turned off and Auto_Trim[1] is turned on. Similarly, when VCTRL is greater than VN2, Auto_Trim[1] is turned off and Auto_Trim[2] is turned on. When VCTRL is greater than NV3, Auto_Trim[2] is turned off and Auto_Trim[3] is turned on, and so on (it can be divided into several levels for resistor voltage division and Auto_Trim control).

[0049] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A PLL adaptive trimming circuit, characterized in that: include: The sampling analog-to-digital conversion module comprises three sampling analog-to-digital conversion units, wherein the in-phase input terminals of the three sampling analog-to-digital conversion units are respectively connected to the voltage-dividing nodes N1-N3 on the voltage-dividing network, the inverting input terminals are all connected to the control voltage VCTRL, and the output terminals respectively output a control signal B, a control signal E and a control signal A; wherein each sampling analog-to-digital conversion unit is composed of a hysteresis comparator COMP1, a comparator COMP2 and an inverter INV1 connected in series in sequence; A digital trimming state machine, comprising a first gate circuit, an N-stage locked loop, and a second gate circuit connected in series in sequence; wherein the input end of the first gate circuit is used to input a control signal A and a control signal B, and the output end outputs a control signal CON; the input end of the N-stage locked loop is used to input a control signal CON, an enable signal EN, a control signal A_Z, and a control signal E_Z, and the output end is used to output a digital signal Auto_Trim[N+1:0]; the input end of the second gate circuit is used to input a power supply voltage VS, an enable signal EN, and an output signal of the N-stage locked loop, and the output end is used to output a digital signal Auto_Trim[N]; The reference signal generating module is composed of a resistor array RES_ARRAY, a plurality of resistors R1 and a transistor Q; the control end of the resistor array RES_ARRAY is used to input a digital signal Auto_Trim[N:0], the power supply end is connected to the power supply voltage VS, the ground end is respectively connected to the reference voltage VREF and the ground voltage VG through a plurality of resistors R1 connected in series, the reference voltage VREF is connected to the gate end of the transistor Q, and the substrate end, source end and drain end of the transistor Q are all connected to the ground voltage VG.

2. A PLL adaptive trimming circuit as claimed in claim 1, characterized in that: The voltage divider network is composed of a plurality of resistors R2 connected in series, wherein the resistor R2 at the head end is connected to the power supply voltage VS, and the resistor R2 at the tail end is connected to the ground voltage VG, and voltage divider nodes N1 to N3 are generated in sequence between every two adjacent resistors R2 from bottom to top.

3. A PLL adaptive trimming circuit as claimed in claim 1, characterized in that: The three sampling analog-to-digital conversion units specifically include: a first sampling analog-to-digital conversion unit, a second sampling analog-to-digital conversion unit and a third sampling analog-to-digital conversion unit; Wherein, in the first sampling analog-to-digital conversion unit, the non-inverting input terminal and the inverting input terminal of the hysteresis comparator COMP1 are respectively connected to the voltage dividing node N1 and the control voltage VCTRL, the non-inverting output terminal and the inverting output terminal of the hysteresis comparator COMP1 respectively output control signals A1 and A2 to the inverting input terminal and the non-inverting input terminal of the comparator COMP2, the output terminal of the comparator COMP2 outputs the control signal B_Z to the input terminal of the inverter INV1, and the output terminal of the inverter INV1 outputs the control signal B; Wherein, in the second sampling analog-to-digital conversion unit, the non-inverting input terminal and the inverting input terminal of the hysteresis comparator COMP1 are respectively connected to the voltage dividing node N2 and the control voltage VCTRL, the non-inverting output terminal and the inverting output terminal of the hysteresis comparator COMP1 are respectively connected to the non-inverting input terminal and the inverting input terminal of the comparator COMP2, the output terminal of the comparator COMP2 outputs the control signal E_Z to the input terminal of the inverter INV1, and the output terminal of the inverter INV1 outputs the control signal E; In the third sampling analog-to-digital conversion unit, the non-inverting input terminal and the inverting input terminal of the hysteresis comparator COMP1 are respectively connected to the voltage dividing node N3 and the control voltage VCTRL, the non-inverting output terminal and the inverting output terminal of the hysteresis comparator COMP1 are respectively connected to the non-inverting input terminal and the inverting input terminal of the comparator COMP2, the output terminal of the comparator COMP2 outputs the control signal A_Z to the input terminal of the inverter INV1, and the output terminal of the inverter INV1 outputs the control signal A.

4. A PLL adaptive trimming circuit as claimed in claim 1, characterized in that: The first gate circuit is composed of NOR gates NOR1~NOR2, NAND gates NAND1~NAND2 and inverter INV2; the control signal A and the control signal B are respectively connected to the two input ends of the NOR gate NOR1, the output end of the NOR gate NOR1 is connected to the input end of the inverter INV2, the output end of the inverter INV2 and the output end of the NAND gate NAND1 are respectively connected to the two input ends of the NAND gate NAND2, the control signal A and the control signal B are respectively connected to the two input ends of the NAND gate NAND1, the output end of the NAND gate NAND2 and the control signal A are respectively connected to the two input ends of the NOR gate NOR2, and the output end of the NOR gate NOR2 outputs the control signal CON.

5. A PLL adaptive trimming circuit as claimed in claim 1, characterized in that: The N-level locked loop includes a first-level locked loop, a second-level locked loop and a third-level locked loop; each level of the locked loop is composed of a NAND gate NAND3, an inverter INV3, a trigger DFF and an inverter INV4; the output end of the NAND gate NAND3 is connected to the input end of the inverter INV3, the output end of the inverter INV3 is connected to the clock end of the trigger DFF, the power supply end of the trigger DFF is connected to the power supply voltage VS, the output end of the trigger DFF outputs a feedback signal by connecting to the inverter INV4, and is connected to the input end of the NAND gate NAND3.

6. A PLL adaptive trimming circuit as claimed in claim 5, characterized in that: In the first-stage locked loop, the input end of the NAND gate NAND3 also includes the input control signal CON and the enable signal EN, the output end of the inverter INV3 outputs the digital signal Auto_Trim[0], and the output end of the trigger DFF is connected to the input end of the NAND gate NAND3 in the second-stage locked loop.

7. A PLL adaptive trimming circuit as claimed in claim 5, characterized in that: In the second-stage locked loop, the input end of the NAND gate NAND3 also includes the input control signal E_Z and the enable signal EN, the output end of the inverter INV3 outputs the digital signal Auto_Trim[1], and the output end of the trigger DFF is connected to the input end of the NAND gate NAND3 in the third-stage locked loop.

8. A PLL adaptive trimming circuit as claimed in claim 5, characterized in that: In the third-level locked loop, the input end of the NAND gate NAND3 also includes the input control signal A_Z and the enable signal EN, the output end of the inverter INV3 outputs the digital signal Auto_Trim[2], and the output end of the trigger DFF is connected to the input end of the NAND gate NAND4 in the second gate circuit.

9. A PLL adaptive trimming circuit as claimed in claim 5, characterized in that: The second gate circuit is composed of a NAND gate NAND4 and an inverter INV5 connected in series in sequence; the input end of the NAND gate NAND4 also includes an input enable signal EN and a power supply voltage VS, and the output end of the inverter INV5 outputs a digital signal Auto_Trim[3].

10. The PLL adaptive trimming circuit according to claim 1, characterized in that: The resistor array RES_ARRAY is composed of a number of resistors R3 connected in series and a number of transmission gate switches T connected in parallel; the power supply end of each transmission gate switch T is connected to an arbitrary number of resistors R3, the ground end is connected to a reference voltage VREF, and the control end is connected to a digital signal Auto_Trim[3:0].

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