A high speed analog comparator circuit with misadjustment correction

Abstract

The application relates to a high-speed analog comparator circuit with offset correction, which comprises a three-stage signal amplification stage circuit and a voltage offset correction circuit. The three-stage signal amplification stage circuit comprises a first-stage circuit part, a second-stage circuit part and a third-stage circuit part connected in cascade. The first-stage circuit part is used for providing a gain to attenuate noise, offset and kickback of the second-stage circuit part and the third-stage circuit part. The second-stage circuit part is used for exponentially increasing differential output of a signal. The third-stage circuit part adopts a bidirectional latch structure to minimize a regeneration time. The first-stage circuit part is further connected with an auxiliary input branch. The voltage offset correction circuit is used for charging and discharging a capacitor of the auxiliary input branch by detecting an output of the three-stage signal amplification stage circuit in a correction mode, so as to control a common-mode level of the auxiliary input branch and reduce voltage offset. The application can meet the requirement of high-speed high-precision ADC design.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a high-speed analog comparator circuit with offset correction. Background Technology

[0002] Among currently popular analog-to-digital converter (ADC) technologies, successive approximation register (SAR) ADCs are widely used in mixed-signal processing systems due to their low power consumption, high accuracy, small size, and relatively simple structure. As the core module of a SAR ADC, the comparator's speed, accuracy, and power consumption have gradually become bottlenecks in its development. Due to limitations in manufacturing processes and circuit architecture, in ADCs operating at speeds exceeding GHz, the comparator's speed completely determines the ADC's total sampling rate, making its latency a critical indicator. Furthermore, in high-precision ADCs, comparator offset can prevent the comparator from comparing two closely spaced voltage values, reducing sensitivity and affecting the ADC's accuracy.

[0003] In current mixed-signal processing systems, ADCs (Analog-to-Digital Comparators) act as a bridge between the analog and digital domains, influencing signal processing quality and signal-to-noise ratio. The design of high-speed, low-offset comparators is crucial for achieving high-performance ADCs. They not only need to respond quickly to changes in the input signal to meet the demands of high-speed sampling, but also reduce offset while maintaining high speed to improve signal processing capabilities.

[0004] Currently, commonly used comparators can be divided into two types: static comparators and dynamic comparators. Static comparators are typically open-loop applications of operational amplifiers, with relatively few components, simple structure, and no need for frequency compensation. However, their response speed is not fast enough, the output common-mode is difficult to determine, and they consume a lot of power during operation. They are gradually being replaced by dynamic comparators in modern ADC applications. Compared to static comparators, dynamic comparators consume almost no power and have a faster comparison speed, but they suffer from significant voltage offset. Traditional high-speed dynamic comparators include StrongArm latch comparators, dual-tailed current latch comparators, two-stage latch comparators, and three-stage latch comparators. These employ a structure where one or more pre-amplifier stages and latches are connected in series. The high bandwidth and gain of the pre-amplifier stage amplifies small signals, and then the latch is used for positive feedback amplification and latching of large signals. However, due to the limited gain of small signals, it is difficult to reduce the comparator delay to below 50 ps. Furthermore, the acceleration method using stacked latch structures reduces the voltage margin of the comparator, making design at low voltage nanometers very difficult. Although the three-stage latch comparator improves the gain of small signals, the increased number of cascaded stages increases delay and offset, making it difficult to meet the requirements of high-speed, high-precision ADC design. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a high-speed analog comparator circuit with offset correction, which can meet the requirements of high-speed and high-precision ADC design.

[0006] The technical solution adopted by this invention to solve its technical problem is as follows: A high-speed analog comparator circuit with offset correction is provided, comprising a three-stage signal amplification stage circuit and a voltage offset correction circuit. The three-stage signal amplification stage circuit includes a cascaded first-stage circuit section, a second-stage circuit section, and a third-stage circuit section. The first-stage circuit section provides a gain to attenuate noise, offset, and kickback of the second-stage and third-stage circuit sections. The second-stage circuit section increases the differential output of the signal exponentially. The third-stage circuit section employs a bidirectional latch structure to minimize regeneration time. The first-stage circuit section is also connected to an auxiliary input branch. The voltage offset correction circuit, in correction mode, charges and discharges the capacitor of the auxiliary input branch by detecting the output of the three-stage signal amplification stage circuit to control the common-mode level of the auxiliary input branch and reduce voltage offset.

[0007] The first-stage circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a first control transistor. The gate of the first NMOS transistor serves as the first input terminal of the first-stage circuit, its source is connected to the drain of the first control transistor, and its drain is connected to the source of the third NMOS transistor. The gate of the second NMOS transistor serves as the second input terminal of the first-stage circuit, its source is connected to the drain of the first control transistor, and its drain is connected to the source of the fourth NMOS transistor. The gate of the third NMOS transistor is connected to the first output terminal of the first-stage circuit, its drain is connected to the drain of the first PMOS transistor, and it serves as the second output terminal of the first-stage circuit. The gate of the fourth NMOS transistor is connected to the second output terminal of the first-stage circuit, its drain is connected to the drain of the second PMOS transistor, and it serves as the first output terminal of the first-stage circuit. The gate of the first PMOS transistor is connected to a clock signal, and its source is connected to a power supply terminal. The gate of the second PMOS transistor is connected to a clock signal, and its source is connected to a power supply terminal. The gate of the first control transistor is connected to a clock signal, and its source is grounded.

[0008] The auxiliary input branch includes a first auxiliary NMOS transistor and a second auxiliary NMOS transistor. The drain of the first auxiliary NMOS transistor is connected to the drain of the first NMOS transistor, and the source is connected to the drain of the first control transistor. The gate of the second auxiliary NMOS transistor is connected to one end of a capacitor, the drain is connected to the drain of the second NMOS transistor, and the source is connected to the drain of the first control transistor. The other end of the capacitor is grounded.

[0009] The second-stage circuit includes a fifth NMOS transistor, a sixth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a second control transistor. The gate of the fifth NMOS transistor is connected to the second output terminal of the first-stage circuit, and its drain is connected to the drain of the third PMOS transistor, serving as the first output terminal of the second-stage circuit. Its source is grounded. The gate of the sixth NMOS transistor is connected to the first output terminal of the first-stage circuit, and its drain is connected to the drain of the fourth PMOS transistor, serving as the second output terminal of the second-stage circuit. Its source is grounded. The gate of the third PMOS transistor is connected to the second output terminal of the second-stage circuit, and its source is connected to the drain of the second control transistor. The gate of the fourth PMOS transistor is connected to the first output terminal of the second-stage circuit, and its source is connected to the drain of the second control transistor. The gate of the second control transistor is connected to the inverted clock signal, and its source is connected to the power supply terminal.

[0010] The third-stage circuit includes a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, and a third control transistor. The gate of the seventh NMOS transistor is connected to the first output terminal of the first-stage circuit, its drain is connected to the drain of the ninth NMOS transistor, and it serves as the second output terminal of the third-stage circuit. Its source is connected to the drain of the third control transistor. The gate of the eighth NMOS transistor is connected to the second output terminal of the first-stage circuit, its drain is connected to the drain of the tenth NMOS transistor, and it serves as the first output terminal of the third-stage circuit. Its source is connected to the drain of the third control transistor. The gate of the ninth NMOS transistor is connected to the first output terminal of the third-stage circuit. One output terminal is connected, the drain is connected to the drain of the fifth PMOS transistor, and the source is connected to the drain of the third control transistor; the gate of the tenth NMOS transistor is connected to the second output terminal of the third stage circuit, the drain is connected to the drain of the sixth PMOS transistor, and the source is connected to the drain of the third control transistor; the gate of the fifth PMOS transistor is connected to the first output terminal of the second stage circuit, the drain is connected to the drain of the seventh PMOS transistor, and the source is connected to the power supply terminal; the gate of the sixth PMOS transistor is connected to the second output terminal of the second stage circuit, the drain is connected to the drain of the eighth PMOS transistor, and the source is connected to the power supply terminal; the gate of the seventh PMOS transistor is connected to the clock signal, and the source is connected to the power supply terminal; the gate of the eighth PMOS transistor is connected to the clock signal, and the source is connected to the power supply terminal.

[0011] The voltage offset correction circuit includes a first NAND gate, a second NAND gate, a first AND gate, a second AND gate, an offset correction PMOS transistor, an offset correction NMOS transistor, a first current source, and a second current source. The first input terminal of the first NAND gate is connected to the first output terminal of the third-stage circuit section, its second input terminal is connected to the second output terminal of the third-stage circuit section, and its output terminal is connected to the first input terminal of the first AND gate. The second input terminal of the first AND gate is connected to the Cal signal, and its output terminal is connected to the second input terminals of the second NAND gate and the second AND gate, respectively. The first input terminal of the second NAND gate is connected to the third-stage circuit section. The first output terminal of the second AND gate is connected to the gate of the offset correction PMOS transistor; the first input terminal of the second AND gate is connected to the second output terminal of the third stage circuit, and the output terminal is connected to the gate of the offset correction NMOS transistor; the source of the offset correction PMOS transistor is connected to the positive terminal of the first current source, and the drain is connected to the drain of the offset correction NMOS transistor; the source of the offset correction NMOS transistor is connected to the negative terminal of the second current source; the drain of the offset correction NMOS transistor is also connected to the capacitor of the auxiliary input branch; the negative terminal of the first current source is connected to the power supply terminal, and the positive terminal of the second current source is grounded.

[0012] Beneficial effects

[0013] By adopting the above-mentioned technical solutions, this invention has the following advantages and positive effects compared with the prior art: This invention reduces the comparator offset by correcting the comparator offset voltage through an auxiliary input branch design, keeping the offset within 1mV, thus enabling its use in high-speed, high-precision ADC designs. Furthermore, this invention reduces the small-signal conversion time by adding a feedforward path, and combined with the high gain of the feedforward and direct paths, the comparator combines the advantages of a two-stage low-latency amplifier with the original three-stage amplification, controlling the comparator delay to around 30Ps, making it suitable for high-speed comparisons above 10GHz. This invention increases the comparator's voltage margin by horizontally cascading it with the latch instead of vertically stacking it, allowing the circuit architecture of this invention to be applied in more advanced processes. Attached Figure Description

[0014] Figure 1 This is a circuit diagram of a high-speed analog comparator circuit with offset correction according to an embodiment of the present invention;

[0015] Figure 2 This is a signal transmission path diagram of the second-level circuit section and the third-level circuit section in the embodiment of the present invention;

[0016] Figure 3 This is a transient simulation circuit diagram of the comparator in an embodiment of the present invention;

[0017] Figure 4 This is a diagram showing the transient simulation results of the comparator in an embodiment of the present invention;

[0018] Figure 5 This is a circuit diagram of the voltage offset correction circuit in an embodiment of the present invention;

[0019] Figure 6 This is a diagram illustrating the comparator offset calibration process in an embodiment of the present invention. Detailed Implementation

[0020] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0021] Embodiments of the present invention relate to a high-speed analog comparator circuit with offset correction, such as... Figure 1 As shown, the circuit includes a three-stage signal amplification stage and a voltage offset correction circuit. The three-stage signal amplification stage includes a cascaded first-stage circuit, a second-stage circuit, and a third-stage circuit. The first-stage circuit provides a gain to attenuate noise, offset, and kickback in the second and third-stage circuits. The second-stage circuit increases the differential output of the signal exponentially. The third-stage circuit employs a bidirectional latch structure to minimize regeneration time. The first-stage circuit is also connected to an auxiliary input branch. The voltage offset correction circuit, in correction mode, charges and discharges the capacitor of the auxiliary input branch by detecting the output of the three-stage signal amplification stage to control the common-mode level of the auxiliary input branch and reduce voltage offset.

[0022] The first-stage circuit in this embodiment includes a first NMOS transistor MN11, a second NMOS transistor MN12, a third NMOS transistor MN13, a fourth NMOS transistor MN14, a first PMOS transistor MP11, a second PMOS transistor MP12, and a first control transistor T1. The gate of the first NMOS transistor MN11 serves as the first input terminal INP of the first-stage circuit, its source is connected to the drain of the first control transistor T1, and its drain is connected to the source of the third NMOS transistor MN13. The gate of the second NMOS transistor MN12 serves as the second input terminal INN of the first-stage circuit, its source is connected to the drain of the first control transistor T1, and its drain is connected to the source of the fourth NMOS transistor MN14. The gate of MOS transistor MN13 is connected to the first output terminal VX+ of the first stage circuit, and its drain is connected to the drain of the first PMOS transistor MP11, serving as the second output terminal VX- of the first stage circuit. The gate of the fourth NMOS transistor MN14 is connected to the second output terminal VX- of the first stage circuit, and its drain is connected to the drain of the second PMOS transistor MP12, serving as the first output terminal VX+ of the first stage circuit. The gate of the first PMOS transistor MP11 is connected to the clock signal CLK, and its source is connected to the power supply terminal. The gate of the second PMOS transistor MP12 is connected to the clock signal CLK, and its source is connected to the power supply terminal. The gate of the first control transistor T1 is connected to the clock signal CLK, and its source is grounded.

[0023] The auxiliary input branch in this embodiment includes a first auxiliary NMOS transistor MNC1 and a second auxiliary NMOS transistor MNC2. The drain of the first auxiliary NMOS transistor MNC1 is connected to the drain of the first NMOS transistor MN11, and the source is connected to the drain of the first control transistor T1. The gate of the second auxiliary NMOS transistor MNC2 is connected to one end of a capacitor C, the drain is connected to the drain of the second NMOS transistor MN12, and the source is connected to the drain of the first control transistor T1. The other end of the capacitor C is grounded.

[0024] The second-stage circuit in this embodiment includes a fifth NMOS transistor MN21, a sixth NMOS transistor MN22, a third PMOS transistor MP21, a fourth PMOS transistor MP22, and a second control transistor T2. The gate of the fifth NMOS transistor MN21 is connected to the second output terminal VX- of the first-stage circuit, and its drain is connected to the drain of the third PMOS transistor MP21, serving as the first output terminal VY+ of the second-stage circuit. Its source is grounded. The gate of the sixth NMOS transistor MN22 is connected to the first output terminal VX+ of the first-stage circuit. The drain of the third PMOS transistor MP21 is connected to the drain of the fourth PMOS transistor MP22 and serves as the second output terminal VY- of the second stage circuit. The source of the third PMOS transistor MP21 is grounded. The gate of the third PMOS transistor MP21 is connected to the second output terminal VY- of the second stage circuit, and the source of the third PMOS transistor MP21 is connected to the drain of the second control transistor T2. The gate of the fourth PMOS transistor MP22 is connected to the first output terminal VY+ of the second stage circuit, and the source of the fourth PMOS transistor MP22 is connected to the drain of the second control transistor T2. The gate of the second control transistor T2 is connected to the inverted clock signal CLKN, and the source of the second control transistor T2 is connected to the power supply.

[0025] The third-stage circuit in this embodiment includes a seventh NMOS transistor MN31, an eighth NMOS transistor MN32, a ninth NMOS transistor MN33, a tenth NMOS transistor MN34, a fifth PMOS transistor MP31, a sixth PMOS transistor MP32, a seventh PMOS transistor MP33, an eighth PMOS transistor MP34, and a third control transistor T3. The gate of the seventh NMOS transistor MN31 is connected to the first output terminal VX+ of the first-stage circuit, its drain is connected to the drain of the ninth NMOS transistor MN33, and it serves as the second output terminal VON of the third-stage circuit. Its source is connected to the drain of the third control transistor T3. The gate of the eighth NMOS transistor MN32 is connected to the second output terminal VX- of the first-stage circuit, its drain is connected to the drain of the tenth NMOS transistor MN34, and it serves as the first output terminal VOP of the third-stage circuit. Its source is connected to the drain of the third control transistor T3. The gate of the ninth NMOS transistor MN33 is connected to the first output terminal VX+ of the first-stage circuit, its drain is connected to the drain of the tenth NMOS transistor MN34, and it serves as the first output terminal VOP of the third-stage circuit. Its source is connected to the drain of the third control transistor T3. The gate of the ninth NMOS transistor MN33 is connected to the first output terminal VX+ of the first-stage circuit, its drain is connected to the drain of the tenth NMOS transistor MN34, and it serves as the first output terminal VOP of the third-stage circuit. Its source is connected to the drain of the third control transistor T3. The first output terminal VOP of the third-stage circuit is connected, its drain is connected to the drain of the fifth PMOS transistor MP31, and its source is connected to the drain of the third control transistor T3. The gate of the tenth NMOS transistor MN34 is connected to the second output terminal VON of the third-stage circuit, its drain is connected to the drain of the sixth PMOS transistor MP32, and its source is connected to the drain of the third control transistor T3. The gate of the fifth PMOS transistor MP31 is connected to the first output terminal VY+ of the second-stage circuit, its drain is connected to the drain of the seventh PMOS transistor MP33, and its source is connected to the power supply. The gate of the sixth PMOS transistor MP32 is connected to the second output terminal VY- of the second-stage circuit, its drain is connected to the drain of the eighth PMOS transistor MP34, and its source is connected to the power supply. The gate of the seventh PMOS transistor MP33 is connected to the clock signal CLK, and its source is connected to the power supply. The gate of the eighth PMOS transistor MP34 is connected to the clock signal CLK, and its source is connected to the power supply.

[0026] The voltage offset correction circuit in this embodiment includes a first NAND gate, a second NAND gate, a first AND gate, a second AND gate, an offset correction PMOS transistor (MPSC), an offset correction NMOS transistor (MNSC), a first current source, and a second current source. The first input terminal of the first NAND gate is connected to the first output terminal (VOP) of the third-stage circuit, and its second input terminal is connected to the second output terminal (VON) of the third-stage circuit. Its output terminal is connected to the first input terminal of the first AND gate. The second input terminal of the first AND gate is connected to the Cal signal, and its output terminal is connected to the second input terminals of the second NAND gate and the second AND gate, respectively. The first input terminal of the second NAND gate is connected to the first output terminal of the third-stage circuit. The first input terminal of the second AND gate is connected to the second output terminal VON of the third stage circuit, and the output terminal is connected to the gate of the offset correction PMOS transistor MPSC. The source of the offset correction PMOS transistor MPSC is connected to the positive terminal of the first current source, and the drain is connected to the drain of the offset correction NMOS transistor MNSC. The source of the offset correction NMOS transistor MNSC is connected to the negative terminal of the second current source. The drain of the offset correction NMOS transistor MNSC is also connected to the capacitor C of the auxiliary input branch. The negative terminal of the first current source is connected to the power supply terminal, and the positive terminal of the second current source is grounded.

[0027] The working principle of the high-speed analog comparator circuit with offset correction in this embodiment is as follows:

[0028] When the clock signal CLK is low, the first, second, and third stage circuits are all in the off state. The first output VX+ and the second output VX- of the first stage circuit are raised to VDD through the first PMOS transistor MP11 and the second PMOS transistor MP12. The second output VON and the first output VOP of the third stage circuit are raised to VDD through the seventh PMOS transistor MP33 and the eighth PMOS transistor MP34. The first output VY+ and the second output VY- of the second stage circuit are pulled down to GND through the fifth NMOS transistor MN21 and the sixth NMOS transistor MN22. The comparator completes the reset.

[0029] When the clock signal CLK is high, the first, second, and third stage circuits are all enabled. Under the influence of the input signal ΔVIN, one of the first output terminals VX+ and VX- of the first stage circuit is raised while the other is pulled low, amplifying the input signal and using it as the input to the second and third stage circuits. Similarly, the first output terminal VY+ and the second output terminal VY- of the second stage circuit are raised while the other is pulled low, further amplifying their difference signal and transmitting it to the third stage circuit. Figure 2 As shown, the second output terminal VON of the third-stage circuit and the first output terminal VOP of the third-stage circuit perform VY difference boosting differentiation through a direct signal path and VX difference pull-down differentiation through a feedforward signal path, thereby accelerating the output differentiation and significantly improving the comparator speed, allowing the comparator to complete the comparison.

[0030] When the Cal signal is low, the output SP of the second NAND gate is high, and the output SN of the second AND gate is low. At this time, both the offset correction PMOS transistor MPSC and the offset correction NMOS transistor MNSC are in the off state, and there is no current path for the calibration capacitor. The comparator is in normal working mode.

[0031] When the Cal signal is high, assuming the comparator has a positive equivalent offset voltage, the comparator output is VOP high and VON low. At this time, the offset correction PMOS transistor MPSC is turned on, and the offset correction NMOS transistor MNSC is turned off. Current flows into the calibration capacitor C, causing its voltage to rise. The transconductance of the right branch increases, balancing the offset voltage. Conversely, assuming the comparator has a negative equivalent offset voltage, the comparator output is VOP low and VON high. At this time, the offset correction PMOS transistor MPSC is turned off, and the offset correction NMOS transistor MNSC is turned on. Current flows out of the calibration capacitor C, causing its voltage to drop. The transconductance of the right branch decreases, balancing the offset voltage.

[0032] When calibration is complete, the comparator offset is 0, the output alternates between high and low levels, and the calibration capacitor C reaches equilibrium during charging and discharging.

[0033] Figure 3 The transient simulation circuit of the three-stage signal amplification stage in this embodiment is presented. The input positive terminal voltage is set to 600mV, the input negative terminal to 595mV, with a difference of 5mV. The clock period is 200Ps, the frequency is 5GHz, and Cadence is used for transient simulation of the circuit, with a simulation duration of 1ns. The simulation results are as follows. Figure 4As shown, the input difference signal is amplified to the output through the direct path and the feedforward path. When the output is VDD / 2, the time taken is 29Ps, which meets the comparison speed requirements of 10GHz and above.

[0034] Figure 5 The circuit diagram of the voltage offset correction circuit in this embodiment is given. The comparator offset correction must be performed before the comparator operates. For example, if the inputs VIP, VIN, and VIC are set to 600mV, and VINC on the upper stage of the capacitor is the correction adjustment terminal, which is the gate voltage of the auxiliary input branch of the negative input terminal, its initial value does not need to be considered; it will reach stability after correction. Furthermore, since the capacitor is charged and discharged based on the output result, a slower comparison clock is set during correction to ensure that the correction is completed quickly. The circuit calibration process is as follows: Figure 6 As shown, the calibration process takes 153ns from the Cal signal being high to the completion of calibration. When calibration begins, VOP always outputs a high level, and the current flowing into the capacitor causes the VINC voltage to rise. When VOP and VON alternately output high levels, calibration is complete. At this time, the capacitor's charging and discharging reach equilibrium, and the voltage VINC fluctuates within 1mV, indicating that the corrected voltage offset is less than 1mV, which meets the design requirements of a high-speed, high-precision ADC.

[0035] It is easy to see that this invention reduces comparator offset by using an auxiliary input branch to correct the comparator offset voltage, keeping the offset below 1mV, thus enabling its use in high-speed, high-precision ADC designs. Furthermore, this invention reduces the conversion time of small signals by adding a feedforward path, and combined with the high gain of the feedforward and direct paths, the comparator gains the advantages of a two-stage low-latency amplifier on top of the original three-stage amplification, controlling the comparator delay to around 30Ps, making it suitable for high-speed comparisons above 10GHz. This invention increases the comparator's voltage margin by horizontally cascading it with latches instead of vertically stacking it, allowing the circuit architecture to be applied in more advanced manufacturing processes.

Claims

1. A high speed analog comparator circuit with misadjustment correction, characterized by, The application relates to a three-stage signal amplification circuit and a voltage offset correction circuit, wherein the three-stage signal amplification circuit comprises a first-stage circuit part, a second-stage circuit part and a third-stage circuit part connected in series; the first-stage circuit part is used for providing a gain to attenuate noise, offset and kickback of the second-stage circuit part and the third-stage circuit part; the second-stage circuit part is used for exponentially increasing differential output of a signal; the third-stage circuit part adopts a bidirectional latch structure to minimize regeneration time; the first-stage circuit part is further connected with an auxiliary input branch; and the voltage offset correction circuit is used for charging and discharging a capacitor of the auxiliary input branch by detecting output of the three-stage signal amplification circuit in a correction mode, so as to control common mode level of the auxiliary input branch to reduce voltage offset. The first-stage circuit part comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor and a first control transistor; a gate of the first NMOS transistor is used as a first input end of the first-stage circuit part, a source is connected with a drain of the first control transistor, and a drain is connected with a source of the third NMOS transistor; a gate of the second NMOS transistor is used as a second input end of the first-stage circuit part, a source is connected with the drain of the first control transistor, and a drain is connected with a source of the fourth NMOS transistor; a gate of the third NMOS transistor is connected with a first output end of the first-stage circuit part, a drain is connected with a drain of the first PMOS transistor and is used as a second output end of the first-stage circuit part; a gate of the fourth NMOS transistor is connected with the second output end of the first-stage circuit part, a drain is connected with a drain of the second PMOS transistor and is used as the first output end of the first-stage circuit part; a gate of the first PMOS transistor is connected with a clock signal, a source is connected with a power supply end; a gate of the second PMOS transistor is connected with the clock signal, and a source is connected with the power supply end; and a gate of the first control transistor is connected with the clock signal, and a source is grounded.

2. The misadjustment corrected high speed analog comparator circuit of claim 1, wherein, The auxiliary input branch comprises a first auxiliary NMOS transistor and a second auxiliary NMOS transistor; a drain of the first auxiliary NMOS transistor is connected with a drain of the first NMOS transistor, and a source is connected with a drain of the first control transistor; a gate of the second auxiliary NMOS transistor is connected with one end of a capacitor, a drain is connected with a drain of the second NMOS transistor, and a source is connected with the drain of the first control transistor; and the other end of the capacitor is grounded.

3. The misadjustment corrected high speed analog comparator circuit of claim 2, wherein, ​ 4. The misadjustment corrected high speed analog comparator circuit of claim 1, wherein, The second stage circuit part comprises a fifth NMOS tube, a sixth NMOS tube, a third PMOS tube, a fourth PMOS tube and a second control tube, the gate of the fifth NMOS tube is connected with the second output end of the first stage circuit part, the drain is connected with the drain of the third PMOS tube and serves as the first output end of the second stage circuit part, and the source is grounded; the gate of the sixth NMOS tube is connected with the first output end of the first stage circuit part, the drain is connected with the drain of the fourth PMOS tube and serves as the second output end of the second stage circuit part, and the source is grounded; the gate of the third PMOS tube is connected with the second output end of the second stage circuit part, and the source is connected with the drain of the second control tube; the gate of the fourth PMOS tube is connected with the first output end of the second stage circuit part, and the source is connected with the drain of the second control tube; the gate of the second control tube is connected with the inverted clock signal, and the source is connected with the power supply end.

5. The misadjustment corrected high speed analog comparator circuit of claim 1, wherein, The third stage circuit part comprises a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube and a third control tube, the gate of the seventh NMOS tube is connected with the first output end of the first stage circuit part, the drain is connected with the drain of the ninth NMOS tube and serves as the second output end of the third stage circuit part, and the source is connected with the drain of the third control tube; the gate of the eighth NMOS tube is connected with the second output end of the first stage circuit part, the drain is connected with the drain of the tenth NMOS tube and serves as the first output end of the third stage circuit part, and the source is connected with the drain of the third control tube; the gate of the ninth NMOS tube is connected with the first output end of the third stage circuit part, the drain is connected with the drain of the fifth PMOS tube, and the source is connected with the drain of the third control tube; the gate of the tenth NMOS tube is connected with the second output end of the third stage circuit part, the drain is connected with the drain of the sixth PMOS tube, and the source is connected with the drain of the third control tube; the gate of the fifth PMOS tube is connected with the first output end of the second stage circuit part, the drain is connected with the drain of the seventh PMOS tube, and the source is connected with the power supply end; the gate of the sixth PMOS tube is connected with the second output end of the second stage circuit part, the drain is connected with the drain of the eighth PMOS tube, and the source is connected with the power supply end; the gate of the seventh PMOS tube is connected with the clock signal, and the source is connected with the power supply end; the gate of the eighth PMOS tube is connected with the clock signal, and the source is connected with the power supply end.

6. The misadjustment corrected high speed analog comparator circuit of claim 1, wherein, The voltage offset correction circuit comprises a first NAND gate, a second NAND gate, a first AND gate, a second AND gate, an offset correction PMOS tube, an offset correction NMOS tube, a first current source and a second current source; a first input end of the first NAND gate is connected with a first output end of the third stage circuit part, a second input end is connected with a second output end of the third stage circuit part, and an output end is connected with a first input end of the first AND gate; a second input end of the first AND gate is connected with a Cal signal, and output ends are connected with a second input end of the second NAND gate and a second input end of the second AND gate respectively; a first input end of the second NAND gate is connected with the first output end of the third stage circuit part, and an output end is connected with a gate of the offset correction PMOS tube; a first input end of the second AND gate is connected with the second output end of the third stage circuit part, and an output end is connected with a gate of the offset correction NMOS tube; a source of the offset correction PMOS tube is connected with a positive pole of the first current source, and a drain is connected with a drain of the offset correction NMOS tube; a source of the offset correction NMOS tube is connected with a negative pole of the second current source; the drain of the offset correction NMOS tube is also connected with a capacitor of the auxiliary input branch; a negative pole of the first current source is connected with a power supply end, and a positive pole of the second current source is grounded.

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