A three-stage pipelined successive approximation analog-to-digital converter

Abstract

The present application relates to a kind of three-stage pipeline type successive approximation analog-digital converter, SAR ADC circuit includes first stage sub-SAR ADC module, second stage sub-SAR ADC module and third stage sub-SAR ADC module connected in turn, shared residual operational amplifier includes two independent first differential input stage and second differential input stage;First stage sub-SAR ADC module, for sampling quantization input signal output first residual signal;First differential input stage, for amplifying first residual signal;Second stage sub-SAR ADC module, for sampling quantization amplified first residual signal after first differential input stage, output second residual signal;Second differential input stage, for amplifying second residual signal;Third stage sub-SAR ADC module, for sampling quantization amplified second residual signal after second differential input stage and output.Two-stage sub-SAR ADC module share a shared residual operational amplifier and amplify, effectively save the area of analog-digital converter overall circuit and reduce power consumption.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, specifically relating to a three-stage pipelined successive approximation analog-to-digital converter. Background Technology

[0002] An analog-to-digital converter (ADC) is an electronic device that converts analog signals into digital signals. It plays a crucial role in many applications, such as audio processing, measurement and control, digital image processing, and audio encoding and decoding. The core principle behind these applications is the diversity and continuity of analog signals, while digital signals offer advantages in terms of ease of storage, processing, and transmission. Therefore, ADCs have a wide range of applications in modern electronics, communications, and data processing.

[0003] Ultrasonic imaging systems require extremely high precision to capture subtle echo signals in order to generate high-resolution images. The resolution and precision of the ADC determine the signal detail that can be captured; high-resolution ADCs (such as 12-bit ADCs) provide higher signal precision, thus helping to form finer and more accurate images. With the development of imaging technology, the number of transducer elements and resonant frequencies are increasing to achieve higher longitudinal and radial resolution, and the precision and bandwidth required by ultrasonic signal processing circuits are also increasing. Pipeline SAR ADCs combine the advantages of Pipeline ADCs and SAR C (Successive approximation Register) ADC architectures, achieving a good balance between power consumption, speed, and resolution, making them particularly suitable for medium-to-high-speed, high-precision applications.

[0004] SAR ADCs (Successive Approximation Register ADCs) are used in some ultrasound imaging techniques. SAR ADCs typically have high resolution (12-bit to 16-bit), making them suitable for ultrasound systems requiring high-resolution imaging. Furthermore, SAR ADCs generally have low power consumption, making them suitable for portable applications and long-term operation. Pipeline ADCs are also commonly used in ultrasound imaging systems. Because they can provide very high sampling rates, typically reaching hundreds of MHz or even higher, pipelined ADCs have a significant advantage in real-time applications requiring high-speed imaging. They provide good dynamic range, which is crucial for the accurate capture of ultrasound signals, especially when dealing with weak echo signals from deep tissues, effectively reducing distortion and ensuring image quality. However, the sampling rate of existing successive approximation ADCs is limited by their successive approximation principle. Although they can provide high sampling accuracy, the sampling speed is usually not high, making them unsuitable for ultrasound systems with high sampling rate requirements. Moreover, because each conversion requires several clock cycles, the conversion time is relatively long. Existing pipelined analog-to-digital converters (ADCs) employ a multi-stage structure, which may introduce delays during the conversion process. This delay can become a bottleneck limiting the application of pipelined ADCs, especially in ultrasound imaging applications that require extremely high speed and extremely low latency. In addition, the multi-stage structure also requires multiple corresponding residual amplifiers for residual methods, which can easily lead to excessive power consumption, thus limiting its application in portable or battery-powered ultrasound imaging systems.

[0005] Therefore, it is necessary to reduce the power consumption and area of ​​the overall analog-to-digital converter circuit, and a low-power, compact analog-to-digital converter structure is proposed. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a three-stage pipelined successive approximation analog-to-digital converter. The technical problem to be solved by this invention is achieved through the following technical solution:

[0007] This invention provides a three-stage pipelined successive approximation analog-to-digital converter, comprising: a SAR ADC circuit and a shared residual operational amplifier; the SAR ADC circuit includes a first-stage sub-SAR ADC module, a second-stage sub-SAR ADC module, and a third-stage sub-SAR ADC module connected in sequence; the shared residual operational amplifier includes two independent first differential input stages and second differential input stages; wherein, the first-stage sub-SAR ADC module is used to sample and quantize the input signal and output a first residual signal; the first differential input stage is used to amplify the first residual signal; the second-stage sub-SAR ADC module is used to sample and quantize the first residual signal amplified by the first differential input stage and output a second residual signal; the second differential input stage is used to amplify the second residual signal; the third-stage sub-SAR ADC module is used to sample and quantize the second residual signal amplified by the second differential input stage and output it.

[0008] In one embodiment of the present invention, the resolutions of the three-level sub-SAR ADC modules connected in sequence are 5-bit, 5-bit and 6-bit respectively.

[0009] In one embodiment of the present invention, the three-stage pipelined successive approximation analog-to-digital converter further includes: a digital correction module, used to correct the output signals of the first-stage sub-SAR ADC module, the second-stage sub-SAR ADC module and the third-stage sub-SAR ADC module respectively to obtain a 14-bit output signal.

[0010] In one embodiment of the present invention, the SAR ADC circuit, the shared residual operational amplifier, and the digital correction module are all controlled by a clock control signal.

[0011] In one embodiment of the present invention, the shared residual operational amplifier includes: PMOS transistors M0, M1, M2, M3, M4, M5, M6, M7, M8, NMOS transistors M9, M10, M11, M12, M13, M14, M15, M16, M17, and M18, a second auxiliary operational amplifier module, and a first auxiliary operational amplifier module; wherein the gate of PMOS transistor M0 is connected to a first bias voltage terminal, and the source is connected to the high-level terminal of the driving power supply. The drains of PMOS transistors M1, M2, M3, M4, M17, and M18 are connected to their sources, respectively. The gate of PMOS transistor M1 receives a first inverted residual signal, and the gate of PMOS transistor M2 receives a first positive residual signal. The gate of PMOS transistor M3 receives a second inverted residual signal, and the gate of PMOS transistor M4 receives a second positive residual signal. The gate of PMOS transistor M17 is connected to the gate of PMOS transistor M18 and to the common-mode signal terminal. The drain of PMOS transistor M17 is connected to the drain of NMOS transistor M10. The drain of PMOS transistor M18 is connected to the drain of NMOS transistor M9. The gate of PMOS transistor M5 receives a first clock signal. The source of PMOS transistor M6 is connected to the drain of PMOS transistor M1, and its drain is connected to the drains of PMOS transistor M7 and NMOS transistor M10, respectively. The gate of PMOS transistor M6 receives the first clock control signal, and its source is connected to the drain of PMOS transistor M2, which in turn is connected to the drains of PMOS transistor M8 and NMOS transistor M9, respectively. The gate of PMOS transistor M7 receives the second clock control signal, and its source is connected to the drain of PMOS transistor M3. The gate of PMOS transistor M8 receives the second clock control signal, and its source is connected to the drain of PMOS transistor M4. The gate of NMOS transistor M9 is connected to the gate of NMOS transistor M10 and also connected to the common-mode feedback signal terminal. The sources of both NMOS transistors M9 and M10 are connected to the low-level terminal of the drive power supply. The drain of NMOS transistor M9 is connected to the source of NMOS transistor M11 and the non-inverting input of the first auxiliary operational amplifier module; the drain of NMOS transistor M10 is connected to the source of NMOS transistor M12 and the inverting input of the first auxiliary operational amplifier module; the gate of NMOS transistor M11 is connected to the non-inverting output of the first auxiliary operational amplifier module, and its drain is connected to the drain of NMOS transistor M13; the gate of NMOS transistor M12 is connected to the inverting output of the first auxiliary operational amplifier module, and its drain is connected to the drain of NMOS transistor M14; the gate of NMOS transistor M13 is connected to the inverting output of the second auxiliary operational amplifier module, and its source is connected to the drain of NMOS transistor M15 and the non-inverting input of the second auxiliary operational amplifier module.The gate of NMOS transistor M14 is connected to the non-inverting output of the second auxiliary operational amplifier module, and its source is connected to the drain of NMOS transistor M16 and the inverting input of the second auxiliary operational amplifier module, respectively. The gate of NMOS transistor M15 is connected to the gate of NMOS transistor M16 and is also connected to the first bias voltage terminal. The sources of both NMOS transistors M15 and M16 are connected to the high-level terminal of the drive power supply.

[0012] In one embodiment of the present invention, the drain of NMOS transistor M11 serves as the inverting differential output terminal of the shared residual operational amplifier; the drain of NMOS transistor M12 serves as the non-inverting differential output terminal of the shared residual operational amplifier.

[0013] In one embodiment of the present invention, the first auxiliary operational amplifier module includes: PMOS transistors M01, M02, M03, M04, M05, M06, M07, M08, M09, NMOS transistors M010, M011, M012, and M013; wherein, the gate of PMOS transistor M01 receives an inverted differential input signal, and its source is connected to the PMOS transistors M01 and M02. The source of transistor M02, the source of PMOS transistor M03, and the drain of PMOS transistor M05 are connected to the source of NMOS transistor M011 and the drain of NMOS transistor M013, respectively. The gate of PMOS transistor M02 receives a positive differential input signal, and its drain is connected to the source of NMOS transistor M010 and the drain of NMOS transistor M012, respectively. The gate of PMOS transistor M03 receives a positive common-mode voltage signal, and its drain is connected to the low-level terminal of the drive power supply. The gate of PMOS transistor M04 receives a first positive bias voltage, and its source is connected to the drive power supply. The high-level terminal of PMOS transistor M06 is connected to the source of PMOS transistor M05 via its drain; the gate of PMOS transistor M05 is supplied with a second positive bias voltage; the gate of PMOS transistor M06 is connected to the gate of PMOS transistor M07 via a first positive bias voltage; the sources of both PMOS transistors M06 and M07 are connected to the high-level terminal of the drive power supply; the drain of PMOS transistor M06 is connected to the source of PMOS transistor M08, and the drain of PMOS transistor M07 is connected to the source of PMOS transistor M09; the gate of PMOS transistor M08 is connected to the high-level terminal of PMOS transistor M09. The gate of PMOS transistor M09 is connected to the gate of NMOS transistor M011, and a second positive bias voltage is input; the drain of PMOS transistor M08 is connected to the drain of NMOS transistor M010; the drain of PMOS transistor M09 is connected to the drain of NMOS transistor M011; the gate of NMOS transistor M010 is connected to the gate of NMOS transistor M011, and a second negative bias voltage is input; the gate of NMOS transistor M012 is connected to the gate of NMOS transistor M013, and a first negative bias voltage is input; the sources of NMOS transistors M012 and M013 are both connected to the low-level terminal of the drive power supply.

[0014] In one embodiment of the present invention, the second auxiliary operational amplifier module includes: NMOS transistors M21, M22, M23, M24, M25, PMOS transistors M26, M27, M28, M29, M210, M211, M212, and M213; wherein, the gate of NMOS transistor M21 receives an inverted differential input signal, and its source is connected to NMOS transistors M21 and M2213 respectively. The source of transistor M22, the source of NMOS transistor M23, and the drain of NMOS transistor M24 are connected to the drains of PMOS transistors M27 and M29, respectively. The gate of NMOS transistor M22 receives a positive differential input signal, and its drain is connected to the drain of PMOS transistor M26 and the source of PMOS transistor M28, respectively. The gate of NMOS transistor M23 receives an inverted common-mode voltage signal, and its drain is connected to the high-level terminal of the drive power supply. The gate of NMOS transistor M24 receives a second inverted bias voltage, and its source is connected to NMOS transistor M25. The drain of the PMOS transistor M25 is connected to the gate of the PMOS transistor M26, which is then connected to the gate of the PMOS transistor M27 and receives a first inverted bias voltage. The sources of both the PMOS transistors M26 and M27 are connected to the high-level end of the drive power supply. The gate of the PMOS transistor M28 is connected to the gate of the PMOS transistor M29 and receives a second inverted bias voltage. The drain of the PMOS transistor M28 is connected to the drain of the NMOS transistor M210. The drain of the PMOS transistor M29 is connected to the drain of the NMOS transistor M210. The gate of NMOS transistor M210 is connected to the drain of NMOS transistor M211; the gate of NMOS transistor M210 is connected to the gate of NMOS transistor M211 and is supplied with a second inverting bias voltage; the source of NMOS transistor M210 is connected to the drain of NMOS transistor M212; the source of NMOS transistor M211 is connected to the source of NMOS transistor M213; the gate of NMOS transistor M212 is connected to the gate of NMOS transistor M213 and is supplied with a first inverting bias voltage; the sources of both NMOS transistors M212 and M213 are connected to the low-level terminal of the drive power supply.

[0015] In one embodiment of the present invention, the three-stage pipelined successive approximation analog-to-digital converter further includes: a common-mode feedback module, which is connected to the positive-inverting differential output terminal and the negative-inverting differential output terminal of the shared residual operational amplifier, respectively, for maintaining the balance between the positive-inverting differential output terminal and the negative-inverting differential output terminal of the shared residual operational amplifier.

[0016] In one embodiment of the present invention, the common-mode feedback module includes: clock switches Φ1, Φ2, Φ3, Φ4, Φ5, and Φ6; capacitors C1, C2, C3, and C4; wherein, the first terminal of clock switch Φ1 is connected to the inverting differential output terminal and the first plate of capacitor C2; the second terminal of clock switch Φ1 is connected to the first terminal of clock switch Φ2 and the first plate of capacitor C1; the second terminal of clock switch Φ2 is connected to the common-mode signal terminal; and the second plate of capacitor C2 is connected to the common-mode feedback signal terminal, the first terminal of clock switch Φ3, and the first plate of capacitor C4. The second plate of capacitor C1 is connected to the second terminal of clock switch Φ3, the first terminal of clock switch Φ4, and the first plate of capacitor C3, respectively; the second terminal of clock switch Φ4 is input with a first inverting bias voltage; the second plate of capacitor C4 is connected to the inverting differential output terminal and the first terminal of clock switch Φ5, respectively; the second plate of capacitor C3 is connected to the second terminal of clock switch Φ5 and the first terminal of clock switch Φ6, respectively; the second terminal of clock switch Φ6 is connected to the common-mode signal terminal; clock switches Φ1, Φ3, and Φ5 are all controlled by the first clock control signal; clock switches Φ2, Φ4, and Φ6 are all controlled by the second clock control signal.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0018] The three-stage pipelined successive approximation analog-to-digital converter of this invention features a shared residual operational amplifier with two independent first and second differential input stages. These stages are used to input the residual signals from the two sub-SAR ADC modules, respectively. Simultaneously, the residual signals from both sub-SAR ADC modules are amplified within a single shared residual operational amplifier, reducing the original two inter-stage amplifiers to one. This effectively saves the overall circuit area of ​​the analog-to-digital converter and reduces power consumption, meeting the requirements of ultrasonic imaging systems for high resolution, high sampling rate, and low power consumption.

[0019] The three-level sub-SAR ADC module of this invention follows the area power consumption allocation, and is distributed into 5-bit, 5-bit and 6-bit resolution structures according to the optimal allocation law of speed, area and power consumption, which meets the design requirements of low power consumption and compactness.

[0020] The shared residual operational amplifier of this invention uses two pairs of switching transistors for control. The switching transistors are controlled by a clock signal. This compact design of using switching transistors helps to save the area of ​​the overall circuit of the analog-to-digital converter and reduce power consumption. By switching the switching transistors, the function of interstage amplification can be realized.

[0021] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the framework of a three-stage pipelined successive approximation analog-to-digital converter provided in an embodiment of the present invention;

[0023] Figure 2 This is a timing diagram of the operation of a three-stage pipelined successive approximation analog-to-digital converter provided in an embodiment of the present invention;

[0024] Figure 3 This is a schematic diagram of a shared residual operational amplifier provided in an embodiment of the present invention;

[0025] Figure 4 This is a schematic diagram of the structure of a first auxiliary operational amplifier module provided in an embodiment of the present invention.

[0026] Figure 5 This is a schematic diagram of the structure of a second auxiliary operational amplifier module provided in an embodiment of the present invention.

[0027] Figure 6 This is a schematic diagram of a common-mode feedback module provided in an embodiment of the present invention. Detailed Implementation

[0028] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description of a three-stage pipelined successive approximation analog-to-digital converter proposed according to the present invention is provided in conjunction with the accompanying drawings and specific embodiments.

[0029] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0030] Example 1

[0031] To meet the performance requirements of ADCs in ultrasound imaging systems and maximize efficiency in terms of area and power consumption, this invention provides a three-stage pipelined successive approximation analog-to-digital converter, such as... Figure 1 As shown,

[0032] In this embodiment, a three-stage pipelined successive approximation analog-to-digital converter includes: a SAR ADC circuit and a shared residual operational amplifier; the SAR ADC circuit includes a first-stage sub-SAR ADC module, a second-stage sub-SAR ADC module, and a third-stage sub-SAR ADC module connected in sequence; the shared residual operational amplifier includes two independent first differential input stages and second differential input stages; wherein, the first-stage sub-SAR ADC module is used to sample and quantize the input signal VIN and output a first residual signal; the first differential input stage is used to amplify the first residual signal; the second-stage sub-SAR ADC module is used to sample and quantize the first residual signal amplified by the first differential input stage and output a second residual signal; the second differential input stage is used to amplify the second residual signal; the third-stage sub-SAR ADC module is used to sample and quantize the second residual signal amplified by the second differential input stage and output it.

[0033] The principle is as follows: the input signal VIN is input to the first-stage sub-SAR ADC module. After sampling and quantization, the first residual signal is output to the first differential input stage of the shared residual operational amplifier. The amplified signal is then input to the second-stage sub-SAR ADC module. The second residual signal, after the second-stage sampling and quantization process, is input to the second differential input stage of the shared residual amplifier. After further amplification, it is input to the third-stage sub-SAR ADC module. In the third-stage sub-SAR ADC module, only sampling and quantization are required, without amplification, thus resulting in the longest conversion time.

[0034] It is worth noting that, due to the architecture of the three-stage sub-SAR ADC module in the SAR ADC circuit, the two amplification stages of the shared residual operational amplifier will not work simultaneously. Therefore, the two residual amplifiers that were originally required can be combined into one, and the residual signals can be input separately by the two differential input stages of the shared residual operational amplifier, thereby reducing the power consumption and area of ​​the overall circuit.

[0035] Furthermore, in order to maximize the efficiency of area power consumption, the resolutions of the three sequentially connected sub-SAR ADC modules are set to 5-bit, 5-bit, and 6-bit according to the optimal distribution law of velocity area power consumption in the SAR ADC circuit.

[0036] Furthermore, all three sub-SAR ADC modules follow the area power consumption allocation formula, and the resulting three-level structure meets the requirements of low-power compact design. Since there is a 1-bit redundancy between each level, a digital correction module is also provided to correct the output signals of the first-level sub-SAR ADC module, the second-level sub-SAR ADC module and the third-level sub-SAR ADC module respectively, so as to obtain a 14-bit output signal.

[0037] Specifically, the digital correction circuit works by primarily consisting of an error detection module and calibration control logic. It processes the residual signal output from the three-stage sub-SAR ADC module. Specifically, by digitally correcting the output of each stage and comparing the error with a preset target, the digital correction circuit feeds these errors back to the corresponding stage when the output deviates from the expected value. Corrections are then made through methods including, but not limited to, gain, bias, and nonlinear compensation, effectively improving accuracy, linearity, and stability. Finally, the digital codes generated by the three-stage sub-SAR ADC module are added with a staggered sum. Due to a 1-bit redundancy between each stage, a 14-bit output signal is ultimately obtained through dynamic range optimization.

[0038] It is understood that the structure of the sub-SAR ADC module and the digital correction circuit in the three-level sub-SAR ADC module can be set with reference to relevant existing technologies, and this embodiment does not limit this.

[0039] In this embodiment, the SAR ADC circuit, the shared residual operational amplifier, and the digital correction module are all controlled by clock control signals.

[0040] It should be noted that the clock control signal can be generated by an external clock generation module. This clock control signal controls the sampling and quantization processes of the three-stage sub-SAR ADC module, as well as the two differential input stages and corresponding amplification stages of the shared residual amplifier. Similarly, each bias voltage signal can also be generated by an external bias signal generation circuit.

[0041] It is worth noting that the timing diagram of the three-stage pipelined successive approximation analog-to-digital converter in this embodiment is as follows: Figure 2 As shown, it can be seen during operation that the two residual amplification stages do not overlap. Since there is no conflict between the two residual amplification processes of the submodule in the SAR ADC circuit, if two amplifiers are used, the power consumption will be too high and the layout area will be too large. Therefore, the two interstage amplifiers originally required can be reduced to one, and a shared residual operational amplifier can be used for amplification.

[0042] like Figure 3As shown, in this embodiment, the shared residual operational amplifier includes: PMOS transistors M0, M1, M2, M3, M4, M5, M6, M7, M8, NMOS transistors M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, a second auxiliary operational amplifier module AN, and a first auxiliary operational amplifier module AP;

[0043] In this configuration, the gate of PMOS transistor M0 is connected to the first bias voltage terminal Vbp1, the source is connected to the high-level terminal VDD of the drive power supply, and the drain is connected to the sources of PMOS transistors M1, M2, M3, M4, M17, and M18, respectively. The gate of PMOS transistor M1 receives the first inverted residual signal Vin1, and the gate of PMOS transistor M2 receives the first positive residual signal Vip1. The gate of PMOS transistor M3 receives the second inverted residual signal Vin2, and the gate of PMOS transistor M4 receives the second positive residual signal Vip2. The gate of PMOS transistor M17 is connected to the gate of PMOS transistor M18 and is also connected to the common-mode signal terminal VCM. The drain of OS transistor M17 is connected to the drain of NMOS transistor M10; the drain of PMOS transistor M18 is connected to the drain of NMOS transistor M9; the gate of PMOS transistor M5 receives the first clock control signal CLK1, its source is connected to the drain of PMOS transistor M1, and its drain is connected to the drains of PMOS transistor M7 and NMOS transistor M10 respectively; the gate of PMOS transistor M6 receives the first clock control signal CLK1, its source is connected to the drain of PMOS transistor M2, and its drain is connected to the drains of PMOS transistor M8 and NMOS transistor M9 respectively; the gate of PMOS transistor M7 receives the second clock control signal CLK2, and its source is connected to the drain of PMOS transistor M3; the gate of PMOS transistor M8 receives the second clock control signal, and its source is connected to... The drain of PMOS transistor M4 is connected to the drain of NMOS transistor M9; the gate of NMOS transistor M9 is connected to the gate of NMOS transistor M10 and to the common-mode feedback signal terminal Vcmc; the sources of NMOS transistors M9 and M10 are both connected to the low-level terminal GND of the drive power supply; the drain of NMOS transistor M9 is connected to the source of NMOS transistor M11 and the non-inverting input terminal of the first auxiliary operational amplifier module AP; the drain of NMOS transistor M10 is connected to the source of NMOS transistor M12 and the inverting input terminal of the first auxiliary operational amplifier module AP; the gate of NMOS transistor M11 is connected to the non-inverting output terminal of the first auxiliary operational amplifier module AP, and its drain is connected to the drain of NMOS transistor M13; the gate of NMOS transistor M12 is connected to the first auxiliary operational amplifier module AP. The inverting output terminal of amplifier module AP has its drain connected to the drain of NMOS transistor M14; the gate of NMOS transistor M13 is connected to the inverting output terminal of the second auxiliary operational amplifier module AN, and its source is connected to the drain of NMOS transistor M15 and the non-inverting input terminal of the second auxiliary operational amplifier module AN; the gate of NMOS transistor M14 is connected to the non-inverting output terminal of the second auxiliary operational amplifier module AN, and its source is connected to the drain of NMOS transistor M16 and the inverting input terminal of the second auxiliary operational amplifier module AN; the gate of NMOS transistor M15 is connected to the gate of NMOS transistor M16 and connected to the first bias voltage terminal Vbp1; the sources of both NMOS transistors M15 and M16 are connected to the high-level terminal VDD of the drive power supply.

[0044] Specifically, the drain of NMOS transistor M11 serves as the inverting differential output VON of the shared residual operational amplifier; the drain of NMOS transistor M12 serves as the non-inverting differential output VOP of the shared residual operational amplifier.

[0045] like Figure 4 As shown, in an optional embodiment, the first auxiliary operational amplifier module AP includes: PMOS transistors M01, M02, M03, M04, M05, M06, M07, M08, M09, NMOS transistors M010, M011, M012, and M013;

[0046] In this configuration, the gate of PMOS transistor M01 receives an inverted differential input signal Vin, and its source is connected to the source of PMOS transistors M02, M03, and M05, respectively. Its drain is connected to the source of NMOS transistors M011 and M013, respectively. The gate of PMOS transistor M02 receives a positive differential input signal Vip, and its drain is connected to the source of NMOS transistors M010 and M012, respectively. The gate of PMOS transistor M03 receives a positive common-mode voltage signal Vmp, and its drain is connected to the low-level terminal GND of the drive power supply. The gate of PMOS transistor M04 receives a first positive bias voltage Vbp1, its source is connected to the high-level terminal VDD of the drive power supply, and its drain is connected to the source of PMOS transistor M05. The gate of PMOS transistor M05 receives a second positive bias voltage Vbp2. The gate of PMOS transistor M06 is connected to the gate of PMOS transistor M07, and outputs... A first positive bias voltage Vbp1 is applied; the sources of PMOS transistors M06 and M07 are both connected to the high-level terminal VDD of the drive power supply; the drain of PMOS transistor M06 is connected to the source of PMOS transistor M08, and the drain of PMOS transistor M07 is connected to the source of PMOS transistor M09; the gate of PMOS transistor M08 is connected to the gate of PMOS transistor M09, and a second positive bias voltage Vbp2 is applied; the drain of PMOS transistor M08 is connected to the drain of NMOS transistor M010; the drain of PMOS transistor M09 is connected to the drain of NMOS transistor M011; the gate of NMOS transistor M010 is connected to the gate of NMOS transistor M011, and a second inverted bias voltage Vbn2 is applied; the gate of NMOS transistor M012 is connected to the gate of NMOS transistor M013, and a first inverted bias voltage Vbn1 is applied; the sources of NMOS transistors M012 and M013 are both connected to the low-level terminal of the drive power supply.

[0047] like Figure 5As shown, in an optional embodiment, the second auxiliary operational amplifier module AN includes: NMOS transistors M21, M22, M23, M24, M25, PMOS transistors M26, M27, M28, M29, M210, M211, M212, and M213;

[0048] In this configuration, the gate of NMOS transistor M21 receives an inverted differential input signal Vin, and its source is connected to the source of NMOS transistors M22, M23, and M24, respectively. Its drain is connected to the drain of PMOS transistors M27 and M29, respectively. The gate of NMOS transistor M22 receives a positive differential input signal Vip, and its drain is connected to the drain of PMOS transistors M26 and M28, respectively. The gate of NMOS transistor M23 receives an inverted common-mode voltage signal Vmn, and its drain is connected to the high-level terminal VDD of the drive power supply. The gate of NMOS transistor M24 receives a second inverted bias voltage Vbn2, and its source is connected to the drain of NMOS transistor M25. The gate of NMOS transistor M25 receives a first inverted bias voltage Vbn1, and its source is connected to the low-level terminal GND of the drive power supply. The gate of PMOS transistor M26 is connected to the gate of PMOS transistor M27 and receives a first positive bias voltage Vbn1. Phase bias voltage Vbp1; the sources of PMOS transistors M26 and M27 are both connected to the high-level terminal of the drive power supply; the gate of PMOS transistor M28 is connected to the gate of PMOS transistor M29 and inputs a second positive bias voltage Vbp2; the drain of PMOS transistor M28 is connected to the drain of NMOS transistor M210; the drain of PMOS transistor M29 is connected to the drain of NMOS transistor M211; the gate of NMOS transistor M210 is connected to the gate of NMOS transistor M211 and inputs a second negative bias voltage Vbn2; the source of NMOS transistor M210 is connected to the drain of NMOS transistor M212; the source of NMOS transistor M211 is connected to the source of NMOS transistor M213; the gate of NMOS transistor M212 is connected to the gate of NMOS transistor M213 and inputs a first negative bias voltage Vbn1; the sources of NMOS transistors M212 and M213 are both connected to the low-level terminal GND of the drive power supply.

[0049] It should be noted that by setting the positive common-mode voltage signal Vmp and the negative common-mode voltage signal Vmn, both PMOS transistor M03 and NMOS transistor M23 are made to operate at appropriate common-mode points. Two auxiliary operational amplifier modules are introduced into the main structure of the shared residual operational amplifier, with both the first auxiliary operational amplifier module AP and the second auxiliary operational amplifier module AN connected to the differential output of the main structure of the shared residual operational amplifier. This is used to compensate for gain, providing a high-gain feedback path to ensure high gain over a wide frequency range, increasing gain without excessively affecting system bandwidth.

[0050] To further improve the output stability of the shared residual operational amplifier in this embodiment, a common-mode feedback module is also provided. The common-mode feedback module is connected to the positive differential output terminal VOP and the negative differential output terminal VON of the shared residual operational amplifier, respectively, to maintain the balance between the positive differential output terminal VOP and the negative differential output terminal VON of the shared residual operational amplifier.

[0051] Specifically, the main function of the common-mode feedback module is to maintain the balance of the output signal by adjusting the common-mode signal between the two differential output terminals, thereby effectively reducing common-mode interference and improving the stability and accuracy of the system.

[0052] Furthermore, since the three-stage pipelined successive approximation analog-to-digital converter in this embodiment uses a two-phase non-alternating clock control signal, this feature can also be utilized in the design to establish a common-mode feedback module (CMFB) based on the two-phase non-alternating clock control signal and clock switch.

[0053] like Figure 6 As shown, specifically, the common-mode feedback module CMFB includes: clock switches Φ1, Φ2, Φ3, Φ4, Φ5, and Φ6; capacitors C1, C2, C3, and C4; wherein, the first terminal of clock switch Φ1 is connected to the inverting differential output terminal VON and the first plate of capacitor C2; the second terminal of clock switch Φ1 is connected to the first terminal of clock switch Φ2 and the first plate of capacitor C1; the second terminal of clock switch Φ2 is connected to the common-mode signal terminal VCM; and the second plate of capacitor C2 is connected to the common-mode... The feedback signal terminal Vcmc, the first terminal of clock switch Φ3, and the first plate of capacitor C4 are connected; the second plate of capacitor C1 is connected to the second terminal of clock switch Φ3, the first terminal of clock switch Φ4, and the first plate of capacitor C3; the second terminal of clock switch Φ4 receives the first inverting bias voltage Vbn1; the second plate of capacitor C4 is connected to the inverting differential output terminal VON and the first terminal of clock switch Φ5; the second plate of capacitor C3 is connected to the second terminal of clock switch Φ5 and the first terminal of clock switch Φ6; the second terminal of clock switch Φ6 is connected to the common-mode signal terminal VCM.

[0054] In the common-mode feedback module, clock switches Φ1, Φ3, and Φ5 are all controlled by the first clock control signal CLK1; clock switches Φ2, Φ4, and Φ6 are all controlled by the second clock control signal CLK2.

[0055] It is worth noting that the common-mode feedback module (CMFB) can operate normally without being limited by the output voltage range of the shared residual operational amplifier, thereby improving the system's flexibility and stability. Furthermore, the design of the CMFB avoids introducing new parasitic zeros and poles, thus reducing complexity and further improving system performance.

[0056] The working principle of the three-stage pipelined successive approximation analog-to-digital converter in this embodiment is that the first differential input stage and the second differential input stage of the shared residual operational amplifier serve as two independent input paths. The first differential input stage and the second differential input stage respectively input the residual signals output from the first-stage sub-SAR ADC module and the second-stage sub-SAR ADC module, which are then amplified in the first-stage amplifier and the second-stage amplifier, respectively. Specifically, the switching transistors PMOS transistors M5 and M6 of the first-stage amplifier are controlled by the first clock control signal CLK1, and the switching transistors PMOS transistors M3 and M4 of the second differential input stage are controlled by the second clock control signal CLK2.

[0057] When amplifying the residual signal output from the first-stage sub-SAR ADC module, the first clock control signal CLK1 is low, and both PMOS transistors M5 and M6 of the first-stage amplifier are turned on to achieve residual amplification. When amplifying the residual signal output from the second-stage sub-SAR ADC module, the second clock control signal CLK2 is low, and both PMOS transistors M7 and M8 of the second-stage amplifier are turned on to achieve residual amplification.

[0058] In the remaining stages, both the first clock control signal CLK1 and the second clock control signal CLK2 are high. The switching transistors PMOS M5 and M6 of the first-stage amplifier, as well as the second differential input transistors PMOS M3 and M4, are all turned off. Both input paths are fully reset outside their respective amplification stages. PMOS transistors M17 and M18 receive common-mode signals, creating a short circuit to eliminate residual charge at the input terminals and reduce the memory effect caused by parasitic capacitance at the input nodes. Furthermore, sharing a single operational amplifier simplifies the circuit structure, saving nearly 20% of the area.

[0059] It is worth noting that the three-stage pipelined successive approximation analog-to-digital converter in this embodiment uses a shared residual amplifier for residual amplification in the distribution law three-stage pipelined SAR ADC circuit with optimal area and power consumption. Controlled by a clock control signal, it can achieve two-stage amplification function using only two pairs of switching transistors (PMOS transistors M5, M6, M7, and M8), which effectively reduces area and power consumption compared to traditional circuits.

[0060] The three-stage pipelined successive approximation analog-to-digital converter of this invention features a shared residual operational amplifier with two independent first and second differential input stages. These stages are used to input the residual signals from the two sub-SAR ADC modules, respectively. Simultaneously, the residual signals from both sub-SAR ADC modules are amplified within a single shared residual operational amplifier, reducing the original two inter-stage amplifiers to one. This effectively saves the overall circuit area of ​​the analog-to-digital converter and reduces power consumption, meeting the requirements of ultrasonic imaging systems for high resolution, high sampling rate, and low power consumption.

[0061] The three-level sub-SAR ADC module of this invention follows the area power consumption allocation, and is distributed into 5-bit, 5-bit and 6-bit resolution structures according to the optimal allocation law of speed, area and power consumption, which meets the design requirements of low power consumption and compactness.

[0062] The shared residual operational amplifier of this invention uses two pairs of switching transistors for control. The switching transistors are controlled by a clock signal. This compact design of using switching transistors helps to save the area of ​​the overall circuit of the analog-to-digital converter and reduce power consumption. By switching the switching transistors, the function of interstage amplification can be realized.

[0063] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0064] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A three-stage pipelined successive approximation analog-to-digital converter, characterized in that, include: SAR ADC circuit and shared residual operational amplifier; The SAR ADC circuit includes a first-stage sub-SAR ADC module, a second-stage sub-SAR ADC module, and a third-stage sub-SAR ADC module connected in sequence. The shared residual operational amplifier includes two independent first differential input stages and second differential input stages. The first-stage sub-SAR ADC module is used to sample and quantize the input signal and output a first residual signal; the first differential input stage is used to amplify the first residual signal; the second-stage sub-SAR ADC module is used to sample and quantize the first residual signal amplified by the first differential input stage and output a second residual signal; the second differential input stage is used to amplify the second residual signal, and the residual amplification stages of the first differential input stage and the second differential input stage do not overlap; the third-stage sub-SAR ADC module is used to sample and quantize the second residual signal amplified by the second differential input stage and output it. It also includes: a digital correction module, used to correct the output signals of the first-stage sub-SAR ADC module, the second-stage sub-SAR ADC module and the third-stage sub-SAR ADC module respectively, to obtain a 14-bit output signal; The SAR ADC circuit, the shared residual operational amplifier, and the digital correction module are all controlled by clock control signals. It also includes a common-mode feedback module, which is connected to the positive-inverting differential output terminal and the negative-inverting differential output terminal of the shared residual operational amplifier, respectively, to maintain the balance between the positive-inverting differential output terminal and the negative-inverting differential output terminal of the shared residual operational amplifier.

2. The three-stage pipelined successive approximation analog-to-digital converter according to claim 1, characterized in that, The resolutions of the three sequentially connected sub-SAR ADC modules are 5-bit, 5-bit, and 6-bit, respectively.

3. The three-stage pipelined successive approximation analog-to-digital converter according to claim 1, characterized in that, The shared residual operational amplifier includes: PMOS transistors M0, M1, M2, M3, M4, M5, M6, M7, M8, NMOS transistors M9, M10, M11, M12, M13, M14, M15, M16, M17, and M18, a second auxiliary operational amplifier module, and a first auxiliary operational amplifier module; In this configuration, the gate of PMOS transistor M0 is connected to the first bias voltage terminal, the source is connected to the high-level terminal of the driving power supply, and the drain is connected to the source of PMOS transistors M1, M2, M3, M4, M17, and M18, respectively. The gate of PMOS transistor M1 receives a first inverted residual signal, and the gate of PMOS transistor M2 receives a first positive residual signal; the gate of PMOS transistor M3 receives a second inverted residual signal, and the gate of PMOS transistor M4 receives a second positive residual signal. The gate of PMOS transistor M17 is connected to the gate of PMOS transistor M18 and is connected to the common-mode signal terminal; the drain of PMOS transistor M17 is connected to the drain of NMOS transistor M10; the drain of PMOS transistor M18 is connected to the drain of NMOS transistor M9. The gate of PMOS transistor M5 receives the first clock control signal, its source is connected to the drain of PMOS transistor M1, and its drain is connected to the drains of PMOS transistor M7 and NMOS transistor M10, respectively; the gate of PMOS transistor M6 receives the first clock control signal, its source is connected to the drain of PMOS transistor M2, and its drain is connected to the drains of PMOS transistor M8 and NMOS transistor M9, respectively. The gate of PMOS transistor M7 receives a second clock control signal, and its source is connected to the drain of PMOS transistor M3; the gate of PMOS transistor M8 receives a second clock control signal, and its source is connected to the drain of PMOS transistor M4. The gate of NMOS transistor M9 is connected to the gate of NMOS transistor M10 and to the common-mode feedback signal terminal; the sources of both NMOS transistors M9 and M10 are connected to the low-level terminal of the driving power supply; the drain of NMOS transistor M9 is connected to the source of NMOS transistor M11 and the non-inverting input terminal of the first auxiliary operational amplifier module; the drain of NMOS transistor M10 is connected to the source of NMOS transistor M12 and the inverting input terminal of the first auxiliary operational amplifier module. The gate of NMOS transistor M11 is connected to the non-inverting output terminal of the first auxiliary operational amplifier module, and its drain is connected to the drain of NMOS transistor M13; the gate of NMOS transistor M12 is connected to the inverting output terminal of the first auxiliary operational amplifier module, and its drain is connected to the drain of NMOS transistor M14. The gate of NMOS transistor M13 is connected to the inverting output terminal of the second auxiliary operational amplifier module, and its source is connected to the drain of NMOS transistor M15 and the non-inverting input terminal of the second auxiliary operational amplifier module, respectively; the gate of NMOS transistor M14 is connected to the non-inverting output terminal of the second auxiliary operational amplifier module, and its source is connected to the drain of NMOS transistor M16 and the inverting input terminal of the second auxiliary operational amplifier module, respectively. The gate of NMOS transistor M15 is connected to the gate of NMOS transistor M16 and is also connected to the first bias voltage terminal; the sources of both NMOS transistors M15 and M16 are connected to the high-level terminal of the driving power supply.

4. The three-stage pipelined successive approximation analog-to-digital converter according to claim 3, characterized in that, The drain of the NMOS transistor M11 serves as the inverting differential output terminal of the shared residual operational amplifier; the drain of the NMOS transistor M12 serves as the non-inverting differential output terminal of the shared residual operational amplifier.

5. The three-stage pipelined successive approximation analog-to-digital converter according to claim 3, characterized in that, The first auxiliary operational amplifier module includes: PMOS transistors M01, M02, M03, M04, M05, M06, M07, M08, M09, NMOS transistors M010, M011, M012, and M013; The gate of the PMOS transistor M01 is connected to an inverted differential input signal, and its source is connected to the source of the PMOS transistor M02, the source of the PMOS transistor M03, and the drain of the PMOS transistor M05. The drain of the PMOS transistor M011 is connected to the source of the NMOS transistor M013. The gate of the PMOS transistor M02 receives a positive differential input signal, and its drain is connected to the source of the NMOS transistor M010 and the drain of the NMOS transistor M012, respectively. The gate of the PMOS transistor M03 is input with a positive common-mode voltage signal, and its drain is connected to the low-level terminal of the driving power supply. The gate of the PMOS transistor M04 is input with a first positive bias voltage, the source is connected to the high-level terminal of the driving power supply, and the drain is connected to the source of the PMOS transistor M05; the gate of the PMOS transistor M05 is input with a second positive bias voltage. The gate of PMOS transistor M06 is connected to the gate of PMOS transistor M07 and is subjected to the first positive bias voltage; the sources of both PMOS transistors M06 and M07 are connected to the high-level terminal of the driving power supply; the drain of PMOS transistor M06 is connected to the source of PMOS transistor M08, and the drain of PMOS transistor M07 is connected to the source of PMOS transistor M09. The gate of the PMOS transistor M08 is connected to the gate of the PMOS transistor M09 and is subjected to the second positive bias voltage; the drain of the PMOS transistor M08 is connected to the drain of the NMOS transistor M010; the drain of the PMOS transistor M09 is connected to the drain of the NMOS transistor M011. The gate of NMOS transistor M010 is connected to the gate of NMOS transistor M011 and is supplied with a second inverting bias voltage; the gate of NMOS transistor M012 is connected to the gate of NMOS transistor M013 and is supplied with a first inverting bias voltage; the sources of both NMOS transistors M012 and M013 are connected to the low-level terminal of the driving power supply.

6. The three-stage pipelined successive approximation analog-to-digital converter according to claim 3, characterized in that, The second auxiliary operational amplifier module includes: NMOS transistors M21, M22, M23, M24, M25, PMOS transistors M26, M27, M28, M29, M210, M211, M212, and M213; The gate of NMOS transistor M21 receives an inverted differential input signal, and its source is connected to the source of NMOS transistor M22, the source of NMOS transistor M23, and the drain of NMOS transistor M24, respectively. Its drain is connected to the drain of PMOS transistor M27 and the source of PMOS transistor M29, respectively. The gate of the NMOS transistor M22 receives a positive differential input signal, and its drain is connected to the drain of the PMOS transistor M26 and the source of the PMOS transistor M28, respectively; the gate of the NMOS transistor M23 receives an inverted common-mode voltage signal, and its drain is connected to the high-level terminal of the driving power supply. The gate of the NMOS transistor M24 is input with a second inverted bias voltage, and its source is connected to the drain of the NMOS transistor M25; the gate of the NMOS transistor M25 is input with a first inverted bias voltage, and its source is connected to the low-level terminal of the driving power supply. The gate of the PMOS transistor M26 is connected to the gate of the PMOS transistor M27 and is subjected to a first positive bias voltage; the sources of both the PMOS transistor M26 and the PMOS transistor M27 are connected to the high-level terminal of the driving power supply. The gate of the PMOS transistor M28 is connected to the gate of the PMOS transistor M29 and is subjected to a second positive bias voltage; the drain of the PMOS transistor M28 is connected to the drain of the NMOS transistor M210; the drain of the PMOS transistor M29 is connected to the drain of the NMOS transistor M211. The gate of NMOS transistor M210 is connected to the gate of NMOS transistor M211 and is subjected to a second inverted bias voltage; the source of NMOS transistor M210 is connected to the drain of NMOS transistor M212; and the source of NMOS transistor M211 is connected to the source of NMOS transistor M213. The gate of the NMOS transistor M212 is connected to the gate of the NMOS transistor M213 and is subjected to a first inverted bias voltage; the sources of both the NMOS transistor M212 and the NMOS transistor M213 are connected to the low-level terminal of the driving power supply.

7. The three-stage pipelined successive approximation analog-to-digital converter according to claim 1, characterized in that, The common-mode feedback module includes: clock switch Φ1, clock switch Φ2, clock switch Φ3, clock switch Φ4, clock switch Φ5, clock switch Φ6, capacitor C1, capacitor C2, capacitor C3, and capacitor C4. Wherein, the first end of the clock switch Φ1 is connected to the inverting differential output terminal and the first plate of the capacitor C2 respectively; the second end of the clock switch Φ1 is connected to the first end of the clock switch Φ2 and the first plate of the capacitor C1 respectively; the second end of the clock switch Φ2 is connected to the common-mode signal terminal; The second plate of capacitor C2 is connected to the common-mode feedback signal terminal, the first terminal of clock switch Φ3, and the first plate of capacitor C4, respectively; the second plate of capacitor C1 is connected to the second terminal of clock switch Φ3, the first terminal of clock switch Φ4, and the first plate of capacitor C3, respectively; the second terminal of clock switch Φ4 is input with a first inverting bias voltage; The second plate of capacitor C4 is connected to the inverting differential output terminal and the first terminal of clock switch Φ5, respectively; the second plate of capacitor C3 is connected to the second terminal of clock switch Φ5 and the first terminal of clock switch Φ6, respectively; the second terminal of clock switch Φ6 is connected to the common-mode signal terminal; The clock switch Φ1, the clock switch Φ3 and the clock switch Φ5 are all controlled by the first clock control signal; The clock switches Φ2, Φ4, and Φ6 are all controlled by the second clock control signal.

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