Data compression chip and data compression method
By designing a data compression chip and using data conversion circuits and encoding circuits for data compression, the problem of complex and difficult to implement in the prior art data compression algorithm is solved, and efficient data transmission and bandwidth pressure are achieved.
Patent Information
- Application Number
- CN202411726909.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-28
- Publication Date
- 2025-04-25
AI Technical Summary
Existing data compression algorithms use software to compress data in computers, and the algorithm is complex and difficult to implement in hardware, resulting in low data transmission rate and high bandwidth pressure.
A data compression chip is designed, including a data conversion circuit and a data encoding circuit. Data transformation is performed through symbol bit rotation, comparison incremental operation, bit plane transformation and bitwise exclusive OR operation, and bit plane data encoding and structural rearrangement are performed when receiving a data output request to obtain compressed data.
By converting the data compression algorithm into hardware circuits, the data transmission rate between chips is improved, the data bandwidth pressure is reduced, and efficient data compression is achieved.
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Figure CN119892103A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of data processing technology, and in particular to a data compression chip and a data compression method. Background Art
[0002] With the advent of the era of big data, the generation and processing of data has become an indispensable part of daily life and work. However, due to the huge amount of data, its storage and transmission have become a major challenge. In order to alleviate the data reading speed gap between the computing unit and the storage unit, a multi-level SRAM cache is set in the processor. The closer the cache is to the computing unit, the smaller its space is, and the faster the reading speed is. However, the processor and the memory still need to be connected through a bus, and each level of cache also needs to be connected. The International Technology Roadmap for Semiconductors (ITRS) points out that the annual growth rate of pins is less than 10%, and the increase in the bandwidth of each pin will also cause the high-speed interface to be configured with additional circuits, which will consume additional static and dynamic power. Therefore, compared with increasing physical bandwidth, studying data compression algorithms can more effectively cope with the growing challenges and is one of the effective ways to solve the bandwidth wall problem brought by the von Neumann architecture.
[0003] If a data compression algorithm is applied during data transmission to speed up the transmission rate between chips, the traditional algorithm still has some disadvantages. For example, the traditional data compression algorithm uses software in the computer to compress data, and its most important indicator is the data compression rate, so the algorithm is often more complicated; and the currently commonly used data compression algorithm will compress by associating the previous and subsequent data or establishing a large-scale dictionary. This process is usually performed in software, which is difficult to implement through hardware, and the compression and decompression process will consume a lot of time, which is difficult to meet the requirements for data transmission. Summary of the invention
[0004] In order to solve the above technical problems, the present disclosure provides a data compression chip and a data compression method.
[0005] According to one aspect of the present disclosure, a data compression chip is provided, the data compression chip comprising: a data conversion circuit, a data encoding circuit and an AXI interface; wherein,
[0006] The data transformation circuit is used to receive input data from the AXI interface, perform data transformation on the input data, and obtain deformed data; wherein the data transformation includes: sign bit rotation, comparison increment operation, bit plane transformation and bitwise XOR operation;
[0007] The data encoding circuit is used to perform bit plane data encoding and structural rearrangement on the deformed data to obtain compressed data when receiving a data output request, and output the compressed data through the AXI interface.
[0008] According to another aspect of the present disclosure, a data compression method is further provided, the method being applied to the data compression chip as described above, the method comprising:
[0009] Receive input data, perform data transformation on the input data, and obtain deformed data; wherein the data transformation includes: sign bit rotation, comparison increment operation, bit plane transformation, and bitwise XOR operation;
[0010] When a data output request is received, bit plane data encoding and structure rearrangement are performed on the deformed data to obtain compressed data.
[0011] The present disclosure also provides an electronic device, the electronic device comprising:
[0012] processor;
[0013] a memory for storing instructions executable by the processor;
[0014] The processor is used to read the executable instructions from the memory and execute the instructions to implement the above data compression method.
[0015] The present disclosure also provides a computer-readable storage medium, wherein the storage medium stores a computer program, and the computer program is used to execute the above data compression method.
[0016] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:
[0017] The data compression chip provided by the embodiment of the present disclosure includes: a data conversion circuit, a data encoding circuit and an AXI interface, and may also include a cache unit; wherein the data conversion circuit is used to receive input data from the AXI interface, perform data conversion on the input data, and obtain deformed data; wherein the data conversion includes: sign bit rotation, comparison increment operation, bit plane conversion and bitwise XOR operation; the data encoding circuit is used to perform bit plane data encoding and structural rearrangement on the deformed data upon receiving a data output request to obtain compressed data, and output the compressed data through the AXI interface. The present disclosure uses the data conversion including sign bit rotation, comparison increment operation, bit plane conversion and bitwise XOR operation as an improved bit plane compression algorithm, based on the improved bit plane compression algorithm, with the data conversion circuit and the data encoding circuit as the main architecture, and also includes a cache unit and an AXI interface structure to form a data compression chip, based on which the compression algorithm is converted into a hardware circuit, providing a dedicated chip for data compression for data transmission, improving the data transmission rate between chips, and reducing the data bandwidth pressure. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0020] Figure 1 This is an architecture diagram of the data compression chip described in the embodiment of the present disclosure;
[0021] Figure 2 This is a schematic diagram of the working process of the data compression chip described in the embodiment of the present disclosure;
[0022] Figure 3 It is a schematic diagram of the structure of the bit plane transformation unit described in the embodiment of the present disclosure;
[0023] Figure 4 A schematic diagram of a bit plane transformation process according to an embodiment of the present disclosure;
[0024] Figure 5 A schematic diagram of a cache array being full according to an embodiment of the present disclosure;
[0025] Figure 6 A schematic diagram of a process of bit plane data encoding according to an embodiment of the present disclosure;
[0026] Figure 7A schematic diagram of a ping-pong structure buffer register according to an embodiment of the present disclosure;
[0027] Figure 8 A flowchart of a data compression method according to an embodiment of the present disclosure;
[0028] Fig. 9 It is a schematic diagram of the structure of the electronic device described in the embodiment of the present disclosure. DETAILED DESCRIPTION
[0029] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.
[0030] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.
[0031] In view of the problems of complex algorithms and lack of hardware implementation in traditional data compression algorithms, the present disclosure provides a data compression chip and a data compression method. The scheme converts the data compression algorithm into a hardware circuit, provides a data compression dedicated chip for data transmission, improves the data transmission rate between chips, and reduces the pressure on data bandwidth. The data compression chip in this scheme is a data lossless compression algorithm chip. The data compression chip uses an improved bit plane compression algorithm, with data conversion circuits and data encoding circuits as the main architecture of the chip, and also includes structures such as a cache unit and an AXI interface. For ease of understanding, the following describes the embodiments of the present disclosure.
[0032] Reference Figure 1 , an embodiment of the present disclosure provides a data compression chip, which at least includes: a data conversion circuit 110, a data encoding circuit 120 and an AXI (Advanced eXtensible Interface, bus protocol) interface 140.
[0033] In another embodiment, the data compression chip may further include: a cache unit 130 connected between the data conversion circuit 110 and the data encoding circuit 120; the cache unit 130 includes a plurality of cache arrays. Based on this, the data compression chip may use the data conversion circuit 110 and the data encoding circuit 120 as the main architecture, and also include the cache unit 130 and the AXI interface 140.
[0034] In the above embodiment, the data conversion circuit 110 is used to receive input data from the AXI interface 140, perform data conversion on the input data, and obtain deformed data; wherein the data conversion includes: sign bit rotation, comparison increment operation, bit plane conversion and bitwise XOR operation. The deformed data obtained by the data conversion circuit 110 can be temporarily stored in the cache unit 130, or directly output to the data encoding circuit 120.
[0035] The cache unit 130 is used to cache the transformed data of the data transformation circuit 110 .
[0036] The data encoding circuit 120 is used to perform bit-plane data encoding and structural rearrangement on the deformed data to obtain compressed data when receiving a data output request, and output the compressed data through the AXI interface 140 .
[0037] Specifically, after the data conversion circuit 110 completes the data conversion of the input data, the deformed data can be temporarily stored in the cache unit 130, waiting for a data output request from the outside. When the cache unit 130 is not empty, when a data output request is received, the data encoding circuit 120 first obtains the temporarily stored deformed data from the cache unit 130, performs bit plane data encoding on the deformed data, and then rearranges the data encoding structure, splices it into 32 bits, and then outputs it.
[0038] Based on the above data compression chip, its workflow can refer to Figure 2 As shown, the following steps S202 to S212 are included.
[0039] Step S202, receiving input data to be processed; wherein the input data includes but is not limited to data in FP32, FP16, INT32, and INT8 formats.
[0040] Step S204, performing data transformation on the input data based on the improved bit plane compression algorithm to obtain deformed data; wherein the data transformation performed by the improved bit plane compression algorithm includes: sign bit rotation, comparison increment operation, bit plane transformation and bitwise XOR operation.
[0041] When this step is implemented by a data transformation circuit, the data transformation circuit controls the execution of data transformation through a state machine and temporarily stores the data being transformed through a data transformation array. The data transformation circuit includes a plurality of bit plane transformation units; Figure 3The schematic diagram of the circuit structure of a single bit-plane data conversion unit shown in FIG. 1 , the bit-plane conversion unit may include: a data conversion array and a first register (i.e., data_in_reg1), a second register (i.e., data_in_reg2), a third register (i.e., dbx_reg1) and a fourth register (i.e., dbx_reg2) connected to the data conversion array; wherein the first register and the second register are arranged at the data input end, and the third register and the fourth register are arranged at the data output end. Figure 3 In the embodiment, the state machine is composed of the above-mentioned multiple registers and combinational logic circuits.
[0042] Based on the circuit structure of the above bit plane transformation unit, this embodiment provides a method for performing data transformation on input data to obtain deformed data, which includes the following contents.
[0043] (1) A sign bit rotation process includes: performing sign bit rotation on input data of a current clock cycle to obtain first data, storing the first data in a first register, and transferring second data existing in the first register in a previous clock cycle to a second register.
[0044] In this embodiment, when a data transmission start signal is received, the state machine of the bit-plane data conversion unit switches from an idle state to a comparison increment operation state, and receives input data in the current clock cycle.
[0045] In one example, when the input data of the current clock cycle is valid 32-bit data, the input data is sign-rotated. The sign-rotation can be understood as cyclically shifting the input data left, that is, shifting the floating-point sign bit from the highest bit to the lowest bit, and shifting the remaining bits of data left by one bit, completing the sign-rotation operation, and obtaining the first data. Then, the first data is assigned to the first register, which is the first-level register data_in_reg1; and the second data existing in the first register in the previous clock cycle is passed to the second register, which is the second-level register data_in_reg2.
[0046] It can be understood that the aforementioned current clock cycle is a relative concept, which is used to characterize a time period for receiving input data and performing sign bit rotation; similarly, the first data and the second data are also relative, and are the data after the sign bits corresponding to the upper and lower clock cycles are rotated. That is to say, the first data existing in the first register in the previous clock cycle becomes the second data that needs to be transferred to the second register in the current clock cycle, and so on. The first data existing in the first register in the current clock cycle becomes the second data that needs to be transferred to the second register in the next clock cycle.
[0047] In another example, when the input data of the current clock cycle is data with a bit width less than 32 bits (such as 16-bit data or 8-bit data), the input data is firstly subjected to sign bit rotation, and then the high bit of the data after the sign bit rotation is supplemented with 0 until the bit width reaches 32 bits, that is, the data after the sign bit rotation is placed in the low bit of 32 bits, and the high bit of 32 bits is filled with 0, thereby obtaining the first data. Then, the first data is assigned to the first register; and the second data existing in the first register in the previous clock cycle is transferred to the second register.
[0048] (2) A comparison increment operation process includes: performing a comparison increment operation on the first data and the second data to obtain third data; writing the third data into a data transformation array, and storing the third data of multiple clock cycles in a column direction in the data transformation array.
[0049] After storing the first data of the current clock cycle into the first register and transferring the second data in the first register of the previous clock cycle to the second register, this embodiment performs a comparison increment operation on the first data of the first register and the second data of the second register. The specific implementation process may include:
[0050] Compare the numerical values of the first data and the second data; based on the comparison result, subtract the data with a smaller numerical value from the data with a larger numerical value to obtain a difference value of the lower 32 bits as an incremental operation; add a high-order extension bit based on the difference to obtain the third data; wherein, if the numerical value of the first data is greater than or equal to the numerical value of the second data, the high-order extension bit is the first numerical value "0"; if the numerical value of the first data is less than the numerical value of the second data, the high-order extension bit is the second numerical value "1".
[0051] By comparing the increment operation and the high-order extension bit, the third data obtained is 33-bit data, and the third data is written into the data transformation array.
[0052] The third data of multiple clock cycles can be obtained through the above embodiment. Therefore, in the data conversion array, the third data of multiple clock cycles are stored in the column direction.
[0053] (3) A bit plane transformation process, comprising: performing bit plane transformation on the data in the data transformation array to obtain bit plane transformation data.
[0054] In the data transformation array that stores data in the column direction, the first column of data is called the base number. In the process of bit plane transformation of each column of data in the data transformation array, the data except the base number is split, and the same weight bits of the original data are reorganized. For details, please refer to Figure 4When receiving the bit plane transformation start signal, the data transformation circuit reads the data in sequence while keeping the data in the data transformation array unchanged, records the base number data base_data in the first column and keeps it unchanged, and then changes from reading by column to reading by row when reading data other than the base number, that is, the highest bit data of each column is composed of the first new data arranged in the row direction, and the second highest bit data is composed of the second new data arranged in the row direction; and so on, until the lowest bit data is composed of the last new data arranged in the row direction; the above new data is recorded as data dbp_flag.
[0055] When reading data other than the basic number, the rows with all "0" values can be recorded. If the new data dbp_flag read is all "0" values, the subscript register corresponding to the new data dbp_flag is assigned a value of "1".
[0056] After the above bit plane transformation, a column of base numbers and new data in each row after transformation are combined into bit plane transformation data.
[0057] (4) A bitwise XOR operation process, comprising: starting from the second clock cycle, sequentially reading a row of bit plane transformation data in the data transformation array, storing the read bit plane transformation data into a third register, and transferring the data existing in the third register in the previous clock cycle to a fourth register; performing a bitwise XOR operation on the data in the third register and the data in the fourth register to obtain the transformed data.
[0058] In this embodiment, when a bitwise XOR operation start signal is received, the first clock cycle outputs a 32-bit base number. Starting from the second clock cycle, each clock cycle reads the upper 31 bits of a row of data in the data transformation array and stores them in the third register (i.e., the first-level register dbx_reg1), and the data read in the previous clock cycle is stored from the third register to the fourth register (i.e., the second-level register dbx_reg2).
[0059] Next, the data in the third register and the data in the fourth register are subjected to a bitwise XOR operation, and the last data is read in sequence to obtain the deformed data. The characteristic of the XOR operation is that when the input is two identical values, the output is "0". For an input that has undergone a mutation in the data, multiple consecutive "1" bits may be generated after the incremental calculation (of course, the use of the comparison incremental operation in this embodiment will reduce the generation of the "1" value), and after the bit plane transformation, the same weight bit of multiple data becomes "1", which will be converted into "0" through the XOR operation. Therefore, this embodiment can further extract the characteristics of the data for compression through the bitwise XOR operation, thereby improving the data compression capability.
[0060] In this embodiment, after the last bit plane transformation data in the data transformation array is read in sequence, the end signal corresponding to the bitwise XOR operation is set to high, and the state machine of the bit plane transformation unit switches to the idle state, waiting for the next data transmission start signal to arrive.
[0061] At the level of the data conversion circuit, in the three main stages of the bit plane data conversion process, the comparison increment operation writes data to the data conversion array, the bit plane conversion and the bitwise XOR operation read data from the data conversion array, and in the process of reading data, the data conversion array cannot write new data, and before the data conversion is completed, the data conversion array cannot output the result. Based on this, in order to maintain continuous data transmission and improve throughput efficiency, the input and output of the data conversion array in this embodiment use a pipeline structure.
[0062] For the input pipeline of the data transformation array, when the first-level array is written, during the data transformation, if there is new data entering, it will be written to the second-level array; when the second-level array is written, the new data will be written to the third-level array; when the third-level array is written, the first-level array has completed the data transformation, and the result is passed to the cache unit, and new data can be written. If a signal that the cache is full is received, the data input is paused, the input state machine state is maintained, and the data in the data transformation array is temporarily stored in the array without output. The output pipeline structure of the data transformation array is similar. After the first-level array completes the data output to the cache unit, it re-enters the write state, and the second-level array starts to output data to the cache unit; after the output of the second-level array is completed, the third-level array continues to output data.
[0063] This embodiment sets the input and output of the data transformation array to use a pipeline structure, which is closely integrated with the data transformation process of the data compression algorithm, and can process continuous input data and integrate and transform it in a data block manner.
[0064] Step S206, determining whether the data does not need to be cached; that is, determining whether to directly output the deformed data to the data encoding circuit.
[0065] Step S208: if caching is required, the deformed data is stored in the cache unit.
[0066] In the above embodiments, data transformation of input data is the most important and time-consuming process. Since the transformed deformed data is still stored in the form of blocks, if the deformed data does not need to be directly encoded and output, it is necessary to cache the deformed data after data transformation. The cache unit includes multiple cache arrays, for example, a total of 8 cache arrays. The structure of the cache unit is similar to the data transformation array, but its functions only include reading and writing, and do not involve logical operations. Multiple cache arrays meet the following requirements: 1) The writing and reading of data blocks in the cache array need to be completed in the same order, that is, the data blocks written first must be read first; 2) When one cache array is writing, another cache array can be read; 3) The address management of the cache array should be simple enough, and it can be determined whether the cache array is fully written or completely empty based on the address. Figure 5 A situation in which the cache array is full is shown. The cache unit generates a cache full signal, back-pressures the input data, and suspends the storage of new data before data is output and an empty cache array is generated.
[0067] Step S210: if caching is not required, output the deformed data to the data encoding circuit.
[0068] Step S212: the data encoding circuit performs bit plane data encoding and structural rearrangement on the deformed data to obtain compressed data.
[0069] When receiving a data output request, the data encoding circuit can read the deformed data from the cache unit, or directly receive the deformed data from the data conversion circuit. The data encoding circuit can include a data encoding unit and a structure rearrangement unit; the data encoding unit is used to perform bit plane data encoding on the deformed data to obtain encoded data; wherein the bit plane data encoding includes: basic number encoding, zero value run encoding and frequent pattern encoding; the structure rearrangement unit is used to perform structure rearrangement on the encoded data using the ping-pong cache to obtain compressed data.
[0070] In this embodiment, the data encoding unit may include three types of encoding methods: basic number encoding, zero-value run encoding and frequent pattern encoding. A specific method for the data encoding unit to encode the deformed data in the bit plane may be referred to in Figure 6 shown.
[0071] Determine whether the deformed data is a base number; if it is a base number, perform base number encoding on the base number to obtain encoded data. Base number encoding is only used for base numbers.
[0072] If it is not a basic number, determine whether the deformed data is all zeros; if it is all zeros, perform zero-value run encoding on the deformed data to obtain encoded data; if it is not all zeros, perform frequent pattern encoding on the deformed data to obtain encoded data.
[0073] In one implementation, zero-value run-length coding is used preferentially for deformation data. If the deformation data is all "0" values, the zero-value counter is incremented by one, and no coded data is generated. If the deformation data is not "0" values, the state of the zero-value counter is first determined. If the previous deformation data is all "0" values, zero-value run-length coding ends, and frequent mode coding is performed while generating run-length coding, and then the two codes are spliced; if the previous deformation data is not "0" values, only frequent mode coding is performed.
[0074] In addition, frequent pattern encoding has a priority order. First, it determines whether the deformed data is all "1" values. If not, it then determines whether it is all "0" values before the bitwise XOR operation based on the carried dbx_flag. If neither is satisfied, it attempts to perform pattern matching with data types that have only a single "1", only two consecutive "1"s, or other types, and generates corresponding encoded data.
[0075] The coded data corresponding to the deformed data is obtained through the above embodiments, and the coded data is then rearranged into 32-bit compressed data for output.
[0076] The structure rearrangement unit in this embodiment uses a ping-pong buffer structure to perform structure rearrangement and output, thereby avoiding code overflow and inability to temporarily store data, which affects data output efficiency. Figure 7 As shown, a ping-pong structure buffer register pp_buf[63:0] is established, and the strobe signal is used to control whether the ping-pong structure buffer register is used to write or read data. When the high 32-bit buffer pp_buf[63:32] writes the encoded data, the data is read from the low 32-bit buffer pp_buf[31:0]. After the high 32-bit buffer is written, the data is read from the high 32-bit buffer and written to the low 32-bit buffer, so as to ensure the continuous output of data with twice the storage space. Figure 7 It shows that when the upper 32-bit buffer is full, the remaining data bits of the current data are written to the lower 32-bit buffer, and then the upper 32-bit buffer is output.
[0077] The above embodiments set up a data encoding unit with encoding priority and a structure rearrangement unit with a ping-pong cache, and convert data blocks composed of data types including but not limited to FP32, INT32, INT8 after bit plane data transformation into encoded data using an encoding method, and rearrange them into 32-bit form for output, thereby achieving a higher compression rate.
[0078] In summary, the data compression chip provided by the embodiment of the present disclosure includes: a data conversion circuit, a data encoding circuit and an AXI interface, and may also include a cache unit; wherein the data conversion circuit is used to receive input data from the AXI interface, perform data conversion on the input data, and obtain deformed data; wherein the data conversion includes: sign bit rotation, comparison increment operation, bit plane conversion and bitwise XOR operation; the data encoding circuit is used to perform bit plane data encoding and structural rearrangement on the deformed data when receiving a data output request to obtain compressed data, and output the compressed data through the AXI interface. The present disclosure uses the data conversion including sign bit rotation, comparison increment operation, bit plane conversion and bitwise XOR operation as an improved bit plane compression algorithm. Based on the improved bit plane compression algorithm, the data conversion circuit and the data encoding circuit are used as the main architecture, and also include a cache unit and an AXI interface structure to form a data compression chip. Based on this, the compression algorithm is converted into a hardware circuit, providing a dedicated chip for data compression for data transmission, improving the data transmission rate between chips, and reducing the data bandwidth pressure.
[0079] like Figure 8 The flowchart of the data compression method shown in the figure, the embodiment of the present disclosure provides a data compression method, which is applied to the data compression chip described in the above embodiment; the data compression method in this embodiment may include:
[0080] Step S302, receiving input data, performing data transformation on the input data to obtain deformed data; wherein the data transformation includes: sign bit rotation, comparison increment operation, bit plane transformation and bitwise XOR operation;
[0081] Step S304: upon receiving a data output request, performing bit plane data encoding and structural rearrangement on the deformed data to obtain compressed data.
[0082] The implementation principle and technical effects of the method provided in this embodiment are the same as those of the aforementioned data compression chip embodiment. For the sake of brief description, for matters not mentioned in the method embodiment, reference may be made to the corresponding contents in the aforementioned data compression chip embodiment.
[0083] Fig. 9 The structure diagram of an electronic device provided by the embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the electronic device 400 includes one or more processors 401 and a memory 402 .
[0084] The processor 401 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 400 to perform desired functions.
[0085] The memory 402 may include one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 401 may run the program instructions to implement the data compression method of the embodiment of the present disclosure described above and / or other desired functions. Various contents such as input signals, signal components, noise components, etc. may also be stored in the computer-readable storage medium.
[0086] In one example, the electronic device 400 may further include: an input device 403 and an output device 404, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).
[0087] In addition, the input device 403 may also include, for example, a keyboard, a mouse, and the like.
[0088] The output device 404 can output various information to the outside, including the determined distance information, direction information, etc. The output device 404 can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.
[0089] Of course, to simplify, Fig. 9 Only some of the components related to the present disclosure in the electronic device 400 are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device 400 may also include any other appropriate components.
[0090] Furthermore, this embodiment also provides a computer-readable storage medium, wherein the storage medium stores a computer program, and the computer program is used to execute the above data compression method.
[0091] A computer program product of a data compression method, device, electronic device and medium provided in the embodiments of the present disclosure includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the previous method embodiments. The specific implementation can be found in the method embodiments and will not be repeated here.
[0092] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0093] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A data compression chip, characterized in that: The data compression chip includes: a data conversion circuit, a data encoding circuit and an AXI interface; wherein, The data transformation circuit is used to receive input data from the AXI interface, perform data transformation on the input data, and obtain deformed data; wherein the data transformation includes: sign bit rotation, comparison increment operation, bit plane transformation and bitwise XOR operation; The data encoding circuit is used to perform bit plane data encoding and structural rearrangement on the deformed data to obtain compressed data when receiving a data output request, and output the compressed data through the AXI interface.
2. The data compression chip according to claim 1, characterized in that: The data conversion circuit includes a plurality of bit plane conversion units; The bit plane transformation unit includes: a data transformation array and a first register, a second register, a third register and a fourth register connected to the data transformation array; wherein the first register and the second register are arranged at the data input end, and the third register and the fourth register are arranged at the data output end.
3. The data compression chip according to claim 2, characterized in that: The step of performing data transformation on the input data to obtain deformed data includes: Rotate the sign bit of the input data of the current clock cycle by the state machine to obtain first data, store the first data into the first register, and transfer the second data existing in the first register in the previous clock cycle to the second register; Performing a comparison increment operation on the first data and the second data to obtain third data; Writing the third data into the data transformation array; In the data transformation array, storing the third data of a plurality of clock cycles in a column direction; Performing bit plane transformation on the data in the data transformation array to obtain bit plane transformation data; Starting from the second clock cycle, sequentially read a row of the bit-plane transformation data in the data transformation array, store the read bit-plane transformation data into a third register, and transfer the data existing in the third register in the previous clock cycle to the fourth register; A bitwise XOR operation is performed on the data in the third register and the data in the fourth register to obtain deformed data.
4. The data compression chip according to claim 2, characterized in that: After the last bit plane transformation data in the data transformation array is read in sequence, the end signal corresponding to the bitwise XOR operation is set to high, and the state machine switches to an idle state.
5. The data compression chip according to claim 2, characterized in that: The input and output of the data transformation array both use a pipeline structure.
6. The data compression chip according to claim 1, characterized in that: The data compression chip further includes: a cache unit connected between the data conversion circuit and the data encoding circuit; the cache unit includes a plurality of cache arrays for caching the deformed data of the data conversion circuit.
7. The data compression chip according to claim 1, characterized in that: The data encoding circuit includes a data encoding unit and a structure rearrangement unit; wherein, The data encoding unit is used to perform bit plane data encoding on the deformed data to obtain encoded data; wherein the bit plane data encoding includes: basis number encoding, zero value run encoding and frequent pattern encoding; The structure rearrangement unit is used to use the ping-pong buffer to rearrange the structure of the encoded data to obtain compressed data.
8. The data compression chip according to claim 7, characterized in that: The data encoding unit is also used for: Determine whether the deformation data is a basic number; If it is the base number, performing base number encoding on the base number to obtain encoded data; If it is not the base number, determining whether the deformed data is all zeros; If it is all zeros, the deformed data is subjected to zero-value run-length encoding to obtain encoded data; If it is not all zeros, frequent pattern encoding is performed on the deformed data to obtain encoded data.
9. The data compression chip according to claim 7, characterized in that: The structural rearrangement unit is also used for: The selection signal is used to control whether the upper 32 bits or the lower 32 bits in the ping-pong structure buffer register are used to write data or read data.
10. A data compression method, characterized in that: The method is applied to the data compression chip described in any one of claims 1 to 9, and the method comprises: Receive input data, perform data transformation on the input data, and obtain deformed data; wherein the data transformation includes: sign bit rotation, comparison increment operation, bit plane transformation, and bitwise XOR operation; When a data output request is received, bit plane data encoding and structure rearrangement are performed on the deformed data to obtain compressed data.