A digital radio frequency device and a laser frequency stabilization device based on a gigabit transceiver

Abstract

The present application discloses a digital radio frequency device and a laser frequency stabilization device based on a gigabit transceiver, relating to the technical field of laser frequency stabilization. The digital radio frequency device includes: an encoding phase module, a phase modulation module, a serial transmission module, and a radio frequency driving module. Among them, the encoding phase module is used to generate an initial encoding phase based on the clock signal frequency of the gigabit transceiver, the preset number of parallel channels, and the target laser frequency shift; the phase modulation module is used to perform phase modulation on the initial encoding phase to generate an encoding phase and a demodulation signal; the serial transmission module is used to generate a digital radio frequency signal based on the encoding phase and the gigabit transceiver; the radio frequency driving module is used to perform power amplification and filtering on the digital radio frequency signal to generate a target digital radio frequency signal. The digital radio frequency device in the present application can provide a digital radio frequency source with low cost, a wide frequency range, and high power stability for the field of space cold atoms, etc.

Description

Technical Field

[0001] This application relates to the technical field of laser frequency stabilization, and particularly to a digital radio frequency device and a laser frequency stabilization device based on a gigabit transceiver. Background Art

[0002] In the field of space cold atoms, a large number of radio frequency sources are required. However, the currently used radio frequency sources have various problems such as high price, low indicators, and complex operation. How to make a radio frequency source with low cost, wide frequency range, and high power stability has become a technical problem to be solved urgently in the field of atomic cold space. Summary of the Invention

[0003] Based on the above problems, this application provides a digital radio frequency device based on a gigabit transceiver, which can provide a digital radio frequency source with low cost, wide frequency range, and high power stability for fields such as space cold atoms.

[0004] The embodiments of this application disclose the following technical solutions:

[0005] The first aspect of this application discloses a digital radio frequency device based on a gigabit transceiver, including:

[0006] An encoding phase module, configured to generate an initial encoding phase based on the clock signal frequency of the gigabit transceiver, the preset number of parallel channels, and the target laser frequency shift;

[0007] A phase modulation module, configured to perform phase modulation on the initial encoding phase to generate an encoding phase and a demodulation signal; the encoding phase has a double sideband; the demodulation signal is a signal having the same frequency as the target sideband; the target sideband is one of the sidebands in the double sideband;

[0008] A serial transmission module, configured to generate a digital radio frequency signal based on the encoding phase and the gigabit transceiver;

[0009] A radio frequency driving module, configured to perform power amplification and filtering on the digital radio frequency signal to generate a target digital radio frequency signal.

[0010] In an optional implementation manner, the encoding phase module includes:

[0011] A first accumulation step determination sub-module, configured to determine a serial phase accumulation step according to the clock signal frequency of the gigabit transceiver and the target laser frequency shift;

[0012] A second accumulation step determination sub-module, configured to determine a parallel phase accumulation step based on the serial phase accumulation step and the number of parallel channels;

[0013] The basic phase determination sub-module is used to determine the basic phase corresponding to the parallel channel at the current counting moment based on the basic phase corresponding to the parallel channel at the previous counting moment and the parallel phase accumulation step; each of the parallel channels has the same basic phase at the same counting moment;

[0014] The encoded phase determination sub-module is used for each of the parallel channels to determine the initial encoded phase of the parallel channel at the current counting moment based on the basic phase of the parallel channel at the current counting moment, the channel encoding of the parallel channel, and the serial phase accumulation step; the channel encoding is a preset digital encoding used to indicate the arrangement order of the corresponding parallel channel among multiple parallel channels.

[0015] In an optional implementation manner, the first accumulation step determination sub-module includes:

[0016] The time step determination unit is used to determine the time step based on the clock signal frequency of the gigabit transceiver;

[0017] The serial phase accumulation step determination unit is used to determine the serial phase accumulation step based on the time step, the target laser frequency shift, and the full phase range.

[0018] In an optional implementation manner, the phase modulation module includes:

[0019] The parameter setting sub-module is used to set the initial phase corresponding to the digital radio frequency signal as the first initial phase;

[0020] The function setting sub-module is used to set the phase modulation depth, the phase modulation signal frequency, and the second initial phase to obtain a phase modulation function;

[0021] The phase modulation sub-module is used to perform phase modulation on the initial encoded phase based on the phase modulation function and the first initial phase to generate the encoded phase and the demodulation signal.

[0022] In an optional implementation manner, the function setting sub-module includes:

[0023] The target address determination unit is used to determine the target address based on the second initial phase and the phase corresponding to the gigabit transceiver; the phase corresponding to the gigabit transceiver is the product of the phase modulation signal frequency and time;

[0024] The target amplitude determination unit is used to determine the target amplitude based on the target address and a preset first look-up table; the first look-up table indicates the correspondence between the address and the amplitude of the sine wave;

[0025] A sine wave determination unit, configured to determine a sine wave function as the phase modulation function based on the phase modulation depth, the phase modulation signal frequency, the second initial phase, the phase corresponding to the gigabit transceiver, and the target amplitude.

[0026] In an alternative implementation, the function setting sub-module includes:

[0027] A triangular wave function setting unit, configured to determine a triangular wave function as the phase modulation function based on the phase corresponding to the gigabit transceiver and a preset triangular wave formula; the phase corresponding to the gigabit transceiver is the product of the phase modulation signal frequency and time.

[0028] In an alternative implementation, the phase modulation sub-module includes:

[0029] A modulation base phase determination unit, configured to determine the modulation base phase corresponding to the parallel channel at the current counting moment based on the modulation base phase corresponding to the parallel channel at the previous counting moment and the parallel phase accumulation step; each parallel channel has the same modulation base phase at the same counting moment;

[0030] An encoded modulation phase determination unit, configured to, for each parallel channel, determine the encoded modulation phase corresponding to the parallel channel at the current counting moment based on the modulation base phase corresponding to the parallel channel at the current counting moment, the channel encoding of the parallel channel, the serial phase accumulation step, the phase modulation function, and the first initial phase;

[0031] An encoded phase determination unit, configured to, for each parallel channel, determine the encoded phase corresponding to the parallel channel at the current counting moment based on the initial encoded phase corresponding to the parallel channel at the current counting moment and the encoded modulation phase corresponding to the parallel channel at the current counting moment.

[0032] In an alternative implementation, the serial transmission module includes:

[0033] A preprocessing module, configured to perform a parameter zeroing operation on the gigabit transceiver to obtain a target gigabit transceiver; the parameter zeroing operation is used to clear the pre-stored protocols and parameters in the gigabit transceiver;

[0034] A digital encoding unit, configured to splice the encoded phases of the highest bits of multiple parallel channels to obtain the digital encoding;

[0035] A digital radio frequency transmission unit, configured to generate the digital radio frequency signal based on the target gigabit transceiver and the digital encoding.

[0036] The second aspect of the present application discloses a laser frequency stabilization device, which includes: a laser, a digital radio frequency module, an electro-optic modulator, a frequency stabilization cavity, an error detection module, and a servo control module;

[0037] The laser is used to output a first laser signal;

[0038] The digital radio frequency module is used to generate the phase of a demodulation signal and a digital radio frequency signal according to a target laser frequency shift; the demodulation signal and the digital radio frequency signal are homologous signals; the digital radio frequency module is the digital radio frequency device disclosed in the first aspect;

[0039] The electro-optic modulator is used to generate a second laser signal according to the first laser signal and the digital radio frequency signal;

[0040] The frequency stabilization cavity is used to output a third laser signal according to the second laser signal;

[0041] The error detection module is used to generate a digital error signal based on the phase of the third laser signal and the demodulation signal;

[0042] The servo control module is used to perform servo control on the laser according to the digital error signal, so that the error value corresponding to the redetected digital error signal is less than a set error threshold.

[0043] In an optional implementation manner, the error detection module includes:

[0044] A detection signal acquisition unit, which is used to detect and process the third laser signal through an analog-to-digital converter and a photodetector to obtain a detection signal;

[0045] An error signal generation unit, which is used to perform mixing and filtering operations on the digital code value of the detection signal and the digital code value corresponding to the phase of the demodulation signal to obtain the digital error signal; the digital code value corresponding to the phase of the demodulation signal is determined based on the phase of the demodulation signal and a preset second look-up table; the second look-up table is used to indicate the corresponding relationship between the phase and the digital code value.

[0046] In an optional implementation manner, the servo control module is specifically used for:

[0047] Performing servo control on the laser according to the digital error signal, digital lead-lag, and digital proportional-integral-derivative regulator, so that the error value corresponding to the redetected digital error signal is less than a set error threshold.

[0048] Compared with the prior art, the present application has the following beneficial effects:

[0049] The present application discloses a digital radio frequency device based on a gigabit transceiver, including: an encoding phase module, a phase modulation module, a serial transmission module, and a radio frequency driving module. Among them, the encoding phase module is used to generate an initial encoding phase based on the clock signal frequency of the gigabit transceiver, the preset number of parallel channels, and the target laser frequency shift; the phase modulation module is used to perform phase modulation on the initial encoding phase to generate an encoding phase and a demodulation signal; the serial transmission module is used to generate a digital radio frequency signal based on the encoding phase and the gigabit transceiver; the radio frequency driving module is used to perform power amplification and filtering on the digital radio frequency signal to generate a target digital radio frequency signal. Since the gigabit transceiver can be integrated on an FPGA, it has the advantages of low cost and strong stability; by changing the signal frequency of the gigabit transceiver, the output of the target digital radio frequency signal with a frequency range of 0-5G can be achieved; therefore, the digital radio frequency device in the present application can provide a digital radio frequency source with low cost, wide frequency range, and high power stability for the field of space cold atoms, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0051] Figure 1 Schematic structural diagram of a digital radio frequency device provided by an embodiment of the present application;

[0052] Figure 2A Schematic diagram of generating an initial encoding phase provided by an embodiment of the present application;

[0053] Figure 2B Schematic diagram of generating an encoding phase provided by an embodiment of the present application;

[0054] Figure 3 Schematic diagram of the relationship between the frequency and power of a digital radio frequency signal provided by an embodiment of the present application;

[0055] Figure 4 Schematic structural diagram of a laser frequency stabilization device provided by an embodiment of the present application;

[0056] Figure 5 Schematic diagram of the frequency distribution of a second laser signal provided by an embodiment of the present application;

[0057] Figure 6 Schematic diagram of a third-order lead-lag frequency response curve provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0058] In the field of space cold atoms, a large number of radio frequency sources are required. However, the currently used radio frequency sources have various problems such as high price, low performance indicators, and complex operation.

[0059] A Gigabit Transceiver (GTX) is a high-performance and highly reliable high-speed serial transceiver that has broad application prospects in various high-speed serial communication interfaces. The Gigabit Transceiver is embedded in the FPGA, with a line speed range usually from 1 Gbps to 12 Gbps and a payload range from 0.8 Gbps to 10 Gbps, capable of meeting the high-speed and real-time transmission requirements of huge amounts of data in modern digital processing technologies and computing technologies.

[0060] This application proposes a digital radio frequency device based on a Gigabit Transceiver, which can provide a digital radio frequency source with low cost, wide frequency range, high power stability, high resolution, and rapid response for fields such as space cold atoms.

[0061] To enable those skilled in the art to better understand the solution of this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of this application.

[0062] Figure 1 It is a schematic structural diagram of a digital radio frequency device provided for the embodiments of this application. Combining Figure 1 As shown, the digital radio frequency device 100 in this application includes: an encoding phase module 101, a phase modulation module 102, a serial transmission module 103, and a radio frequency driving module 104.

[0063] The encoding phase module 101 is used to generate an initial encoding phase based on the clock signal frequency of the GTX transceiver, the preset number of parallel channels, and the target laser frequency shift.

[0064] The phase modulation module 102 is used to perform phase modulation on the initial encoding phase to generate an encoding phase and a demodulation signal. Among them, the encoding phase has double sidebands; the demodulation signal is a signal with the same frequency as the target sideband; the target sideband is one of the sidebands in the double sidebands.

[0065] The serial transmission module 103 is used to generate a digital radio frequency signal based on the encoding phase and the GTX transceiver.

[0066] The radio frequency driving module 104 is used to perform power amplification and filtering on the digital radio frequency signal to generate a target digital radio frequency signal.

[0067] In an alternative implementation, the encoding phase module 101 includes:

[0068] A first accumulation step determination sub-module, configured to determine a serial phase accumulation step according to the clock signal frequency of the GTX transceiver and the target laser frequency shift;

[0069] A second accumulation step determination sub-module, configured to determine a parallel phase accumulation step based on the serial phase accumulation step and the number of parallel channels;

[0070] A basic phase determination sub-module, configured to determine the basic phase corresponding to the parallel channel at the current counting moment based on the basic phase corresponding to the parallel channel at the previous counting moment and the parallel phase accumulation step; each parallel channel has the same basic phase at the same counting moment;

[0071] An encoding phase determination sub-module, configured to, for each parallel channel, determine the initial encoding phase of the parallel channel at the current counting moment based on the basic phase of the parallel channel at the current counting moment, the channel encoding of the parallel channel, and the serial phase accumulation step; the channel encoding is a preset digital encoding used to indicate the arrangement order of the corresponding parallel channel among multiple parallel channels.

[0072] In an alternative implementation, the first accumulation step determination sub-module includes:

[0073] A time step determination unit, configured to determine a time step based on the clock signal frequency of the GTX transceiver;

[0074] A serial phase accumulation step determination unit, configured to determine a serial phase accumulation step based on the time step, the target laser frequency shift, and the full phase range.

[0075] Figure 2A FIG. is a schematic diagram of generating an initial encoding phase provided by an embodiment of the present application. Next, in combination with Figure 2A , the process of generating the initial encoding phase through the encoding phase module 101 will be described in detail. This process can be summarized into three steps:

[0076] The first step: Determine the parallel phase accumulation step.

[0077] A gigabit transceiver is a high-speed serial transceiver with a maximum sampling rate exceeding 10 GHz. However, 10 GHz is not applicable to the internal logic units of the FPGA. In the present application, through the parallel encoding method, the parallel encoding is configured to the transmission port of the GTX, and the parallel-to-serial operation is performed inside the GTX to achieve a 10G serial transmission speed.

[0078] In digital circuits, integer division of the clock frequency can be achieved through a counter. The data transmission clock of GTX can be as high as 10G. Through integer division, theoretically, positive integer division of 10 / 2N (N = 1, 2, 3...) can be achieved; among them, 10 / 2N corresponds to the frequency of the output signal; 10G is the highest serial transceiver clock frequency supported by GTX, and 2N is the division coefficient (N is the width of half a cycle. The lengths of the positive and negative two cycles of a square wave are the same, so the division coefficient is an integer multiple of two).

[0079] The characteristic of integer division is that the duty cycle of the output waveform remains stable at 50%. The disadvantage is that the output frequencies are finite points and the intervals are not fixed, and the higher the frequency, the larger the interval. In many application scenarios, a stable 50% duty cycle is not pursued, and fractional division can be achieved by changing the 0, 1 ratio.

[0080] It should be emphasized that the clock signal frequency of the gigabit transceiver, the target laser frequency shift, the number of serial channels (also known as the parallel bit width), and the encoding of the serial channels are preset according to the usage requirements.

[0081] For example, in this application, the clock signal frequency of the gigabit transceiver is set to 10G and the number of serial channels is set to 64.

[0082] At a 10GHz serial clock, the common parallel bit width is 64, and the corresponding parallel clock (also known as the parallel clock within the phase modulation module) is 156.25MHz. Therefore, the phase counter is 64-way parallel at a 156.25MHz clock, corresponding to 64-bit parallel encoding respectively. In the case of 64-way parallel, the single-channel counter's single-time cumulative phase is the phase step at the parallel clock, and the initial phase is the phase offset of the counter corresponding to the encoding at the serial clock.

[0083] Taking the sine signal y1(t) = sin(ω1t + φ O ) as an example, the real-time phase of this sine signal is ω1t + φ O , ω1 is the angular frequency, φ O is the initial phase, t is the time, and y1(t) is the expression of the sine function. The real-time phase of the sine signal has a linear relationship with time, that is, the time-domain waveform of the sine signal has a linear relationship with time. Therefore, a counter can be used to achieve the accumulation of the phase; that is, it can be calculated how much the real-time phase of the corresponding sine signal increases within the time length when the counter increases by one number, and then the time-domain waveform of the sine signal can be obtained.

[0084] However, the counter can keep increasing, and its accumulation is infinite. The sine signal belongs to a periodic signal. After its phase accumulates to 2π, it will start accumulating from zero again. Therefore, the integer cycle part in the phase accumulation can be removed through phase folding, and the fractional cycle can be corresponded to the accumulation range of the counter. In this way, the process of resetting the counter and starting to count again after it accumulates beyond the range is equivalent to the process of performing phase folding and re-accumulating the phase after the phase accumulation reaches 2π.

[0085] If the clock signal frequency of the gigabit transceiver is 10G, then the time step is 1 / 10G; if the phase full range is 2π, then in the case of the target laser frequency shift of △F, the corresponding serial phase accumulation step is equal to 2π×target laser frequency shift×time step, that is, equal to 2π×△F×(1 / 10G); this process is implemented by the first accumulation step determination sub-module.

[0086] In the case where the clock speed is reduced a lot, it is necessary to improve the counter accumulation frequency through parallel multiplexing to achieve that the phase accumulation frequency is equal to the serial transmission frequency.

[0087] In this application, the preset number of parallel channels is 64. After obtaining the serial phase accumulation step, the product of the serial phase accumulation step and the number of parallel channels is used as the parallel phase accumulation step corresponding to the parallel clock in the phase modulation module. That is, the parallel phase accumulation step = serial phase accumulation step×64; this process is implemented by the second accumulation step determination sub-module.

[0088] Step 2: Determine the base phase of the parallel channels at the T-th counting moment.

[0089] It can be understood that each parallel channel in the parallel channels is counting simultaneously. At the same counting moment, each parallel channel among the 64 parallel channels has the same base phase. When the digital radio frequency device is not started, the base phase of each parallel channel is 0.

[0090] After obtaining the parallel phase accumulation step and starting the digital radio frequency device, for any counting moment, such as the T-th counting moment, the base phase of the parallel channels at the current counting moment (the T-th counting moment) can be determined according to the base phase corresponding to the previous counting moment (the (T - 1)-th counting moment) and the parallel phase accumulation step.

[0091] Specifically, the base phase of the parallel channels at the T-th counting moment = the base phase of the parallel channels at the (T - 1)-th counting moment + the parallel phase accumulation step; this process is implemented by the base phase determination sub-module.

[0092] Step 3: Determine the initial coding phase of the parallel channels at the T-th counting moment.

[0093] For each of the 64 parallel channels, based on the base phase of the parallel channel at the current counting moment, the channel encoding of the parallel channel, and the serial phase accumulation step, determine the initial encoding phase of the parallel channel at the current counting moment.

[0094] Specifically, the initial encoding phase of the parallel channel at the T-th counting moment = the base phase of the parallel channel at the T-th counting moment + the serial phase accumulation step × the channel encoding of the parallel channel.

[0095] Exemplarily, the initial encoding phase of the M-th parallel channel at the T-th counting moment = the base phase of the M-th parallel channel at the T-th counting moment + the serial phase accumulation step × the channel encoding of the M-th parallel channel; where M is an integer greater than 0 and less than 64.

[0096] Wherein, when the number of parallel channels is 64, the range of channel encoding is 0 - 63. Each of the 64 parallel channels has a channel encoding. The channel encoding is a preset digital encoding used to indicate the arrangement order of the corresponding parallel channel among multiple parallel channels; this process is implemented by the encoding phase determination sub-module.

[0097] In an alternative implementation, the phase modulation module 102 includes:

[0098] A parameter setting sub-module for setting the initial phase corresponding to the digital radio frequency signal as the first initial phase;

[0099] A function setting sub-module for setting the phase modulation depth, the phase modulation signal frequency, and the second initial phase to obtain a phase modulation function;

[0100] A phase modulation sub-module for performing phase modulation on the initial encoding phase based on the phase modulation function and the first initial phase to generate an encoding phase and a demodulation signal.

[0101] In an alternative implementation, the function setting sub-module includes:

[0102] A target address determination unit for determining a target address based on the second initial phase and the phase corresponding to the GTX transceiver; the phase corresponding to the GTX transceiver is the product of the phase modulation signal frequency and time;

[0103] A target amplitude determination unit for determining a target amplitude based on the target address and a preset first look-up table; the first look-up table indicates the correspondence between the address and the amplitude of the sine wave;

[0104] A sine wave determination unit for determining a sine wave function as the phase modulation function based on the phase modulation depth, the phase modulation signal frequency, the second initial phase, the phase corresponding to the GTX transceiver, and the target amplitude.

[0105] In another alternative implementation, the function setting sub-module includes:

[0106] A triangular wave function setting unit, configured to determine a triangular wave function as a phase modulation function based on the phase corresponding to the GTX transceiver and a preset triangular wave formula; the phase corresponding to the GTX transceiver is the product of the phase modulation signal frequency and time.

[0107] In one alternative implementation, the phase modulation sub-module includes:

[0108] A modulation base phase determination unit, configured to determine the modulation base phase corresponding to the parallel channel at the current counting moment based on the modulation base phase corresponding to the parallel channel at the previous counting moment and the parallel phase accumulation step; each parallel channel has the same modulation base phase at the same counting moment;

[0109] An encoded modulation phase determination unit, configured to, for each parallel channel, determine the encoded modulation phase corresponding to the parallel channel at the current counting moment based on the modulation base phase corresponding to the parallel channel at the current counting moment, the channel encoding of the parallel channel, the serial phase accumulation step, the phase modulation function, and the first initial phase;

[0110] An encoded phase determination unit, configured to, for each parallel channel, determine the encoded phase corresponding to the parallel channel at the current counting moment based on the initial encoded phase corresponding to the parallel channel at the current counting moment and the encoded modulation phase corresponding to the parallel channel at the current counting moment.

[0111] It should be noted that the initial encoded phase output by the encoding phase module 101 in this application, after the initial encoded phase is input to the phase modulation module 102, the phase modulation module 101 can perform phase modulation on the initial encoded phase to generate an encoded phase; in another case, the phase modulation module 101 may not perform phase modulation on the initial encoded phase and directly determine the initial encoded phase as the encoded phase.

[0112] Based on the phase modulation module 102, the process of generating the modulation phase can be summarized into three steps:

[0113] The first step: Determine the first initial phase.

[0114] The expression of phase modulation is: y2(t)=A C ×sin(ω C ×t + m(t) + φ C ). Wherein, y2(t) is the expression of phase modulation, t is time, A C is the carrier amplitude, ω C is the carrier frequency, m(t) is the phase modulation function, φC is the initial phase of the radio frequency signal.

[0115] The initial phase φ corresponding to the digital radio frequency signal can be set through the parameter setting sub-module C and the set value is used as the first initial phase. Among them, φ C The setting range is [0, 2π].

[0116] Second step, determine the phase modulation function.

[0117] The expression of the phase modulation function is: m(t)=β m ×sin(ω m ×t + φ m ). Among them, m(t) is the phase modulation function, t is time, β m is the phase modulation depth, ω m is the phase modulation signal frequency, φ m is the initial phase of the phase modulation signal, that is, the second initial phase.

[0118] The phase modulation function can be obtained by setting the phase modulation depth, the phase modulation signal frequency, and the second initial phase.

[0119] In an optional implementation manner, the phase modulation function can be set to a sine wave function through the target address determination unit, the target amplitude determination unit, and the sine wave determination unit in the function setting sub-module, including the following steps:

[0120] First, through the target address determination unit, based on the second initial phase and the phase corresponding to the GTX transceiver, determine the target address.

[0121] The phase corresponding to the GTX transceiver is the product of the phase modulation signal frequency and time, which is ω m ×t, briefly recorded as P m .

[0122] Take the sum value of the second initial phase φ m and the phase P m corresponding to the GTX transceiver as the target address.

[0123] Secondly, through the target amplitude determination unit, based on the target address and the preset first look-up table, determine the target amplitude.

[0124] The preset first look-up table indicates the correspondence between the address and the amplitude of the sine wave.

[0125] Exemplarily, the sine wave amplitude corresponding to the target address in sin_bram can be found as the target amplitude. Among them, sin_bram is a lookup table generated by the ip core of bram, and the phase corresponding to the address range of sin_bram is 0 - 2π; the stored data calculates the target amplitude with the target address as the phase, and the expression is as shown in formula (1):

[0126] addr = mod{(P m + φ m ),2π}×2 ADDR_WIDTH (1)

[0127] Among them, addr is the target address, the mod{} function is the remainder operation, P m is the phase corresponding to the GTX transceiver, φ m is the second initial phase, and ADDR_WIDTH is the address width of the lookup table; through this formula, the address in binary corresponding to the periodic phase can be obtained as shown in formula (2):

[0128] data = 2 DATA_WIDTH-1 ×{sin(2π×addr÷2 ADDR_WIDTH ) + 1}(2)

[0129] Among them, data is the target amplitude, that is, the stored data in the sine signal lookup table, ADDR_WIDTH is the address width of the lookup table, and DATA_WIDTH is the data width stored in the lookup table; the functions of other letters refer to the introduction in the foregoing embodiments and will not be elaborated here.

[0130] Substitute the phase modulation depth β m , the phase modulation signal frequency ω m , the second initial phase φ m , the phase P m corresponding to the GTX transceiver, and the target amplitude into m(t)=β m ×sin(ω m ×t + φ m ), and the obtained sine wave function is used as the phase modulation function.

[0131] In an alternative implementation, the phase modulation function can be set to a triangular wave function through the triangular wave function setting unit in the function setting sub-module.

[0132] Specifically, the phase P m corresponding to the GTX transceiver can be substituted into the preset triangular wave function through the triangular wave function setting unit to obtain the triangular wave function.

[0133] The expression of the preset triangular wave function is as shown in formula (3):

[0134] (3)

[0135] Where Tri(t) is a triangular wave function, P m is the phase corresponding to the GTX transceiver, and β m is the phase modulation depth.

[0136] In the third step, based on the phase modulation function and the first initial phase, phase modulation is performed on the encoded phase to generate a modulated phase and a demodulated signal.

[0137] Figure 2B FIG. is a schematic diagram of generating an encoded phase provided by an embodiment of the present application. Combining Figure 2B as shown, the generation process of the encoded phase is as follows:

[0138] (1) Determine the parallel phase accumulation step corresponding to the preset 64 parallel channels in the modulation phase module 102.

[0139] Among them, the parallel phase accumulation step corresponding to the parallel clock in the phase modulation module, that is, the parallel phase accumulation step = serial phase accumulation step × 64. This step can refer to the description of the first step of the process of generating the initial encoded phase based on the encoded phase module 101 in the foregoing embodiment. Details are not described herein again.

[0140] It should be emphasized that the clock signal frequencies in the encoded phase module 101 and the phase modulation module 102 in the present application are both set with reference to the clock signal frequency of the same gigabit transceiver; the encoded phase module 101 and the phase modulation module 102 count separately, but the two counts are synchronized; that is, when the encoded phase module 101 reaches the Tth counting moment, the phase modulation module 102 also reaches the Tth counting moment.

[0141] (2) Determine the modulation base phase of the parallel channel in the phase modulation module 102 at the Tth counting moment.

[0142] Among them, the modulation base phase of the parallel channel at the Tth counting moment = the modulation base phase of the parallel channel at the (T - 1)th counting moment + the parallel phase accumulation step.

[0143] In the present application, the base phase in the phase modulation module 102 at the current counting moment is referred to as the modulation base phase at the current counting moment.

[0144] The process of calculating the modulation base phase can refer to the description of the second step of the process of generating the initial encoded phase based on the encoded phase module 101 in the foregoing embodiment. Details are not described herein again.

[0145] (3) Determine the encoded modulation phase of each parallel channel in the phase modulation module 102 at the Tth counting moment.

[0146] For each of the 64 parallel channels, based on the modulation base phase of the parallel channel at the current counting moment, the channel coding of the parallel channel, the serial phase accumulation step size, and the modulation function, determine the coded modulation phase of the parallel channel at the current counting moment.

[0147] Specifically, the coded modulation phase of the parallel channel at the T-th counting moment = the modulation function of the parallel channel at the T-th counting moment × (the modulation base phase of the parallel channel at the T-th counting moment + the serial phase accumulation step size × the channel coding of the parallel channel).

[0148] For example, the coded modulation phase of the M-th parallel channel at the T-th counting moment = the modulation function of the M-th parallel channel at the T-th counting moment × (the modulation base phase of the M-th parallel channel at the T-th counting moment + the serial phase accumulation step size × the channel coding of the M-th parallel channel).

[0149] Among them, for the modulation function of the parallel channel at the T-th counting moment, referring to the introduction in the foregoing embodiments, one of the sine modulation function or the triangular wave modulation function can be selected as the modulation function.

[0150] (4) In the acquisition coding phase module 101, obtain the initial coding phase of each of the 64 preset parallel channels at the T-th counting moment.

[0151] For the generation process of the initial coding phase, refer to Figure 2A the description in, which will not be elaborated here.

[0152] (5) In the phase modulation module 102, determine the coding phase of each of the 64 preset parallel channels.

[0153] For each of the 64 parallel channels, based on the initial coding phase of the parallel channel at the current counting moment and the coded modulation phase of the parallel channel at the current counting moment, the coding phase of the parallel channel at the current counting moment can be determined.

[0154] Specifically, for each of the 64 parallel channels, the coding phase of the parallel channel at the T-th counting moment = the initial coding phase of the parallel channel at the T-th counting moment + the coded modulation phase of the parallel channel at the T-th counting moment. In this way, the coding phase of each of the 64 parallel channels can be obtained.

[0155] In an alternative implementation, the serial transmission module 103 includes:

[0156] A preprocessing module for performing parameter zeroing operations on a gigabit transceiver to obtain a target gigabit transceiver; the parameter zeroing operation is used to clear the pre-stored protocols and parameters in the gigabit transceiver;

[0157] A digital encoding unit for splicing the encoding phases of the most significant bits of multiple parallel channels to obtain a digital encoding;

[0158] A digital radio frequency transmitting unit for generating a digital radio frequency signal based on the target gigabit transceiver and the digital encoding.

[0159] The gigabit transceiver (GTX) is mainly applied in FPGA (Field Programmable Gate Array), and it uses the programmable resources inside the FPGA for flexible configuration to adapt to different requirements, such as Ethernet, etc. There are often some preset parameters and protocols in the gigabit transceiver. The preset parameters include but are not limited to differential output swing and on-chip termination resistance; the preset protocol can be the Aurora protocol; in actual applications, the specific parameters and protocols of the gigabit transceiver may vary according to the specific FPGA model, application requirements, and interface standards.

[0160] Before starting the solution in this application, it is necessary to clear the built-in parameters or protocols in the gigabit transceiver. At the same time, the bit width of the parallel channels also needs to be set to obtain a target gigabit transceiver. It should be noted that the serial clock speed must be divisible by the parallel clock.

[0161] Then, the phase modulation encoding 102 transports the encoding phases of the parallel channels output at the current counting moment to the serial transmission module 103. The digital encoding unit in the serial transmission module 103 splices the encoding phases of the most significant bits of 64 parallel channels to obtain a digital encoding.

[0162] Finally, based on the target gigabit transceiver and the digital encoding, a digital radio frequency signal is output.

[0163] Since the digital radio frequency signal is a square wave, it contains many high-frequency harmonics in addition to the carrier wave. Although in many cases, the harmonics do not affect the use, but if there are requirements for the harmonic power, it is necessary to use a filter for filtering. In the case of a large output frequency range, a single filtering circuit cannot meet the use requirements, so a radio frequency switchable filtering circuit can be added. At the same time, because the power of the digital radio frequency signal output by the serial transmission module is generally small and cannot meet the driving requirements of most radio frequency devices. Therefore, in this application, a radio frequency driving module 104 is configured after the serial transmission module 103.

[0164] The digital radio frequency signal output by the serial transmission module 103 enters the radio frequency driving module 104, where it is power-amplified and filtered to generate a target digital radio frequency signal.

[0165] Figure 3 This is a schematic diagram of the relationship between the frequency and power of a digital radio frequency signal provided by an embodiment of the present application. In the present application, Figure 3 The curve indicating the relationship between the power of the digital radio frequency signal and the frequency is called the output amplitude-frequency characteristic curve. Combining Figure 3 As shown, the peak power of the radio frequency signal output by GTX is approximately -3 dBm, and the power attenuation can be maintained within 3 dB in the range of 0 - 1 GHz, but the attenuation is relatively fast in the range of 1 - 5 GHz. If the output frequency point changes frequently and there are certain requirements for power, an equalizer can be used to make the radio frequency output by GTX relatively flat in the range of 0 - 1 GHz. The frequency points greater than 1 GHz can meet the power requirements after multiple stages of radio frequency amplification, and the power difference between different frequencies can be compensated by a voltage-controlled attenuator.

[0166] The digital radio frequency device disclosed in the foregoing embodiment includes a gigabit transceiver integrated on the FPGA, which has the advantages of low cost and strong stability; by changing the signal frequency of the gigabit transceiver, the output of the target digital radio frequency signal in the frequency range of 0 - 5 GHz can be achieved; up to 16 radio frequency signals can be output, which is sufficient to meet a large number of radio frequency requirements; the adjustment speed of the frequency and phase in the present application is extremely fast, the upper limit of the speed adjustment is the GTX system clock, and it can output continuously, which can provide a digital radio frequency source with low cost, wide frequency range, high power stability, high resolution and rapid response for the field of space cold atoms, etc. In the present application, while outputting the radio frequency signal, behavior modulation can also be performed to generate double sidebands, which can be used in the PDH frequency stabilization optical path (Pound-Drever-Hall laser frequency stabilization optical path), saving the use of radio frequency devices in the PDH frequency stabilization optical path.

[0167] Figure 4 This is a schematic diagram of the structure of a laser frequency stabilization device provided by an embodiment of the present application. Combining Figure 4 As shown, the laser frequency stabilization device in the present application includes: a laser 401, an electro-optic modulator 402, a frequency stabilization cavity 403, an error detection module 404, a servo control module 405, and a digital radio frequency module 406. Figure 4 The digital radio frequency module 406 in

[0168] Figure 4 is the digital radio frequency module disclosed in the foregoing embodiment.

[0169] The digital radio frequency module 406 is used to generate a demodulation signal and a digital radio frequency signal according to the target laser frequency shift; among them, the demodulation signal and the digital radio frequency signal are homologous signals.

[0170] An electro-optic modulator 402 is configured to receive a first laser signal output by a laser 401 and a digital radio frequency signal output by a digital radio frequency module 406, and generate a second laser signal. That is, the phase of the first laser signal output by the laser is modulated. According to Bessel functions, the modulated laser signal carries multiple sidebands, and the sideband distribution is related to the frequency of the digital radio frequency signal.

[0171] A frequency stabilization cavity 403 is configured to lock the laser wavelength to the characteristic cavity length of the cavity after receiving the second laser signal. That is, when the second laser signal passes through the frequency stabilization cavity 403, a third laser signal is output.

[0172] After the third laser signal is reflected by the cavity mirror, it is detected by a photodetector as cavity reflected light and converted into a detection signal.

[0173] An error detection module 404 receives the phase of the detection signal (essentially the third laser signal) and the demodulation signal output by the digital radio frequency module 406, and generates a digital error signal.

[0174] After receiving the digital error signal, a servo control module 405 generates a current modulation signal, and uses the current modulation signal to perform servo control on the laser 401, so that the error value corresponding to the redetected digital error signal is less than a set error threshold. The specific value of the error threshold is not limited in this application.

[0175] It can be understood that in addition to adopting a servo control mode, that is, using an analog-to-digital converter to collect the error signal, performing servo control operations on the collected error signal to obtain a feedback signal, scaling the feedback signal, and adjusting the frequency control of the frequency synthesis module to achieve digital radio frequency feedback; it is also possible to use a frequency sweep mode, that is, after setting the frequency sweep range, frequency sweep compensation, and frequency sweep interval on the host computer, the digital radio frequency outputs according to the set value, and through the servo control module 405, the synthesis of a single-frequency square wave is achieved, and then the phase is modulated.

[0176] Exemplarily, the expression of the first laser signal output by the laser 401 is shown in formula (4):

[0177] (4)

[0178] Where, E in formula (4) 10 is the optical intensity of the first laser signal, t is time, ω is the laser frequency of the first laser signal, E1(t) is the function of the first laser signal changing with time, and i is used to represent the imaginary part, so that a complex number can be expressed as the sum of the real part and the imaginary part.

[0179] The digital radio frequency signal output by the digital radio frequency module 406 itself has a double sideband; using the digital radio frequency signal with a double sideband to drive the electro-optic modulator 402 to perform phase modulation on the first laser signal can make the modulated laser signal, that is, the second laser signal, have a second-order sideband in the double sideband; among them, the first-order sideband is used for laser frequency shift, and the second-order sideband is used for PDH frequency stabilization.

[0180] The expression of the second laser signal after electro-optic modulation is shown in formula (5):

[0181] (5)

[0182] Among them, E2(t) in formula (5) is a function of the second laser signal changing with time, E 20 is the optical intensity of the second laser signal, Ω is the digital radio frequency carrier frequency and also the frequency corresponding to the first-order sideband, β is the modulation depth of the first-order sideband, γ is the digital radio frequency sideband frequency and also the frequency corresponding to the second-order sideband, δ is the modulation depth of the second-order sideband; the meanings of the remaining letters refer to the description in formula (4) and will not be elaborated here.

[0183] Figure 5 is a schematic diagram of the frequency distribution of a second laser signal provided by an embodiment of the present application. As shown in combination Figure 5 , the frequency of the first laser signal before entering the electro-optic modulator is ω, the carrier frequency of the digital radio frequency signal is Ω, the phase modulation frequency is γ, and the frequencies included in the digital radio frequency signal are Ω - γ, Ω, Ω + γ; the main frequency components of the second laser signal after passing through the electro-optic modulator are: ω - Ω - γ, ω - Ω, ω - Ω + γ, ω, ω + Ω - γ, ω + Ω, ω + Ω + γ.

[0184] Among them, ω - Ω and ω + Ω are related to the carrier frequency of the digital radio frequency signal in the first-order sideband, and ω - Ω - γ, ω - Ω + γ, ω + Ω - γ, ω + Ω + γ are related to the sidebands of the digital radio frequency signal in the second-order sideband. In the present application, the frequency components of ω - Ω or ω + Ω are locked to the frequency stabilization cavity, so as to realize laser frequency shift, and the corresponding second-order sidebands can replace the sideband modulation in the conventional PDH frequency stabilization.

[0185] In an optional implementation manner, the error detection module 404 in the present application includes:

[0186] A detection signal acquisition unit, configured to detect and process the third laser signal through an analog-to-digital converter and a photodetector to obtain a detection signal;

[0187] An error signal generation unit is configured to perform mixing and filtering operations on the digital code value of the detection signal and the digital code value corresponding to the phase of the demodulation signal to obtain a digital error signal; the digital code value corresponding to the phase of the demodulation signal is determined based on the phase of the demodulation signal and a preset second look-up table; the second look-up table is used to indicate the correspondence between the phase and the digital code value.

[0188] It should be noted that in the process of determining the digital code value corresponding to the phase of the demodulation signal based on the phase of the demodulation signal and the preset second look-up table, a multiplication operation is also required to scale the digital code value. The multiplication operation combines binary multiplication with binary shift (shifting one bit to the right is equivalent to dividing by 2), so that decimal multiplication can be achieved. The calculation process of the modulation depth disclosed in the foregoing embodiments of the present application also uses the multiplication operation.

[0189] The digital radio frequency output by the serial transmission module 103 of the present application has a double sideband, and this double sideband is equivalent to the double sideband generated by modulation in the laser frequency stabilization optical path. Therefore, the demodulation signal and the phase modulation signal of the digital radio frequency signal should be homologous signals.

[0190] Conventionally used mixers and low-pass filters are all analog devices, and the demodulation signal needs to be output separately. The digital radio frequency device used in the present invention can directly generate a homologous digital demodulation signal within the FPGA.

[0191] In the present application, the third laser signal is detected and processed through an analog-to-digital converter and a photodetector to generate a detection signal; the detection signal generated by the photodetector is collected by a high-speed analog-to-digital converter; then, a digital mixer and a digital low-pass filter are used to perform mixing and filtering operations on the digital code value of the detection signal and the digital code value corresponding to the phase of the demodulation signal to obtain a digital error signal.

[0192] Among them, the digital code value corresponding to the phase of the demodulation signal is determined based on the phase of the demodulation signal and a preset second look-up table; the second look-up table is used to indicate the correspondence between the phase and the digital code value.

[0193] Among them, the digital mixer is implemented using a multiplier, and the multiplier can directly call the IP core of the FPGA.

[0194] The digital low-pass filter can be implemented using a capacitive digital integrator, and the expression of the capacitive digital integrator is shown in formula (6):

[0195] y(n) = y(n - 1) + a×in (n); a = 2π×F P ÷F S (6)

[0196] Among them, y(n) represents the output of the integrator at discrete time n; y(n - 1) represents the output of the integrator at the previous discrete time n - 1; in(n) represents the input signal at discrete time n; a is the integration coefficient, F S is the sampling rate, F P is the pole frequency.

[0197] In an alternative implementation, the servo control module in the present application is specifically configured to: perform servo control on the laser according to the digital error signal, digital lead-lag, and digital proportional-integral-derivative regulator, so that the error value corresponding to the redetected digital error signal is less than the set error threshold.

[0198] The error detection module in the present application is a digital module and outputs a digital signal; the servo control module is also a digital module. The servo control module in the present application includes a digital lead-lag and a digital proportional-integral-derivative controller (digital PID, Proportional-Integral-Derivative). The digital PID includes the fast feedback and slow feedback required for laser frequency stabilization; the digital lead-lag provides bandwidth modulation for the fast feedback of the laser, reduces the high-frequency gain, and increases the phase margin.

[0199] In an alternative implementation, the digital lead-lag in the present application is of the third order, and 3 pairs of pole-zero points can be added. Among them, when the system input amplitude is non-zero and the input frequency makes the system output zero, this input frequency value is the zero point, and the influence of the zero point on the frequency response curve is lead. When the system input amplitude is non-zero and the input frequency makes the system output infinite (the system stability is damaged and oscillation occurs), this frequency value is the pole, and the influence of the pole on the frequency response curve is lag.

[0200] At each pole, the gain decays by -3dB and the phase shifts by -45 degrees. After each pole, for every tenfold frequency increase, the gain drops by 20dB. The zero point is the opposite of the pole; at each zero point, the gain increases by 3dB and the phase shifts by 45 degrees. After the zero point, for every tenfold frequency increase, the gain increases by 20dB.

[0201] In the digital lead-lag, the operation of adding a pole is digital integration, and the operation of adding a zero point is digital differentiation.

[0202] The pole operation formula is the same as the expression of the capacitive digital integrator, which will not be elaborated here.

[0203] The zero point operation is as shown in formula (7):

[0204] y(m) = (b + 1)×in(m) - b×in(m - 1); b = F S ÷(2π×F Z )(7)

[0205] Among them, y(m) represents the output of the differentiator at discrete time m; b is the differentiation coefficient, F S is the sampling rate, F Z is the zero-frequency, in(m) represents the input signal at discrete time m; in(m - 1) represents the input signal at discrete time m - 1.

[0206] Figure 6 This is a schematic diagram of a third-order lead-lag frequency response curve provided by an embodiment of the present application. Figure 6 (a) is a schematic diagram indicating the change of amplitude with frequency, briefly called the schematic diagram of "amplitude-frequency response"; Figure 6 (b) is a schematic diagram indicating the change of phase with frequency, briefly called the schematic diagram of "phase-frequency response". In the present application, in order to prevent the situation of excessive high-frequency gain but insufficient phase margin leading to loop oscillation while improving the high-frequency phase, a third-order digital lead-lag is introduced into the servo control module to achieve Figure 6 (a) and Figure 6 (b) effects. As Figure 6 shown, let the gain first decay at the middle two frequency points and then increase at high frequencies; the phase change is not obvious at low frequencies, and the phase change due to integration is within an acceptable range. The phase and gain at medium frequencies are both worse, but the phase and gain at high frequencies are both better.

[0207] It should be noted that the pole-zero positions used in the actual working process are determined according to the loop parameters. One of the advantages of digital lead-lag is that both the pole-zero positions and the pole-zero orders can be adjusted according to the actual usage. Figure 6 It is mainly to illustrate the influence of pole-zero on the loop bandwidth.

[0208] The above is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A digital radio frequency device based on a gigabit transceiver, characterized in that, The device includes: An encoding phase module, configured to generate an initial encoding phase based on the clock signal frequency of a gigabit transceiver, the number of preset parallel channels, and a target laser frequency shift; A phase modulation module, configured to perform phase modulation on the initial encoding phase to generate an encoding phase and a demodulation signal; the encoding phase has a double sideband; the demodulation signal is a signal having the same frequency as that of a target sideband; the target sideband is one of the sidebands in the double sideband; A serial transmission module, configured to generate a digital radio frequency signal based on the encoding phase and the gigabit transceiver; A radio frequency driving module, configured to perform power amplification and filtering on the digital radio frequency signal to generate a target digital radio frequency signal.

2. The device according to claim 1, characterized in that The encoding phase module includes: A first accumulation step determination sub-module, configured to determine a serial phase accumulation step according to the clock signal frequency of the gigabit transceiver and the target laser frequency shift; A second accumulation step determination sub-module, configured to determine a parallel phase accumulation step based on the serial phase accumulation step and the number of parallel channels; A basic phase determination sub-module, configured to determine the basic phase corresponding to the parallel channel at the current counting moment based on the basic phase corresponding to the parallel channel at the previous counting moment and the parallel phase accumulation step; each parallel channel has the same basic phase at the same counting moment; An encoding phase determination sub-module, configured to, for each parallel channel, determine the initial encoding phase of the parallel channel at the current counting moment based on the basic phase of the parallel channel at the current counting moment, the channel encoding of the parallel channel, and the serial phase accumulation step; the channel encoding is a preset digital encoding for indicating the arrangement order of the corresponding parallel channel among multiple parallel channels.

3. The device according to claim 2, wherein, The first accumulation step determination sub-module includes: A time step determination unit, configured to determine a time step based on the clock signal frequency of the gigabit transceiver; A serial phase accumulation step determination unit, configured to determine the serial phase accumulation step based on the time step, the target laser frequency shift, and a full phase range.

4. The device according to claim 2, characterized in that, The phase modulation module includes: A parameter setting sub-module, configured to set the initial phase corresponding to the digital radio frequency signal as a first initial phase; A function setting sub-module, configured to set a phase modulation depth, a phase modulation signal frequency, and a second initial phase to obtain a phase modulation function; A phase modulation sub-module, configured to perform phase modulation on the initial encoding phase based on the phase modulation function and the first initial phase to generate the encoding phase and the demodulation signal.

5. The device according to claim 4, characterized in that, The function setting sub-module includes: A target address determination unit, configured to determine a target address based on the second initial phase and the phase corresponding to the gigabit transceiver; the phase corresponding to the gigabit transceiver is the product of the phase modulation signal frequency and time; A target amplitude determination unit, configured to determine a target amplitude based on the target address and a preset first look-up table; the first look-up table indicates the correspondence between the address and the amplitude of a sine wave. A sine wave determination unit for determining a sine wave function as the phase modulation function based on the phase modulation depth, the phase modulation signal frequency, the second initial phase, the phase corresponding to the gigabit transceiver, and the target amplitude.

6. The device according to claim 4, characterized in that The function setting sub-module includes: A triangular wave function setting unit for determining a triangular wave function as the phase modulation function based on the phase corresponding to the gigabit transceiver and a preset triangular wave formula; the phase corresponding to the gigabit transceiver is the product of the phase modulation signal frequency and time.

7. The device according to claim 4, characterized in that, The phase modulation sub-module includes: A modulation base phase determination unit for determining the modulation base phase corresponding to the parallel channel at the current counting moment based on the modulation base phase corresponding to the parallel channel at the previous counting moment and the parallel phase accumulation step; each parallel channel has the same modulation base phase at the same counting moment; An encoded modulation phase determination unit for, for each parallel channel, determining the encoded modulation phase corresponding to the parallel channel at the current counting moment based on the modulation base phase corresponding to the parallel channel at the current counting moment, the channel encoding of the parallel channel, the serial phase accumulation step, the phase modulation function, and the first initial phase; An encoded phase determination unit for, for each parallel channel, determining the encoded phase corresponding to the parallel channel at the current counting moment based on the initial encoded phase corresponding to the parallel channel at the current counting moment and the encoded modulation phase corresponding to the parallel channel at the current counting moment.

8. The device according to claim 2, characterized in that, The serial transmission module includes: A preprocessing module for performing a parameter zeroing operation on the gigabit transceiver to obtain a target gigabit transceiver; the parameter zeroing operation is used to clear the pre-stored protocols and parameters in the gigabit transceiver; A digital encoding unit for splicing the encoded phases of the highest bits of multiple parallel channels to obtain the digital encoding; A digital radio frequency transmission unit for generating the digital radio frequency signal based on the target gigabit transceiver and the digital encoding.

9. A laser frequency stabilization device, characterized in that, The device includes: a laser, a digital radio frequency module, an electro-optic modulator, a frequency stabilization cavity, an error detection module, and a servo control module; The laser for outputting a first laser signal; The digital radio frequency module for generating the phase of the demodulation signal and the digital radio frequency signal according to the target laser frequency shift; the demodulation signal and the digital radio frequency signal are homologous signals; the digital radio frequency module is the device according to any one of claims 1-8; The electro-optic modulator for generating a second laser signal according to the first laser signal and the digital radio frequency signal; The frequency stabilization cavity for outputting a third laser signal according to the second laser signal; The error detection module for generating a digital error signal based on the phase of the third laser signal and the demodulation signal; The servo control module for performing servo control on the laser according to the digital error signal so that the error value corresponding to the redetected digital error signal is less than a set error threshold.

10. The device according to claim 9, characterized in that, The error detection module includes: A detection signal acquisition unit, configured to detect and process the third laser signal through an analog-to-digital converter and a photodetector to obtain a detection signal; An error signal generation unit, configured to perform mixing and filtering operations on the digital code value of the detection signal and the digital code value corresponding to the phase of the demodulation signal to obtain the digital error signal; the digital code value corresponding to the phase of the demodulation signal is determined based on the phase of the demodulation signal and a preset second look-up table; the second look-up table is used to indicate the correspondence between the phase and the digital code value.

11. The device according to claim 9, characterized in that, The servo control module is specifically configured to: Perform servo control on the laser according to the digital error signal, the digital lead-lag, and the digital proportional-integral-derivative regulator, so that the error value corresponding to the redetected digital error signal is less than a set error threshold.

Images