Method and device for recovering clock data and equalization system

Abstract

The invention discloses a method and a device for recovering clock data and an equalization system. The method comprises the following steps: extracting a first tap coefficient value of a first equalizer and a second tap coefficient value of a second equalizer based on a current working clock; determining a phase state of the current working clock according to a comparison result between the first tap coefficient value and the second tap coefficient value; if the phase state represents phase advance or phase delay, calculating a coefficient difference value between the first tap coefficient value and the second tap coefficient value; and adjusting the clock phase of the current working clock according to the phase state and the coefficient difference value so as to output the working clock with the clock phase opposite to the phase state. According to the invention, data recovery performance and resource consumption can be effectively balanced.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and in particular to a method and device for recovering clock data, and an equalization system. Background Art

[0002] In communication systems, a phase-locked loop is a key circuit component that is used to lock the clock component in the received signal and adjust the local clock to match the clock of the data stream through a feedback mechanism, thereby ensuring accurate reception and processing of the signal. A phase-locked loop (PLL) usually includes a phase detector, a loop filter, and a voltage-controlled oscillator (VCO).

[0003] As the core part of the clock data recovery (CDR) method, PLL can handle jitter and clock drift during signal transmission to ensure that the receiving end can accurately recover the data. However, the oversampling scheme in the clock data recovery method usually consumes more clock power.

[0004] Some clock data recovery methods directly use the center position of the sampling point where the first front cursor coefficient and the first rear cursor coefficient of the equalizer in the communication system are located as the sampling point of CDR to reduce resource consumption. The communication system usually includes a forward feedback equalizer (FFE) and a decision feedback equalizer (DFE). FFE is used to eliminate forward interference, and DFE is used to eliminate backward interference. Combining these two equalizers can eliminate the inter-symbol interference generated by the channel. Since the decision feedback equalizer belongs to the feedback circuit, the design of the CDR solution based on the phase-locked loop is complex. In terms of hardware resources, it requires a precise phase detector and voltage-controlled oscillator. In terms of software resources, the phase interpolation CDR solution requires a large amount of logic resources and complex algorithm processing, and the oversampling CDR solution needs to process more data in the digital domain. Summary of the invention

[0005] The present invention provides a method and device for recovering clock data, and an equalization system, which can effectively balance data recovery performance and resource consumption.

[0006] In one aspect of the present invention, a method for recovering clock data is provided. The method comprises: extracting a first tap coefficient value of a first equalizer and a second tap coefficient value of a second equalizer based on a current working clock; determining a phase state of the current working clock according to a comparison result between the first tap coefficient value and the second tap coefficient value; if the phase state indicates a phase advance or a phase delay, calculating a coefficient difference between the first tap coefficient value and the second tap coefficient value; and adjusting a clock phase of the current working clock according to the phase state and the coefficient difference to output a working clock having a clock phase relative to the phase state.

[0007] In another aspect of the present invention, a device for recovering clock data is provided. The device includes: an extraction module configured to extract a first tap coefficient value of a first equalizer and a second tap coefficient value of a second equalizer based on a current working clock; a calculation module configured to determine the phase state of the current working clock according to a comparison result between the first tap coefficient value and the second tap coefficient value, and if the phase state indicates a phase advance or phase delay, calculate the coefficient difference between the first tap coefficient value and the second tap coefficient value; and an adjustment module configured to adjust the clock phase of the current working clock according to the phase state and the coefficient difference, so as to output a working clock having a clock phase relative to the phase state.

[0008] In another aspect of the present invention, an equalization system is provided, which includes: the above-mentioned device for recovering clock data, and a first equalizer and a second equalizer electrically coupled to the device.

[0009] According to the technical solution of the present invention, the tap coefficient values ​​of the first equalizer and the second equalizer are respectively extracted according to the current working clock, that is, the tap coefficients of the first equalizer and the second equalizer are sampled based on the current working clock, so that the clock phase change is characterized by the tap coefficient values ​​of the two equalizers. The phase state of the current working clock is determined according to the comparison result of the two tap coefficient values, and the clock phase change amount is determined according to the coefficient difference between the two tap coefficients, so as to adjust the clock phase according to the phase state of the current clock and the clock phase change amount, and realize clock data recovery. Compared with the method of realizing clock data recovery through phase difference, the present invention characterizes the clock phase change based on the tap coefficient of the equalizer, thereby completing the clock phase adjustment, and realizes the clock data recovery function based on the oversampling method, while effectively simplifying the processing logic of the clock data, reducing the complexity of the clock recovery algorithm, and effectively balancing the data recovery performance and resource consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A flowchart of a method for recovering clock data according to an embodiment of the present invention; Figure 2 It is a waveform change diagram of a digital signal after it propagates through a line; Figure 3 A flowchart of a method for adjusting a clock phase according to an embodiment of the present invention; Figure 4 Schematic diagram of waveforms of different clock phases according to an embodiment of the present invention Figure 5 A waveform diagram of a digital signal after being transmitted through different line lengths according to an embodiment of the present invention; Figure 6 A block diagram of a device for recovering clock data according to an embodiment of the present invention; Figure 7 A schematic diagram of an implementation scheme of an adjustment module according to an embodiment of the present invention; Figure 8 FIG. 4 is an architecture diagram of a balancing system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0011] In order to explain the technical content, achieved objectives and effects of the present invention in detail, the following is an explanation in combination with the implementation modes and the accompanying drawings.

[0012] In the prior art, some clock data recovery methods directly use the center position of the sampling point where the first front cursor coefficient and the first rear cursor coefficient of the equalizer in the communication system are located as the sampling point of CDR to reduce resource consumption. The communication system usually includes a forward feedback equalizer (FFE) and a decision feedback equalizer (DFE). FFE is used to eliminate forward interference, and DFE is used to eliminate backward interference. Combining these two equalizers can eliminate the inter-symbol interference generated by the channel. Since the decision feedback equalizer belongs to the feedback circuit, the design of the CDR solution based on the phase-locked loop is complex. In terms of hardware resources, a precise phase detector and voltage-controlled oscillator are required. In terms of software resources, the phase interpolation CDR solution requires a large amount of logic resources and complex algorithm processing, and the oversampling CDR solution needs to process more data in the digital domain.

[0013] In order to solve at least the above technical problems, the present disclosure provides a method for recovering clock data. According to the present disclosure, the tap coefficient values ​​of the first equalizer and the second equalizer are respectively extracted according to the current working clock, that is, the tap coefficients of the first equalizer and the second equalizer are sampled based on the current working clock, so as to characterize the clock phase change by comparing the two tap coefficient values. The phase state of the current working clock is determined according to the tap coefficient values ​​of the two equalizers, and the clock phase change amount is determined according to the coefficient difference between the two tap coefficients, so as to adjust the clock phase according to the phase state of the current clock and the clock phase change amount, and realize clock data recovery. In this way, compared with the method of realizing clock data recovery by phase difference, according to the embodiment of the present disclosure, the clock phase change is characterized based on the tap coefficient of the equalizer, so as to complete the clock phase adjustment, and the clock data recovery function is realized based on the oversampling method, while effectively simplifying the processing logic of the clock data, reducing the complexity of the clock recovery algorithm, and effectively balancing the data recovery performance and resource consumption.

[0014] The tap coefficient is the weight value corresponding to each tap (filter) in the equalizer. The tap coefficient is generally obtained by the equalizer through adaptive iterative update based on the digital signal, which determines how the equalizer processes the digital signal to eliminate inter-symbol interference. The forward feedback equalizer is used to eliminate the forward interference of the signal, and the decision feedback equalizer is used to eliminate the backward interference of the signal. According to an embodiment of the present disclosure, the first equalizer is a forward feedback equalizer, and the second equalizer is a decision feedback equalizer. The current clock phase state can be determined by comparing the tap coefficients of the first equalizer and the second equalizer, and clocks of different phases are selected as the working clock according to the current clock phase state to achieve switching of clock data.

[0015] Hereinafter, the technical solution according to the present disclosure will be described with reference to specific embodiments and in conjunction with the accompanying drawings.

[0016] Figure 1 1 is a flow chart showing a method 100 for recovering clock data according to an embodiment of the present disclosure. Figure 1 The method 100 includes the following steps 102 to 108.

[0017] In step 102, a first tap coefficient value of a first equalizer and a second tap coefficient value of a second equalizer based on a current operating clock are extracted.

[0018] In some embodiments, the first tap coefficient value extracted under the current working clock is the same as the working level to which the second tap coefficient value belongs. For example, the first-level tap coefficient value of the first equalizer and the first-level tap coefficient value of the second equalizer are extracted under the current working clock. It should be noted that the tap coefficient of the equalizer can be a positive number or a negative number, and the tap coefficient value described in the present invention refers to the absolute value of the tap coefficient.

[0019] In step 104, the phase state of the current working clock is determined according to a comparison result between the first tap coefficient value and the second tap coefficient value.

[0020] In some embodiments, the first equalizer is used to eliminate the forward interference of the target signal, and the second equalizer is used to eliminate the backward interference of the target signal. In this embodiment, determining the phase state of the current working clock according to the comparison result between the first tap coefficient value and the second tap coefficient value includes: if the first tap coefficient value is less than the second tap coefficient value, then determining the phase state of the current working clock is phase advance, and if the first tap coefficient value is greater than the second tap coefficient value, then determining the phase state of the current working clock is phase delay. In this way, ideally, the signal position of the working clock is accurately sampled at the highest point in the center of the signal, and the tap coefficients of the two equalizers should be in a consistent state. When the phase state is offset, there is a difference between the tap coefficients of the two equalizers. Thus, the phase state of the current working clock can be determined according to the tap coefficient.

[0021] Figure 2 This is a diagram showing the waveform change of a digital signal after it propagates through a line. The digital signal before propagating through the line is a square wave, and the digital signal after propagating through the line is a curve wave. Figure 2 , the waveform with the center position forward is the forward tail, that is, the forward interference, and the waveform with the center position backward is the backward tail, that is, the backward interference. Figure 2 In (a), when the clock phase of the receiving end matches the clock phase of the transmitting end, the clock phase in the receiving end can be accurately sampled to the center position (the highest point). At this time, the tap coefficient F1 sampled by the forward feedback equalizer should be consistent with the tap coefficient D1 of the decision feedback equalizer. Figure 2 In (b), when the clock phase of the receiving end is advanced, the sampling point is located to the left of the center position. At this time, the tap coefficient F1 obtained by the forward feedback equalizer is smaller than the tap coefficient D1 of the decision feedback equalizer. Figure 2 In (c), when the clock phase of the receiving end is delayed, the sampling point is located to the right of the center position. At this time, the tap coefficient F1 obtained by sampling the forward feedback equalizer is greater than the tap coefficient D1 of the decision feedback equalizer. Therefore, by comparing the tap coefficients of the two equalizers, it can be determined whether the current clock phase is advanced or delayed.

[0022] In step 106, if the phase state indicates phase advance or phase delay, a coefficient difference between the first tap coefficient value and the second tap coefficient value is calculated.

[0023] In some embodiments, the coefficient difference between the two tap coefficients is calculated with the first tap coefficient value as the minuend and the second tap coefficient value as the subtrahend, that is, the coefficient difference S=the first tap coefficient value F-the second tap coefficient value D.

[0024] In step 108, the clock phase of the current working clock is adjusted according to the phase state and the coefficient difference, so as to output a working clock having a clock phase opposite to the phase state.

[0025] In some embodiments, if the phase state is phase advance, a working clock having a clock phase delayed by one unit is output according to the coefficient difference. If the phase state is phase delay, a working clock having a clock phase advanced by one unit is output according to the coefficient difference. In this way, when the phase state is advanced, the clock phase is delayed by one unit, so that the sampling point of the working clock moves to the left, thereby approaching the highest point of the signal. When the phase state is delayed, the clock phase is advanced by one unit, so that the sampling point of the working clock moves to the right, thereby approaching the highest point of the signal. The adjustment process of the working clock does not require phase interpolation processing, which effectively reduces the complexity of the clock data recovery algorithm.

[0026] Figure 3 2 is a flow chart showing a method 200 for adjusting a clock phase according to an embodiment of the present disclosure. Figure 3 , since the tap coefficient values ​​of the first equalizer and the second equalizer are updated and changed in real time according to the digital signal, there is a certain error in the updating process. If the clock phase is adjusted according to the real-time change of the two tap coefficient values, the update error of the tap coefficient value will be introduced into the clock phase, resulting in an adjustment error of the clock phase. Therefore, the present invention accumulates the real-time change of the tap coefficient value in each extraction cycle, and the clock phase is switched only when the accumulated result is greater than or less than the switching threshold.

[0027] In some embodiments, based on the comparison result between the accumulated value of the coefficient difference in a set period and the phase switching threshold, the next working clock is selected from multiple working clocks with different clock phases until the comparison result between the first tap coefficient value and the second tap coefficient value meets a predetermined condition.

[0028] In some embodiments, outputting a working clock having a clock phase delayed by one unit according to the coefficient difference includes: calculating a first cumulative result of all coefficient differences whose phase state is phase advance including the current extraction cycle according to a preset cumulative weight, and controlling whether the clock phase of the current working clock is delayed by one unit of clock phase according to the first cumulative result. In this way, the cumulative weight is used to control the speed at which the current working clock performs clock phase adjustment. When the cumulative weight is large, the growth rate of the first cumulative result is faster, so that the first cumulative result can reach the critical point of phase adjustment faster. When the cumulative weight is small, the growth rate of the first cumulative result is slow, so that the first cumulative result slowly reaches the critical point of phase adjustment. Compared with the timing adjustment of clock data, the present invention can effectively control the accuracy and stability of clock adjustment through cumulative weights.

[0029] In a specific scenario, the first accumulated result calculated in the last extraction cycle is S1[n-1], and the preset accumulated weight is α. If the first tap coefficient value and the second tap coefficient value sampled in the current extraction cycle are F n and D n , then the coefficient difference S1 of the current extraction cycle n =F n -D n , the first accumulated result of the current extraction cycle S1[n]=α×S1[n-1]+S1 n Since the coefficient differences under the advanced phase are all negative values, the first accumulation result S1 is calculated based on the coefficient differences of the advanced phase, and therefore, the first accumulation result is a negative value.

[0030] In some embodiments, controlling whether the clock phase of the current working clock is delayed by one unit of the clock phase according to the first accumulated result includes: detecting whether the first accumulated result is greater than the first phase switching threshold; if so, switching the clock phase of the current working clock to a working clock having a first clock phase delayed by one unit; otherwise, returning to execute the extraction of the first tap coefficient value of the first equalizer and the second tap coefficient value of the second equalizer based on the current working clock. In this way, the clock phase is adjusted only when the offset value of the clock phase is greater than the first phase switching threshold, and the switching frequency of the clock phase can be effectively controlled by the first phase switching threshold. When adjusting the clock phase, the clock phase is directly switched to the first clock phase delayed by one unit to avoid adjusting the clock phase by phase interpolation and other methods, thereby effectively simplifying the clock data recovery algorithm.

[0031] In a specific scenario, if the first accumulated result is a negative value, it is detected whether the absolute value of the first accumulated result is greater than the first phase switching threshold. The first phase switching threshold is 0.5. Since the coefficient difference of each extraction cycle is accumulated and calculated based on the accumulated weight, the absolute value of the first accumulated result S1 will be greater than the first phase switching threshold in a certain extraction cycle, and the clock phase will be adjusted forward by one unit from the current clock phase.

[0032] In some embodiments, outputting a working clock with a clock phase advanced by one unit according to the coefficient difference includes: calculating a second cumulative result of all coefficient differences whose phase state is phase delay including the current extraction cycle according to a preset cumulative weight, and controlling whether the clock phase of the current working clock is advanced by one unit of clock phase according to the second cumulative result. In this way, the coefficient difference is cumulatively counted for the phase offset under different clock phases, so that the clock phase is adjusted for different phase states according to different cumulative results.

[0033] In a specific scenario, the second accumulated result calculated in the last extraction cycle is S2[n-1], and the preset accumulated weight is α. If the first tap coefficient value and the second tap coefficient value sampled in the current extraction cycle are F n and D n , then the coefficient difference S2 of the current extraction cycle n =F n -D n , the second accumulated result S2[n]=α×S2[n-1]+S2 n Since the coefficient differences under the advanced phase are all positive values, the second accumulation result S1 is calculated based on the coefficient differences of the advanced phase, and therefore, the second accumulation result is a positive value.

[0034] In some embodiments, controlling whether the clock phase of the current working clock is advanced by one unit of the clock phase according to the second accumulated result includes: detecting whether the second accumulated result is greater than the second phase switching threshold; if so, switching the clock phase of the current working clock to a working clock with a second clock phase advanced by one unit; otherwise, returning to perform the extraction of the first tap coefficient value of the first equalizer and the second tap coefficient value of the second equalizer based on the current working clock. In this way, when the phase switching threshold is smaller, the accumulated result of the coefficient difference reaches the phase switching threshold faster, thereby speeding up the clock phase adjustment speed. When the phase switching threshold is larger, the accumulated result of the coefficient difference reaches the phase switching threshold slower, thereby ensuring the stability of the clock phase. Therefore, the phase switching threshold needs to be set to an appropriate value, while ensuring the dynamic switching of the clock phase, ensuring the stability of the clock phase adjustment, and avoiding frequent switching of the clock phase. When adjusting the clock phase, directly switch the clock phase to the second clock phase advanced by one unit to avoid adjusting the clock phase by phase interpolation and other methods, effectively simplifying the clock data recovery algorithm.

[0035] In a specific scenario, the second phase switching threshold is 0.5. Since the coefficient difference of each extraction cycle is accumulated based on the accumulated weight, the second accumulated result S2 will be greater than the second phase switching threshold in a certain extraction cycle, and the clock phase will be adjusted backward by one unit from the current clock phase.

[0036] The phase switching threshold is determined according to specific usage requirements. For example, during the debugging process, it is expected that the clock phase is adjusted once at the 4096th cycle. The accumulated result S[n] at 4096 cycles is collected and used as a reference value so that the clock phase can be adjusted in time after the 4096 cycles are offset. In other words, the determination of the phase switching threshold needs to be set according to the clock frequency and clock quality. If the speed of clock adjustment needs to be accelerated, the phase switching threshold needs to be set smaller.

[0037] The accumulation weight used to calculate the first accumulation result and the second accumulation result is the same. When the phase switching threshold is determined, the switching speed of the clock phase can be effectively adjusted by adjusting the accumulation weight. The accumulation weight should be much smaller than 1. In some embodiments, if the clock phase jitter is severe, the accumulation weight can be set to 10. -6 , which is convenient for timely adjustment of the clock phase; if the clock phase is stable, the cumulative weight can be set to 10 -8 , ensuring the accuracy of the clock phase.

[0038] Figure 4 is a waveform diagram showing different clock phases according to an embodiment of the present disclosure. Figure 4, if the first clock phase is taken as the standard clock phase, the second to eighth clock phases are delayed by 1 / 8 of the standard clock phase respectively. In a specific scenario, if the clock phase of the current extraction cycle is the fourth clock phase and is in the phase advance state, the current clock phase is adjusted backward by one unit, that is, the fifth clock phase is output. If the clock phase of the current extraction cycle is the fourth clock phase and is in the phase delay state, the current clock phase is adjusted forward by one unit, that is, the third clock phase is output. Among them, the smaller the unit phase difference between each clock phase, that is, the finer the clock phase division, the more accurate the clock phase adjustment and the more accurate the sampling result, but the resources consumed are greater.

[0039] In some embodiments, adjusting the clock phase of the current working clock according to the phase state and the coefficient difference includes: obtaining a preset phase compensation amount, and compensating the coefficient difference according to the phase compensation amount, so as to adjust the clock phase according to the compensated coefficient difference. In this way, since the signal is attenuated after line transmission, there is a difference between the forward interference and the backward interference. Usually, the backward interference is more serious than the forward interference, that is, the first tap coefficient value is not necessarily completely equal to the second tap coefficient value. Therefore, the relative change of the clock phase cannot be accurately evaluated by relying solely on the coefficient difference. It is necessary to compensate for the backward interference through the phase compensation amount to eliminate the error of the coefficient caused by the difference in the degree of interference, so that the evaluation of the relative change of the clock phase is more accurate.

[0040] In a specific scenario, the preset phase compensation amount is Vcomp. The compensation process for the coefficient difference according to the phase compensation amount is as follows: the compensated coefficient difference S n ' = coefficient difference before compensation S n + Phase compensation amount Vcomp, that is, the coefficient difference after compensation S n =F n -D n +Vcomp, the accumulated result S[n]=α×S[n-1]+S n '.

[0041] In some embodiments, the method may further include: obtaining the attenuated signal amplitude of the target signal, predicting the line length used to transmit the target signal according to the attenuated signal amplitude, determining the attenuated waveform of the target signal according to the line length, determining the difference data between the forward interference and the backward interference according to the attenuated waveform, and setting the phase compensation amount according to the difference data. In this way, the transmission line length can be estimated by the attenuated signal amplitude, the signal waveform can be inferred by the line length, and the severity of the forward interference and backward interference can be calculated by the waveform, thereby determining the difference between the two interferences, and then determining the phase compensation amount. Among them, the longer the line length, the greater the interference difference, and the greater the phase compensation value.

[0042] In some embodiments, if the first equalizer and the second equalizer are fixedly operated in a specific circuit, the compensation value may be set to a fixed value corresponding to the specific circuit.

[0043] Figure 5 It is a waveform diagram showing the digital signal after being transmitted through different line lengths. Figure 5 , Figure 5 (a) is the waveform of the digital signal after being transmitted through a shorter line length. Figure 5 (b) is the waveform of the digital signal after it is transmitted through a moderate line length. Figure 5 (c) in the figure is the waveform of the digital signal after being transmitted over a longer line length. In the figure, the horizontal axis represents the signal period, the vertical axis represents the signal amplitude, and the black dots represent the first tap coefficient and the second tap coefficient when the clock phase is sampled at the center position (highest point). It can be seen that the longer the line length, the greater the difference between the first tap coefficient F and the second tap coefficient D, that is, the greater the difference in forward and backward interference, so the longer the line length, the greater the corresponding phase compensation amount.

[0044] According to another aspect of the present invention, Figure 6 is a block diagram showing an apparatus 300 for recovering clock data according to an embodiment of the present invention. Figure 6 The device 300 includes an extraction module 302 , a calculation module 304 and an adjustment module 306 .

[0045] The extraction module 302 is configured to extract a first tap coefficient value of the first equalizer and a second tap coefficient value of the second equalizer based on a current working clock.

[0046] The calculation module 304 is configured to determine the phase state of the current working clock based on the comparison result between the first tap coefficient value and the second tap coefficient value, and if the phase state indicates phase advance or phase delay, then calculate the coefficient difference between the first tap coefficient value and the second tap coefficient value.

[0047] The adjustment module 306 is configured to adjust the clock phase of the current working clock according to the phase state and the coefficient difference, so as to output a working clock having a clock phase opposite to the phase state.

[0048] It should be understood that the calculation module 304 and the adjustment module 306 may be further configured to respectively execute the corresponding steps or actions in the method described in the above embodiments, which will not be described in detail herein.

[0049] Figure 72 is a schematic diagram showing a scheme for recovering clock data by the adjustment module 306 according to an embodiment of the present invention. Figure 7 The adjustment module 306 selects a phase clock from the first phase clock to the Nth phase clock as the adjusted phase clock according to the dynamic clock correction signal used to adjust the clock phase.

[0050] According to yet another aspect of the present invention, Figure 8 4 is a diagram showing an architecture of a balancing system 400 according to an embodiment of the present invention. Figure 8 The system 400 includes a first equalizer 402, a second equalizer 403, and the above-mentioned device 300 for recovering clock data. The first equalizer 402 and the second equalizer 404 are both electrically coupled to the device 300.

[0051] In some embodiments, the system 400 further includes an analog-to-digital converter 406 and a decision device 408. The analog-to-digital converter 406 is used to convert the analog signal transmitted by the line into a digital signal to obtain the target signal. The decision device 408 is used to cooperate with the first equalizer 402 and the second equalizer 406 to continuously adjust the filtering characteristics of the equalizer to ensure that the received signal can be accurately restored to the original digital signal.

[0052] In summary, the present invention provides a method and device for recovering clock data, and an equalization system. The tap coefficients of the first equalizer and the second equalizer are sampled based on the current working clock. When the coefficient difference between the two tap coefficient values ​​is not 0, it indicates that the current clock phase is offset. At the same time, the offset state and offset degree of the clock phase can be determined based on the size relationship between the two tap coefficient values. If the offset state is advanced, the clock phase is delayed after a certain period of offset; if the offset state is delayed, the clock phase is advanced after a certain period of offset. Thus, the clock data is recovered regularly. Compared with the method of realizing clock data recovery through phase difference, the present invention characterizes the clock phase change based on the tap coefficient of the equalizer, thereby completing the clock phase adjustment. While realizing the clock data recovery function based on the oversampling method, it effectively simplifies the processing logic of the clock data, reduces the complexity of the clock recovery algorithm, and effectively balances the data recovery performance and resource consumption.

[0053] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for recovering clock data, characterized in that: include: Extracting a first tap coefficient value of a first equalizer and a second tap coefficient value of a second equalizer based on a current working clock; Determining a phase state of the current working clock according to a comparison result between the first tap coefficient value and the second tap coefficient value; If the phase state indicates a phase advance or a phase delay, calculating a coefficient difference between the first tap coefficient value and the second tap coefficient value; as well as The clock phase of the current working clock is adjusted according to the phase state and the coefficient difference to output a working clock having a clock phase opposite to the phase state.

2. The method according to claim 1, characterized in that The first equalizer is used to eliminate forward interference of the target signal, and the second equalizer is used to eliminate backward interference of the target signal. Wherein determining the phase state of the current working clock according to the comparison result between the first tap coefficient value and the second tap coefficient value comprises: If the first tap coefficient value is less than the second tap coefficient value, determining that the phase state of the current working clock is phase advance; and If the first tap coefficient value is greater than the second tap coefficient value, it is determined that the phase state of the current working clock is phase delay.

3. The method according to claim 2, characterized in that Adjusting the clock phase of the current working clock according to the phase state and the coefficient difference to output a working clock having a phase relative to the phase state includes: If the phase state is phase advance, outputting a working clock with a clock phase delayed by one unit according to the coefficient difference; If the phase state is phase delay, the clock phase of the output having the coefficient difference is advanced by one unit of the working clock.

4. The method according to claim 3, characterized in that The working clock having a clock phase delayed by one unit according to the coefficient difference output includes: Calculating a first accumulation result of all coefficient differences of the phase state of the phase advance including the current extraction cycle according to a preset accumulation weight; and Whether the clock phase of the current working clock is delayed by one unit of clock phase is controlled according to the first accumulation result.

5. The method according to claim 4, characterized in that Controlling whether the clock phase of the current working clock is delayed by one unit of clock phase according to the first accumulation result includes: Detecting whether the first accumulated result is greater than a first phase switching threshold; If yes, switching the current working clock to a working clock having a first clock phase delayed by one unit; and Otherwise, the process returns to extracting the first tap coefficient value of the first equalizer and the second tap coefficient value of the second equalizer based on the current operating clock.

6. The method according to claim 3, characterized in that The working clock having a clock phase advanced by one unit according to the coefficient difference output comprises: Calculating a second accumulation result of all coefficient differences whose phase state is phase delay including the current extraction cycle according to a preset accumulation weight; and Whether the clock phase of the current working clock is advanced by one unit of clock phase is controlled according to the second accumulated result.

7. The method according to claim 6, characterized in that Controlling whether the clock phase of the current working clock is advanced by one unit of clock phase according to the second accumulated result includes: Detecting whether the second accumulated result is greater than a second phase switching threshold; If so, switching the current working clock to a working clock having a second clock phase that is one unit ahead; and Otherwise, the process returns to extracting the first tap coefficient value of the first equalizer and the second tap coefficient value of the second equalizer based on the current operating clock.

8. The method according to claim 4 or 6, characterized in that: Adjusting the clock phase of the current working clock according to the phase state and the coefficient difference includes: Obtaining a preset phase compensation amount; and The coefficient difference is compensated according to the phase compensation amount, so as to adjust the clock phase according to the coefficient difference after the compensation process.

9. The method according to claim 8, characterized in that Also includes: Obtaining the attenuated signal amplitude of the target signal; Predicting a line length for transmitting the target signal according to the attenuated signal amplitude; determining an attenuation waveform of the target signal according to the line length; Determine difference data between the forward interference and the backward interference according to the attenuation waveform; The phase compensation amount is set according to the difference data.

10. The method according to claim 1, characterized in that Adjusting the clock phase of the current working clock according to the phase state and the coefficient difference to output a working clock having a clock phase relative to the phase state includes: According to the comparison result between the accumulated value of the coefficient difference in the set period and the phase switching threshold, the next working clock is selected from multiple working clocks with different clock phases until the comparison result between the first tap coefficient value and the second tap coefficient value meets the predetermined conditions.

11. A device for recovering clock data, characterized in that: include: An extraction module, configured to extract a first tap coefficient value of a first equalizer and a second tap coefficient value of a second equalizer based on a current working clock; a calculation module configured to determine the phase state of the current working clock according to a comparison result between the first tap coefficient value and the second tap coefficient value, and if the phase state indicates a phase advance or a phase delay, calculate a coefficient difference between the first tap coefficient value and the second tap coefficient value; as well as The adjustment module is configured to adjust the clock phase of the current working clock according to the phase state and the coefficient difference to output a working clock having a clock phase relative to the phase state.

12. A balancing system, characterized in that: include: The device according to claim 11; as well as A first equalizer and a second equalizer are electrically coupled to the device.

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