Pixel array and image sensor including same

Abstract

An image sensor includes a first floating diffusion region (FD) and first four photoelectric conversion devices (PD); a second pixel including a second FD and second four PDs, the second pixel being placed directly adjacent to the first pixel in the first direction in a plan view; a third pixel including a third FD and third four PDs, the third pixel being placed directly adjacent to the first pixel in a second direction perpendicular to the first direction in plan view; a first microlens on the first pixel; a second microlens on the second pixel; a third microlens on the third pixel; a first driving transistor configured to be connected to the first four PDs and the second four PDs; and a first selection transistor connected to the first driving transistor; a reset transistor configured to be connected to the first FD and the second FD; and a green filter on the first to third pixels; wherein each of the first four PDs to the third four PDs is arranged in a 2 * 2 matrix.

Description

[0001] This application is a divisional application of the invention patent application with the application date of June 8, 2022, application number 202210644841.0, and invention name “Pixel array and image sensor including the same”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2021-0075608 filed in the Korean Intellectual Property Office on June 10, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] Embodiments relate to pixel arrays and image sensors including the same. Background Art

[0005] An image sensor is a device for capturing a two-dimensional (2D) or three-dimensional (3D) image of an object. An image sensor generates an image of an object by using a photoelectric conversion device that reacts according to the intensity of light reflected by the object. With the recent development of complementary metal oxide semiconductor (CMOS) technology, CMOS image sensors using CMOS have been widely used. As the resolution of an image sensor increases, a pixel structure with a reduced area is desired due to a reduced pitch between a plurality of pixels included in a pixel array of the image sensor. Summary of the invention

[0006] According to an embodiment, a pixel array included in an image sensor is provided, the pixel array comprising: a plurality of pixels arranged in a matrix and a plurality of column lines, each column line being commonly connected to pixels arranged on the same column among the plurality of pixels. Each of the plurality of pixels comprises four sub-pixels. Each of the four sub-pixels comprises: four photoelectric conversion devices; a floating diffusion region storing charges generated by the four photoelectric conversion devices; and four transfer gates configured to transfer the charges generated by the four photoelectric conversion devices to the floating diffusion region. The four floating diffusion regions included in the four sub-pixels are electrically connected to each other via internal wiring. Each of the plurality of pixels further comprises: a reset gate configured to reset the four floating diffusion regions by providing a power supply voltage to the internal wiring; a first drive gate configured to receive a first voltage via the internal wiring; and a first selection gate arranged adjacent to the first drive gate in a first direction.

[0007] According to an embodiment, a pixel array included in an image sensor is provided, the pixel array comprising: a plurality of pixels, each pixel comprising a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel; and a plurality of column lines, each column line being commonly connected to pixels arranged on the same column among the plurality of pixels. Each of the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel comprises: four photoelectric conversion devices arranged in a matrix; and a floating diffusion region storing charges generated by the four photoelectric conversion devices. The first floating diffusion region of the first sub-pixel, the second floating diffusion region of the second sub-pixel, the third floating diffusion region of the third sub-pixel and the fourth floating diffusion region of the fourth sub-pixel are electrically connected to each other via wiring, and the wiring is formed in a pixel region where the pixel is formed. Each of the plurality of pixels also includes an output circuit connected to a corresponding column line and wiring among the plurality of column lines, and configured to share the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel. The first circuit comprises: a reset transistor configured to provide a reset voltage to the wiring; at least one drive transistor comprising a gate connected to the wiring; and at least one selection transistor connected to the first drive transistor and the column line.

[0008] According to an embodiment, there is provided an image sensor including a pixel array, the pixel array including: a plurality of pixels, wherein each of the plurality of pixels includes a plurality of floating diffusion regions arranged between a plurality of transfer transistors, the plurality of floating diffusion regions being connected to each other via wiring; a row driver configured to drive rows connected to the plurality of pixels in units of rows; and an analog-to-digital conversion circuit configured to receive a plurality of sensing signals from a plurality of column lines connected to the pixel array, and perform analog-to-digital conversion on the plurality of sensing signals.

[0009] According to an embodiment, a pixel array is provided, comprising: a semiconductor substrate having a first surface and a second surface and comprising a plurality of floating diffusion regions adjacent to the first surface; and a wiring structure arranged on the first surface. The wiring structure comprises: a plurality of transfer gates arranged symmetrically with respect to each of the plurality of floating diffusion regions; and wiring configured to electrically connect four adjacent floating diffusion regions among the plurality of floating diffusion regions.

[0010] More specifically, according to an embodiment, an image sensor is provided, comprising a first floating diffusion region (FD) and first four photoelectric conversion devices (PD); a second pixel, comprising a second FD and a second four PD, the second pixel being placed directly adjacent to the first pixel along a first direction in a plan view; a third pixel, comprising a third FD and a third four PD, the third pixel being placed directly adjacent to the first pixel along a second direction perpendicular to the first direction in a plan view; a first microlens on the first pixel; a second microlens on the second pixel; a third microlens on the third pixel; a first drive transistor, configured to be connected to the first four PDs and the second four PDs; and a first selection transistor, connected to the first drive transistor; a reset transistor, configured to be connected to the first FD and the second FD; and a green filter on the first to third pixels; wherein each of the first four PDs to the third four PDs is arranged in a 2×2 matrix. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Features will become apparent to those skilled in the art by describing in detail example embodiments with reference to the accompanying drawings, in which:

[0012] Figure 1 is a block diagram of an image sensor according to an example embodiment;

[0013] Figure 2 shows a pixel array according to an example embodiment;

[0014] Figure 3 is a circuit diagram of a pixel included in a pixel array according to an example embodiment;

[0015] Figure 4 is a plan view of a pixel according to an example embodiment;

[0016] Figure 5 is a vertical cross-sectional view of a pixel array according to an example embodiment;

[0017] Fig. 6A and Figure 6B is a plan view of a pixel according to an example embodiment;

[0018] Figure 7 is a plan view of a pixel according to an example embodiment;

[0019] Figure 8 is a circuit diagram of a pixel according to an example embodiment;

[0020] Fig. 9A , Fig. 9B and Fig. 9C is a plan view of a pixel according to an example embodiment;

[0021] Fig. 10A and Fig. 10Bis a plan view of a pixel according to an example embodiment;

[0022] Fig.11A , Fig. 11B and Fig. 11C is a plan view of a pixel according to an example embodiment;

[0023] Fig. 12A , Fig. 12B and Fig. 12C is a plan view of a pixel according to an example embodiment;

[0024] Fig.13A , Fig. 13B , Fig. 13C , Fig.13D , Fig.13E and Fig.13F is a plan view of a pixel according to an example embodiment;

[0025] Fig.14A , Fig. 14B , Fig. 14C , Fig.14D , Fig.14E and Fig.14F is a plan view of a pixel according to an example embodiment;

[0026] Fig.15A , Fig. 15B and Fig. 15C is a plan view of a pixel according to an example embodiment;

[0027] Fig.16A , Fig. 16B , Fig. 16C and Fig.16D shows a microlens arranged in a pixel according to an example embodiment;

[0028] Fig.17A , Fig. 17B , Fig. 17C , Fig.17D , Fig.17E and Fig.17F shows a color filter arranged in a pixel array according to an example embodiment;

[0029] Fig.18 is a block diagram of an electronic device including a multi-camera module; and

[0030] Fig.19 yes Fig.18 Detailed block diagram of a multi-camera module. DETAILED DESCRIPTION

[0031] Figure 1 is a block diagram of an image sensor 100 according to example embodiments.

[0032] The image sensor 100 may be mounted on an electronic device having an image or light sensing function. For example, the image sensor 100 may be mounted on an electronic device such as a camera, a smart phone, a wearable device, an Internet of Things (IoT), a tablet personal computer (PC), a personal digital assistant (PDA), a portable multimedia player (PMP), or a navigation device. The image sensor 100 may also be mounted on an electronic device included as a component in a vehicle, furniture, manufacturing equipment, a door, various types of measuring devices, and the like.

[0033] The image sensor 100 may include a pixel array 110, a row driver 120, a ramp signal generator 130, an analog-to-digital conversion (ADC) circuit 140, a data output circuit 150, and a timing controller 160. The image sensor 100 may further include a signal processor 170.

[0034] The pixel array 110 may include a plurality of row lines RL, a plurality of column lines CL, and a plurality of pixels PX connected to the plurality of row lines RL and the plurality of column lines CL and arranged in a matrix. Pixels PX arranged at the same position in the column direction may be connected to the same column line CL.

[0035] Each pixel PX can sense light by using a photoelectric conversion device, and can output an image signal corresponding to an electrical signal based on the sensed light. The photoelectric conversion device can be a photosensitive device formed of an organic or inorganic material, such as an inorganic photodiode, an organic photodiode, a perovskite photodiode, a phototransistor, a photogate, or a pinned photodiode.

[0036] In the pixel array 110, each pixel PX may include a plurality of sub-pixels, and each of the plurality of sub-pixels may include a plurality of photoelectric conversion devices. Each sub-pixel may include a floating diffusion region storing charges generated by the plurality of photoelectric conversion devices. The plurality of floating diffusion regions respectively included in the plurality of sub-pixels may be electrically connected to each other through internal wiring, so the plurality of sub-pixels included in the pixel PX may share the plurality of floating diffusion regions.

[0037] Each pixel PX may include four sub-pixels. Each of the four sub-pixels may include four photoelectric conversion devices arranged in a matrix and four transfer transistors respectively connected to the four photoelectric conversion devices. A floating diffusion region may be arranged at the center of each sub-pixel. The four floating diffusion regions included in the four sub-pixels may be electrically connected to each other through internal wiring to form a floating diffusion node.

[0038] Each pixel PX may include an output circuit for outputting an image signal to a column line based on charges stored in the plurality of floating diffusion regions. The output circuit may include a plurality of transistors, such as a reset transistor, a drive transistor, and a selection transistor.

[0039] The pixel array 110 and the pixels PX included in the pixel array 110 will be referred to as Figures 2 to 17F This is described in further detail below.

[0040] The row driver 120 may drive the pixel array 110 in units of rows. The row driver 120 may decode a row control signal (e.g., an address signal) received from the timing controller 160, and may select at least one row line from the row lines constituting the pixel array 110 in response to the decoded row control signal. For example, the row driver 120 may generate a selection signal for selecting one of a plurality of rows. The pixel array 110 may output a pixel signal, such as a pixel voltage, from a row selected according to the selection signal received from the row driver 120. The pixel signal may include a reset signal and an image signal.

[0041] The row driver 120 may transmit a control signal for outputting a pixel signal to the pixel array 110. The pixel PX may output the pixel signal in response to the control signal.

[0042] The ramp signal generator 130 may generate a ramp signal RAMP (eg, a ramp voltage) whose level rises or falls at a predetermined slope under the control of the timing controller 160. The ramp signal RAMP may be provided to a plurality of correlated double sampling (CDS) circuits 141 included in the ADC circuit 140.

[0043] The ADC circuit 140 may include a plurality of CDS circuits 141 and a plurality of counters 142. The ADC circuit 140 may convert a pixel signal (e.g., a pixel voltage) received from the pixel array 110 into a pixel value as a digital signal. A pixel signal received via each of the plurality of column lines CL may be converted into a pixel value as a digital signal by each CDS circuit 141 and each counter 142.

[0044] The CDS circuit 141 may compare a pixel signal (e.g., a pixel voltage) received via the column line CL with the ramp signal RAMP, and may output the comparison result as a comparison result signal. When the ramp signal RAMP and the pixel signal have the same level, the CDS circuit 141 may output a comparison signal that is transformed from a first level (e.g., a logic high) to a second level (e.g., a logic low). The time point of the level transition of the comparison signal may be determined according to the level of the pixel signal.

[0045] The CDS circuit 141 may sample a pixel signal received from the pixel PX according to a CDS method. The CDS circuit 141 may sample a reset signal received as a pixel signal and compare the reset signal with a ramp signal RAMP to generate a comparison signal based on the reset signal. The CDS circuit 141 may store the reset signal. Then, the CDS circuit 141 may sample an image signal related to the reset signal and compare the image signal with the ramp signal RAMP to generate a comparison signal based on the image signal.

[0046] The counter 142 may count the level transition time points of the comparison result signal outputted from the CDS circuit 141 , and may output the count value as a pixel value.

[0047] The counter 142 may use an up-counter (in which the count value is sequentially increased based on the count clock signal provided by the timing controller 160 and the operation circuit), an up / down counter, or a bitwise inversion counter. The image sensor 100 may further include a code generator for generating a plurality of code values ​​having a resolution based on a preset number of bits as the count code, and the counter 142 may include a latch circuit and an arithmetic circuit, the latch circuit latching the value of the count code based on the comparison result signal.

[0048] The data output circuit 150 may temporarily store and output the pixel values ​​output by the ADC circuit 140. The data output circuit 150 may include a plurality of column memories 151 and a column decoder 152. Each column memory 151 may store a pixel value received from the counter 142. Each of the plurality of column memories 151 may be included in the counter 142. The plurality of pixel values ​​stored in the plurality of column memories 151 may be output as image data IDTA under the control of the column decoder 152.

[0049] The timing controller 160 may output a control signal to each of the row driver 120 , the ramp signal generator 130 , the ADC circuit 140 , and the data output circuit 150 to control operation or timing of the row driver 120 , the ramp signal generator 130 , the ADC circuit 140 , and the data output circuit 150 .

[0050] The signal processor 170 may perform noise reduction, gain adjustment, waveform shaping, interpolation, white balance adjustment, gamma correction, edge emphasis, binning, etc. on the image data IDTA. The signal processor 170 may be included in a processor outside the image sensor 100 .

[0051] Figure 2 A pixel array 110 is shown according to an example embodiment.

[0052] Reference Figure 2 , the pixel array 110 may include a plurality of pixels in a matrix, for example, first to fourth pixels PX1 to PX4. The plurality of pixels may be arranged in a plurality of rows and columns. Figure 2 The first to fourth pixels PX1 to PX4 arranged on the first and second rows R1 and R2 and the first and second columns C1 and C2 are shown, but this is only for convenience of description, and the pixel array 110 may include a greater number of pixels. The number of pixels may be determined according to the resolution of the pixel array 110.

[0053] Figure 1 The plurality of row lines RL may each extend in a first direction (e.g., an X-axis direction), and pixels arranged in the same row may be connected to the same row line. For example, a first pixel PX1 and a second pixel PX2 arranged in a first row R1 may be connected to the same row line, and a third pixel PX3 and a fourth pixel PX4 arranged in a second row R2 may be connected to another same row line.

[0054] Figure 1 The plurality of column lines CL may each extend in the second direction (e.g., the Y-axis direction), and the pixels arranged on the same column may be connected to the same column line. For example, the first pixel PX1 and the third pixel PX3 arranged on the first column C1 may be connected to the same column line, and the second pixel PX2 and the fourth pixel PX4 arranged on the second column C2 may be connected to another same column line. Pixel signals may be read from the plurality of pixels in units of rows via the column lines.

[0055] Each of the first to fourth pixels PX1 to PX4 may include a plurality of floating diffusion regions FD storing charges. The plurality of floating diffusion regions FD may be electrically connected to each other via internal wirings WR extending in the first and second directions within each of the first to fourth pixels PX1 to PX4. The first to fourth pixels PX1 to PX4 may have the same pixel structure, which will be referred to as Figure 4 Describe in detail.

[0056] Figure 3 is a circuit diagram of a pixel PXa included in a pixel array according to example embodiments. Figure 3 The pixel PXa is Figure 2 The first pixel PX1 to the fourth pixel PX4 of the pixel array 110 are applicable.

[0057] Reference Figure 3, the pixel PXa may include first to fourth sub-pixels SPX1 to SPX4, a reset transistor RX, first and second drive transistors DX1 and DX2, and first and second select transistors SX1 and SX2. The reset transistor RX, the first and second drive transistors DX1 and DX2, and the first and second select transistors SX1 and SX2 may constitute an output circuit of the pixel PXa.

[0058] The first subpixel SPX1 may include first to fourth photoelectric conversion devices PD11 to PD14 and first to fourth transfer transistors TX11 to TX14. Each of the first to fourth photoelectric conversion devices PD11 to PD14 may generate a photocharge (hereinafter referred to as charge) corresponding to the received optical signal. The first to fourth photoelectric conversion devices PD11 to PD14 may be connected to the first to fourth transfer transistors TX11 to TX14, respectively. The first to fourth transfer transistors TX11 to TX14 may be turned on in response to the active levels (e.g., logic high) of the transmission signals TS11 to TS14, respectively.

[0059] The second subpixel SPX2 may include first to fourth photoelectric conversion devices PD21 to PD24, and first to fourth transfer transistors TX21 to TX24 respectively connected to the first to fourth photoelectric conversion devices PD21 to PD24. The first to fourth transfer transistors TX21 to TX24 may be turned on in response to active levels (e.g., logic high) of transmission signals TS21 to TS24, respectively.

[0060] The third subpixel SPX3 may include first to fourth photoelectric conversion devices PD31 to PD34, and first to fourth transfer transistors TX31 to TX34 respectively connected to the first to fourth photoelectric conversion devices PD31 to PD34. The first to fourth transfer transistors TX31 to TX34 may be turned on in response to active levels (e.g., logic high) of transmission signals TS31 to TS34, respectively.

[0061] The fourth subpixel SPX4 may include first to fourth photoelectric conversion devices PD41 to PD44, and first to fourth transfer transistors TX41 to TX44 respectively connected to the first to fourth photoelectric conversion devices PD41 to PD44. The first to fourth transfer transistors TX41 to TX44 may be turned on in response to the active levels (e.g., logic high) of the transmission signals TS41 to TS44, respectively.

[0062] According to a read mode, the plurality of transmission signals TS11 to TS14 , TS21 to TS24 , TS3 to TS41 , and TS44 may have active levels at the same or different time points.

[0063] For example, in the first read mode, the plurality of transmission signals TS11 to TS14 , TS21 to TS24 , TS3 to TS41 to TS44 may be different signals and thus may have valid levels at different time points.

[0064] In the second read mode (eg, charge addition mode), the plurality of transmission signals TS11 to TS14 , TS21 to TS24 , TS31 to TS3 , and TS41 to TS44 may be the same signal and thus may have a valid level at the same point in time.

[0065] In the third reading mode, the transmission signals TS11 to TS14 of the first subpixel SPX1 may be the same signal, the transmission signals TS21 to TS24 of the second subpixel SPX2 may be the same signal, the transmission signals TS31 to TS34 of the third subpixel SPX3 may be the same signal, and the transmission signals TS41 to TS44 of the fourth subpixel SPX4 may be the same signal.

[0066] The first to fourth transfer transistors TX11 to TX14 , TX21 to TX24 , TX31 to TX34 , and TX41 to TX44 may be turned on to transfer charges generated by the corresponding photoelectric conversion devices to the floating diffusion node FN.

[0067] The first sub-pixel SPX to the fourth sub-pixel SPX4 respectively include Figure 4 The first to fourth floating diffusion regions FD1 to FD4 may be electrically connected to each other via the internal wiring WR to form a floating diffusion node FN. Therefore, the capacitance of the capacitor formed in the floating diffusion node FN may be Figure 4 The capacitance of each of the first to fourth floating diffusion areas FD1 to FD4 is four times greater.

[0068] The pixel power supply voltage VDDP may be applied to the drain of the reset transistor RX, and the source of the reset transistor RX may be connected to the floating diffusion node FN. The reset transistor RX may be turned on in response to the active level of the reset signal RS, and may provide the pixel power supply voltage VDDP as a reset voltage to the floating diffusion node FN, thereby resetting the floating diffusion node FN.

[0069] The pixel power supply voltage VDDP may be applied to respective drains of the first drive transistor DX1 and the second drive transistor DX2. Respective sources of the first drive transistor DX1 and the second drive transistor DX2 may be connected to respective drains of the first selection transistor SX1 and the second selection transistor SX2. The gates of the first drive transistor DX1 and the second drive transistor DX2 may be connected to the floating diffusion node FN. The first drive transistor DX1 and the second drive transistor DX2 may operate as source followers. The first drive transistor DX1 and the second drive transistor DX2 may receive a voltage based on the potential of the floating diffusion node FN, which is applied to respective gates of the first drive transistor DX1 and the second drive transistor DX2, and the first drive transistor DX1 and the second drive transistor DX2 may output a pixel signal based on the received voltage.

[0070] The respective sources of the first selection transistor SX1 and the second selection transistor SX2 may be connected to the column line CL. The first selection transistor SX1 and the second selection transistor SX2 may be turned on in response to the active level of the selection signal SEL applied to the respective gates of the first selection transistor SX1 and the second selection transistor SX2, thereby outputting the pixel signal output by the first drive transistor DX1 and the second drive transistor DX2 to the column line CL. When the first selection transistor SX1 and the second selection transistor SX2 are turned on, the pixel signal output by the source of the first drive transistor DX1 and the second drive transistor DX2 may be output to the column line CL.

[0071] Despite Figure 3 The pixel PXa includes two first and second drive transistors DX1 and DX2 and two first and second select transistors SX1 and SX2, but this may vary, for example, Figure 2 A pixel included in the pixel array 110 may include one driving transistor and one selecting transistor, or the pixel may include three or more driving transistors and three or more selecting transistors.

[0072] Figure 4 is a plan view of a pixel PXa according to example embodiments. Figure 4 The pixel PXa is suitable for Figure 2 The pixel array 110 includes first to fourth pixels PX1 to PX4.

[0073] Reference Figure 4 , the pixel PXa may include first to fourth sub-pixels SPX1 to SPX4. The first to fourth sub-pixels SPX1 to SPX4 may have the same pixel structure.

[0074] The first sub-pixel SPX1 may include first to fourth photoelectric conversion devices PD11 to PD14 , first to fourth transfer gates TG11 to TG14 , and a first floating diffusion area FD1 .

[0075] The first to fourth transmission gates TG11 to TG14 are Figure 3 The first transfer transistors TX11 to the fourth transfer transistors TX14 transfer the charges generated by the first photoelectric conversion devices PD11 to the fourth photoelectric conversion devices PD14 to the first floating diffusion area FD1. The charges received by the first floating diffusion area FD1 may be stored.

[0076] The first to fourth photoelectric conversion devices PD11 to PD14 may be arranged in a matrix. The first floating diffusion region FD1 may be arranged at the center of the first subpixel PSX1. The first to fourth transfer gates TG11 to TG14 may be arranged symmetrically with respect to the first floating diffusion region FD1. The first to fourth transfer gates TG11 to TG14 may be arranged to surround the first floating diffusion region FD1.

[0077] The second sub-pixel SPX2 may include the first photoelectric conversion device PD21 to the fourth photoelectric conversion device PD24, the first transfer gate TG21 to the fourth transfer gate TG24, and the second floating diffusion area FD2. The third sub-pixel SPX3 may include the first photoelectric conversion device PD31 to the fourth photoelectric conversion device PD34, the first transfer gate TG31 to the fourth transfer gate TG34, and the third floating diffusion area FD3. The fourth sub-pixel SPX4 may include the first photoelectric conversion device PD41 to the fourth photoelectric conversion device PD44, the first transfer gate TG41 to the fourth transfer gate TG44, and the fourth floating diffusion area FD4. The respective pixel structures of the second sub-pixel SPX2, the third sub-pixel SPX3, and the fourth sub-pixel SPX4 are the same as the pixel structure of the first sub-pixel SPX1, so their repeated description is omitted.

[0078] The internal wiring WR may be connected to the first to fourth floating diffusion areas FD1 to FD4 via the contacts CT. The first to fourth floating diffusion areas FD1 to FD4 may be electrically connected to each other via the internal wiring WR to form Figure 3 The internal wiring WR may be formed in a pixel region in which pixels PXa are formed on a two-dimensional (2D) plane according to a first direction (eg, an X-axis direction) and a second direction (eg, a Y-axis direction). Figure 2, the internal wiring WR included in the first pixel PX1 is formed within the pixel region of the first pixel PX1 and does not extend to other pixels, for example, the second to fourth pixels PX2 to PX4 .

[0079] The internal wiring WR may extend in a first direction (e.g., an X-axis direction) to connect the first floating diffusion area FD1 to the second floating diffusion area FD2 and the third floating diffusion area FD3 to the fourth floating diffusion area FD4. The internal wiring WR may also extend in a second direction (e.g., a Y-axis direction) to connect the first floating diffusion area FD1 and the second floating diffusion area FD2 to the third floating diffusion area FD3 and the fourth floating diffusion area FD4. Therefore, the first sub-pixel SPX1 to the fourth sub-pixel SPX4 may share the first floating diffusion area FD1 to the fourth floating diffusion area FD4. Therefore, the useful area of ​​the pixel PXa may be increased.

[0080] The pixel PXa may include a reset gate RG, first and second driving gates SFG1 and SFG2 , first and second selection gates SG1 and SG2 , and a dummy gate DMY.

[0081] The reset gate RG can be Figure 3 The gate of the reset transistor RX. Figure 3 The pixel power supply voltage VDDP may be applied to the drain of the reset transistor RX. The source of the reset transistor RX may be connected to the internal wiring WR via the contact CT. When the reset transistor RX is turned on, the pixel power supply voltage may be applied to the first to fourth floating diffusion areas FD1 to FD4 via the internal wiring WR, thereby resetting the first to fourth floating diffusion areas FD1 to FD4. Therefore, the charges remaining in the first to fourth floating diffusion areas FD1 to FD4 may be removed.

[0082] The first driving gate SFG1 and the second driving gate SFG2 may be Figure 3 The first selection gate SG1 and the second selection gate SG2 may be Figure 3 The first and second drive gates SFG1 and SFG2 may be connected to the internal wiring WR via the contact CT.

[0083] The respective drains of the first selection gate SG1 and the second selection gate SG2 may be connected to the respective sources of the first drive transistor DX1 and the second drive transistor DX2, respectively. The respective sources of the first selection gate SG1 and the second selection gate SG2 may be connected to the column line via the contact CT. When the first selection transistor SX1 and the second selection transistor SX2 are turned on, the pixel signals output by the respective sources of the first drive transistor DX1 and the second drive transistor DX2 may be output to the column line.

[0084] The first drive gate SFG1 and the second drive gate SFG2 and the first selection gate SG1 and the second selection gate SG2 may be arranged side by side along a first direction (e.g., the X-axis direction) at one side (e.g., the upper or lower part of PXa). The first drive gate SFG1 and the second drive gate SFG2 and the first selection gate SG1 and the second selection gate SG2 may be arranged parallel to each other at one side (e.g., the upper or lower part of PXa). Figure 1 The row line RL is arranged.

[0085] The first and second drive gates SFG1 and SFG2 may be connected to the internal wiring WR via the contact CT. The first drive gate SFG1 may be connected to the first terminal T1 of the internal wiring WR. The second drive gate SFG2 may be connected to the second terminal T2 of the internal wiring WR.

[0086] The first and second selection gates SG1 and SG2 may be disposed between the first and second driving gates SFG1 and SFG2. The first and second selection gates SG1 and SG2 may be disposed outside the first and second driving gates SFG1 and SFG2.

[0087] The reset gate RG may be arranged at the center of the pixel PXa. The dummy gate DMY may be arranged side by side with the reset gate RG in the first direction. The reset gate RG and the dummy gate DMY may be arranged between the first and second sub-pixels SPX1 and SPX2 and the third and fourth sub-pixels SPX3 and SPX4. The reset gate RG and the dummy gate DMY may be arranged symmetrically with respect to each other in the first direction with respect to the center of the pixel PXa. In another embodiment ( Figure 4 (not shown in FIG. 1 ), the pixel PXa may not include the dummy gate DMY.

[0088] As described above, in the pixel PXa, the first subpixel SPX1 to the fourth subpixel SPX4 can share the first floating diffusion area FD1 to the fourth floating diffusion area FD4. The first subpixel SPX1 to the fourth subpixel SPX4 can share the output circuit. Therefore, the useful area of ​​the pixel PXa can be increased, and the size of the pixel PXa can be reduced. Because the first floating diffusion area FD1 to the fourth floating diffusion area FD4 are shared within the pixel PXa, the sensing sensitivity of the pixel PXa can be improved. Therefore, the Figure 2 The resolution and sensing sensitivity of pixel array 110 are determined.

[0089] Figure 5 is a vertical cross-sectional view of a pixel array 110 according to example embodiments. Figure 5 is the pixel array 110 along Figure 4 A vertical cross-sectional view taken along line AA'.

[0090] Reference Figure 5 The pixel array 110 may include a semiconductor substrate 111 (hereinafter, substrate 111) having a first surface 111B and a second surface 111F opposite to each other, an incident layer 112 arranged on the first surface 111B of the substrate 111, and a wiring layer 113 (or wiring structure) arranged on the second surface 111F of the substrate 111.

[0091] The substrate 111 may include one or more of Si, Ge, SiGe, SiC, GaAs, InAs, or InP. The substrate 111 may be doped with impurities of a first conductivity type. For example, the first conductivity type may be a P type, and the impurities of the first conductivity type may be boron.

[0092] A first deep trench isolation (DTI) portion DTI1 and a second DTI portion DTI2 may be arranged in the substrate 111. The first DTI portion DTI1 may penetrate the substrate 111 and extend from the first surface 111B to the second surface 111F. The second DTI portion DTI2 may extend from the first surface 111B toward the second surface 111F, but may be spaced apart from the second surface 111F. The first DTI portion DTI1 and the second DTI portion DTI2 may include one or more of a silicon oxide layer, a hafnium oxide layer, an aluminum oxide layer, or a polysilicon layer doped with impurities. Each of the first DTI portion DTI1 and the second DTI portion DTI2 may have a single-layer or multi-layer structure.

[0093] The first DTI portion DTI1 may separate sub-pixels (e.g., the first sub-pixel SPX1 and the second sub-pixel SPX2) from each other, and the second DTI portion DTI2 may separate regions within the sub-pixels from each other. For example, the second DTI portion DTI2 may separate the first region AR11 from the second region AR12 within the first sub-pixel SPX1 in a first direction (e.g., the X-axis direction), and may separate the first region AR21 from the second region AR22 within the second sub-pixel SPX2. The first DTI portion DTI1 and the second DTI portion DTI2 may prevent crosstalk between pixels PXa, between sub-pixels, and between regions of each sub-pixel.

[0094] The first photoelectric conversion device PD11 and the second photoelectric conversion device PD12 may be arranged in the first area AR11 and the second area AR12 of the first sub-pixel SPX1, respectively. The first photoelectric conversion device PD21 and the second photoelectric conversion device PD22 may be arranged in the first area AR21 and the second area AR22 of the second sub-pixel SPX2, respectively. Each of the photoelectric conversion devices PD11, PD12, PD21 and PD22 may include a region doped with impurities of a second conductive type opposite to the first conductive type. For example, the second conductive type may be an N-type, and the impurities of the second conductive type may include impurities such as phosphorus, arsenic, bismuth and / or antimony. The region of the substrate 111 doped with impurities of the second conductive type may form a PN junction with the region of the substrate 111 doped with impurities of the first conductive type and adjacent to the aforementioned region to form the photoelectric conversion devices PD11, PD12, PD21 and PD22.

[0095] The first surface 111B of the substrate 111 may be a light incident surface, and light may be incident via the incident layer 112 and the first surface 111B. The incident layer 112 may include a microlens ML and a color filter CF. The anti-reflection layer AF may be arranged between the first surface 111B of the substrate 111 and the color filter CF. The anti-reflection layer AF, the color filter CF, and the microlens ML may be arranged to be sequentially stacked on the first surface 110B of the substrate 111.

[0096] exist Figure 5, a single microlens ML is arranged on each of a plurality of photoelectric conversion devices (e.g., the first photoelectric conversion device PD11 and the second photoelectric conversion device PD12 of the first sub-pixel SPX1 and the first photoelectric conversion device PD21 and the second photoelectric conversion device PD22 of the second sub-pixel SPX2), but this may vary, for example, a single microlens ML may be arranged on two or four photoelectric conversion devices. For example, one microlens ML may be arranged on the first photoelectric conversion device PD11 and the second photoelectric conversion device PD12 of the first sub-pixel SPX1, and another microlens ML may be arranged on the first photoelectric conversion device PD21 and the second photoelectric conversion device PD22 of the second sub-pixel SPX2. As another example, a single microlens ML may be arranged in each sub-pixel, that is, on the fourth photoelectric conversion device (e.g., the first photoelectric conversion device PD11 to the fourth photoelectric conversion device PD14 of the first sub-pixel SPX1) included in one sub-pixel.

[0097] The color filter CF can transmit light in a specific spectral band, i.e., light of a specific color. A plurality of color filters CF can constitute a color filter array. The color filter array can have a Bayer pattern. A plurality of color filters can include a red filter, a blue filter, and two green filters, and the red filter, the blue filter, and the two green filters can be arranged 2×2, and the two green filters can be arranged diagonally. A plurality of color filters CF can include a red filter, a blue filter, a green filter, and a white filter arranged 2×2. A plurality of color filters CF can include a red filter, two yellow filters, and a blue filter arranged 2×2, and the two green filters can be arranged diagonally. However, this can be changed, for example, the plurality of color filters can include filters combined with different colors. For example, the plurality of color filters can include a yellow filter, a cyan filter, and a green filter.

[0098] The first color filter CF1 may be arranged on the first sub-pixel SPX1, and the second color filter CF2 may be arranged on the second sub-pixel SPX2. The first color filter CF1 and the second color filter CF2 may transmit light of the same color or different colors. According to the color of the light transmitted by the color filter CF, the color sensed by the corresponding sub-pixel (the first sub-pixel SPX1 or the second sub-pixel SPX2) or the corresponding pixel PXa may be determined.

[0099] The floating diffusion regions (e.g., the first floating diffusion region FD1 and the second floating diffusion region FD2) may be formed adjacent to the second surface 111F of the substrate 111 and may be located at the center of the first subpixel SPX1 and the second subpixel SPX2, respectively. The first floating diffusion region FD1 and the second floating diffusion region FD2 may be regions doped with impurities of the second conductive type.

[0100] The gates of the transistors (e.g., the first transmission gates TG11 and TG21 and the second transmission gates TG12 and TG22) may be formed adjacent to the second surface 111F of the substrate 111 within the wiring layer 113. The first transmission gates TG11 and TG21 and the second transmission gates TG12 and TG22 may be formed adjacent to the first floating diffusion area FD1 and the second floating diffusion area FD2. Figure 5 Only the transmission gates, for example, the first transmission gates TG11 and TG21 and the second transmission gates TG12 and TG22 are shown, but Figure 4 The reset gate RG, Figure 4 The driving gates SFG1 and SFG2, Figure 4 The select gates SG1 and SG2 and Figure 4 The dummy gate DMY may be formed adjacent to the second surface 111F of the substrate 111 .

[0101] Well region (not in Figure 5 ) may be formed around the gates (eg, the first transfer gates TG11 and TG21 and the second transfer gates TG12 and TG22). A well region may be formed adjacent to the second surface 111F within the substrate 111. The well region may function as a drain and a source of the transistor.

[0102] The wiring layer 113 may include conductive lines 113-2, each of which includes a plurality of layers and is arranged in the interlayer insulating layer 113-1. The conductive lines 113-2 may transmit a control signal provided to each transistor or a signal between a pixel and the outside. The conductive lines 113-2 may be formed of a conductive material including a metal material such as copper or aluminum by using a patterning method, and may each extend in a first direction (e.g., an X-axis direction) and a second direction (e.g., a Y-axis direction).

[0103] exist Figure 4 In the pixel PXa of FIG. 1 , the internal wiring WR included in the conductive line 113-2 may be connected to the first floating diffusion area FD1 and the second floating diffusion area FD2 via the contact CT penetrating the interlayer insulating layer 113-1, and the first floating diffusion area FD1 may be electrically connected to the second floating diffusion area FD2. The internal wiring WR may be formed in the pixel area AR_PX. The internal wiring WR may electrically connect a plurality of sub-pixels (e.g., Figure 3 A plurality of floating diffusion regions (eg, Figure 4 The first floating diffusion area FD1 to the fourth floating diffusion area FD4).

[0104] Fig. 6A and Figure 6B is a plan view of pixels PXb and PXc according to example embodiments. Fig. 6A and Figure 6B The pixels PXb and PXc are Figure 4 Therefore, we will now focus on and describe Fig. 6A and Figure 6B and Figure 4 The difference between.

[0105] Reference Fig. 6A and Figure 6B , each of the pixels PXb and PXc may include a first sub-pixel SPX1 to a fourth sub-pixel SPX4, and the first sub-pixel SPX1 to the fourth sub-pixel SPX4 have the same structure. Each of the first sub-pixel SPX1 to the fourth sub-pixel SPX4 may include a first photoelectric conversion device PD1 to a fourth photoelectric conversion device PD4, a first transfer gate TG1 to a fourth transfer gate TG4, and a floating diffusion area. The first floating diffusion area FD1 to the fourth floating diffusion area FD4 may be arranged at the respective centers of the first sub-pixel SPX1 to the fourth sub-pixel SPX4, respectively. The internal wiring WR may be connected to the first floating diffusion area FD1 to the fourth floating diffusion area FD4 via the contact CT.

[0106] Each of the pixels PXb and PXc may include a reset gate RG, first and second drive gates SFG1 and SFG2, first and second select gates SG1 and SG2, and a dummy gate DMY. The first and second drive gates SFG1 and SFG2 may be connected to the internal wiring WR via a contact CT.

[0107] Reference Fig. 6A The internal wiring WR may extend in the second direction to connect the first floating diffusion area FD1 to the third floating diffusion area FD3 and the second floating diffusion area FD2 to the fourth floating diffusion area FD4. The internal wiring WR may also extend in the first direction to connect the first floating diffusion area FD1 to the second floating diffusion area FD2.

[0108] The first and second drive gates SFG1 and SFG2 and the first and second selection gates SG1 and SG2 may be arranged side by side in a first direction (e.g., X-axis direction) at the center of the pixel PXb. The first and second drive gates SFG1 and SFG2 and the first and second selection gates SG1 and SG2 may be arranged between the first and second sub-pixels SPX1 and SPX2 and the third and fourth sub-pixels SPX2 and SPX4.

[0109] The reset gate RG may be arranged in the upper portion (or lower portion, not shown) of the pixel PXb, and the dummy gate DMY may be arranged symmetrically with the reset gate RG in the first direction about the center of the pixel PXb. The reset gate RG and the dummy gate DMY may be arranged symmetrically with each other in the first direction about the internal wiring WR.

[0110] Reference Figure 6B , the internal wiring WR may extend in the second direction to connect the first floating diffusion area FD1 to the third floating diffusion area FD3 and the second floating diffusion area FD2 to the fourth floating diffusion area FD4. The internal wiring WR may also extend in the first direction to connect the first floating diffusion area FD1 and the third floating diffusion area FD3 to the second floating diffusion area FD2 and the fourth floating diffusion area FD4.

[0111] The first drive gate SFG1 and the second drive gate SFG2 and the first selection gate SG1 and the second selection gate SG2 may be arranged side by side along a second direction (e.g., the Y-axis direction) on one side (e.g., the left side (or right side, not shown) of the pixel PXc). The first drive gate SFG1 and the second drive gate SFG2 and the first selection gate SG1 and the second selection gate SG2 may be arranged parallel to each other. Figure 1 The column lines CL are arranged.

[0112] The reset gate RG and the dummy gate DMY may be disposed at the center of the pixel PXc, and may be arranged symmetrically to each other in the second direction about the center of the pixel PXa.

[0113] As mentioned above Fig. 6A As described above, the first and second driving gates SFG1 and SFG2 and the first and second selection gates SG1 and SG2 may be disposed at the center of the pixel PXc, and the dummy gate DMY may be disposed outside the pixel PXc, for example, at one side of the pixel PXb.

[0114] As mentioned above Figure 6B As described above, the first and second driving gates SFG1 and SFG2 and the first and second selection gates SG1 and SG2 may be arranged side by side along the second direction at one side of the pixel PXc, and the reset gate RG and the dummy gate DMY may be arranged side by side along the second direction at the center of the pixel PXc.

[0115] Figure 7 is a plan view of a pixel PXd according to example embodiments. Figure 7 The pixel PXd is Figure 4 Therefore, we will now focus on and describe Figure 7 and Figure 4 The difference between.

[0116] Reference Figure 7 , the pixel PXd may include the first subpixel SPX1 to the fourth subpixel SPX4, and the first subpixel SPX1 to the fourth subpixel SPX4 have the same structure. The first floating diffusion area FD1 to the fourth floating diffusion area FD4 may be arranged at the center of each of the first subpixel SPX1 to the fourth subpixel SPX4, respectively. The internal wiring WR may be connected to the first floating diffusion area FD1 to the fourth floating diffusion area FD4 via the contact CT.

[0117] The pixel PXd may include a reset gate RG, a driving gate SFG, a selection transistor SG, and a dummy gate DMY.

[0118] and Figure 4 Compared to the pixel PXa, the pixel PXd may include a single drive gate SFG and a single select transistor SG.

[0119] The driving gate SFG and the selection transistor SG may be disposed at the center of an upper portion of the pixel PXd. The driving gate SFG may be connected to the internal wiring WR via a contact CT.

[0120] The dummy gate DMY may be arranged symmetrically with the selection transistor SG in the first direction with respect to the driving gate SFG.

[0121] The internal wiring WR may extend in the first direction to connect the first floating diffusion area FD1 to the second floating diffusion area FD2 and the third floating diffusion area FD3 to the fourth floating diffusion area FD4. The internal wiring WR may also extend in the second direction to connect the first floating diffusion area FD1 and the second floating diffusion area FD2 to the third floating diffusion area FD3 and the fourth floating diffusion area FD4. The first terminal T1 of the internal wiring WR may be connected to the drive gate SFG via the contact CT.

[0122] Figure 8 is a circuit diagram of a pixel PXf according to an example embodiment. Figure 8 The pixel PXf is suitable for Figure 2 The pixel array 110 includes first to fourth pixels PX1 to PX4.

[0123] Reference Figure 8 , the pixel PXf may include first to fourth sub-pixels SPX1 to SPX4, a reset transistor RX, a gain control transistor CX, first and second drive transistors DX1 and DX2, and first and second select transistors SX1 and SX2. The reset transistor RX, the gain control transistor CX, the first and second drive transistors DX1 and DX2, and the first and second select transistors SX1 and SX2 may constitute an output circuit of the pixel PXf.

[0124] and Figure 3 Compared with the pixel PXa, the pixel PXf may further include a gain control transistor CX.

[0125] The gain control transistor CX may be turned on in response to the gain control signal CS. A capacitor may be formed on the drain of the gain control transistor CX and may store charge. The drain of the gain control transistor CX may be referred to as a floating diffusion node FN1. When the reset transistor RX is turned off and the gain control transistor CX is turned on, the floating diffusion node FN1 may be electrically connected to the floating diffusion node FN, and thus the capacitance of the floating diffusion node FN may increase.

[0126] The conversion gain of the pixel PXf may be inversely proportional to the capacitance of the floating diffusion node FN, and thus the conversion gain when the gain control transistor CX is turned off may be higher than the conversion gain CX when the gain control transistor CX is turned on. When the gain control transistor CX is turned off, this may be referred to as a high conversion gain (HCG) mode, and when the gain control transistor CX is turned on, this may be referred to as a low conversion gain (LCG) mode. When a small amount of light is incident on the pixel PXf at night or in a dark environment, the conversion gain may be increased. Figure 1 When the pixel array 110 of the image sensor 100 is on, the pixel array 110 can operate in the HCG mode. The minimum amount of light that can be sensed can be due to Figure 1 The signal-to-noise ratio (SNR) of the image sensor 100 is increased, and the low light sensing performance of the image sensor 100 can be improved. When a large amount of light is incident on the image sensor 100 (for example, in daytime or bright environment), Figure 1 When the pixel array 110 of the image sensor 100 is connected to the pixel array 110, the pixel array 110 can operate in the LCG mode. The full well capacity (FWC) of the pixel PXf can be increased, so the high light sensing performance of the image sensor 100 can be improved.

[0127] As described above, the pixel PXf can provide a dual conversion gain, so the image sensor 100 can generate high-quality images in bright environments and dark environments. The image sensor 100 can continuously generate a first image generated in the HCG mode and a second image generated in the LCG mode, and can combine the first image with the second image to generate an image with a high dynamic range.

[0128] Although the pixel PXf includes Figure 8A single gain control transistor CX in the pixel PXf is used, but this can vary, for example, the pixel PXf can include two or more gain control transistors CX connected in series with each other. The conversion gain of the pixel PXf can be determined according to the number of gain control transistors CX that are turned on. For example, in the case of a pixel based on the pixel PXf but including two gain control transistors CX, when both gain control transistors CX are turned off, this can be referred to as HCG mode, when one of the two gain control transistors CX is turned on, this can be referred to as intermediate conversion gain (MCG), and when the two gain control transistors CS are turned on, this can be referred to as LCG mode.

[0129] Fig. 9A , Fig. 9B and Fig. 9C is a plan view of pixels PXf1 , PXf2 , and PXf3 according to example embodiments. Fig. 9A , Fig. 9B and Fig. 9C The pixels PXf1, PXf2 and PXf3 are Figure 4 Therefore, we will now focus on and describe Fig. 9A , Fig. 9B and Fig. 9C and Figure 4 The difference between.

[0130] Reference Fig. 9A , the pixel PXf1 may include first to fourth subpixels SPX1 to SPX4, and the first to fourth subpixels SPX1 to SPX4 have the same structure. The first to fourth floating diffusion areas FD1 to FD4 may be arranged at the respective centers of the first to fourth subpixels SPX1 to SPX4, respectively. The internal wiring WR may be connected to the first to fourth floating diffusion areas FD1 to FD4 via the contact CT.

[0131] The pixel PXf1 may include first and second driving gates SFG1 and SFG2, first and second selection gates SG1 and SG2, a reset gate RG, a gain control gate CG, and a dummy gate DMY. The first and second driving gates SFG1 and SFG2 may be connected to the internal wiring WR via a contact CT.

[0132] The first drive gate SFG1 and the second drive gate SFG2 and the first selection gate SG1 and the second selection gate SG2 may be arranged side by side along the first direction at the upper portion (or lower portion, not shown) of the pixel PXf1. The reset gate RG, the gain control gate CG, and the dummy gate DMY may be arranged side by side along the first direction between the first and second sub-pixels SPX1 and SPX2 and the third and fourth sub-pixels SPX3 and SPX4. The reset gate RG may be arranged at the center of the pixel PXf1. The gain control gate CG and the dummy gate DMY may be arranged symmetrically with respect to the reset gate RG.

[0133] The wiring WRfd may be connected to the well region between the conversion gate CG and the reset gate RG via the contact CT, that is, to the Figure 8 The floating diffusion node FN1 of the adjacent pixel PXf1 may be connected to the floating diffusion node FN1 of the adjacent pixel PXf1. The wiring WRfd may extend in the first direction and / or the second direction, so that a capacitor may be formed on the floating diffusion node FN1. As the length of the wiring WRfd increases, the capacitance of the floating diffusion node FN1 may increase. The wiring WRfd may be connected to the floating diffusion node FN1 of the adjacent pixel PXf1, so that the adjacent pixel PXf1 may share the floating diffusion node FN1.

[0134] In the implementation method (not in Fig. 9A ), the first drive gate SFG1 and the second drive gate SFG2 and the first selection gate SG1 and the second selection gate SG2 can be arranged side by side along the second direction on the left or right side of the pixel PXf1, and the reset gate RG, the gain control gate CG and the dummy gate DMY can be arranged side by side along the second direction between the first and third sub-pixels SPX1 and SPX3 and the second and fourth sub-pixels SPX2 and SPX4.

[0135] Reference Fig. 9B The pixel PXf2 may include first to fourth subpixels SPX1 to SPX4, first and second driving gates SFG1 and SFG2, first and second selection gates SG1 and SG2, a reset gate RG, a gain control gate CG, and a dummy gate DMY.

[0136] The first selection gate SG1 and the second selection gate SG2 may be arranged side by side along the first direction between the first and second sub-pixels SPX1 and SPX2 and the third and fourth sub-pixels SPX3 and SPX4. The reset gate RG, the gain control gate CG and the dummy gate DMY may be arranged side by side along the first direction at the upper portion (or lower portion, not shown) of the pixel PXf2.

[0137] In the implementation method (not in Fig. 9B), the first drive gate SFG1 and the second drive gate SFG2 and the first selection gate SG1 and the second selection gate SG2 can be arranged side by side along the second direction between the first and third sub-pixels SPX1 and SPX3 and the second and fourth sub-pixels SPX2 and SPX4, and the reset gate RG, the gain control gate CG and the dummy gate DMY can be arranged side by side along the first direction on the left or right side of the pixel PXf2.

[0138] Reference Fig. 9C The pixel PXf3 may include first to fourth sub-pixels SPX1 to SPX4, first and second driving gates SFG1 and SFG2, first and second selection gates SG1 and SG2, a reset gate RG, and a gain control gate CG.

[0139] Fig. 9C The structure of the pixel PXf3 is Fig. 9A However, the pixel PXf3 does not include the dummy gate DMY, and the reset gate RG and the gain control gate CG may be symmetrically arranged in the first direction with respect to the pixel PXf3.

[0140] Fig. 10A and Fig. 10B is a plan view of pixels PXg1 and PXg2 according to example embodiments. Fig. 10A The pixel PXg1 is Fig. 9A Therefore, we will now focus on and describe Fig. 9A and Fig. 10A The difference between.

[0141] Reference Fig. 10A , the pixel PXg1 may include first to fourth subpixels SPX1 to SPX4, and the first to fourth subpixels SPX1 to SPX4 have the same structure. The first to fourth floating diffusion areas FD1 to FD4 may be arranged at the respective centers of the first to fourth subpixels SPX1 to SPX4, respectively. The internal wiring WR may be connected to the first to fourth floating diffusion areas FD1 to FD4 via the contact CT.

[0142] The pixel PXg1 may include a driving gate SFG, a selection gate SG, a reset gate RG, a gain control gate CG, and a dummy gate DMY. The driving gate SFG may be connected to the internal wiring WR via a contact CT.

[0143] The reset gate RG, the gain control gate CG and the dummy gate DMY may be arranged side by side in the first direction between the first and second subpixels SPX1 and SPX2 and the third and fourth subpixels SPX3 and SPX4. The gain control gate CG and the dummy gate DMY may be arranged symmetrically to each other in the first direction about the reset gate RG.

[0144] and Fig. 9A Compared with the pixel PXf1, the pixel PXg1 includes a single drive gate SFG and a single select transistor SG.

[0145] The driving gate SFG and the selection transistor SG may be disposed at the center of an upper portion (or a lower portion, not shown) of the pixel PXg1.

[0146] In the implementation method (not in Fig. 10A ), the dummy gate may be arranged symmetrically with the selection transistor SG about the driving gate SFG in the first direction.

[0147] In the implementation method (not in Fig. 10A ), the driving gate SFG and the selection transistor SG can be arranged side by side along the first direction between the first and second sub-pixels SPX1 and SPX2 and the third and fourth sub-pixels SPX3 and SPX4, and the reset gate RG, the gain control gate CG and the dummy gate DMY can be arranged side by side along the first direction at the top or bottom of the pixel PXg1.

[0148] In the implementation method (not in Fig. 10A ), the reset gate RG, the gain control gate CG, and the dummy gate DMY may be arranged side by side along the second direction between the first and third sub-pixels SPX1 and SPX3 and the second and fourth sub-pixels SPX2 and SPX4, and the drive gate SFG and the selection transistor SG may be arranged side by side along the second direction at the center of the left side or right side of the pixel PXg1. Alternatively, the drive gate SFG and the selection transistor SG may be arranged side by side along the second direction between the first and third sub-pixels SPX1 and SPX3 and the second and fourth sub-pixels SPX2 and SPX4, and the reset gate RG, the gain control gate CG, and the dummy gate DMY may be arranged side by side along the second direction at the center of the left side or right side of the pixel PXg1.

[0149] Reference Fig. 10B , the pixel PXg2 may not include the dummy gate DMY, and the reset gate RG and the gain control gate CG may be arranged symmetrically to each other in the first direction about the center of the pixel PXg2.

[0150] Fig.11A , Fig. 11B and Fig. 11C is a plan view of pixels PXh1 , PXh2 , and PXh3 according to example embodiments. Fig.11A The pixel PXh1 is Fig. 9A Therefore, we will now focus on and describe Fig. 9A and Fig.11A The difference between.

[0151] Reference Fig.11A , the pixel PXh1 may include first to fourth subpixels SPX1 to SPX4, and the first to fourth subpixels SPX1 to SPX4 have the same structure. The first to fourth floating diffusion areas FD1 to FD4 may be arranged at the respective centers of the first to fourth subpixels SPX1 to SPX4, respectively. The internal wiring WR may be connected to the first to fourth floating diffusion areas FD1 to FD4 via the contact CT.

[0152] The pixel PXh1 may include first and second drive gates SFG1 and SFG2, first and second selection gates SG and SG2, a reset gate RG, first and second gain control gates CG1 and CG2, and a dummy gate DMY. The first and second drive gates SFG1 and SFG2 may be connected to the internal wiring WR via a contact CT.

[0153] The first drive gate SFG1 and the second drive gate SFG2 and the first selection gate SG1 and the second selection gate SG2 may be arranged side by side along the first direction at the upper portion (or lower portion, not shown) of the pixel PXh1. The second gain control gate CG2, the first gain control gate CG1, the reset gate RG, and the dummy gate DMY may be arranged side by side along the first direction between the first and second sub-pixels SPX1 and SPX2 and the third and fourth sub-pixels SPX3 and SPX4. The second gain control gate CG2 and the dummy gate DMY may be arranged symmetrically with respect to the center of the pixel PXh1 in the first direction. The first gain control gate CG1 and the reset gate RG may be arranged symmetrically with respect to each other in the first direction.

[0154] The wiring WRfd1 may be connected to a well region between the first conversion gate CG1 and the reset gate RG via a contact CT. The wiring WRfd2 may be connected to a well region between the second conversion gate CG2 and the first conversion gate CG1. Each of the wirings WRfd1 and WRfd2 may extend in the first direction and / or the second direction. At least one of the wirings WRfd1 and WRfd2 may be connected to one of the floating diffusion nodes of the adjacent pixel PXh1.

[0155] In the implementation method (not in Fig.11A), the first drive gate SFG1 and the second drive gate SFG2 and the first selection gate SG1 and the second selection gate SG2 can be arranged side by side along the second direction on the left or right side of the pixel PXh1, and the second gain control gate CG2, the first gain control gate CG1, the reset gate RG and the dummy gate DMY can be arranged side by side along the second direction between the first and third sub-pixels SPX1 and SPX3 and the second and fourth sub-pixels SPX2 and SPX4.

[0156] Reference Fig. 11B The pixel PXh2 may include first to fourth subpixels SPX1 to SPX4, first and second driving gates SFG1 and SFG2, first and second selection gates SG1 and SG2, a reset gate RG, first and second gain control gates CG1 and CG2, and a dummy gate DMY.

[0157] The first selection gate SG1 and the second selection gate SG2 and the first drive gate SFG1 and the second drive gate SFG2 may be arranged side by side along the first direction between the first and second sub-pixels SPX1 and SPX2 and the third and fourth sub-pixels SPX3 and SPX4. The second gain control gate CG2, the first gain control gate CG1, the reset gate RG and the dummy gate DMY may be arranged side by side along the first direction at the upper portion (or lower portion, not shown) of the pixel PXh2.

[0158] In the implementation method (not in Fig. 11B ), the first drive gate SFG1 and the second drive gate SFG2 and the first selection gate SG1 and the second selection gate SG2 can be arranged side by side along the second direction between the first and third sub-pixels SPX1 and SPX3 and the second and fourth sub-pixels SPX2 and SPX4, and the second gain control gate CG2, the first gain control gate CG1, the reset gate RG and the dummy gate DMY can be arranged side by side along the first direction on the left or right side of the pixel PXh2.

[0159] Reference Fig. 11C The pixel PXh3 may include first to fourth subpixels SPX1 to SPX4, first and second driving gates SFG1 and SFG2, first and second selection gates SG1 and SG2, a reset gate RG, a first gain control gate CG1, and a second gain control gate CG2.

[0160] Except that the pixel PXh3 does not include a dummy gate DMY, Fig. 11C The structure of the pixel PXh3 is Fig.11A The structure of the pixel PXh1 is similar.

[0161] The second gain control gate CG2, the first gain control gate CG1 and the reset gate RG may be arranged side by side in the first direction at the center of the pixel PXh3. The first gain control gate CG1 may be arranged at the center of the pixel PXh3, and the second gain control gate CG2 and the reset gate RG may be arranged symmetrically with respect to the first gain control gate CG1 in the first direction.

[0162] Fig. 12A , Fig. 12B and Fig. 12C is a plan view of pixels PXi1 , PXi2 , and PXi3 according to example embodiments. Fig. 12A The pixel PXi1 is Fig.11A Therefore, we will now focus on and describe Fig. 12A and Fig.11A The difference between.

[0163] Reference Fig. 12A , the pixel PXi1 may include first to fourth subpixels SPX1 to SPX4, and the first to fourth subpixels SPX1 to SPX4 have the same structure. The first to fourth floating diffusion areas FD1 to FD4 may be arranged at the respective centers of the first to fourth subpixels SPX1 to SPX4, respectively. The internal wiring WR may be connected to the first to fourth floating diffusion areas FD1 to FD4 via the contact CT.

[0164] The pixel PXi1 may include a driving gate SFG, a selection gate SG, a reset gate RG, a first gain control gate CG1, a second gain control gate CG2, and a dummy gate DMY. The driving gate SFG may be connected to an internal wiring WR via a contact CT.

[0165] The driving gate SFG and the selection transistor SG may be arranged side by side along the first direction at an upper portion (or a lower portion, not shown) of the pixel PXi1.

[0166] In the implementation method (not in Fig. 12A ), the dummy gate DMY may be arranged symmetrically with the selection transistor SG about the driving gate SFG in the first direction.

[0167] The second gain control gate CG2 , the first gain control gate CG1 , the reset gate RG, and the dummy gate DMY may be arranged side by side in the first direction between the first and second sub-pixels SPX1 and SPX2 and the third and fourth sub-pixels SPX3 and SPX4 .

[0168] In the implementation method (not in Fig. 12A), the driving gate SFG and the selection transistor SG can be arranged side by side along the second direction on the left or right side of the pixel PXi1, and the second gain control gate CG2, the first gain control gate CG1, the reset gate RG and the dummy gate DMY can be arranged side by side along the second direction between the first and third sub-pixels SPX1 and SPX3 and the second and fourth sub-pixels SPX2 and SPX4.

[0169] Reference Fig. 12B The pixel PXh2 may include first to fourth sub-pixels SPX1 to SPX4, a driving gate SFG, a selection transistor SG, a reset gate RG, a first gain control gate CG1, a second gain control gate CG2, and a dummy gate DMY.

[0170] The driving gate SFG and the selection transistor SG may be arranged side by side along the first direction between the first and second sub-pixels SPX1 and SPX2 and the third and fourth sub-pixels SPX3 and SPX4. The second gain control gate CG2, the first gain control gate CG1, the reset gate RG and the dummy gate DMY may be arranged side by side along the first direction at the upper portion (or lower portion, not shown) of the pixel PXi2.

[0171] In the implementation method (not in Fig. 12B ), the driving gate SFG and the selection transistor SG can be arranged side by side along the second direction between the first and third sub-pixels SPX1 and SPX3 and the second and fourth sub-pixels SPX2 and SPX4, and the second gain control gate CG2, the first gain control gate CG1, the reset gate RG and the dummy gate DMY can be arranged side by side along the first direction on the left or right side of the pixel PXi2.

[0172] Reference Fig. 12C The pixel PXi3 may include first to fourth sub-pixels SPX1 to SPX4, a driving gate SFG, a selection transistor SG, a second gain control gate CG2, a first gain control gate CG1, and a reset gate RG.

[0173] Except that the pixel PXi3 does not include a dummy gate DMY, Fig. 12C The structure of the pixel PXi3 is Fig.11A The structure of the pixel PXh3 is similar.

[0174] The second gain control gate CG2, the first gain control gate CG1 and the reset gate RG may be arranged side by side in the first direction at the center of the pixel PXi3. The first gain control gate CG1 may be arranged at the center of the pixel PXi3, and the second gain control gate CG2 and the reset gate RG may be arranged symmetrically with respect to the first gain control gate CG1 in the first direction.

[0175] Fig.13A , Fig. 13B , Fig. 13C , Fig.13D , Fig.13E and Fig.13F is a plan view of pixels PXj1, PXj2, PXj3, PXj4, PXj5, and PXj6 according to example embodiments.

[0176] Reference FIG. 13A to FIG. 13F , the pixels PXj1 , PXj2 , PXj3 , PXj4 , PXj5 , and PXj6 may include first to fourth sub-pixels SPX1 to SPX4 .

[0177] The first to fourth sub-pixels SPX1 to SPX4 may be arranged side by side in a first direction (eg, an X-axis direction). The first direction may be Figure 1 The row direction of the pixel array 110.

[0178] Each of the first to fourth subpixels SPX1 to SPX4 may include first to fourth photoelectric conversion devices PD1 to PD4, first to fourth transfer gates TG1 to TG4, and floating diffusion regions FD. The first to fourth floating diffusion regions FD1 to FD4 may be arranged at respective centers of the first to fourth subpixels SPX1 to SPX4, respectively. The internal wiring WR may be connected to the first to fourth floating diffusion regions FD1 to FD4 via contacts CT.

[0179] Reference Fig.13A , the pixel PXj1 may include a driving gate SFG, a selection gate SG, a reset gate RG, and a dummy gate DMY.

[0180] The dummy gate DMY, the reset gate RG, the driving gate SFG, and the selection gate SG may be arranged side by side along the first direction at an upper portion (or a lower portion, not shown) of the pixel PXj1.

[0181] The driving gate SFG, selecting gate SG, reset gate RG and dummy gate DMY may be arranged at the center of the upper portion (or lower portion, not shown) of the pixel PXj1, but their respective positions may be adjusted.

[0182] The source of the reset gate RG and the drive gate SFG may be connected to the internal wiring WR via a contact CT.

[0183] Reference Fig. 13B , the pixel PXj2 can also drive the gate SFG, the selection gate SG, the reset gate RG, the gain control gate CG and the dummy gate DMY.

[0184] The dummy gate DMY, reset gate RG, gain control gate CG, drive gate SFG and selection gate SG may be arranged side by side along the first direction at the upper portion (or lower portion, not shown) of the pixel PXj2. The gain control gate CG and the dummy gate DMY may be arranged at both sides of the reset gate RG, respectively.

[0185] The wiring WRfd1 may be connected to a well region between the reset gate RG and the gain control gate CG via a contact CT, and may extend in the first direction and the second direction.

[0186] Reference Fig. 13C The pixel PXj3 may include a driving gate SFG, a selection gate SG, a reset gate RG, a first gain control gate CG1 and a second gain control gate CG2, and a dummy gate DMY.

[0187] The dummy gate DMY, the reset gate RG, the first and second gain control gates CG1 and CG2, the driving gate SFG, and the selection gate SG may be arranged side by side along the first direction at an upper portion (or lower portion, not shown) of the pixel PXj3.

[0188] The wirings WRfd1 and WRfd2 may be connected to a well region between the reset gate RG and the first gain control gate CG1 and a well region between the first and second gain control gates CG1 and CG2 via contacts CT, respectively. Each of the wirings WRfd1 and WRfd2 may extend in the first and second directions.

[0189] Reference Fig.13D , the pixel PXj4 may include first and second driving gates SFG1 and SFG2, first and second selection gates SG1 and SG2, a reset gate RG, and a dummy gate DMY.

[0190] The dummy gate DMY, the reset gate RG, the first drive gate SFG1, the first and second selection gates SG1 and SG2, and the second drive gate SFG2 may be arranged side by side along the first direction at the upper portion (or (lower portion, not shown) of the pixel PXj2. The first and second selection gates SG1 and SG2 may be arranged between the first and second drive gates SFG1 and SFG2.

[0191] Sources of the first drive gate SFG1 , the second drive gate SFG2 , and the reset gate RG may be connected to the internal wiring WR via a contact CT.

[0192] Reference Fig.13E, the pixel PXj5 may include first and second driving gates SFG1 and SFG2, first and second selection gates SG1 and SG2, a reset gate RG, a gain control gate CG, and a dummy gate DMY.

[0193] The dummy gate DMY, the reset gate RG, the gain control gate CG, the first driving gate SFG1, the first and second selection gates SG1 and SG2, and the second driving gate SFG2 may be arranged side by side along the first direction at the upper portion (or lower portion, not shown) of the pixel PXj5.

[0194] Reference Fig.13F The pixel PXj6 may include first and second driving gates SFG1 and SFG2, first and second selection gates SG1 and SG2, a reset gate RG, first and second gain control gates CG1 and CG2, and a dummy gate DMY.

[0195] The dummy gate DMY, the reset gate RG, the first and second control gates CG1 and CG2, the first drive gate SFG1, the first and second selection gates SG1 and SG2, and the second drive gate SFG2 can be arranged side by side along the first direction at the upper part (or lower part, not shown) of the pixel PXj6.

[0196] Fig.14A , Fig. 14B , Fig. 14C , Fig.14D , Fig.14E and Fig.14F is a plan view of pixels PXk1 , PXk2 , PXk3 , PXk4 , PXk5 , and PXk6 according to example embodiments.

[0197] Reference FIG. 14A to FIG. 14F , the pixels PXk1 , PXk2 , PXk3 , PXk4 , PXk5 , and PXk6 may include first to fourth sub-pixels SPX1 to SPX4 .

[0198] The first to fourth sub-pixels SPX1 to SPX4 may be arranged side by side in the second direction (eg, the Y-axis direction). The second direction may be Figure 1 The column direction of the pixel array 110.

[0199] Each of the first to fourth sub-pixels SPX1 to SPX4 may include first to fourth photoelectric conversion devices PD1 to PD4 , first to fourth transfer gates TG1 to TG4 , and a floating diffusion area FD.

[0200] The first to fourth floating diffusion areas FD1 to FD4 may be arranged at respective centers of the first to fourth subpixels SPX1 to SPX4, respectively. The internal wiring WR may be connected to the first to fourth floating diffusion areas FD1 to FD4 via contacts CT.

[0201] Reference Fig.14A , the pixel PXk1 may include a driving gate SFG, a selection gate SG, a reset gate RG, and a dummy gate DMY.

[0202] The dummy gate DMY, the reset gate RG, the driving gate SFG, and the selection gate SG may be arranged side by side along the second direction at a left portion (or a right portion, not shown) of the pixel PXk1.

[0203] The driving gate SFG, the selecting gate SG, the reset gate RG and the dummy gate DMY may be arranged at the center of the left portion (or right portion, not shown) of the pixel PXk1. However, their respective positions may be adjusted.

[0204] The source of the reset gate RG and the drive gate SFG may be connected to the internal wiring WR via a contact CT.

[0205] Reference Fig. 14B , the pixel PXk2 may include a driving gate SFG, a selection gate SG, a reset gate RG, a gain control gate CG and a dummy gate DMY.

[0206] The dummy gate DMY, the reset gate RG, the control gate CG, the drive gate SFG, and the selection gate SG may be arranged side by side along the second direction at a left portion (or a right portion, not shown) of the pixel PXk2.

[0207] The gain control gate CG and the dummy gate DMY may be disposed above and below the reset gate RG, respectively. The wiring WRfd1 may be connected to a well region between the reset gate RG and the gain control gate CG via a contact CT, and may extend in the first and second directions.

[0208] Reference Fig. 14C The pixel PXk3 may include a driving gate SFG, a selection gate SG, a reset gate RG, first and second gain control gates CG1 and CG2, and a dummy gate DMY.

[0209] The dummy gate DMY, the reset gate RG, the first and second gain control gates CG1 and CG2 , the driving gate SFG, and the selection gate SG may be arranged side by side along the second direction at the left (or right, not shown) of the pixel PXk3 .

[0210] The wirings WRfd1 and WRfd2 may be connected to a well region between the reset gate RG and the first gain control gate CG1 and a well region between the first and second gain control gates CG1 and CG2 via contacts CT, respectively. Each of the wirings WRfd1 and WRfd2 may extend in the first and second directions.

[0211] Reference Fig.14D , the pixel PXk4 may include first and second driving gates SFG1 and SFG2 , first and second selection gates SG1 and SG2 , a reset gate RG, and a dummy gate DMY.

[0212] The dummy gate DMY, the reset gate RG, the first driving gate SFG1, the first and second selection gates SG1 and SG2, and the second driving gate SFG2 may be arranged side by side along the second direction at the left portion (or (right portion, not shown) of the pixel PXk2. The first and second selection gates SG1 and SG2 may be arranged between the first and second driving gates SFG1 and SFG2.

[0213] Sources of the first drive gate SFG1 , the second drive gate SFG2 , and the reset gate RG may be connected to the internal wiring WR via a contact CT.

[0214] Reference Fig.14E , the pixel PXk5 may include first and second driving gates SFG1 and SFG2 , first and second selection gates SG1 and SG2 , a reset gate RG, a gain control gate CG, and a dummy gate DMY.

[0215] The dummy gate DMY, the reset gate RG, the control gate CG, the first driving gate SFG1, the first and second selection gates SG1 and SG2, and the second driving gate SFG2 may be arranged side by side along the second direction at the left (or right, not shown) of the pixel PXk5.

[0216] Reference Fig.14F , the pixel PXk6 may include first and second driving gates SFG1 and SFG2, first and second selection gates SG1 and SG2, a reset gate RG, first and second gain control gates CG1 and CG2, and a dummy gate DMY.

[0217] The dummy gate DMY, the reset gate RG, the first and second gain control gates CG1 and CG2, the first drive gate SFG1, the first and second selection gates SG1 and SG2, and the second drive gate SFG2 can be arranged side by side along the second direction at the left (or right, not shown) of the pixel PXk6.

[0218] Fig.15A , Fig. 15B and Fig. 15C is a plan view of pixels PX11 , PX12 , and PX13 according to example embodiments.

[0219] Reference FIG. 15A to FIG. 15C , the pixels PXl1 , PXl2 , and PXl3 may include first to fourth sub-pixels SPX1 to SPX4 .

[0220] The first to fourth sub-pixels SPX1 to SPX4 may be arranged side by side in the second direction (eg, the Y-axis direction). The second direction may be Figure 1 The column direction of the pixel array 110.

[0221] Each of the first to fourth sub-pixels SPX1 to SPX4 may include first to fourth photoelectric conversion devices PD1 to PD4 , first to fourth transfer gates TG1 to TG4 , and a floating diffusion area FD.

[0222] The first to fourth floating diffusion areas FD1 to FD4 may be arranged at respective centers of the first to fourth subpixels SPX1 to SPX4, respectively. The internal wiring WR may be connected to the first to fourth floating diffusion areas FD1 to FD4 via contacts CT.

[0223] Reference Fig.15A , the pixel PX11 may include first and second driving gates SFG1 and SFG2 , first and second selection gates SG1 and SG2 , a reset gate RG, and first to third dummy gates DMY1 to DMY3 .

[0224] The first dummy gate DMY1, the first selection gate SG1, the first drive gate SFG1, the second dummy gate DMY2, the reset gate RG, the second drive gate SFG2, the second selection gate SG2 and the third dummy gate DMY3 may be arranged side by side along the second direction at the left (or right, not shown) of the pixel PXl1.

[0225] The first driving gate SFG1 and the first selection gate SG1 may be disposed between the first dummy gate DMY1 and the second dummy gate DMY2. The reset gate RG, the second driving gate SFG2 and the second selection gate SG2 may be sequentially disposed between the second dummy gate DMY2 and the third dummy gate DMY3.

[0226] Sources of the first drive gate SFG1 , the second drive gate SFG2 , and the reset gate RG may be connected to the internal wiring WR via a contact CT.

[0227] Reference Fig. 15B ,and Fig.15A Compared with the pixel PXl1, the pixel PXl2 may further include a gain control gate CG.

[0228] The gain control gate CG may be disposed between the reset gate RG and the second drive gate SFG2. The wiring WRfd1 may be connected to a well region between the reset gate RG and the gain control gate CG via a contact CT and may extend in the first direction and the second direction.

[0229] Reference Fig. 15C ,and Fig.15A Compared with the pixel PXl1, the pixel PXl3 may further include a first gain control gate CG1 and a second gain control gate CG2.

[0230] The first gain control gate CG1 and the second gain control gate CG2 may be disposed between the reset gate RG and the second drive gate SFG2. The wirings WRfd1 and WRfd2 may be connected to the well region between the reset gate RG and the first gain control gate CG1 and the well region between the first gain control gate CG1 and the second gain control gate CG2 via contacts CT, respectively. Each of the wirings WRfd1 and WRfd2 may extend in the first direction and the second direction.

[0231] Fig.16A , Fig. 16B , Fig. 16C and Fig.16D A microlens ML arranged in a pixel PX according to example embodiments is illustrated.

[0232] The pixels according to the various embodiments described above are applied to the pixel PX according to the present embodiment.

[0233] The pixel PX may include first to fourth subpixels SPX1 to SPX4. Each of the first to fourth subpixels SPX1 to SPX4 may include a floating diffusion region FD and a plurality of photoelectric conversion devices PD. The plurality of photoelectric conversion devices PD included in the first to fourth subpixels SPX1 to SPX4 may be connected to each other via internal wiring.

[0234] Reference Fig.16A , a microlens ML may be arranged above each photoelectric conversion device PD. A plurality of microlenses ML may be arranged for each of the plurality of photoelectric conversion devices PD included in the pixel PX. The pixel PX may output a pixel signal based on charges respectively generated by the plurality of photoelectric conversion devices PD, or may output a pixel signal based on charges respectively generated by some or all of the plurality of photoelectric conversion devices PD.

[0235] Reference Fig. 16B, the microlens ML may be arranged above a group of four photoelectric conversion devices PD included in each of the first to fourth subpixels SPX1 to SPX4. Therefore, a single microlens ML may be arranged in each of the first to fourth pixels SPX1 to SPX4. The pixel PX may output a pixel signal based on charges generated by the first to fourth pixels SPX1 to SPX4, respectively, or may output a pixel signal based on charges generated by some or all of the first to fourth pixels SPX1 to SPX4, respectively.

[0236] Reference Fig. 16C and Fig.16D , a single microlens ML may be arranged for every two adjacent photoelectric conversion devices among the plurality of photoelectric conversion devices PD. Fig. 16C As shown, a single microlens ML may be arranged on two photoelectric conversion devices adjacent to each other along the first direction. Fig.16D As shown, a single microlens ML may be arranged on two photoelectric conversion devices adjacent to each other along the second direction.

[0237] In another embodiment (not in Fig. 16C and Fig.16D ), the microlens ML may be arranged on two photoelectric conversion devices adjacent to each other along a first direction in some of the first to fourth subpixels SPX1 to SPX4, and the microlens ML may be arranged on two photoelectric conversion devices adjacent to each other along a second direction in other subpixels SPX1 to SPX4.

[0238] Fig.17A , Fig. 17B , Fig. 17C , Fig.17D , Fig.17E and Fig.17F Color filters arranged in the pixel array 110 according to example embodiments are shown.

[0239] The pixels according to the various embodiments described above are applied to the pixel PX according to the present embodiment.

[0240] The pixel PX may include first to fourth subpixels SPX1 to SPX4. Each of the first to fourth subpixels SPX1 to SPX4 may include a floating diffusion region FD and a plurality of photoelectric conversion devices PD. The plurality of photoelectric conversion devices PD included in the first to fourth subpixels SPX1 to SPX4 may be connected to each other via internal wiring.

[0241] Reference Fig.17A , the first to fourth pixels PX1 to PX4 may be arranged in a 2×2 matrix.

[0242] The color filters may be arranged per pixel. A red color filter CF_R may be arranged on the first pixel PX1. A green color filter CF_G may be arranged on the second pixel PX2 and the third pixel PX3. A blue color filter CF_B may be arranged on the fourth pixel PX4.

[0243] The above combination of one red color filter CF_R, two green color filters CF_G, and one blue color filter CF_B may be referred to as a Bayer pattern.

[0244] In the pixel array 110 , every four pixels arranged in a 2×2 matrix may have a Bayer pattern.

[0245] In other embodiments (not in Fig.17A ), the color combination of the color filters arranged on the first pixel PX1 to the fourth pixel PX4 may be changed. For example, a white color filter may be arranged on one of the second pixel PX2 and the third pixel PX3. As another example, a white color filter may be arranged on the second pixel PX2 and the third pixel PX3. As another example, a yellow color filter may be arranged on the second pixel PX2 and the third pixel PX3.

[0246] Reference Fig. 17B , the first to fourth sub-pixels SPX1 to SPX4 may be arranged in a 2×2 matrix.

[0247] and Fig.17A In contrast, in FIG. 17 , color filters may be arranged per sub-pixel. A red color filter CF_R may be arranged on a first sub-pixel SPX1. A green color filter CF_G may be arranged on a second sub-pixel SPX2 and a third sub-pixel SPX3. A blue color filter CF_B may be arranged on a fourth sub-pixel SPX4. Each of the plurality of pixels PX arranged in the pixel array 110 may have a Bayer pattern.

[0248] Reference Fig. 17C , the first to fourth pixels PX1 to PX4 may be arranged in the second direction. Each of the first to fourth pixels PX1 to PX4 may include first to fourth sub-pixels SPX1 to SPX4 arranged side by side in the first direction.

[0249] A red color filter CF_R may be arranged in the first and second sub-pixels SPX1 and SPX2 of the first and second pixels PX1 and PX2. A green color filter CF_G may be arranged in the third and fourth sub-pixels SPX3 and SPX4 of the first and second pixels PX1 and PX2 and the first and second sub-pixels SPX1 and SPX2 of the third and fourth pixels PX3 and PX4, respectively. A blue color filter CF_B may be arranged in the third and fourth sub-pixels SPX3 and SPX4 of the third and fourth pixels PX3 and PX4. In this way, in the pixel array 110, every sixteen pixels arranged in an 8×8 matrix may have a Bayer pattern.

[0250] Reference Fig.17D , the first pixel PX1 and the second pixel PX2 may be arranged in the second direction, and each of the first pixel PX1 and the second pixel PX2 may include first to fourth sub-pixels SPX1 to SPX4 arranged side by side in the first direction.

[0251] The red color filter CF_R may be respectively arranged in the first sub-pixel SPX1 and the third sub-pixel SPX3 of the first pixel PX1. The green color filter CF_G may be respectively arranged in the second sub-pixel SPX2 and the fourth sub-pixel SPX4 of the first pixel PX1. The green color filter CF_G may be respectively arranged in the first sub-pixel SPX1 and the third sub-pixel SPX3 of the second pixel PX2. The blue color filter CF_B may be respectively arranged in the second sub-pixel SPX2 and the fourth sub-pixel SPX4 of the second pixel PX2. In this way, every four sub-pixels arranged in a 2×2 matrix may have a Bayer pattern.

[0252] Reference Fig.17E , the first to fourth pixels PX1 to PX4 may be arranged in the first direction, and each of the first to fourth pixels PX1 to PX4 may include first to fourth sub-pixels SPX1 to SPX4 arranged side by side in the second direction.

[0253] A red color filter CF_R may be arranged in the first and second sub-pixels SPX1 and SPX2 of the first and second pixels PX1 and PX2. A green color filter CF_G may be arranged in the third and fourth sub-pixels SPX3 and SPX4 of the first and second pixels PX1 and PX2 and the first and second sub-pixels SPX1 and SPX2 of the third and fourth pixels PX3 and PX4, respectively. A blue color filter CF_B may be arranged in the third and fourth sub-pixels SPX3 and SPX4 of the third and fourth pixels PX3 and PX4. In this way, in the pixel array 110, every sixteen pixels arranged in an 8×8 matrix may have a Bayer pattern.

[0254] Reference Fig.17F, the first pixel PX1 and the second pixel PX2 may be arranged in the first direction. Each of the first pixel PX1 and the second pixel PX2 may include first to fourth sub-pixels SPX1 to SPX4 arranged side by side in the second direction.

[0255] The red color filter CF_R may be respectively arranged in the first sub-pixel SPX1 and the third sub-pixel SPX3 of the first pixel PX1. The green color filter CF_G may be respectively arranged in the second sub-pixel SPX2 and the fourth sub-pixel SPX4 of the first pixel PX1. The green color filter CF_G may be respectively arranged in the first sub-pixel SPX1 and the third sub-pixel SPX3 of the second pixel PX2. The blue color filter CF_B may be respectively arranged in the second sub-pixel SPX2 and the fourth sub-pixel SPX4 of the second pixel PX2. In this way, every four sub-pixels arranged in a 2×2 matrix may have a Bayer pattern.

[0256] Fig.18 An electronic device including a multi-camera module is shown. Fig.19 yes Fig.18 Detailed block diagram of the camera module.

[0257] Reference Fig.18 , the electronic device 1000 may include a camera module group 1100 , an application processor 1200 , a power management integrated circuit (PMIC) 1300 , and an external memory 1400 .

[0258] The camera module group 1100 may include a plurality of camera modules 1100a, 1100b, and 1100c. Fig.18 An embodiment in which three camera modules 1100a, 1100b, and 1100c are arranged is shown, but in other embodiments, the camera module group 1100 may include, for example, two camera modules, or may include k (where k is a natural number greater than or equal to 4) camera modules.

[0259] In the following, reference will be made to Fig.19 A detailed configuration of the camera module 1100 b is described in more detail, and the following description may be equally applied to the other camera modules 1100 a and 1100 c according to an embodiment.

[0260] Reference Fig.19 , the camera module 1100 b may include a prism 1105 , an optical path folding element (hereinafter referred to as “OPFE”) 1110 , an actuator 1130 , an image sensing device 1140 , and a storage 1150 .

[0261] The prism 1105 may include a reflective surface 1107 of a light reflective material and change the path of light L incident from the outside. The prism 1105 may change the path of light L incident in a first direction X to a second direction Y perpendicular to the first direction X. In addition, the prism 1105 may rotate on the central axis 1106 of the reflective surface 1107 of the light reflective material in the A direction or the B direction, thereby changing the path of light L incident in the first direction X to a second direction Y perpendicular thereto. In this case, the OPFE 1110 may also move in a third direction Z perpendicular to the first direction X and the second direction Y. The maximum rotation angle of the prism 1105 in the A direction may be less than 15 degrees in the +A direction and may be greater than 15 degrees in the -A direction. The prism 1105 may move within a range of about 20 degrees, or may move between 10 and 20 degrees or between 15 and 20 degrees in the +B or -B direction, and the moving angles may be the same as each other in the +B or -B direction, or may be within a range of 1 degree. The reflective surface 1107 of the light reflective material of the prism 1105 may move in a third direction (e.g., Z direction) parallel to the extension direction of the central axis 1106. The camera module 1100b may include two or more prisms to change the path of the light L incident along the first direction X to the second direction Y perpendicular to the first direction X, to the first direction X or the third direction Z, and then to the second direction Y again in various ways.

[0262] OPFE 1110 may include, for example, m (m is a natural number) groups of optical lenses. The m lenses may be moved in the second direction Y to change the optical zoom ratio of the camera module 1100b. For example, when the basic optical zoom ratio of the camera module 1100b is referred to as Z, and when the m optical lenses included in OPFE 1110 are moved, the optical zoom ratio of the camera module 1100b may be changed to 3Z, 5Z or more. The actuator 1130 may move the OPFE 1110 or the optical lens (hereinafter referred to as the optical lens) to a specific position. For example, the actuator 1130 may adjust the position of the optical lens for precise sensing so that the image sensor 1142 is located at the focal length of the optical lens.

[0263] The image sensing device 1140 may include an image sensor 1142, a control logic 1144, and a memory 1146. The image sensor 1142 may sense an image of a sensing target by using light L provided through an optical lens.

[0264] Refer to above Figures 2 to 17F The described pixels and pixel arrays are suitable for image sensor 1142.

[0265] The pixel may include a plurality of sub-pixels (e.g., four sub-pixels), each of which includes a plurality of photoelectric conversion devices and a floating diffusion region. The plurality of floating diffusion regions of the plurality of sub-pixels may be electrically connected to each other via wiring. The plurality of sub-pixels may each have improved sensitivity. Therefore, the image sensor 1142 may have improved resolution and improved image quality.

[0266] The control logic 1144 may control the operation of the camera module 1100b and process the sensed image. For example, the control logic 1144 may control the operation of the camera module 1100b according to the control signal provided by the control signal line CSLb, and may extract image data corresponding to a specific image in the sensed image (e.g., a face, arm, leg, etc. in the image) or perform image processing such as denoising. In some embodiments, the image sensor 1142 may include a pixel array, and the control logic 1144 may include an analog-to-digital converter and an image signal processor for processing the sensed image.

[0267] The memory 1146 may store information such as calibration data 1147 for operation of the camera module 1100b. The calibration data 1147 may be information for causing the camera module 1100b to generate image data by using light L provided from the outside, and may include, for example, information about a degree of rotation, information about a focal length, information about an optical axis, etc. When the camera module 1100b includes a multi-state camera whose focal length changes according to the position of an optical lens, the calibration data 1147 may include a focal length value for each position (or state) of the optical lens and information about autofocus.

[0268] The storage 1150 may store image data sensed by the image sensor 1142. The storage 1150 may be arranged outside the image sensing device 1140, and may be implemented in a stacked form with a sensor chip constituting the image sensing device 1140. In some embodiments, the image sensor 1142 may include a first chip, and the control logic 1144, the storage 1150, and the memory 1146 may include a second chip, so that the two chips may be stacked. The storage 1150 may include an electrically erasable programmable read-only memory (EEPROM).

[0269] Each of the plurality of camera modules 1100a, 1100b, and 1100c may include an actuator 1130. Therefore, the plurality of camera modules 1100a, 1100b, and 1100c may each include calibration data 1147 that is the same as or different from each other according to operations of the actuator 1130 included in the plurality of camera modules 1100a, 1100b, and 1100c.

[0270] One camera module (eg, 1100 b ) may be a folded lens type camera module including the above-described prism 1105 and OPFE 1110 , and the other camera modules (eg, 1100 a and 1100 c ) may be vertical type camera modules not including the prism 1105 and OPFE 1110 .

[0271] One camera module (e.g., 1100c) may be a vertical depth camera for extracting depth information by using, for example, infrared rays (IR). In this case, the application processor 1200 may merge image data provided from the depth camera with image data provided from another camera module (e.g., 1100a or 1100b) and provide a three-dimensional (3D) depth image.

[0272] Two or more camera modules (eg, 1100a and 1100b) may have different field of view angles, respectively. For example, the optical lenses of the two or more camera modules (eg, 1100a and 1100b) may be different from each other.

[0273] The field of view angle of each of the plurality of camera modules 1100a, 1100b, and 1100c may be different from each other. For example, the camera module 1100a may be an ultra-wide-angle camera, the camera module 1100b may be a wide-angle camera, and the camera module 1100c may be a telephoto camera. In this case, the optical lenses included in each of the plurality of camera modules 1100a, 1100b, and 1100c may also be different from each other.

[0274] The camera modules 1100a, 1100b, and 1100c may be physically separated and arranged from each other. That is, the sensing area of ​​one image sensor 1142 is not divided by the plurality of camera modules 1100a, 1100b, and 1100c, and an independent image sensor 1142 may be arranged inside each of the plurality of camera modules 1100a, 1100b, and 1100c.

[0275] Reference Fig.18 , the application processor 1200 may include an image processing device 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 may be implemented separately from the plurality of camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the plurality of camera modules 1100a, 1100b, and 1100c may be implemented as separate semiconductor chips. The image processing device 1210 may include a plurality of sub-image processors 1212a, 1212b, and 1212c, an image generator 1214, and a camera module controller 1216.

[0276] The image processing device 1210 may include a plurality of sub-image processors 1212a, 1212b, and 1212c corresponding to the plurality of camera modules 1100a, 1100b, and 1100c, respectively.

[0277] The image data generated from each of the camera modules 1100a, 1100b, and 1100c may be provided to the corresponding sub-image processors 1212a, 1212b, and 1212c through image signal lines ISLa, ISLb, and ISLc separated from each other. For example, the image data generated by the camera module 1100a may be provided to the sub-image processor 1212a through the image signal line ISLa, the image data generated by the camera module 1100b may be provided to the sub-image processor 1212b through the image signal line ISLb, and the image data generated by the camera module 1100c may be provided to the sub-image processor 1212c through the image signal line ISLc. Such image data transmission may be performed by using, for example, a camera serial interface (CSI) based on a mobile industry processor interface (MIPI).

[0278] One sub-image processor may be arranged to correspond to a plurality of camera modules. For example, sub-image processor 1212a and sub-image processor 1212c may be arranged to correspond to a plurality of camera modules. Fig.15A As shown, the sub-image processor 1212b is integrated into one sub-image processor without being separated from each other, and the image data provided from the camera modules 1100a and 1100c can be selected by a selection element (e.g., a multiplexer), etc., and then provided to the integrated sub-image processor. In this case, the sub-image processor 1212b can receive image data from the camera module 1100b without being integrated therein.

[0279] The image data generated by the camera module 1100a can be provided to the sub-image processor 1212a through the image signal line ISLa, the image data generated by the camera module 1100b can be provided to the sub-image processor 1212b through the image signal line ISLb, and the image data generated by the camera module 1100c can be provided to the sub-image processor 1212c through the image signal line ISLc. In addition, the image data processed by the sub-image processor 1212b can be directly provided to the image generator 1214, and the image data processed by the sub-image processors 1212a and 1212c can be selected by a selection element (e.g., a multiplexer) and the like, and then provided to the image generator 1214.

[0280] Each of the sub-image processors 1212a, 1212b and 1212c can perform image processing on the image data provided from the camera modules 1100a, 1100b and 1100c, such as bad pixel correction, 3A adjustment of automatic focus correction, automatic white balance and automatic exposure, noise reduction, sharpening, gamma control and re-mosaicing.

[0281] Re-mosaic signal processing may be performed on each of the camera modules 1100a, 1100b, and 1100c, and then the results of the re-mosaic signal processing may be provided to the sub-image processors 1212a, 1212b, and 1212c.

[0282] The image data processed by each of the sub image processors 1212a, 1212b, and 1212c may be provided to the image generator 1214. The image generator 1214 may generate an output image by using the image data provided from each of the sub image processors 1212a, 1212b, and 1212c according to the image generation information or the mode signal.

[0283] The image generator 1214 may generate an output image by merging at least some of the image data generated by the image processors 1212a, 1212b, and 1212c according to the image generation information or the mode signal. In addition, the image generator 1214 may generate an output image by selecting any one of the image data generated by the image processors 1212a, 1212b, and 1212c according to the image generation information or the mode signal.

[0284] The image generation information may include a zoom signal or a zoom factor.The mode signal may be a signal based on a mode selected by a user, for example.

[0285] When the image generation information is a zoom signal (zoom factor), and when the camera modules 1100a, 1100b, and 1100c have different fields of view (angles of view), the image generator 1214 may perform different operations depending on the type of the zoom signal. For example, when the zoom signal is a first signal, the image generator 1214 may generate an output image by using image data output from the sub-image processors 1212a and 1212b among the image data output from the sub-image processors 1212a and 1212b. When the zoom signal is a second signal different from the first signal, the image generator 1214 may generate an output image by using image data output from the sub-image processors 1212c and 1212b among the image data output from the sub-image processors 1212a and 1212c. If the zoom signal is a third signal different from the first signal and the second signal, the image generator 1214 does not perform image data merging and generates an output image by selecting any one of the image data output from each of the sub-image processors 1212a, 1212b, and 1212c. The method of processing image data may be modified to meet application standards.

[0286] The image processing device 1210 may include a selector (not shown) that selects the outputs of the sub-image processors 1212a, 1212b, and 1212c and sends the selected outputs to the image generator 1214. The selector may be implemented as a multiplexer, such as a 3×1 multiplexer. In this case, the selector may perform different operations according to the zoom signal or the zoom factor. For example, when the zoom signal is the fourth signal (e.g., the zoom ratio is the first ratio), the selector may select any one of the outputs of the sub-image processors 1212a, 1212b, and 1212c and send the selected output to the image generator 1214. In addition, when the zoom signal is a fifth signal different from the fourth signal (e.g., the zoom ratio is the second ratio), the selector may send p (p is a natural number greater than or equal to 2) outputs of the outputs of the sub-image processors 1212a, 1212b, and 1212c to the image generator 1214 in sequence. For example, the selector may send the output of the sub-image processor 1212b and the output of the sub-image processor 1212c to the image generator 1214 in sequence. In addition, the selector may send the output of the sub-image processor 1212a and the output of the sub-image processor 1212b to the image generator 1214 in sequence. The image generator 1214 may generate one output image by merging the p outputs received in sequence. The sub-image processors 1212a, 1212b, and 1212c may perform image processing such as re-mosaicing, scaling down to a video / preview resolution size, gamma correction, and high dynamic range (HDR) processing, and then the processed image data may be sent to the image generator 1214. Therefore, even when the processed image data is provided to the image generator 1214 through the selector and one signal line, the image merging operation of the image generator 1214 may be performed at high speed.

[0287] The image generator 1214 may receive a plurality of image data having different exposure times from at least one of the plurality of sub-image processors 1212a, 1212b, and 1212c, and perform high dynamic range (HDR) processing on the plurality of image data, thereby generating merged image data having an increased dynamic range.

[0288] The camera module controller 1216 may provide control signals to the camera modules 1100a, 1100b, and 1100c. The control signals generated by the camera module controller 1216 may be provided to the corresponding camera modules 1100a, 1100b, and 1100c through control signal lines CSLa, CSLb, and CSLc separated from each other.

[0289] Any one of the plurality of camera modules 1100a, 1100b, and 1100c may be designated as a master camera (e.g., 1100b) according to image generation information or a mode signal including a zoom signal, and the other camera modules (e.g., 1100a and 1100c) may be designated as slave cameras. Such information may be included in a control signal and provided to the corresponding camera modules 1100a, 1100b, and 1100c through control signal lines CSLa, CSLb, and CSLc separated from each other. The camera modules that operate as a master and a slave may be changed according to a zoom factor or an operation mode signal. For example, when the field of view of camera module 1100a is wider than the field of view of camera module 1100b and its zoom factor indicates a low zoom ratio, camera module 1100a may operate as a master, and camera module 1100b may operate as a slave. In contrast, when the zoom factor indicates a high zoom ratio, the camera module 1100b may operate as a master, and the camera module 1100a may operate as a slave.

[0290] The control signal provided from the camera module controller 1216 to each of the camera modules 1100a, 1100b, and 1100c may include a synchronization enable signal. For example, when the camera module 1100b is a master camera and the camera modules 1100a and 1100c are slave cameras, the camera module controller 1216 may send a synchronization enable signal to the camera module 1100b. Upon receiving the synchronization enable signal, the camera module 1100b may generate a synchronization signal based on the provided synchronization enable signal and send the generated synchronization signal to the camera modules 1100a and 1100c through the synchronization signal line SSL. The camera module 1100b and the camera modules 1100a and 1100c may synchronize with the synchronization signal to send image data to the application processor 1200.

[0291] The control signal provided to the plurality of camera modules 1100a, 1100b, and 1100c from the camera module controller 1216 may include mode information according to the mode signal. The camera modules 1100a, 1100b, and 1100c may operate in a first or second operation mode associated with a sensing speed based on the mode information. The camera modules 1100a, 1100b, and 1100c may generate an image signal at a first speed (e.g., generate an image signal of a first frame rate) in a first operation mode, and encode the image signal at a second speed higher than the first speed (e.g., encode an image signal of a second frame rate higher than the first frame rate), and transmit the encoded image signal to the application processor 1200. The second speed may be lower than or equal to 30 times the first speed.

[0292] The application processor 1200 may store the received image signal (i.e., the encoded image signal) in the memory 1230 included therein or in the external memory 1400 outside the application processor 1200, and then read the encoded image signal from the memory 1230 or the external memory 1400 and decode the encoded signal, and display the image data generated based on the decoded image signal. For example, a corresponding sub-image processor among the plurality of sub-image processors 1212a, 1212b, and 1212c of the image processing device 1210 may perform decoding, and may also perform image processing on the decoded image signal.

[0293] The camera modules 1100a, 1100b, and 1100c may each generate an image signal at a third speed lower than the first speed (e.g., an image signal at a third frame rate lower than the first frame rate) in the second operation mode and transmit the image signal to the application processor 1200. The image signal provided to the application processor 1200 may be an uncoded signal. The application processor 1200 may perform image processing on the received image signal or store the image signal in the memory 1230 or the external memory 1400.

[0294] The PMIC 1300 may supply power, such as a power supply voltage, to the plurality of camera modules 1100a, 1100b, and 1100c. For example, under the control of the application processor 1200, the PMIC 1300 may supply a first power to the camera module 1100a through a power signal line PSLa, a second power to the camera module 1100b through a power signal line PSLb, and a third power to the camera module 1100c through a power signal line PSLc. The PMIC 1300 may generate power corresponding to each of the plurality of camera modules 1100a, 1100b, and 1100c in response to a power control signal PCON from the application processor 1200, and may also adjust the level of the power. The power control signal PCON may include a power adjustment signal for each operation mode of the plurality of camera modules 1100a, 1100b, and 1100c. For example, the operation mode may include a low power mode, in which case the power control signal PCON may include information about the camera module operating in the low power mode and the power level to be set. The levels of power supplied to the plurality of camera modules 1100a, 1100b, and 1100c may be the same as or different from each other. In addition, the level of power may be dynamically changed.

[0295] As described above, the embodiments relate to an image sensor, and more particularly, to a pixel array having a pixel structure in which a plurality of photoelectric conversion devices share a floating diffusion region, and an image sensor including the pixel array. The embodiments may provide a pixel array having a pixel structure in which sixteen photoelectric conversion devices share a floating diffusion region, and an image sensor including the pixel array.

[0296] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, it will be apparent to one of ordinary skill in the art at the time of filing this application that features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically indicated. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. An image sensor, comprising: A first pixel including a first floating diffusion region (FD) and first four photoelectric conversion devices (PD); a second pixel including a second FD and second four PDs, the second pixel being directly adjacent to the first pixel along the first direction in a plan view; a third pixel including a third FD and a third four PDs, the third pixel being directly adjacent to the first pixel along a second direction perpendicular to the first direction in a plan view; a first microlens, on the first pixel; a second microlens, on a second pixel; a third microlens, on a third pixel; a first driving transistor configured to be connected to the first four PDs and the second four PDs; a first selection transistor connected to the first drive transistor; a reset transistor configured to be connected to the first FD and the second FD; as well as a green filter on the first to third pixels; Among them, each of the first four PDs to the third four PDs is arranged in a 2×2 matrix.

2. The image sensor according to claim 1, further comprising: Deep trench isolation separates the first pixel from the second pixel. Wherein, the deep trench isolation penetrates the substrate. 3 . The image sensor according to claim 1 , wherein the first FD and the second FD are connected via a first wiring.

4. The image sensor according to claim 3, further comprising: a fourth pixel, including a fourth FD and a fourth PD, the fourth pixel being directly adjacent to the second pixel in a plan view; as well as The fourth microlens, on the fourth pixel, Among them, the green filter is placed on the first to fourth pixels.

5. The image sensor according to claim 4 , wherein the third FD and the fourth PD are connected via a second wiring, in, Each of the first and second wirings extends in a first direction in a plan view. 6 . The image sensor according to claim 5 , wherein the second wiring is spaced apart from the first wiring along the second direction.

7. The image sensor according to claim 4, further comprising: an additional transistor, connected in series to the reset transistor, and The additional transistor is configured to be connected to the first FD and the second FD.

8. The image sensor according to claim 7, further comprising: The second driving transistor is configured to be connected to the third fourth PD and the fourth fourth PD.

9. The image sensor according to claim 7, further comprising: The third wiring, Among them, the first to fourth FDs are connected to each other via the first to third wirings.

10. An image sensor, comprising: A first pixel including a first floating diffusion region (FD) and first four photoelectric conversion devices (PD); a second pixel including a second FD and second four PDs; A third pixel includes a third FD and a third fourth PD; a fourth pixel including a fourth FD and a fourth PD; a first microlens, on the first pixel; a second microlens, on a second pixel; a third microlens, on a third pixel; a fourth microlens, on a fourth pixel; as well as a green filter on the first to fourth pixels; Among them, each of the first to fourth pixels is arranged in a 2×2 matrix.

11. The image sensor according to claim 10, further comprising: a reset transistor configured to be connected to the first and second FDs; as well as an additional transistor, connected in series to the reset transistor, wherein the first FD and the second FD extend in a first direction in a plan view via a first wiring, and The second pixel is directly adjacent to the first pixel along the first direction in a plan view. 12 . The image sensor according to claim 11 , wherein the reset transistor and the additional transistor are disposed along a first direction in a plan view.

13. The image sensor according to claim 11, further comprising: substrate; as well as A first deep trench isolation separates the first pixel from the second pixel. Wherein, the first deep trench isolation penetrates the substrate.

14. The image sensor according to claim 13, further comprising: The second deep trench isolation separates the first four PDs from each other. Wherein, the second deep trench isolation penetrates the substrate.

15. The image sensor according to claim 11, further comprising: a first driving transistor configured to be connected to the first four PDs and the second four PDs; a first selection transistor connected to the first drive transistor; as well as The second driving transistor is configured to be connected to the third fourth PD and the fourth fourth PD. 16 . The image sensor of claim 15 , wherein the second driving transistor is further configured to be connected to first four PDs, second four PDs, third four PDs, and fourth four PDs.

17. The image sensor according to claim 16, further comprising: The second selection transistor is connected to the second driving transistor. 18 . The image sensor of claim 17 , wherein the first driving transistor and the first selecting transistor are arranged along a second direction perpendicular to the first direction in a plan view.

19. An image sensor, comprising: substrate; A first pixel including a first floating diffusion region (FD) and first four photoelectric conversion devices (PD); a second pixel including a second FD and second four PDs; A third pixel includes a third FD and a third fourth PD; a fourth pixel including a fourth FD and a fourth PD; a first microlens, on the first pixel; a second microlens, on a second pixel; a third microlens, on a third pixel; a fourth microlens, on a fourth pixel; A first deep trench isolation separates the first pixel from the second pixel; The second deep trench isolation separates the first four PDs from each other. Green filter, on the first to fourth pixels, The first to fourth pixels are arranged in a 2×2 matrix. wherein each of the first four PDs to the second four PDs is arranged in a 2×2 matrix, and Wherein, the first to the second deep trench isolation penetrates the substrate.

20. The image sensor according to claim 19, further comprising: 16 PDs, arranged in a 4×4 matrix; as well as Red filter, on 16 PDs.

Images