Circuit board, electronic equipment and circuit board manufacturing method

Abstract

The invention discloses a circuit board, electronic equipment, a circuit board manufacturing method and a circuit board, and aims to solve the problem that the wiring space of the circuit board is occupied due to the fact that the aperture of a through hole is large in the circuit board, in the circuit board, a plurality of sub-boards are stacked, a first anti-plating block is located in one sub-board, and a second anti-plating block is located in the other sub-board; the through hole comprises a first through hole and a second through hole which are communicated with each other, and the second through hole penetrates through the first anti-plating block, the second anti-plating block, and the daughter board and the first dielectric layer between the first anti-plating block and the second anti-plating block; when the conductive layer is formed through electroplating, the first anti-plating block and the second anti-plating block prevent the conductive layer from being formed on the hole wall of the second through hole, so that the formed conductive layer covers the hole wall of the first through hole, chambering is not needed, the hole diameter of the through hole can be reduced, the through hole is prevented from occupying too much wiring space of the circuit board, and the wiring density of the circuit board can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of electronic equipment, and specifically to a circuit board, an electronic device, and a method for manufacturing a circuit board. Background Art

[0002] Multilayer circuit boards have been widely used due to their high integration. Multilayer circuit boards include multiple core boards stacked in layers, with circuit layers on both surfaces of each core board. In order to achieve the connection between different circuit layers, it is generally necessary to form through holes that penetrate each core board, and form a conductive layer on the hole wall of the through hole, and then expand the through hole to remove part of the conductive layer, leaving only the part of the conductive layer required to connect the two circuit layers. However, by expanding the hole to remove part of the conductive layer, the aperture of the through hole is large, which occupies the wiring space of the circuit board. Summary of the invention

[0003] The embodiments of the present application provide a circuit board, an electronic device, and a method for manufacturing a circuit board, which can improve the wiring density of the circuit board.

[0004] In a first aspect, an embodiment of the present application provides a circuit board, comprising: a plurality of sub-boards, a second circuit layer, a first anti-plating block and a second anti-plating block, wherein the plurality of sub-boards are stacked, and a first dielectric layer is stacked between adjacent sub-boards; the sub-board comprises a core board and a first circuit layer arranged on a surface of the core board; the second circuit layer is arranged on an outermost sub-board among the plurality of sub-boards, and a second dielectric layer is arranged between the second circuit layer and the outermost sub-board among the plurality of sub-boards; a through hole penetrates each sub-board, each first dielectric layer, the second dielectric layer and the second circuit layer;

[0005] The first anti-plating block and the second anti-plating block are located in different sub-boards; the through hole comprises a first through hole and a second through hole that are connected, and the second through hole penetrates the first anti-plating block, the second anti-plating block, and the sub-board and the first dielectric layer between the first anti-plating block and the second anti-plating block;

[0006] The circuit board also includes a conductive layer. The first anti-plating block and the second anti-plating block are used to prevent the conductive layer from being formed on the hole wall of the second through hole, so that the conductive layer covers the hole wall of the first through hole.

[0007] The circuit board provided in the embodiment of the present application is provided with a plurality of stacked sub-boards, a first dielectric layer is stacked between adjacent sub-boards, the sub-boards include a core board and a first circuit layer arranged on the surface of the core board; the outermost sub-board among the plurality of sub-boards is provided with a second dielectric layer and a second circuit layer, and the second dielectric layer is located between the second circuit layer and the outermost sub-board; the through hole passes through each sub-board, each first dielectric layer, second dielectric layer and second circuit layer; the first anti-plating block is located in one sub-board, and the second anti-plating block is located in another sub-board; the through hole includes a first through hole and a second through hole that are connected, and the second through hole passes through the first anti-plating block, the second anti-plating block, and the sub-board and the first dielectric layer between the first anti-plating block and the second anti-plating block; the first anti-plating block and the second anti-plating block are used to prevent the conductive layer from being formed on the hole wall of the second through hole, so that the conductive layer covers the hole wall of the first through hole; the second circuit layer can be connected to one or more first circuit layers corresponding to the first through hole through the conductive layer. Compared with forming a conductive layer on the entire hole wall of the through hole and then removing part of the conductive layer by expanding the hole, in the embodiment of the present application, when the conductive layer is formed by electroplating, the first anti-plating block and the second anti-plating block prevent the conductive layer from being formed on the hole wall of the second through hole, so that the formed conductive layer covers the hole wall of the first through hole, and there is no need to expand the hole. The aperture of the through hole can be reduced, the through hole is prevented from occupying too much wiring space of the circuit board, and the wiring density of the circuit board can be improved.

[0008] In some embodiments that may include the above embodiments, a first groove and a second groove are provided on the hole wall of the second through hole, a first anti-plating block is provided in the first groove, and a side wall of the first anti-plating block facing the center line of the second through hole is located in the first groove; a second anti-plating block is provided in the second groove, and a side wall of the second anti-plating block facing the center line of the second through hole is located in the second groove. After forming a seed layer on the hole wall of the first through hole and the hole wall of the second through hole, a portion of the first anti-plating block in the first groove is removed so that the side wall of the first anti-plating block facing the center line of the second through hole is located in the first groove; similarly, a portion of the second anti-plating block in the second groove is removed so that the side wall of the second anti-plating block facing the center line of the second through hole is located in the second groove. With such a configuration, the seed layer located on the first anti-plating block and the second anti-plating block can be removed before electroplating to avoid the formation of a conductive layer on the first anti-plating block and the second anti-plating block due to the residue of the seed layer.

[0009] In some embodiments that may include the above embodiments, the first groove is located on the core board in the corresponding sub-board, or the first groove is located on the core board and the first circuit layer in the corresponding sub-board; the second groove is located on the core board in the corresponding sub-board, or the second groove is located on the core board and the first circuit layer in the corresponding sub-board. Compared with the method of removing part of the conductive layer by expanding the hole, the method of expanding the hole will cause part of the conductive layer that does not transmit signals to remain on the hole wall of the through hole, thereby affecting signal transmission (for example, causing increased return loss, greater crosstalk, greater insertion loss, etc.); and the embodiment of the present application, through the above arrangement, there is no residual part of the conductive layer that does not transmit signals in the first through hole, which can avoid the residual part of the conductive layer affecting signal transmission (such as reducing return loss, crosstalk, insertion loss, etc.).

[0010] In some embodiments that may include the above embodiments, the first anti-plating block and the second anti-plating block are both obtained by curing the filling material, and the filling material includes: epoxy-modified acrylic resin. During production, the above materials can be mixed to form ink (filling material) with a certain fluidity, and then the ink is filled into the first groove and the second groove, and cured (such as heat curing) to form the first anti-plating block and the second anti-plating block.

[0011] In the above implementation, the adhesion between the epoxy-modified acrylic resin and the seed layer is relatively small, so that the seed layer can fall off the first anti-plating block and the second anti-plating block during the cleaning process before electroplating; in addition, the epoxy-modified acrylic resin can also react with the chemical solution, so that after the seed layer is formed, part of the first anti-plating block and the second anti-plating block can be removed by the chemical solution to avoid part of the seed layer remaining on the first anti-plating block and the second anti-plating block; furthermore, the epoxy-modified acrylic resin has a certain strength and can play a supporting role.

[0012] In some embodiments that may include the above embodiments, the filling material further includes: fillers, diluents, defoamers and leveling agents. Among them, the fillers can improve the mechanical properties of the first anti-plating block and the second anti-plating block. For example, the material of the fillers can include at least one of polytetrafluoroethylene, calcium carbonate, talcum powder and barium sulfate. The diluent can adjust the viscosity of the ink before curing to facilitate filling the ink into the first groove and the second groove; for example, the material of the diluent can include at least one of diethylene glycol ethyl ether acetate, nylon acid dimethyl ester and dimethyl phenol. The defoamer can remove bubbles in the ink before curing to avoid the presence of bubbles in the first anti-plating block and the second anti-plating block. For example, the material of the defoamer can include at least one of polyether ester and polyurethane. The leveling agent can adjust the fluidity of the ink before curing, thereby avoiding the formation of bubbles between the ink and the groove wall of the first groove and the second groove; for example, the leveling agent includes at least one of n-butyl acrylate and xylene.

[0013] In some embodiments that may include the above embodiments, the first resist block and the second resist block further include: a photosensitizer.

[0014] Under light, the photosensitizer can promote the reaction between the main resin and the monomer in the ink, thereby achieving the curing of the ink to form the first resist block and the second resist block. Exemplarily, the photosensitizer can include at least one of 2-methyl-1-(4-methylthiophenyl)-2-morpholinyl-1-propanone and 2-isopropylthioxanthone.

[0015] When filling the first groove and the second groove with ink, part of the ink will remain outside the first groove and the second groove. Therefore, after filling the ink, the first mask can be covered on the sub-plate with the first groove, and the first opening is provided on the first mask, and the first opening is directly opposite to the first groove. The first mask is exposed and developed, so that the ink in the first groove is solidified, thereby forming a first anti-plating block, while the ink outside the first groove is not exposed to light and is not solidified, so that the ink remaining outside the first groove can be removed. Similarly, after filling the ink, the second mask is covered on the sub-plate with the second groove, and the second opening is provided on the second mask, and the second opening is directly opposite to the second groove. The second mask is exposed and developed, so that the ink in the second groove is solidified, thereby forming a second anti-plating block, while the ink outside the second groove is not exposed to light and is not solidified, so that the ink remaining outside the second groove can be removed.

[0016] Through the above arrangement, the ink remaining outside the first groove and the second groove is removed while the ink inside the first groove and the second groove is solidified, which simplifies the difficulty of manufacturing the circuit board.

[0017] In some embodiments that may include the above embodiments, the mass fraction of epoxy modified acrylic resin is 25%-35%, the mass fraction of filler is 20%-40%, the mass fraction of photosensitizer is 3%-5%, the mass fraction of defoamer and leveling agent is 1%-3%, and the mass fraction of diluent is 10%-20%. In this way, the proportion of each component is appropriate, and while ensuring that the ink has a certain fluidity, bubbles can be avoided in the ink filled in the first groove and the second groove, and bubbles can also be avoided from forming between the ink and the groove wall of the first groove and the second groove.

[0018] In some embodiments that may include the above embodiments, there are multiple second through holes, and the multiple second through holes are arranged at intervals along the center line of the through hole, and the adjacent second through holes are connected through the first through hole. Correspondingly, the multiple second through holes are arranged at intervals along the center line of the through hole, there is a first through hole between two adjacent second through holes, and the two adjacent second through holes are connected through the first through hole. In this way, the conductive layer on the hole wall of the first through hole between the two second through holes can realize the connection between at least two first circuit layers corresponding to the first through hole; thereby improving the wiring density of the circuit board.

[0019] In some embodiments that may include the above embodiments, there are multiple through holes, and the multiple through holes are arranged at intervals. Such an arrangement can further improve the wiring density of the circuit board. It is understood that the first through hole and the second through hole in each through hole can be located at different positions to improve the flexibility of wiring.

[0020] In some embodiments that may include the above embodiments, among the plurality of through holes, the conductive layer in one through hole is connected to the conductive layer in another through hole through the first circuit layer connected thereto. The conductive layer in one through hole may be connected to the conductive layer in another through hole through the first circuit layer connected thereto, so as to realize signal transmission between the two through holes.

[0021] In an implementation in which the number of second through holes in the through hole is multiple, the conductive layer in a first through hole located between two second through holes can be connected to the conductive layers in other through holes through at least one first circuit layer connected thereto to achieve signal transmission between the two through holes.

[0022] In some embodiments including the above embodiments, the through hole is filled with an insulator. The through hole can be sealed by the insulator to prevent impurities such as water or dust from entering the through hole; of course, the insulator can also play a certain supporting role, thereby improving the strength of the circuit board.

[0023] In a second aspect, an embodiment of the present application further provides an electronic device, comprising: a housing and the circuit board as described above, wherein the circuit board is arranged on the housing.

[0024] The electronic device provided in the embodiment of the present application includes the circuit board in any of the above embodiments, so the two can solve the same technical problems and achieve the same technical effects.

[0025] In a third aspect, the present application also provides a method for manufacturing a circuit board, including:

[0026] A first anti-plating block and a second anti-plating block are formed in a plurality of sub-boards, wherein the first anti-plating block and the second anti-plating block are located in different sub-boards; the sub-boards include a core board and a first circuit layer arranged on a surface of the core board;

[0027] The plurality of sub-boards are stacked and arranged, and a first dielectric layer is formed between two adjacent sub-boards;

[0028] forming a second dielectric layer on the outermost sub-board among the plurality of sub-boards, and forming a second circuit layer on the second dielectric layer;

[0029] Forming through holes, the through holes penetrating the second circuit layer, the second dielectric layer, each sub-board and each first dielectric layer; the through holes include a first through hole and a second through hole that are connected, the second through hole penetrating the first anti-plating block, the second anti-plating block, and the sub-board and the first dielectric layer between the first anti-plating block and the second anti-plating block;

[0030] forming a seed layer on a hole wall of the through hole;

[0031] The seed layer is electroplated to form a conductive layer, and the first resist block and the second resist block are used to prevent the conductive layer from being formed on the hole wall of the second through hole, so that the conductive layer covers the hole wall of the first through hole.

[0032] Through the above-mentioned arrangement, when the conductive layer is formed by electroplating, the first anti-plating block and the second anti-plating block prevent the conductive layer from being formed on the hole wall of the second through hole, so that the formed conductive layer covers the hole wall of the first through hole. There is no need to expand the hole, the aperture of the through hole can be reduced, and the through hole is prevented from occupying too much wiring space of the circuit board, which can improve the wiring density of the circuit board.

[0033] In some embodiments that may include the above embodiments, before electroplating through the seed layer, the process further includes: removing part of the first resist block and part of the second resist block through the through hole to remove the seed layer on the first resist block and the second resist block. So that the side wall of the first resist block facing the center line of the second through hole is located in the first groove, and the side wall of the second resist block facing the center line of the second through hole is located in the second groove, thereby removing the seed layer on the first resist block and the second resist block. In this way, the seed layer on the first resist block and the second resist block can be removed before electroplating to avoid the formation of a conductive layer on the first resist block and the second resist block due to the residual seed layer.

[0034] In some embodiments that may include the above embodiments, forming the first anti-plating block and the second anti-plating block in the plurality of sub-boards includes: forming a first groove on one of the plurality of sub-boards, forming a second groove on another of the plurality of sub-boards, forming the first anti-plating block in the first groove, and forming the second anti-plating block in the second groove. Through the above arrangement, the first anti-plating block is formed in the first groove, and the second anti-plating block is formed in the second groove, which facilitates the manufacture and formation of the first anti-plating block and the second anti-plating block; in addition, by setting the positions of the first groove and the second groove, the positions of the first anti-plating block and the second anti-plating block can be adjusted.

[0035] In some embodiments that may include the above embodiments, forming the first anti-plating block in the first groove and forming the second anti-plating block in the second groove includes: forming a filling material in the first groove and the second groove by a printing process; removing the remaining filling material outside the first groove and the second groove; and curing the filling material to form the first anti-plating block and the second anti-plating block. Since the filling material has a certain fluidity, it is easy to form residual filling material outside the first groove and the second groove during the filling process. Removing the residual filling material can avoid the residual filling material from affecting the subsequent production of the circuit board and the operation of the circuit board.

[0036] In some embodiments that may include the above embodiments, removing the residual filling material outside the first groove and the second groove includes: covering a first mask on a sub-plate, the first mask is provided with a first opening, the first opening is directly facing the first groove, exposing the first mask, and performing a development process to remove the filling material outside the first groove; covering a second mask on another sub-plate, the second mask is provided with a second opening, the second opening is directly facing the second groove, exposing the second mask, and performing a development process to remove the filling material outside the second groove. Through the above settings, the residual filling material outside the first groove and the second groove is removed by exposure and development technology, the processing accuracy is high, and damage to the filling material in the first groove and the second groove can be avoided.

[0037] In some embodiments that may include the above embodiments, forming a first anti-plating block in the first groove and forming a second anti-plating block in the second groove includes: filling the first groove and the second groove with filling material by a dispensing process to form the first anti-plating block in the first groove, and forming the second anti-plating block in the second groove. In this way, the dispensing process has a high precision, and the filling material can be accurately filled in the first groove and the second groove, which can simplify the manufacturing process and reduce the difficulty of manufacturing the circuit board.

[0038] In some embodiments that may include the above embodiments, after forming the second circuit layer, the second dielectric layer, each sub-board and each first dielectric layer are pressed together. The second circuit layer, the second dielectric layer, each sub-board and each first dielectric layer are pressed and heated at the same time to solidify each first dielectric layer, thereby connecting each sub-board together, and the second dielectric layer connects the second circuit layer to the outermost sub-board. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of the structure of the circuit board provided in the embodiment of the present application Figure 1 ;

[0040] Figure 2 A schematic diagram of the structure of the circuit board provided in the embodiment of the present application Figure 2;

[0041] Figure 3 A schematic diagram of the structure of a circuit board in the related art Figure 1 ;

[0042] Figure 4 A schematic diagram of the structure of a circuit board in the related art Figure 2 ;

[0043] Figure 5 A schematic diagram of the connection between two through holes in a circuit board provided in an embodiment of the present application;

[0044] Figure 6 A schematic diagram of the structure of the circuit board provided in the embodiment of the present application Figure 3 ;

[0045] Figure 7 A flowchart of a circuit board manufacturing method provided in an embodiment of the present application;

[0046] Figure 8 A schematic diagram of the structure after a metal layer is formed on the surface of a core board in the circuit board manufacturing method provided in an embodiment of the present application;

[0047] Fig. 9 A schematic diagram of the structure after the first circuit layer is formed in the circuit board manufacturing method provided in an embodiment of the present application;

[0048] Fig.10 A schematic diagram of the structure after the first groove and the second groove are formed in the circuit board manufacturing method provided in an embodiment of the present application;

[0049] Fig.11 A schematic diagram of the structure after the first groove and the second groove are filled with filling material in the circuit board manufacturing method provided in an embodiment of the present application;

[0050] Fig.12 A schematic diagram of the structure after the first anti-plating block and the second anti-plating block are formed in the circuit board manufacturing method provided in an embodiment of the present application;

[0051] Fig.13 A schematic diagram of the structure after the second circuit layer, the second dielectric layer, each sub-board and each first dielectric layer are pressed together in the circuit board manufacturing method provided in an embodiment of the present application;

[0052] Fig.14 A schematic diagram of the structure after a through hole is formed in the circuit board manufacturing method provided in an embodiment of the present application;

[0053] Fig.15 A schematic diagram of the structure after a seed layer is formed in the circuit board manufacturing method provided in an embodiment of the present application;

[0054] Fig.16Schematic diagram of the structure after the conductive layer is formed in the circuit board manufacturing method provided in the embodiment of the present application Figure 1 ;

[0055] Fig.17 A schematic diagram of the structure after removing part of the first anti-plating block and part of the second anti-plating block in the circuit board manufacturing method provided in an embodiment of the present application;

[0056] Fig.18 Schematic diagram of the structure after the conductive layer is formed in the circuit board manufacturing method provided in the embodiment of the present application Figure 2 .

[0057] Explanation of the reference numerals: 10: sub-board; 20: first dielectric layer; 30: second dielectric layer; 40: second circuit layer; 50: through hole; 101: core board; 102: first circuit layer; 501: first through hole; 502: second through hole; 503: first anti-plating block; 504: second anti-plating block; 505: first groove; 506: second groove; 507: conductive layer; 508: seed layer; 509: filling material. DETAILED DESCRIPTION

[0058] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0059] In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features.

[0060] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left", "right", "horizontal" and "vertical" are defined relative to the orientation of the components schematically placed in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they may change accordingly according to changes in the orientation of the components placed in the drawings.

[0061] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, an electrical connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0062] The embodiment of the present application provides an electronic device, which may include a mobile phone, a computer, a tablet computer, a smart bracelet, a smart watch, etc. The embodiment of the present application does not limit the electronic device. In the embodiment of the present application, the electronic device includes a housing and a circuit board arranged on the housing; in the implementation mode in which the electronic device includes a mobile phone, the housing may include a middle frame of the mobile phone, and the corresponding electronic device may include a motherboard arranged on the middle frame; in the implementation mode in which the electronic device includes a computer, the housing may include a computer chassis, and correspondingly, the circuit board may include a motherboard located inside the chassis.

[0063] Please refer to Figure 1 In the embodiment of the present application, the circuit board is a multi-layer circuit board. Accordingly, the circuit board includes a plurality of sub-boards 10, and the plurality of sub-boards 10 are stacked. Each sub-board 10 includes a core board 101 and a first circuit layer 102 located on the surface of the core board 101. Exemplarily, each sub-board 10 may include two first circuit layers 102. Accordingly, each surface ( Figure 1 A first circuit layer 102 is disposed on both the upper surface and the lower surface of the circuit board (in the direction shown). It is understandable that the first circuit layer 102 may have a certain circuit pattern to meet the wiring requirements of the circuit board; in addition, the circuit patterns corresponding to each first circuit layer 102 may be the same or different, and the embodiment of the present application does not limit this.

[0064] In the above implementation, the core board 101 is an insulating board, so as to support the two first circuit layers 102 thereon while preventing the two first circuit layers 102 thereon from short-circuiting. Exemplarily, the core board 101 may include: epoxy glass cloth laminate (FR-4 for short), a substrate made of wood fiber and resin (FR-1 for short), etc. The embodiment of the present application does not limit the material of the core board 101.

[0065] In the embodiment of the present application, the first dielectric layer 20 is stacked between adjacent sub-boards 10, and the connection between adjacent sub-boards 10 can be achieved through the first dielectric layer 20, and the insulation between two first circuit layers 102 close to each other in adjacent sub-boards 10 can also be achieved. Exemplarily, the first dielectric layer 20 may include a prepreg, and during manufacturing, multiple sub-boards 10 are stacked, and a layer of prepreg is arranged between adjacent sub-boards 10, and then the connection between adjacent sub-boards 10 can be achieved by hot pressing.

[0066] The prepreg may include glass fiber and epoxy resin. For example, the epoxy resin is applied to the glass fiber sheet. When heated, the epoxy resin is gelled, and the sub-boards 10 on both sides can be bonded. Of course, the prepreg may also include paper and epoxy resin applied to the paper. It is understandable that the embodiment of the present application does not limit the material of the first dielectric layer 20, as long as it can achieve the connection between adjacent sub-boards 10 and the insulation between the two first circuit layers 102 close to each other in the adjacent sub-boards 10.

[0067] Continue to refer to Figure 1 In the embodiment of the present application, the circuit board further includes a second circuit layer 40 and a second dielectric layer 30. The second circuit layer 40 is disposed on the outermost sub-board 10 among the plurality of sub-boards 10, and the second dielectric layer 30 is disposed between the second circuit layer 40 and the outermost sub-board 10 among the plurality of sub-boards 10. The second dielectric layer 30 can be used to connect the second circuit layer 40 to the outermost sub-board 10 among the plurality of sub-boards 10, and can also be used to insulate the second circuit layer 40 from the outermost first circuit layer 102 on the outermost sub-board 10 among the plurality of sub-boards 10. Exemplarily, the material of the second dielectric layer 30 can also be the same as or different from the material of the first dielectric layer 20, and the embodiment of the present application does not limit the material of the second dielectric layer 30.

[0068] In some embodiments, there may be two second circuit layers 40, one of which is disposed on the outermost sub-board 10 among the plurality of sub-boards 10 ( Figure 1 Another second circuit layer 40 is disposed on another sub-board 10 (the sub-board 10 located at the top layer among the plurality of sub-boards 10) located at the outermost side. Figure 1 A second dielectric layer 30 is disposed between each second circuit layer 40 and the sub-board 10 adjacent thereto to achieve connection between the second circuit layer 40 and the sub-board 10 adjacent thereto. Each second circuit layer 40 has a certain pattern, and the circuit patterns of the two second circuit layers 40 may be the same or different, and the pattern of the second circuit layer 40 may be the same or different from the pattern of the first circuit layer 102, which is not limited in the present application embodiment, and the pattern of the second circuit layer 40 may be reasonably set according to the wiring requirements of the circuit board.

[0069] Continue to refer to Figure 1In the embodiment of the present application, the circuit board further includes a first anti-plating block 503 and a second anti-plating block 504, and the first anti-plating block 503 and the second anti-plating block 504 are located in different sub-boards 10; that is, the first anti-plating block 503 is set in one of the plurality of sub-boards 10, and the second anti-plating block 504 is set in another of the plurality of sub-boards 10. It can be understood that by reasonably selecting the sub-board 10 where the first anti-plating block 503 and the second anti-plating block 504 are located, the positions of the first anti-plating block 503 and the second anti-plating block 504 in the circuit board can be adjusted ( Figure 1 longitudinal position in the orientation shown).

[0070] In the above implementation, a through hole 50 is provided on the circuit board, and the through hole 50 passes through each sub-board 10, each first dielectric layer 20, each second dielectric layer 30 and each second circuit layer 40, that is, the through hole 50 passes through the entire circuit board. The through hole 50 includes a first through hole 501 and a second through hole 502 that are connected, that is, the center lines of the first through hole 501 and the second through hole 502 coincide, and one end of the first through hole 501 is connected with one end of the second through hole 502. Among them, the second through hole 502 passes through the first anti-plating block 503 and the second anti-plating block 504, and the sub-board 10 and the first dielectric layer 20 between the first anti-plating block 503 and the second anti-plating block 504, that is, part of the through holes 50 that pass through the first anti-plating block 503, the second anti-plating block 504, and each sub-board 10 and the first dielectric layer 20 located between the first anti-plating block 503 and the second anti-plating block 504 is the second through hole 502, and the rest of the through holes 50 are the first through holes 501.

[0071] In the embodiment of the present application, a conductive layer 507 is disposed on the hole wall of the first through hole 501, and the conductive layer 507 covers the hole wall of the first through hole 501, and the conductive layer 507 is connected to the second circuit layer 40 and at least one first circuit layer 102 corresponding to the hole wall of the first through hole 501, and the connection between at least one first circuit layer 102 corresponding to the hole wall of the first through hole 501 and the second circuit layer 40 can be achieved through the conductive layer 507. Signals can be transmitted through the conductive layer 507 to achieve signal transmission between the second circuit layer 40 and at least one first circuit layer 102 corresponding to the first through hole 501.

[0072] Exemplarily, the first through hole 501 can penetrate the second circuit layer 40 and a first circuit layer 102 in the sub-board 10 near it, and accordingly, the conductive layer 507 can realize the connection between the circuit layer and the second circuit layer 40. Of course, the first through hole 501 can penetrate multiple first circuit layers 102 while penetrating the second circuit layer 40, and accordingly, the conductive layer 507 can be connected to at least one of the multiple first circuit layers 102 while being connected to the second circuit layer 40, so as to realize the connection between the second circuit layer 40 and at least one first circuit layer 102. It can be understood that the pattern of each first circuit layer 102 can be reasonably set according to actual use requirements to adjust the number of first circuit layers 102 connected to the conductive layer 507 and the position of each first circuit layer 102 connected to the conductive layer 507, and the embodiment of the present application is not limited to this.

[0073] It is understandable that the conductive layer 507 can be formed by electroplating. Accordingly, the first anti-plating block 503 and the second anti-plating block 504 are used to prevent the conductive layer 507 from being formed on the hole wall of the second through hole 502. Exemplarily, when electroplating, a seed layer can be first formed on the hole wall of the through hole 50, and the seed layer covers the hole wall of the first through hole 501 and the hole wall of the second through hole 502, and the adhesion between the seed layer and the first anti-plating block 503 and the second anti-plating block 504 is relatively small; before electroplating, the circuit board generally needs to be cleaned; during the cleaning process, the seed layer on the first anti-plating block 503 and the second anti-plating block 504 falls off due to the low adhesion, while the seed layer on the hole wall of other through holes 50 is retained; then the circuit board is placed in the electroplating solution, and the conductive layer 507 can be formed at the seed layer by supplying power to the seed layer. Among them, since there is no seed layer on the first anti-plating block 503 and the second anti-plating block 504, accordingly, the seed layer on the hole wall of the second through hole 502 between the first anti-plating block 503 and the second anti-plating block 504 will not be charged, so that the conductive layer 507 is only formed on the hole wall of the first through hole 501, and the conductive layer 507 will not be formed on the hole wall of the second through hole 502.

[0074] Exemplarily, the material of the seed layer may include a colloid or a coating containing palladium ions. The embodiment of the present application does not limit the material of the seed layer, as long as the seed layer can be electroplated to form the conductive layer 507 .

[0075] Please refer to Figure 2In the embodiment of the present application, the sub-board 10 where the first anti-plating block 503 and the second anti-plating block 504 are located is reasonably arranged, so that the second circuit layer 40 can be connected to the first circuit layer 102 on different sub-boards 10. It can be understood that in some embodiments, there can be multiple through holes 50, and the multiple through holes 50 are arranged at intervals; wherein, the positions of the first anti-plating block 503 and the second anti-plating block 504 corresponding to each through hole 50 can be the same, thereby improving the wiring density of the circuit board; of course, the positions of the first anti-plating block 503 and the second anti-plating block 504 corresponding to each through hole 50 can also be different, thereby realizing the connection between the second circuit layer 40 and different first circuit layers 102 through the conductive layer 507 in different through holes 50, and the embodiment of the present application does not limit this.

[0076] For example, Figure 2 The first anti-plating block 503 corresponding to the first through hole 50 on the left side is located in the topmost sub-board 10, the second anti-plating block 504 is located in the bottommost sub-board 10, and the first through hole 501 above the second through hole 502 penetrates the second circuit layer 40 at the top and the first circuit layer 102 in the upper middle part of the topmost sub-board 10; accordingly, the conductive layer 507 only connects the second circuit layer 40 at the top and a first circuit layer 102 close to the second circuit layer 40; and the first through hole 501 below the second through hole 502 only penetrates the second circuit layer 40 at the bottom and the corresponding second dielectric layer 30, and the conductive layer 507 in the first through hole 501 is not connected to other first circuit layers 102.

[0077] Figure 2 The first anti-plating block 503 corresponding to the second through hole 50 on the left is located in the second sub-board 10, and the second anti-plating block 504 is located in the bottom sub-board 10; the first through hole 501 above the second through hole 502 penetrates the upper second circuit layer 40 and the two first circuit layers 102 on the top sub-board 10, and accordingly, the conductive layer 507 in the first through hole 501 is connected to the upper second circuit layer 40 and the upper first circuit layer 102 in the top sub-board 10, wherein the first circuit layer 102 in the lower part of the top sub-board 10 may not contact the conductive layer 507. The first through hole 501 below the second through hole 502 only penetrates the second circuit layer 40 at the bottom and the corresponding second dielectric layer 30, and the conductive layer 507 in the first through hole 501 is not connected to other first circuit layers 102.

[0078] Figure 2The first anti-plating block 503 corresponding to the third through hole 50 on the left is located in the third sub-board 10, and the second anti-plating block 504 is located in the bottom sub-board 10; the first through hole 501 above the second through hole 502 penetrates the upper second circuit layer 40, the two first circuit layers 102 on the top sub-board 10, and the two first circuit layers 102 on the second sub-board 10; accordingly, the conductive layer 507 in the first through hole 501 is connected to the upper second circuit layer 40, the upper first circuit layer 102 in the top sub-board 10, and the upper first circuit layer 102 in the second sub-board 10, wherein the lower first circuit layer 102 in the second sub-board 10 may not contact the conductive layer 507. The first through hole 501 below the second through hole 502 only penetrates the bottom second circuit layer 40 and the corresponding second dielectric layer 30, and the conductive layer 507 in the first through hole 501 is not connected to other first circuit layers 102.

[0079] Figure 2 The first anti-plating block 503 corresponding to the fifth through hole 50 on the left side is located in the second sub-board 10, and the second anti-plating block 504 is located in the third sub-board 10. The first through hole 501 above the second through hole 502 penetrates the top-most second circuit layer 40 and the two first circuit layers 102 in the first sub-board 10. Correspondingly, the conductive layer 507 in the first through hole 501 can be connected to the top-most second circuit layer 40 and the first circuit layer 102 in the upper part of the first sub-board 10; wherein, the first circuit layer 102 in the lower part of the first sub-board 10 may not be connected to the conductive layer 507. The first through hole 501 below the second through hole 502 penetrates the second circuit layer 40 at the bottom, the two first circuit layers 102 in the bottom sub-board 10, and the first circuit layer 102 in the lower middle part of the third sub-board 10; accordingly, the conductive layer 507 in the first through hole 501 can be connected to the second circuit layer 40 at the bottom and the first circuit layer 102 in the upper middle part of the bottom sub-board 10; while the first circuit layer 102 in the lower middle part of the bottom sub-board 10 and the first circuit layer 102 in the lower middle part of the third sub-board 10 are not connected to the conductive layer 507.

[0080] Figure 2The first anti-plating block 503 corresponding to the sixth through hole 50 on the left side is located in the topmost sub-board 10, and the second anti-plating block 504 is located in the third sub-board 10. The first through hole 501 above the second through hole 502 penetrates the second circuit layer 40 and the second dielectric layer 30 located in the top layer, and the corresponding conductive layer 507 in the first through hole 501 is not connected to the first circuit layer 102; while the first through hole 501 below the second through hole 502 penetrates the second circuit layer 40 at the bottom, the two first circuit layers 102 in the bottom sub-board 10, and the first circuit layer 102 in the lower part of the third sub-board 10; accordingly, the conductive layer 507 in the first through hole 501 can be connected to the second circuit layer 40 at the bottom and the first circuit layer 102 in the upper part of the bottom sub-board 10; while the first circuit layer 102 in the lower part of the bottom sub-board 10 and the first circuit layer 102 in the lower part of the third sub-board 10 are not connected to the conductive layer 507.

[0081] It is understandable that the circuit board may have one or more of the above-mentioned through holes 50. Of course, the positions of the first anti-plating block 503 and the second anti-plating block 504 corresponding to the through holes 50 are not limited to Figure 1 and Figure 2 The positions shown can reasonably set the positions of the first anti-plating block 503 and the second anti-plating block 504 according to actual use needs.

[0082] The circuit board provided in the embodiment of the present application comprises a plurality of stacked sub-boards 10, wherein a first dielectric layer 20 is stacked between adjacent sub-boards 10, and the sub-boards 10 comprise a core board 101 and a first circuit layer 102 arranged on the surface of the core board 101; a second dielectric layer 30 and a second circuit layer 40 are arranged on the outermost sub-board 10 among the plurality of sub-boards 10, and the second dielectric layer 30 is arranged between the second circuit layer 40 and the outermost sub-board 10; a through hole 50 passes through each sub-board 10, each first dielectric layer 20, the second dielectric layer 30 and the second circuit layer 40; a first anti-plating block 503 is arranged in one sub-board 10, and a second anti-plating block 504 is arranged in one sub-board 10; In another sub-board 10; the through hole 50 includes a first through hole 501 and a second through hole 502 that are connected, and the second through hole 502 passes through the first anti-plating block 503, the second anti-plating block 504, and the sub-board 10 and the first dielectric layer 20 between the first anti-plating block 503 and the second anti-plating block 504; the first anti-plating block 503 and the second anti-plating block 504 are used to prevent the conductive layer 507 from being formed on the hole wall of the second through hole 502, so that the conductive layer 507 covers the hole wall of the first through hole 501; the conductive layer 507 can realize the connection between the second circuit layer 40 and one or more first circuit layers 102 corresponding to the first through hole 501. Figure 3In the circuit board shown in the figure, a conductive layer 507 is formed on the entire hole wall of the through hole 50, and then part of the conductive layer 507 is removed by expanding the hole. In the embodiment of the present application, when the conductive layer 507 is formed by electroplating, the first anti-plating block 503 and the second anti-plating block 504 prevent the conductive layer 507 from being formed on the hole wall of the second through hole 502, so that the formed conductive layer 507 covers the hole wall of the first through hole 501, and there is no need to expand the hole. The aperture of the through hole 50 can be reduced, so that the through hole 50 is prevented from occupying too much wiring space of the circuit board, and the wiring density of the circuit board can be improved.

[0083] Figure 4 In the related technology shown, during the production, the two sub-boards 10 that need to be electrically connected are first pressed together to form a sub-circuit board; then the sub-circuit board is drilled to form a through hole 50, and a conductive layer 507 is formed on the hole wall of the through hole 50 by electroplating, and at least two first circuit layers 102 in the two sub-boards 10 are connected through the conductive layer 507. Thereafter, the sub-circuit boards are pressed together to form a circuit board. In other words, each sub-circuit board needs to be pressed, drilled, and electroplated, and then all the sub-circuit boards are pressed together, resulting in a more complicated production process. In addition, due to errors generated during the pressing process, each pressing will result in a certain layer deviation (offset between adjacent sub-boards 10); and Figure 4 The related art shown requires multiple pressings, resulting in large layer deviations and errors in the circuit board.

[0084] In the embodiment of the present application, Figure 1 As shown, during the production, each sub-board 10 and the second circuit layer 40 can be pressed together first, and then a through hole 50 is formed; thereafter, a seed layer is formed in the through hole 50, and electroplating is performed through the seed layer to form a conductive layer 507; only one pressing, one drilling, and one electroplating are required to complete the production and processing of the circuit board. Figure 4 Compared with the related art shown in the figure, the manufacturing process of the circuit board can be simplified. In addition, since only one pressing is required, the layer deviation of the circuit board can be reduced, thereby reducing the error of the circuit board.

[0085] In the embodiment of the present application, a first groove 505 and a second groove 506 are arranged on the hole wall of the second through hole 502, and the first anti-plating block 503 is arranged in the first groove 505, and the side wall of the first anti-plating block 503 facing the center line of the second through hole 502 is located in the first groove 505; the second anti-plating block 504 is arranged in the second groove 506, and the side wall of the second anti-plating block 504 facing the center line of the second through hole 502 is located in the second groove 506. After the seed layer is formed on the hole wall of the first through hole 501 and the hole wall of the second through hole 502, part of the first anti-plating block 503 in the first groove 505 is removed, so that the side wall of the first anti-plating block 503 facing the center line of the second through hole 502 is located in the first groove 505; similarly, part of the second anti-plating block 504 in the second groove 506 is removed, so that the side wall of the second anti-plating block 504 facing the center line of the second through hole 502 is located in the second groove 506. With this arrangement, the seed layer on the first resist block 503 and the second resist block 504 can be removed before electroplating to avoid the formation of the conductive layer 507 on the first resist block 503 and the second resist block 504 due to the residual seed layer.

[0086] Exemplarily, acid, alkali or other liquid that can react with the first anti-plating block 503 and the second anti-plating block 504 can be injected into the through hole 50 to remove part of the first anti-plating block 503 and the second anti-plating block 504. The embodiment of the present application does not limit the material of the liquid, as long as it can remove part of the first anti-plating block 503 and the second anti-plating block 504.

[0087] Continue to refer to Figure 1 In the above implementation, the first groove 505 is located on the core board 101 in the corresponding sub-board 10, that is, the first through hole 501 above the second through hole 502 penetrates to the first circuit layer 102 located at the upper part of the sub-board 10 where the first groove 505 is located. Accordingly, the conductive layer 507 can connect the first circuit layer 102 and the second circuit layer 40 located at the upper part. Figure 3 Compared with the embodiment shown in the figure, the hole expansion method will cause part of the conductive layer 507 that does not transmit signals to remain on the hole wall of the through hole 50, thereby affecting signal transmission (for example, causing increased return loss, greater crosstalk, greater insertion loss, etc.); while in the embodiment of the present application, by making the first through hole 501 on the upper part of the second through hole 502 penetrate to the first circuit layer 102 located at the upper part of the sub-board 10 where the first groove 505 is located, the conductive layer 507 in the first through hole 501 is used for signal transmission, and there is no residual part of the conductive layer 507 that does not transmit signals in the first through hole 501. In this way, it is possible to avoid the residual part of the conductive layer 507 from affecting signal transmission (such as reducing return loss, crosstalk, insertion loss, etc.).

[0088] In other implementations, the first groove 505 is located on the core board 101 and at least one first circuit layer 102 in the corresponding sub-board 10. Exemplarily, the first groove 505 can be located on the core board 101 and two first circuit layers 102 in the corresponding sub-board 10; or, the first groove 505 is located on the core board 101 and the first circuit layer 102 located at the upper portion in the corresponding sub-board 10; or, the first groove 505 is located on the core board 101 and the first circuit layer 102 located at the lower portion in the corresponding sub-board 10. At this time, the first through hole 501 penetrates to the first circuit layer 102 located at the upper portion of the sub-board 10 corresponding to the first groove 505, and the conductive layer 507 in the first through hole 501 can connect the first circuit layer 102 and the second conductive layer 507 located at the upper portion. In this way, the presence of residual partial conductive layer 507 in the first through hole 501 can be avoided to prevent the residual partial conductive layer 507 from affecting signal transmission.

[0089] It is understandable that the position of the first groove 505, that is, the longitudinal position of the first anti-plating block 503 in the core board 101, can be reasonably set according to the circuit patterns of the two first circuit layers 102 in the sub-board 10. For example, when the first circuit layer 102 in the upper part of the sub-board 10 has no circuit pattern in the area corresponding to the first groove 505, or when the first circuit layer 102 in the upper part of the sub-board 10 has a circuit pattern in the area corresponding to the first groove 505, but the conductive layer 507 needs to be connected to the first circuit layer 102, the first groove 505 needs to be set outside the first circuit layer 102 in the upper part of the sub-board 10. When the first circuit layer 102 in the lower part of the sub-board 10 has no circuit pattern in the area corresponding to the first groove 505, the first groove 505 can be outside the first circuit layer 102 in the lower part of the sub-board 10; when the first circuit layer 102 in the lower part of the sub-board 10 has a circuit pattern in the area corresponding to the first groove 505, the first groove 505 can be set inside the first circuit layer 102 in the lower part of the sub-board 10.

[0090] Continue to refer to Figure 1 Similarly, the second groove 506 is located on the core board 101 in the corresponding sub-board 10, that is, the first through hole 501 below the second through hole 502 penetrates to the first circuit layer 102 located at the bottom of the sub-board 10 where the second groove 506 is located. Correspondingly, the conductive layer 507 in the first through hole 501 below the second through hole 502 can connect the first circuit layer 102 and the second circuit layer 40 located at the bottom. Figure 3 Compared with the configuration shown in the figure, the conductive layer 507 in the first through hole 501 is all used for signal transmission, and there is no residual conductive layer 507 that is not used for signal transmission in the first through hole 501. This configuration can avoid the residual conductive layer 507 from affecting signal transmission (such as reducing return loss, crosstalk, insertion loss, etc.).

[0091] In other implementations, the second groove 506 is located on the core board 101 and at least one first circuit layer 102 in the corresponding sub-board 10. Exemplarily, the second groove 506 can be located on the core board 101 and two first circuit layers 102 in the corresponding sub-board 10; or, the second groove 506 is located on the core board 101 and the first circuit layer 102 located at the bottom in the corresponding sub-board 10; or, the second groove 506 is located on the core board 101 and the first circuit layer 102 located at the top in the corresponding sub-board 10. At this time, the first through hole 501 at the bottom of the second through hole 502 penetrates to the first circuit layer 102 located at the bottom of the sub-board 10 corresponding to the second groove 506, and the conductive layer 507 in the first through hole 501 can connect the first circuit layer 102 and the second conductive layer 507 located at the bottom. In this way, the presence of residual partial conductive layer 507 in the first through hole 501 can be avoided to avoid the residual partial conductive layer 507 affecting signal transmission.

[0092] It is understandable that the position of the second groove 506, that is, the position of the second anti-plating block 504 in the core board 101, can be reasonably set according to the circuit patterns of the two first circuit layers 102 in the daughter board 10. For example, when the first circuit layer 102 in the lower part of the daughter board 10 has no circuit pattern in the area corresponding to the second groove 506, or when the first circuit layer 102 in the lower part of the daughter board 10 has a circuit pattern in the area corresponding to the second groove 506, but the conductive layer 507 needs to be connected to the first circuit layer 102, the second groove 506 needs to be set outside the first circuit layer 102 in the lower part of the daughter board 10. When the first circuit layer 102 in the upper part of the daughter board 10 has no circuit pattern in the area corresponding to the second groove 506, the second groove 506 can be outside the first circuit layer 102 in the upper part of the daughter board 10; when the first circuit layer 102 in the upper part of the daughter board 10 has a circuit pattern in the area corresponding to the second groove 506, the second groove 506 can be set inside the first circuit layer 102 in the upper part of the daughter board 10.

[0093] In the embodiment of the present application, the first anti-plating block 503 and the second anti-plating block 504 are both obtained by curing the filling material, and the filling material may include: epoxy-modified acrylic resin. During the production, the above materials may be mixed to form ink (filling material) with a certain fluidity, and then the ink is filled into the first groove 505 and the second groove 506, and cured (such as heat curing), thereby forming the first anti-plating block 503 and the second anti-plating block 504.

[0094] In the above implementation, the adhesion between the epoxy-modified acrylic resin and the seed layer is relatively small, so that the seed layer can fall off the first anti-plating block 503 and the second anti-plating block 504 during the cleaning process before electroplating; in addition, the epoxy-modified acrylic resin can also react with the chemical solution, so that after the seed layer is formed, part of the first anti-plating block 503 and the second anti-plating block 504 can be removed by the chemical solution to avoid part of the seed layer remaining on the first anti-plating block 503 and the second anti-plating block 504; furthermore, the epoxy-modified acrylic resin has a certain strength and can play a supporting role.

[0095] In some implementations, the filling material may also include a filler, a diluent, a defoamer, and a leveling agent. The filler may improve the mechanical properties of the first anti-plating block 503 and the second anti-plating block 504. For example, the material of the filler may include at least one of polytetrafluoroethylene, calcium carbonate, talcum powder, and barium sulfate. The diluent may adjust the viscosity of the ink before curing to facilitate filling the ink into the first groove 505 and the second groove 506; for example, the material of the diluent may include at least one of diethylene glycol ethyl ether acetate, nylon acid dimethyl ester, and dimethyl phenol. The defoamer may remove bubbles in the ink before curing to avoid bubbles in the first anti-plating block 503 and the second anti-plating block 504. For example, the material of the defoamer may include at least one of polyether ester and polyurethane. The leveling agent may adjust the fluidity of the ink before curing to avoid bubbles between the ink and the groove wall of the first groove 505 and the second groove 506; for example, the leveling agent includes at least one of n-butyl acrylate and xylene.

[0096] In some embodiments, the first resist block 503 and the second resist block 504 further include a photosensitizer, which can promote the reaction of the main resin and the monomer in the ink under light, thereby achieving the curing of the ink to form the first resist block 503 and the second resist block 504. Exemplarily, the photosensitizer can include at least one of 2-methyl-1-(4-methylthiophenyl)-2-morpholinyl-1-propanone and 2-isopropylthioxanthone.

[0097] It is understandable that when the ink is filled into the first groove 505 and the second groove 506, part of the ink will remain outside the first groove 505 and the second groove 506. Therefore, after the ink is filled, the first mask can be covered on the sub-plate 10 having the first groove 505, and the first mask is provided with a first opening, and the first opening is directly opposite to the first groove 505. The first mask is exposed and developed, so that the ink in the first groove 505 is solidified to form the first resist block 503, while the ink outside the first groove 505 is not exposed to light and is not solidified, so that the ink remaining outside the first groove 505 can be removed. Similarly, after filling with ink, a second mask is covered on the sub-plate 10 having the second groove 506, and a second opening is provided on the second mask, the second opening is opposite to the second groove 506, the second mask is exposed and developed, so that the ink in the second groove 506 is solidified, thereby forming a second anti-plating block 504, while the ink outside the second groove 506 is not exposed to light and is not solidified, so that the residual ink outside the second groove 506 can be removed.

[0098] Through the above arrangement, the ink remaining outside the first groove 505 and the second groove 506 is removed while the ink inside the first groove 505 and the second groove 506 is solidified, thereby simplifying the manufacturing difficulty of the circuit board.

[0099] In the above implementation, the mass fraction of epoxy modified acrylic resin is 25%-35% (such as 25%, 30%, 35%, etc.), the mass fraction of filler is 20%-40% (such as 20%, 30%, 40%, etc.), the mass fraction of photosensitizer is 3%-5% (such as 3%, 4%, 5%, etc.), the mass fraction of defoamer and leveling agent is 1%-3% (such as 1%, 2%, 3%, etc.), and the mass fraction of diluent is 10%-20% (such as 10%, 15%, 20%, etc.). In this way, the proportion of each component is appropriate, and bubbles can be avoided in the ink filled in the first groove 505 and the second groove 506 while ensuring that the ink has a certain fluidity, and bubbles can also be avoided from forming between the ink and the groove wall of the first groove 505 and the second groove 506.

[0100] Please refer to Figure 5 In the implementation manner where there are multiple through holes 50, the conductive layer 507 in one through hole 50 can be connected to the conductive layer 507 in another through hole 50 through the first circuit layer 102 connected thereto, so as to realize the transmission of signals between the two through holes 50. In some implementation manners, the conductive layer 507 in one through hole 50 is connected to the second circuit layer 40 ( Figure 1 The conductive layer 507 in another through hole 50 is connected to the second circuit layer 40 ( Figure 1As shown), the conductive layers 507 in the two through holes 50 are connected via the first circuit layer 102, thereby achieving connection between the top layer and the bottom layer of the circuit board, facilitating vertical power supply.

[0101] Please refer to Figure 6 In the embodiment of the present application, in the through hole 50, there are multiple second through holes 502; the corresponding multiple second through holes 502 are arranged at intervals along the center line of the through hole 50, there is a first through hole 501 between two adjacent second through holes 502, and the two adjacent second through holes 502 are connected through the first through hole 501. In this way, the conductive layer 507 on the hole wall of the first through hole 501 between the two second through holes 502 can realize the connection between at least two first circuit layers 102 corresponding to the first through hole 501, thereby improving the wiring density of the circuit board.

[0102] It is understandable that the number of sub-boards 10 between two second through holes 502 and the first circuit layer 102 connected to the conductive layer 507 in the first through hole 501 between the two second through holes 502 can be reasonably set according to actual needs.

[0103] In some embodiments, there are multiple through holes 50 on the circuit board, and the multiple through holes 50 are arranged at intervals. Such an arrangement can further improve the wiring density of the circuit board. It is understandable that the first through hole 501 and the second through hole 502 in each through hole 50 can be located at different positions to improve the flexibility of wiring.

[0104] In an implementation where the number of second through holes 502 in the through hole 50 is multiple, the conductive layer 507 in the first through hole 501 located between the two second through holes 502 can be connected to the conductive layer 507 in other through holes 50 through at least one first circuit layer 102 connected thereto, so as to realize signal transmission between the two through holes 50.

[0105] In some embodiments, one or more through holes 50 in the circuit board can also remove part of the conductive layer 507 by expanding the hole to retain part of the conductive layer 507 required for connection. In other words, the circuit board has through holes 50 whose position of the conductive layer 507 is controlled by the first anti-plating block 503 and the second anti-plating block 504, and also has through holes 50 whose position of the conductive layer 507 is controlled by expanding the hole; the through holes 50 whose position of the conductive layer 507 is controlled by the first anti-plating block 503 and the second anti-plating block 504 can be used in situations where the signal transmission requirements are high, while the through holes 50 whose position of the conductive layer 507 is controlled by expanding the hole can be used in situations where the signal transmission requirements are not high. With such a configuration, the production of the circuit board is more flexible.

[0106] In the embodiment of the present application, the through hole 50 may be filled with an insulator (not shown), and the material of the insulator may include resin, solder resist, etc. The insulator may be used to seal the through hole 50 to prevent impurities such as water or dust from entering the through hole 50; of course, the insulator may also play a certain supporting role, thereby improving the strength of the circuit board.

[0107] Please refer to Figure 7 The present application also provides a circuit board manufacturing method, which can be used to manufacture the circuit board in the above embodiment. The circuit board manufacturing method includes:

[0108] S101: forming a first resist block and a second resist block in a plurality of sub-boards, wherein the first resist block and the second resist block are located in different sub-boards.

[0109] Please refer to Figure 8 and Fig. 9 In an embodiment of the present application, the sub-board 10 may include a core board 101, and two first circuit layers 102 stacked on two surfaces of the core board 101, that is, one first circuit layer 102 is arranged on one surface of the core board 101, and the other first circuit layer 102 is arranged on the other surface of the core board 101.

[0110] like Figure 8 As shown, for example, before forming the first anti-plating block and the second anti-plating block, a metal layer 103 may be formed on both surfaces of the core board 101, and then the two metal layers 103 are patterned to form two first circuit layers 102 (such as Fig. 9 shown).

[0111] In some embodiments, the two metal layers 103 may be formed by electroplating. Of course, the two metal layers 103 may be directly attached to the core board 101, and then part of the metal layers 103 may be removed by etching or milling to form a first circuit layer 102 with a certain pattern. In other embodiments, a metal layer with a certain pattern may be directly formed on the core board 101 by electroplating to form the first circuit layer 102.

[0112] Please refer to Fig.10In the embodiment of the present application, forming the first anti-plating block and the second anti-plating block in the plurality of sub-boards 10 includes: forming a first groove 505 on one of the plurality of sub-boards 10, forming a second groove 506 on another of the plurality of sub-boards 10, forming the first anti-plating block in the first groove 505, and forming the second anti-plating block in the second groove 506. Through the above arrangement, the first anti-plating block is formed in the first groove 505, and the second anti-plating block is formed in the second groove, which facilitates the manufacture and formation of the first anti-plating block and the second anti-plating block; in addition, by setting the positions of the first groove 505 and the second groove 506, the positions of the first anti-plating block and the second anti-plating block can be adjusted.

[0113] In the above implementation, the first groove 505 and the second groove 506 can be formed on the sub-board 10 by drilling. Of course, the first groove 505 and the second groove 506 can also be formed on the sub-board 10 by laser grooving. Due to the good coherence of the laser, the size accuracy and position accuracy of the first groove 505 and the second groove 506 can be improved.

[0114] Please refer to Fig.11 and Fig.12 In some embodiments, forming the first anti-plating block 503 in the first groove 505 and forming the second anti-plating block 504 in the second groove 506 includes: forming a filling material 509 (such as the ink in the above embodiment) in the first groove 505 and the second groove 506 by a printing process; curing the filling material 509 to form the first anti-plating block 503 and the second anti-plating block 504. It can be understood that in the printing process, the steel plate with the printing port is covered on the sub-board 10, the printing port is facing the first groove 505, and then the filling material 509 is applied on the printing port, and at the same time, part of the filling material 509 will be filled in the first groove 505. Similarly, the steel plate with the printing port is covered on the sub-board 10, the printing port is facing the second groove 506, and then the filling material 509 is applied on the printing port, and at the same time, part of the filling material 509 will be filled in the second groove 506. With such a configuration, the filling material 509 can be directly filled into the first groove 505 and the second groove 506. Compared with coating the filling material 509 on the entire sub-board 10 and then filling the filling material 509 into the first groove 505 and the second groove 506, the amount of filling material 509 can be saved, thereby reducing the production cost of the circuit board.

[0115] After forming the filling material 509, the circuit board manufacturing method provided in the embodiment of the present application further includes removing the filling material 509 remaining outside the first groove 505 and the second groove 506. Since the filling material 509 has a certain fluidity, it is easy to form residual filling material 509 outside the first groove 505 and the second groove 506 during the filling process. Removing the residual filling material 509 can prevent the residual filling material 509 from affecting the subsequent manufacturing of the circuit board and the operation of the circuit board.

[0116] Exemplarily, the filling material 509 may include a photosensitizer, and accordingly, removing the filling material 509 remaining outside the first groove 505 and the second groove 506 includes: covering a first mask on a sub-board 10, the first mask being provided with a first opening, the first opening facing the first groove 505, exposing the first mask, and performing a development process to remove the filling material 509 outside the first groove 505. It can be understood that when the first mask is exposed, the photosensitizer can promote the reaction of the main resin and the monomer in the ink, thereby achieving the curing of the ink; while the filling material 509 remaining outside the first groove 505 is not exposed, the unexposed filling material 509 can be removed by a specific solution, and the exposed filling material 509 does not react with the solution due to the reaction, and is retained to form the first anti-plating block 503 located in the first groove 505.

[0117] Similarly, a second mask is covered on another sub-board 10, and a second opening is provided on the second mask, and the second opening is directly facing the second groove 506. The second mask is exposed and developed to remove the filling material 509 outside the second groove 506. It can be understood that when the second mask is exposed, the photosensitizer can promote the reaction between the main resin and the monomer in the ink, thereby achieving the curing of the ink; while the filling material 509 remaining outside the first groove 505 is not exposed, and the unexposed filling material 509 can be removed by a specific potion, and the exposed filling material 509 does not react with the potion due to the reaction, and is retained to form a second resist block 504 located in the second groove 506.

[0118] Through the above arrangement, the filling material 509 remaining outside the first groove 505 and the second groove 506 is removed by exposure and development techniques, with high processing accuracy, which can avoid damaging the filling material 509 inside the first groove 505 and the second groove 506.

[0119] In other embodiments, forming the first anti-plating block 503 in the first groove 505 and forming the second anti-plating block 504 in the second groove 506 includes: filling the first groove 505 and the second groove 506 with a filling material 509 by a dispensing process to form the first anti-plating block 503 in the first groove 505 and the second anti-plating block 504 in the second groove 506. In this way, the dispensing process has a high precision, and the filling material 509 can be accurately filled in the first groove 505 and the second groove 506, which can simplify the manufacturing process and reduce the difficulty of manufacturing the circuit board. Accordingly, the filling material 509 may not include a photosensitizer. After the filling material 509 is filled in the first groove 505 and the second groove 506, the filling material 509 can be cured by heating to form the first anti-plating block 503 located in the first groove 505 and the second anti-plating block 504 located in the second groove 506.

[0120] Continue to refer to Figure 7 In the embodiment of the present application, after forming the first anti-plating block 503 and the second anti-plating block 504, the following steps are further included:

[0121] S102: stacking a plurality of sub-boards to form a first dielectric layer between two adjacent sub-boards.

[0122] like Fig.13 As shown, the first dielectric layer 20 can be used to connect adjacent sub-boards 10 , and can also be used to insulate the first circuit layers 102 in two adjacent sub-boards 10 that are close to each other.

[0123] For example, the first dielectric layer 20 may be in a sheet shape, and accordingly, a plurality of first dielectric layers 20 and a plurality of sub-boards 10 may be alternately stacked together. Of course, the first dielectric layer 20 may also be in a colloid state or have a certain fluidity, and accordingly, the first dielectric layer 20 may be coated on a sub-board 10, and then another sub-board 10 may be attached to the first dielectric layer 20, and then the first dielectric layer 20 may be formed on the sub-board 10, and the process may be repeated.

[0124] Continue to refer to Figure 7 In the above implementation, the circuit board manufacturing method provided in the embodiment of the present application further includes:

[0125] S103: forming a second dielectric layer on the outermost sub-board among the plurality of sub-boards, and forming a second circuit layer on the second dielectric layer.

[0126] Continue to refer to Fig.13For example, the second dielectric layer 30 may be in the form of a sheet, and accordingly, the second dielectric layer 30 may be attached to the outermost sub-board 10 ; of course, the second dielectric layer 30 may also be in the form of a colloid or have a certain fluidity, and accordingly, the second dielectric layer 30 may be coated on the outermost sub-board 10 .

[0127] In the above implementation, the second circuit layer 40 having a certain pattern can be formed on the second dielectric layer 30 by electroplating; of course, a metal layer can also be first formed on the second dielectric layer 30, and part of the metal layer can be removed by milling or etching to form the second circuit layer 40 having a certain pattern.

[0128] In the embodiment of the present application, after forming the second circuit layer 40, the second dielectric layer 30, each sub-board 10 and each first dielectric layer 20 are pressed together. In other words, the second circuit layer 40, the second dielectric layer 30, each sub-board 10 and each first dielectric layer 20 are pressed and heated at the same time, so that each first dielectric layer 20 is cured, and then each sub-board 10 is connected together, and at the same time, the second dielectric layer 30 connects the second circuit layer 40 to the outermost sub-board 10.

[0129] It can be understood that in the embodiment of the present application, there are two second dielectric layers 30 and two second circuit layers 40, one second dielectric layer 30 and one second circuit layer 40 are arranged on the uppermost sub-board 10, and the other second dielectric layer 30 and another second circuit layer 40 are arranged on the lowermost sub-board 10.

[0130] Continue to refer to Figure 7 The circuit board manufacturing method provided in the embodiment of the present application further includes, after forming the second circuit layer 40:

[0131] S104: forming a through hole, wherein the through hole penetrates the second circuit layer, the second dielectric layer, each sub-board and each first dielectric layer.

[0132] Please refer to Fig.14 It is understandable that the through hole 50 can be formed by drilling, or by laser drilling. The laser drilling method can improve the size accuracy and position accuracy of the through hole 50.

[0133] In the above implementation, the through hole 50 includes a first through hole 501 and a second through hole 502 that are connected. The second through hole 502 passes through the first anti-plating block 503, the second anti-plating block 504, and the sub-board 10 and the first dielectric layer 20 between the first anti-plating block 503 and the second anti-plating block 504. The first through hole 501 is connected to one end of the second through hole 502.

[0134] Continue to refer to Figure 7The circuit board manufacturing method provided in the embodiment of the present application further includes, after forming the through hole 50:

[0135] S105: forming a seed layer on the hole wall of the through hole.

[0136] like Fig.15 As shown, it is understandable that the material of the seed layer 508 may include a colloid or coating containing palladium ions for subsequent electroplating. The seed layer 508 covers the hole walls of the first through hole 501 and the second through hole 502 .

[0137] Continue to refer to Figure 7 The circuit board manufacturing method provided in the embodiment of the present application further includes, after forming the seed layer 508:

[0138] S106: Electroplating is performed through the seed layer to form a conductive layer.

[0139] like Fig.16 As shown, illustratively, the circuit board is placed in the electroplating solution, and power can be supplied to the seed layer 508 to form a conductive layer 507 on the seed layer 508. During the electroplating process, the first anti-plating block 503 and the second anti-plating block 504 are used to prevent the conductive layer 507 from being formed on the hole wall of the second through hole 502, so that the conductive layer 507 covers the hole wall of the first through hole 501. It can be understood that the seed layer 508 covers the hole wall of the first through hole 501 and the hole wall of the second through hole 502, and the adhesion between the seed layer 508 and the first anti-plating block 503 and the second anti-plating block 504 is relatively small; before electroplating, the circuit board generally needs to be cleaned; during the cleaning process, the seed layer 508 on the first anti-plating block 503 and the second anti-plating block 504 falls off due to the low adhesion, while the seed layer 508 on the hole walls of other through holes 50 is retained; thereafter, the circuit board is placed in the plating solution, and by supplying power to the seed layer 508, a conductive layer 507 can be formed at the seed layer 508. Among them, since there is no seed layer 508 on the first anti-plating block 503 and the second anti-plating block 504, accordingly, the seed layer 508 on the hole wall of the second through hole 502 between the first anti-plating block 503 and the second anti-plating block 504 will not be charged, so that the conductive layer 507 is only formed on the hole wall of the first through hole 501, and the conductive layer 507 will not be formed on the hole wall of the second through hole 502.

[0140] In the above implementation, the first through hole 501 is located outside the second through hole 502, and the first through hole 501 passes through the second circuit layer 40. Accordingly, during electroplating, power can be supplied to the seed layer 508 at the hole wall of the first through hole 501 through the second circuit layer 40. In other implementations, the second through hole 502 is multiple (e.g. Figure 6As shown), a plurality of second through holes 502 are arranged at intervals along the center line of the through hole 50, and a first through hole 501 is provided between adjacent second through holes 502. Accordingly, a seed layer 508 at the hole wall of the first through hole 501 between adjacent second through holes 502 can be connected to one or more first circuit layers 102 penetrated by the first through hole 501. During electroplating, the seed layer 508 at the hole wall of the first through hole 501 between adjacent second through holes 502 can be powered by the first circuit layer 102 connected thereto, thereby forming a conductive layer 507 at the hole wall of the first through hole 501 between adjacent second through holes 502.

[0141] The circuit board manufactured by the circuit board manufacturing method provided in the embodiment of the present application comprises a plurality of stacked sub-boards 10, wherein a first dielectric layer 20 is stacked between adjacent sub-boards 10, and the sub-boards 10 comprise a core board 101 and a first circuit layer 102 arranged on the surface of the core board 101; a second dielectric layer 30 and a second circuit layer 40 are arranged on the outermost sub-board 10 among the plurality of sub-boards 10, and the second dielectric layer 30 is located between the second circuit layer 40 and the outermost sub-board 10; a through hole 50 penetrates each sub-board 10, each first dielectric layer 20, the second dielectric layer 30 and the second circuit layer 40; a first anti-plating block 503 is located in one sub-board 10, and a second anti-plating block 504 is located in one sub-board 10, and a second anti-plating block 505 is located in one sub-board 10, and a second anti-plating block 506 is located in one sub-board 10, and a second anti-plating block 507 is located in one sub-board 10, and a second anti-plating block 508 is located in one sub-board 10, and a second anti-plating block 509 is located in one sub-board 10, and a second anti-plating block 501 is located in one sub-board 10, and a second anti-plating block 502 is located in one sub-board 10, and a second anti-plating block 503 is located in one sub-board 10, and a second anti-plating block 504 is located in one sub-board 10, and a second anti-plating block 505 is located in one sub-board 10, and a second anti-plating block 506 is located in one sub-board 10, and a second anti-plating block 507 is Block 504 is located in another sub-board 10; through hole 50 includes a first through hole 501 and a second through hole 502 that are connected, and the second through hole 502 passes through the first anti-plating block 503, the second anti-plating block 504, and the sub-board 10 and the first dielectric layer 20 between the first anti-plating block 503 and the second anti-plating block 504; the first anti-plating block 503 and the second anti-plating block 504 are used to prevent the conductive layer 507 from being formed on the hole wall of the second through hole 502, so that the conductive layer 507 covers the hole wall of the first through hole 501; the conductive layer 507 can realize the connection between the second circuit layer 40 and one or more first circuit layers 102 corresponding to the first through hole 501. Figure 3 In the circuit board shown in the figure, a conductive layer 507 is formed on the entire hole wall of the through hole 50, and then part of the conductive layer 507 is removed by expanding the hole. In the embodiment of the present application, when the conductive layer 507 is formed by electroplating, the first anti-plating block 503 and the second anti-plating block 504 prevent the conductive layer 507 from being formed on the hole wall of the second through hole 502, so that the formed conductive layer 507 covers the hole wall of the first through hole 501, and there is no need to expand the hole. The aperture of the through hole 50 can be reduced, so that the through hole 50 is prevented from occupying too much wiring space of the circuit board, and the wiring density of the circuit board can be improved.

[0142] Please refer to Fig.17 and Fig.18In some embodiments, before electroplating through the seed layer 508, the process further includes: removing part of the first resist block 503 and part of the second resist block 504 through the through hole 50, so that the side wall of the first resist block 503 facing the center line of the second through hole 502 is located in the first groove 505, and the side wall of the second resist block 504 facing the center line of the second through hole 502 is located in the second groove 506, thereby removing the seed layer 508 on the first resist block 503 and the second resist block 504. In this way, the seed layer 508 on the first resist block 503 and the second resist block 504 can be removed before electroplating to avoid the formation of the conductive layer 507 on the first resist block 503 and the second resist block 504 due to the residue of the seed layer 508.

[0143] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0144] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A circuit board, characterized in that: include: A plurality of sub-boards, wherein the plurality of sub-boards are stacked, and a first dielectric layer is stacked between adjacent sub-boards; The sub-board includes a core board and a first circuit layer arranged on a surface of the core board; A second circuit layer, wherein the second circuit layer is disposed on the outermost sub-board among the plurality of sub-boards, and a second dielectric layer is disposed between the second circuit layer and the outermost sub-board among the plurality of sub-boards; A through hole, wherein the through hole penetrates each of the sub-boards, each of the first dielectric layer, the second dielectric layer and the second circuit layer; a first anti-plating block and a second anti-plating block, wherein the first anti-plating block and the second anti-plating block are located in different sub-plates; the through hole comprises a first through hole and a second through hole that are connected, wherein the second through hole passes through the first anti-plating block, the second anti-plating block, and the sub-plate and the first dielectric layer between the first anti-plating block and the second anti-plating block; Conductive layer, the first anti-plating block and the second anti-plating block are used to prevent the conductive layer from being formed on the hole wall of the second through hole, so that the conductive layer covers the hole wall of the first through hole.

2. The circuit board according to claim 1, characterized in that: A first groove and a second groove are arranged on the hole wall of the second through hole, the first anti-plating block is arranged in the first groove, and the side wall of the first anti-plating block facing the center line of the second through hole is located in the first groove; the second anti-plating block is arranged in the second groove, and the side wall of the second anti-plating block facing the center line of the second through hole is located in the second groove.

3. The circuit board according to claim 2, characterized in that: The first groove is located on the core board in the corresponding sub-board, or the first groove is located on the core board and the first circuit layer in the corresponding sub-board; the second groove is located on the core board in the corresponding sub-board, or the second groove is located on the core board and the first circuit layer in the corresponding sub-board.

4. The circuit board according to any one of claims 1 to 3, characterized in that: The first anti-plating block and the second anti-plating block are both obtained by curing a filling material, and the filling material includes: epoxy-modified acrylic resin.

5. The circuit board according to claim 4, characterized in that: The filling material also includes: a photosensitizer.

6. The circuit board according to claim 5, characterized in that: The mass fraction of the photosensitizer is 3%-5%.

7. The circuit board according to claim 5 or 6, characterized in that: The photosensitizer includes at least one of 2-methyl-1-(4-methylthiophenyl)-2-morpholinyl-1-propanone and 2-isopropylthioxanthone.

8. The circuit board according to any one of claims 4 to 7, characterized in that: The filling material also includes: filler, diluent, defoamer and leveling agent.

9. The circuit board according to claim 8, characterized in that: The mass fraction of the epoxy modified acrylic resin is 25%-35%, the mass fraction of the filler is 20%-40%, the mass fraction of the defoamer and the leveling agent is 1%-3%, and the mass fraction of the diluent is 10%-20%.

10. The circuit board according to claim 8 or 9, characterized in that: The filler includes at least one of polytetrafluoroethylene, calcium carbonate, talc and barium sulfate; the defoamer includes at least one of polyether ester and polyurethane; the leveling agent includes at least one of n-butyl acrylate and xylene; the diluent includes at least one of diethylene glycol ethyl ether acetate, dimethyl nylonate and dimethylphenol.

11. The circuit board according to any one of claims 1 to 10, characterized in that: There are a plurality of the second through holes, and the plurality of the second through holes are arranged at intervals along the center line of the through hole, and adjacent second through holes are connected through the first through hole.

12. The circuit board according to any one of claims 1 to 11, characterized in that: There are multiple through holes, and the multiple through holes are arranged at intervals.

13. The circuit board according to claim 12, characterized in that: Among the plurality of through holes, the conductive layer in one through hole is connected to the conductive layer in another through hole through the first circuit layer connected thereto.

14. The circuit board according to any one of claims 1 to 13, characterized in that: The through hole is filled with an insulator.

15. An electronic device, characterized in that: include: A housing and a circuit board as claimed in any one of claims 1 to 14, wherein the circuit board is arranged on the housing.

16. A method for manufacturing a circuit board, characterized in that: include: A first anti-plating block and a second anti-plating block are formed in a plurality of sub-boards, wherein the first anti-plating block and the second anti-plating block are located in different sub-boards; the sub-boards include a core board and a first circuit layer arranged on a surface of the core board; The plurality of sub-boards are stacked to form a first dielectric layer between two adjacent sub-boards; forming a second dielectric layer on the outermost sub-board among the plurality of sub-boards, and forming a second circuit layer on the second dielectric layer; Forming a through hole, wherein the through hole penetrates the second circuit layer, the second dielectric layer, each of the sub-boards and each of the first dielectric layers; the through hole comprises a first through hole and a second through hole that are connected, and the second through hole penetrates the first anti-plating block, the second anti-plating block, and the sub-board and the first dielectric layer between the first anti-plating block and the second anti-plating block; forming a seed layer on the hole wall of the through hole; The seed layer is electroplated to form a conductive layer, and the first resist block and the second resist block are used to prevent the conductive layer from being formed on the hole wall of the second through hole, so that the conductive layer covers the hole wall of the first through hole.

17. The method for manufacturing a circuit board according to claim 16, characterized in that: Before electroplating through the seed layer, the method further includes: removing a portion of the first resist block and a portion of the second resist block through the through hole to remove the seed layer on the first resist block and the second resist block.

18. The method for manufacturing a circuit board according to claim 16 or 17, characterized in that: Forming the first anti-plating block and the second anti-plating block in a plurality of sub-boards includes: forming a first groove on one of the plurality of sub-boards, forming a second groove on another of the plurality of sub-boards, forming the first anti-plating block in the first groove, and forming the second anti-plating block in the second groove.

19. The method for manufacturing a circuit board according to claim 18, characterized in that: Forming the first anti-plating block in the first groove and forming the second anti-plating block in the second groove includes: forming a filling material in the first groove and the second groove through a printing process; removing the filling material remaining outside the first groove and the second groove; and curing the filling material to form the first anti-plating block and the second anti-plating block.

20. The method for manufacturing a circuit board according to claim 19, characterized in that: Removing the filling material remaining outside the first groove and the second groove includes: covering a first mask plate on one of the sub-plates, the first mask plate being provided with a first opening, the first opening facing the first groove, exposing the first mask plate, and performing a development process to remove the filling material outside the first groove; covering a second mask plate on the other sub-plate, the second mask plate being provided with a second opening, the second opening facing the second groove, exposing the second mask plate, and performing a development process to remove the filling material outside the second groove.

21. The method for manufacturing a circuit board according to claim 18, characterized in that: Forming the first anti-plating block in the first groove and forming the second anti-plating block in the second groove includes: filling the first groove and the second groove with filling material through a dispensing process to form the first anti-plating block in the first groove, and forming the second anti-plating block in the second groove.

22. The method for manufacturing a circuit board according to any one of claims 16 to 21, characterized in that: After forming the second circuit layer, the method includes: pressing the second circuit layer, the second dielectric layer, each of the sub-boards and each of the first dielectric layers.

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