Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, relates to the technical field of semiconductor chips, and aims to solve the problem of how to reduce electromagnetic interference generated between transistors. The semiconductor structure includes a plurality of first transistors and an isolation structure. The at least two first transistors are arranged along a first direction. The isolation structure is located between two adjacent first transistors in the first direction. The isolation structure comprises a twin crystal induction layer and a conductor layer, and the twin crystal induction layer is located between the conductor layer and the first transistor and makes contact with the conductor layer. The semiconductor structure is used for realizing data reading and writing operations.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is composed of multiple memory cells, each of which is composed of a capacitor controlled by a transistor, that is, DRAM is a memory cell of 1 transistor and 1 capacitor (1T1C).

[0003] As the integration of memory arrays increases, the distance between transistors becomes closer and closer. How to reduce the electromagnetic interference generated between transistors is a problem that needs to be solved at present. Summary of the invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, and a storage system, which aim to solve the problem of how to reduce electromagnetic interference generated between transistors.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, a semiconductor structure is provided. The semiconductor structure includes a plurality of first transistors and an isolation structure. At least two first transistors are arranged along a first direction. The isolation structure is located between two first transistors adjacent to each other in the first direction. The isolation structure includes a twin inducing layer and a conductor layer, wherein the twin inducing layer is located between the conductor layer and the first transistor and contacts the conductor layer.

[0007] In the semiconductor structure provided by the present disclosure, due to the low crystal energy and high stability of the twin structure, the risk of crystallization of the conductor layer is reduced under high temperature process, and the voids generated inside the conductor layer due to the recombination of the crystal grains can be reduced. In this way, when the etching depth is controlled by controlling the etching time, the accuracy of the etching depth can be improved, which is conducive to improving the uniformity of the height of the end of the conductor layer close to the bonding surface, and is conducive to improving the precise control of the height of the two ends of the conductor layer in the third direction.

[0008] At this time, precise control of the height of the conductor layer at both ends in the third direction can effectively isolate interference between two adjacent first transistors located on opposite sides of the isolation structure while preventing the conductor layer from causing leakage current in the first transistor.

[0009] In some embodiments, the lattice type of the twin inducing layer is a face-centered cubic lattice, and the crystal orientation is

[111] .

[0010] In some embodiments, the material of the twin inducing layer includes aluminum oxide and / or hafnium oxide.

[0011] In some embodiments, the crystal structure of the conductor layer is a twin structure.

[0012] In some embodiments, the material of the conductor layer includes titanium nitride.

[0013] In some embodiments, the isolation structure further includes a first insulating layer and a second insulating layer. Along a third direction, the first insulating layer is located on one side of the conductor layer. The third direction is perpendicular to the first direction. Along the third direction, the first insulating layer is located on the other side of the conductor layer.

[0014] In some embodiments, the twin inducing layer includes a first portion and a second portion, wherein the first portion is located between the conductor layer and the first transistor, and the second portion is located between the first insulating layer and the first transistor, and between the second insulating layer and the first transistor.

[0015] In some embodiments, the thickness of the second portion is less than the thickness of the first portion.

[0016] In some embodiments, the plurality of first transistors are divided into a plurality of first transistor groups, each of the first transistor groups includes two first transistors arranged in the first direction, and at least two first transistor groups are arranged along the first direction. The isolation structure is located between two adjacent first transistor groups. The first transistor group includes a gate structure and a semiconductor body, and along the first direction, the semiconductor body is arranged on opposite sides of the gate structure.

[0017] In some embodiments, the semiconductor structure further includes an isolation layer, and the at least one isolation layer is located between the gate structure and the semiconductor body, and between the isolation structure and the semiconductor body.

[0018] In some embodiments, the gate structure includes a gate dielectric layer, a gate layer and an insulating structure. The gate dielectric layer is disposed on the sidewall of the semiconductor body. The gate layer is disposed on a side of the gate dielectric layer away from the semiconductor body. The insulating structure covers at least two ends of the gate layer in a third direction. The third direction is perpendicular to the first direction.

[0019] In some embodiments, two ends of the conductor layer in the third direction are located between two ends of any adjacent gate layer in the third direction.

[0020] On the other hand, a method for preparing a semiconductor structure is provided, comprising: forming an intermediate semiconductor structure. The intermediate semiconductor structure comprises a substrate and a plurality of first grooves, wherein the substrate has a first surface and a second surface arranged opposite to each other along a third direction, and the first grooves are arranged on the first surface of the substrate and extend along the second direction. The plurality of first grooves are arranged in the first direction. The second direction intersects with the first direction and is perpendicular to the third direction. An isolation structure is formed in the first groove. The isolation structure comprises a twin inducing layer and a conductor layer, wherein the twin inducing layer is located between the conductor layer and the sidewall of the first groove and contacts the conductor layer.

[0021] In some embodiments, the forming of the intermediate semiconductor structure includes: forming a protective layer on the first surface of the substrate. Forming a first trench and a second trench on the first surface of the substrate. The first trench and the second trench extend along the second direction and are alternately arranged in the first direction. Forming an isolation layer on the substrate. The isolation layer covers the first surface of the substrate, and the bottom wall and side wall of the first trench and the second trench. Forming a sacrificial layer in the first trench and the second trench. Removing the sacrificial layer in the first trench.

[0022] In some embodiments, forming an isolation structure in the first trench comprises: forming an initial isolation structure in the first trench. The initial isolation structure comprises a twin-inducing film and a conductor film, the twin-inducing film at least covering the sidewall and the bottom wall of the first trench, and the conductor film being located on a side of the twin-inducing film away from the substrate and in contact with the twin-inducing film. Removing a portion of the substrate located on a side of the twin-inducing film away from the first surface, so that the twin-inducing film is exposed. Removing a portion of the twin-inducing film exposed, so that the conductor film is exposed. Removing a first preset portion of the conductor film.

[0023] In some embodiments, the forming of the initial isolation structure in the first trench comprises: forming a twin-inducing film. The twin-inducing film covers the first surface of the substrate and the sidewalls and bottom wall of the first trench. Forming a conductor film on the twin-inducing film. The conductor film covers the twin-inducing film and fills the first trench. Removing the portion of the conductor film covering the first surface of the substrate and the second preset portion of the conductor film located in the first trench. Removing the portion of the twin-inducing film covering the first surface of the substrate, the portion of the isolation layer covering the first surface of the substrate, and the protective layer.

[0024] In some embodiments, a second preset portion of the conductor film located in the first groove is removed to form a first sub-groove. Before removing the portion of the twin-inducing film covering the first surface of the substrate, the portion of the isolation layer covering the first surface of the substrate, and the protective layer, the initial isolation structure is formed in the first groove, and further includes: forming a first insulating film in the first sub-groove. The first insulating film covers the first surface of the substrate and fills the first sub-groove. In the process of removing the portion of the twin-inducing film covering the first surface of the substrate, the portion of the isolation layer covering the first surface of the substrate, and the protective layer, the portion of the first insulating film covering the first surface of the substrate is also removed.

[0025] In some embodiments, the lattice type of the twin inducing layer is a face-centered cubic lattice, and the crystal orientation is

[111] .

[0026] In some embodiments, the material of the twin inducing layer includes aluminum oxide and / or hafnium oxide.

[0027] In some embodiments, the crystal structure of the conductor layer is a twin structure.

[0028] It can be understood that the beneficial effects that can be achieved by the method for preparing the semiconductor structure provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor structure described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0030] Figure 1 is a three-dimensional structural diagram of a memory according to some embodiments;

[0031] Figure 2 is a cross-sectional view of a memory according to some embodiments;

[0032] Figure 3 for Figure 1 A structural diagram of a storage unit in ;

[0033] Figure 4 for Figure 3 The equivalent circuit diagram of the memory cell shown;

[0034] Figure 5is a top view of a semiconductor structure according to some embodiments;

[0035] Figure 6 for Figure 5 A cross-sectional view along the section line AA;

[0036] Figure 7 is a structural diagram of a face-centered cubic lattice according to some embodiments;

[0037] Figure 8 is a structural diagram of a crystal having a crystal orientation of

[100] according to some embodiments;

[0038] Fig. 9 is a structural diagram of a crystal having a crystal orientation of

[110] according to some embodiments;

[0039] Fig.10 is a structural diagram of a crystal having a crystal orientation of

[111] according to some embodiments;

[0040] Figures 11 to 17 is a flow chart of a method for preparing a semiconductor structure according to some embodiments;

[0041] Fig.18 is a process step diagram of a method for preparing a semiconductor structure according to some embodiments;

[0042] Fig.19 is a top view of a substrate according to some embodiments;

[0043] Fig. 20 and Fig.21 is a process step diagram of a method for preparing a semiconductor structure according to some embodiments;

[0044] Fig. 22 is a block diagram of a storage system according to some embodiments;

[0045] Fig.23 is a block diagram of a storage system according to some other embodiments. DETAILED DESCRIPTION

[0046] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0047] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0048] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0049] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0050] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0051] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0052] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0053] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0054] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0055] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0056] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0057] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0058] Figure 1 is a three-dimensional structural diagram of a memory according to some embodiments, Figure 2 is a cross-sectional view of a memory according to some embodiments, Figure 3 for Figure 1 The structure diagram of a storage unit in Figure 4 for Figure 3 The equivalent circuit diagram of the memory cell is shown.

[0059] It should be noted that in Figure 1 and Figure 2In the embodiment, the memory 10 extends in the XY plane, and the first direction X and the second direction Y are, for example, two orthogonal directions in the plane where the memory 10 is located (for example, the plane where the common layer GD is located): the first direction X is, for example, the extension direction of the bit line BL, and the second direction Y is, for example, the extension direction of the word line WL. The third direction Z is perpendicular to the plane where the memory 10 is located, that is, perpendicular to the XY plane.

[0060] See also Figure 1 and Figure 2 Some embodiments of the present disclosure provide a memory 10 including a semiconductor device 100 and a peripheral device 200. The peripheral device 200 may be disposed on one side of the semiconductor device 100.

[0061] like Figure 2 As shown, the semiconductor device 100 may include a memory cell array 110 and a common layer GD. The peripheral device 200 may be disposed on a side of the memory cell array 110 away from the common layer GD, for example.

[0062] See also Figure 2 and Figure 3 The common layer GD can be connected to a first reference voltage, which can be a ground voltage or other voltages. The material of the common layer GD can be, for example, a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials.

[0063] See also Figure 1 and Figure 2 The memory cell array 110 includes a plurality of memory cells 111 arranged in an array along a first direction X and a second direction Y.

[0064] Among them, Figure 3 and Figure 4 As shown, the memory cell 111 includes a first transistor T1 and a capacitor C. The first electrode of the first transistor T1 is connected to the bit line BL, the second electrode of the first transistor T1 is connected to one plate of the capacitor C, and the other plate of the capacitor C can be connected to the common layer GD. The gate of the first transistor T1 is connected to the word line WL. In this way, the first transistor T1 can be turned on or off by applying a voltage through the word line WL, and when the first transistor T1 is turned on, the bit line BL performs a read or write operation on the first transistor T1.

[0065] In some embodiments, see Figure 1 and Figure 2 The semiconductor device 100 may further include an array interconnect layer 120 .

[0066] The array interconnect layer 120 may be coupled to the storage unit 111 to implement transmission of electrical signals between the storage unit 111 and an external circuit (such as the peripheral circuit mentioned below).

[0067] For example, Figure 2 As shown, the array interconnect layer 120 may include one or more first interconnect conductor layers 121, one or more first interlayer insulating layers 122, and a plurality of first contacts 123 insulated from each other by the first interlayer insulating layers 122. Different first interconnect conductor layers 121 may be coupled via the first contacts 123.

[0068] The material of the first interconnect conductor layer 121 and the first contact 123 may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials.

[0069] The material of the first interlayer insulating layer 122 is an insulating material, and the insulating material is, for example, a combination of one or more of silicon oxide, silicon nitride, and a high dielectric constant insulating material, or may be other suitable materials.

[0070] like Figure 2 As shown, the peripheral device 200 may include a peripheral circuit. The peripheral circuit is configured to control and sense the array device. The peripheral circuit may be any suitable digital, analog, and / or mixed signal control and sensing circuit for supporting the operation (or work) of the array device, including but not limited to a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor). The peripheral circuit may also include any other circuit compatible with an advanced logic process, including a logic circuit (e.g., a processor and a programmable logic device (PLD) or a storage circuit (e.g., a static random access memory (SRAM)).

[0071] In some embodiments, Figure 2 As shown, the peripheral device 200 may include a substrate 210, a second transistor T2 disposed on the substrate 210, and a peripheral interconnect layer 220 disposed on the substrate 210. The peripheral circuit may include the second transistor T2.

[0072] The substrate 210 may be made of single crystal silicon or other suitable materials, such as silicon germanium, germanium or silicon-on-insulator thin film. The peripheral interconnection layer 220 is coupled to the second transistor T2 to transmit electrical signals between the transistor T2 and the peripheral interconnection layer 220 .

[0073] For example, Figure 2 As shown, the peripheral interconnection layer 220 may include one or more second interconnection conductor layers 231, one or more second interlayer insulating layers 232, and a plurality of second contacts 233 insulated from each other by the second interlayer insulating layers 232. Different second interconnection conductor layers 231 may be coupled via the second contacts 233.

[0074] The second interconnect conductor layer 231 and the second contact 233 may be made of a conductive material, such as tungsten, cobalt, copper, aluminum, or a combination of one or more metal silicides, or other suitable materials.

[0075] The material of the second interlayer insulating layer 232 is an insulating material, and the insulating material is, for example, a combination of one or more of silicon oxide, silicon nitride, and a high dielectric constant insulating material, or other suitable materials.

[0076] The peripheral interconnect layer 220 can be coupled to the array interconnect layer 120, so that the semiconductor device 100 and the peripheral device 200 can be coupled. Specifically, since the peripheral interconnect layer 220 is coupled to the array interconnect layer 120, the peripheral circuit in the peripheral device 200 can be coupled to the memory cell 111 in the semiconductor device 100 to achieve the transmission of electrical signals between the peripheral circuit and the memory cell 111.

[0077] In some possible implementations, the peripheral interconnect layer 220 is bonded to the array interconnect layer 120, so that the second contact 233 in the peripheral interconnect layer 220 contacts the corresponding first contact 123 in the array interconnect layer 120, so that the peripheral circuit in the peripheral device 200 can be coupled to the memory cell 111 in the semiconductor device 100. The surface where the peripheral interconnect layer 220 and the array interconnect layer 120 contact can be referred to as a bonding surface S.

[0078] See also Figure 1 and Figure 2 Some embodiments of the present disclosure provide a semiconductor structure 400 . The memory 10 includes the semiconductor structure 400 .

[0079] Exemplarily, the semiconductor structure 400 may be a memory 10, for example, the semiconductor structure 400 includes a semiconductor device 100 and a peripheral device 200. Exemplarily, the semiconductor structure 400 may also be a part of the memory 10, for example, the semiconductor structure 400 is a semiconductor device 100 in the memory 10, which is not specifically limited in the embodiments of the present disclosure.

[0080] In some embodiments, see Figure 2 and Figure 5, the semiconductor structure 400 includes a plurality of first transistors T1 and an isolation structure 410 .

[0081] like Figure 5 As shown, at least two first transistors T1 are arranged along a first direction X. Exemplarily, a plurality of first transistors T1 are arranged in an array along the first direction X and the second direction Y.

[0082] For example, see Figure 5 and Figure 6 , the first transistor T1 includes a semiconductor body 420 and a gate layer 431. The semiconductor body 420 extends along the third direction Z, and includes a first electrode 421, a channel 422, and a second electrode 423 of the first transistor T1. The first electrode 421 and the second electrode 423 are two opposite ends of the semiconductor body 420 in the third direction Z, and the channel 422 is located between the first electrode 421 and the second electrode 423. In addition, the gate layer 431 is disposed on the sidewall of the semiconductor body 420 to form the gate of the first transistor T1.

[0083] It should be noted that the material of the channel 422 includes a semiconductor material, and the materials of the first electrode 421 and the second electrode 423 may include a semiconductor material doped with a P-type dopant or an N-type dopant.

[0084] In addition, the orthographic projection of the channel 422 on the reference plane is located within the range of the orthographic projection of the gate layer 431 on the reference plane, so that the first pole 421 and the second pole 423 at both ends of the channel 422 can be turned on or off under the control of the voltage of the gate layer 431. The reference plane is perpendicular to the first direction X.

[0085] That is, when the voltage received by the gate layer 431 from the word line WL is greater than the threshold voltage of the first transistor T1, the first transistor T1 is turned on. When the voltage received by the gate layer 431 from the word line WL is less than or equal to the threshold voltage of the first transistor T1, the first transistor T1 is turned off.

[0086] like Figure 5 As shown, the isolation structure 410 extends along the second direction Y, and the isolation structure 410 is located between two adjacent first transistors T1 in the first direction X, so that the two adjacent first transistors T1 in the first direction X are insulated.

[0087] For example, see Figure 5 and Figure 6The isolation structure 410 includes a conductor layer 411, which can be connected to a second reference voltage to isolate the gate layer 431 of one of the two adjacent first transistors T1 located on opposite sides of the isolation structure 410 from interfering with the semiconductor body 420 (channel 422) of the other first transistor T1, thereby reducing the electromagnetic interference generated between the adjacent first transistors T1.

[0088] It should be noted that the second reference voltage may be, for example, a negative voltage, or other voltages. The material of the conductor layer 411 includes a conductive material; for example, the material of the conductor layer 411 includes titanium nitride.

[0089] It should be understood that see Figure 5 and Figure 6 The orthographic projection of the conductor layer 411 on the reference plane at least partially overlaps with the orthographic projection of the adjacent gate layer 431 on the reference plane, so as to reduce the interference generated by one of the two first transistors T1 located on opposite sides of the isolation structure 410 to the other.

[0090] In addition, when the orthographic projection of the conductor layer 411 on the reference plane covers the gate layer 431 , the conductor layer 411 may have an adverse effect on the conduction and cutoff of the channel 422 , thereby increasing the risk of leakage current of the first transistor T1 .

[0091] Based on this, Figure 5 and Figure 6 As shown, the orthographic projection of the conductor layer 411 on the reference plane is within the range of the orthographic projection of any adjacent gate layer 431 on the reference plane. That is, the two ends of the conductor layer 411 in the third direction Z are located between the two ends of any adjacent gate layer 431 in the third direction Z, so as to avoid the risk of the conductor layer 411 causing leakage current in the first transistor T1.

[0092] In addition, when the second reference voltage is fixed, the larger the overlap area between the orthographic projection of the conductor layer 411 on the reference plane and the orthographic projection of the adjacent gate layer 431 on the reference plane is, the better the shielding effect of the conductor layer 411 is. Therefore, it is very important to control the height of both ends of the conductor layer 411 in the third direction Z (the distance from the bonding surface S).

[0093] It should be understood that when the conductor layer 411 is directly etched to control the height of both ends of the conductor layer 411 in the third direction Z, the conductor layer 411 needs to undergo at least two etching processes. The first etching is performed from the side of the conductor layer 411 away from the bonding surface S, so that the end of the conductor layer 411 away from the bonding surface S is lower than the end of the gate layer 431 away from the bonding surface S. The second etching is performed from the side of the conductor layer 411 close to the bonding surface S, so that the end of the conductor layer 411 close to the bonding surface S is higher than the end of the gate layer 431 close to the bonding surface S.

[0094] However, there are other process steps between the first etching and the second etching, and the process conditions of at least one of the other process steps include high temperature, which can cause grain reorganization of the conductor layer 411, resulting in voids inside the conductor layer 411. Since voids are generated inside the conductor layer 411, in the second etching, when the conductor layer 411 is directly etched and the etching depth is controlled by controlling the etching time, the etching depth cannot be accurately controlled, resulting in the height of the end of the conductor layer 411 close to the bonding surface S being difficult to control.

[0095] Based on this, see Figure 5 and Figure 6 In the semiconductor structure 400 provided in the present disclosure, the isolation structure 410 also includes a twin inducing layer 412, which is located between the conductor layer 411 and the first transistor T1 and contacts the conductor layer 411 to induce the growth direction of the lattice of the conductor layer 411 so that the crystal of the conductor layer 411 forms a twin structure.

[0096] In this case, due to the low crystal energy and high stability of the twin structure, the risk of crystallization of the conductor layer 411 is reduced under high temperature process, which can reduce the voids generated inside the conductor layer 411 due to the recombination of the crystals. Therefore, in the second etching, when the etching depth is controlled by controlling the etching time, the accuracy of the etching depth can be improved, which is conducive to improving the uniformity of the height of the end of the conductor layer 411 close to the bonding surface S, and is conducive to improving the precise control of the height of the two ends of the conductor layer 411 in the third direction Z.

[0097] At this time, the precise control of the height of the two ends of the conductor layer 411 in the third direction Z can make the overlapping area between the conductor layer 411 and the adjacent gate layer 431 larger while avoiding the conductor layer 411 causing leakage current in the first transistor T1, thereby effectively isolating the interference between the two adjacent first transistors T1 located on the opposite sides of the isolation structure 410.

[0098] Figure 7 is a structural diagram of a face-centered cubic lattice according to some embodiments; Figure 8 is a structural diagram of a crystal having a crystal orientation of

[100] according to some embodiments; Fig. 9 is a structural diagram of a crystal having a crystal orientation of

[110] according to some embodiments; Fig.10 FIG. 4 is a structural diagram of a crystal having a crystal orientation of

[111] according to some embodiments.

[0099] It should be understood that the twin inducing layer 412 is in contact with the conductor layer 411 , and the conductor layer 411 may be formed along the grain growth of the twin inducing layer 412 . At this time, the crystal structure of the conductor layer 411 depends on the lattice type and crystal orientation of the twin inducing layer 412 .

[0100] For example, Figure 7 As shown, the lattice type of the twin inducing layer 412 is a face-centered cubic lattice. Fig.10 As shown, the crystal orientation of the twin inducing layer 412 is

[111] . In this case, the conductor layer 411 can grow along the grains of the twin inducing layer 412, thereby forming a conductor layer 411 with a crystal structure of a twin structure. The material of the twin inducing layer 412 can include aluminum oxide and / or hafnium oxide, for example.

[0101] In some embodiments, Figure 6 As shown, the isolation structure 410 further includes a first insulating layer 413, and the first insulating layer 413 is located on one side of the conductor layer 411 along the third direction Z. For example, along the third direction Z, the first insulating layer 413 is located on a side of the conductor layer 411 away from the bonding surface S.

[0102] It should be noted that the material of the first insulating layer 413 includes any one of silicon oxide, silicon nitride, silicon oxynitride and a high dielectric constant insulating material. For example, the material of the first insulating layer 413 includes silicon nitride.

[0103] The end of the first insulating layer 413 away from the conductive layer 411 is flush with the end of the semiconductor body 420, that is, the first insulating layer 413 fills the gap between the semiconductor body 420 on the upper side of the conductive layer 411 to play a flat and supporting role.

[0104] In some embodiments, Figure 6 As shown, the isolation structure 410 further includes a second insulating layer 414, and the second insulating layer 414 is located on the other side of the conductor layer 411 along the third direction Z. For example, along the third direction Z, the second insulating layer 414 is located on the side of the conductor layer 411 close to the bonding surface S. That is, the first insulating layer 413 and the second insulating layer 414 are located on opposite sides of the conductor layer 411.

[0105] The end of the second insulating layer 414 away from the conductive layer 411 is flush with the end of the semiconductor body 420, that is, the second insulating layer 414 fills the gap between the semiconductor body 420 under the conductive layer 411 to play a flat and supporting role.

[0106] It should be noted that the material of the second insulating layer 414 includes any one of silicon oxide, silicon nitride, silicon oxynitride and a high dielectric constant insulating material; for example, the material of the second insulating layer 414 includes silicon nitride.

[0107] In some embodiments, Figure 6 As shown, the twin inducing layer 412 includes a first portion 4121 and a second portion 4122 , wherein the first portion 4121 is located between the conductor layer 411 and the first transistor T1 , and the second portion 4122 is located between the first insulating layer 413 and the first transistor T1 , and between the second insulating layer 414 and the first transistor T1 .

[0108] It should be noted that the thickness of the second portion 4122 of the twin inducing layer 412 is smaller than the thickness of the first portion 4121 .

[0109] For example, Figure 6 As shown, the two ends of the twin inducing layer 412 in the third direction Z are flush with the two ends of the semiconductor body 420, so that a conductor film 411' with a twin structure can be formed in the gap between the semiconductor bodies 420 of two adjacent first transistors T1 (see Fig.18 ), so that after removing the first preset portion and the second preset portion mentioned below, a conductor layer 411 with a twin structure is formed.

[0110] In some embodiments, see Figure 5 , the plurality of first transistors T1 are divided into a plurality of transistor groups T10 , each first transistor group T10 includes two first transistors T1 arranged in the first direction X, and at least two first transistor groups T10 are arranged along the first direction X.

[0111] On this basis, if Figure 5 As shown, the isolation structure 410 can be located between two adjacent first transistor groups T10. The first transistor group T10 includes a gate structure 430 and a semiconductor body 420. The gate structure 430 extends along the second direction Y, and along the first direction X, the semiconductor body 420 is disposed on opposite sides of the gate structure 430.

[0112] That is, the isolation structures 410 and the gate structures 430 are arranged alternately in the first direction X. In this way, Figure 5 and Figure 6 The gate layer 431 and the gate dielectric layer 432 of the two first transistors T1 in the first transistor group T10 are located between two adjacent semiconductor bodies 420. The distance between the two semiconductor bodies 420 is large, which facilitates the preparation of the gate layer 431 and the gate dielectric layer 432. The process difficulty is low, which is conducive to reducing production costs.

[0113] In some embodiments, Figure 6As shown, the semiconductor structure 400 further includes an isolation layer 440, which is located between the gate structure 430 and the semiconductor body 420, and between the isolation structure 410 and the semiconductor body 420, to provide insulation protection and prevent the sidewalls of the semiconductor body 420 from being damaged by etching.

[0114] It should be noted that the material of the isolation layer 440 includes any one of silicon oxide, silicon nitride, silicon oxynitride and a high dielectric constant insulating material. For example, the material of the isolation layer 440 includes silicon oxide. Moreover, the isolation layer 440 may be a single-layer structure or a multi-layer structure, which is not specifically limited in the embodiments of the present disclosure.

[0115] In some embodiments, Figure 6 As shown, the gate structure 430 includes a gate layer 431 and a gate dielectric layer 432. The gate layer 431 is disposed on a side of the gate dielectric layer 432 away from the semiconductor body 420 to form a gate of the first transistor T1. The gate dielectric layer 432 is disposed on the sidewall of the semiconductor body 420 to insulate the gate layer 431 from the corresponding semiconductor body 420.

[0116] In some embodiments, Figure 6 As shown, the gate structure 430 further includes an insulating structure 433, which at least covers two ends of the gate layer 431 in the third direction Z to play a supporting role, thereby reducing the risk of collapse of the semiconductor structure 400. At the same time, the insulating structure 433 can also play an insulating role to prevent the gate layer 431 from being short-circuited with other conductive structures (such as the first pole 421 of the semiconductor body 420).

[0117] For example, see Figure 6 , the insulating structure 433 includes a first insulating portion 4330 and a second insulating portion 4340 .

[0118] like Figure 6 As shown, the first insulating portion 4330 includes a third portion 4331 and a fourth portion 4332. Along the first direction X, the third portion 4331 is located between the gate layers 431 in the same gate structure 430 to reduce the risk of short circuit between the gate layers 431 in the same gate structure 430 and provide support. Along the third direction Z, the fourth portion 4332 covers the gate layer 431 and one end of the third portion 4331, and is located between the gate dielectric layers 432 in the same gate structure 430 to play a flat and support role.

[0119] like Figure 6As shown, the second insulating portion 4340 is disposed between two adjacent semiconductor bodies 420. Along the third direction Z, the second insulating portion 4340 covers the gate layer 431, the gate dielectric layer 432 and the other end of the third portion 4331 away from the fourth portion 4332 to prevent the gate layer 431 from shorting with the first electrode 421 of the semiconductor body 420 and provide support.

[0120] In some embodiments, see Figure 6 , the second insulating part 4340 includes a third insulating layer 4341 and a fourth insulating layer 4342 .

[0121] like Figure 6 As shown, the third insulating layer 4341 is located between the fourth insulating layer 4342 and the semiconductor body 420 on both sides, and on the side of the fourth insulating layer 4342 away from the first insulating portion 4330. The portion of the third insulating layer 4341 located on the side of the fourth insulating layer 4342 away from the first insulating portion 4330 may be flush with the end of the semiconductor body 420.

[0122] The embodiment of the present disclosure provides a method for preparing a semiconductor structure 400, such as Fig.11 As shown, the preparation method includes steps S100 to S200.

[0123] S100: See Fig.18 and Fig. 20 , forming an intermediate semiconductor structure 400'.

[0124] In the above steps, the intermediate semiconductor structure 400' includes a substrate 500 and a plurality of first trenches 510. Along the third direction Z, the substrate 500 has a first surface 500A and a second surface 500B opposite to each other, and the first trenches 510 are disposed on the first surface 500A of the substrate 500. Fig. 20 , the first trench 510 extends along the second direction Y, and a plurality of first trenches 510 are arranged in the first direction X.

[0125] In some embodiments, see Fig.12 , S100 includes S110~S150.

[0126] S110: See Fig. 20 , a protection layer 610 is formed on the first surface 500A of the substrate 500 .

[0127] In the above steps, the protective layer 610 covers the first surface 500A of the substrate 500 to protect the substrate and prevent subsequent etching and stripping processes from damaging the first surface 500A of the substrate 500. The protective layer 610 can be formed by a thin film deposition process or a coating process.

[0128] It should be noted that the thin film deposition process includes any one of chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD), physical vapor deposition (Physical Vapor Deposition, referred to as PVD), and atomic layer deposition (Atomic Layer Deposition, referred to as ALD).

[0129] S120: See Fig. 20 , a first trench 510 and a second trench 520 are formed on the first surface 500A of the substrate 500 .

[0130] In the above steps, the first trench 510 and the second trench 520 extend along the second direction Y and are alternately arranged in the first direction X. Moreover, the first trench 510 and the second trench 520 extend from the first surface 500A of the substrate 500 to the inside of the substrate 500, and do not penetrate the substrate 500. The first trench 510 and the second trench 520 can be formed by a dry or wet etching process.

[0131] For example, Fig. 20 As shown, the substrate 500 includes a first substrate 511, and a second substrate 512 and a semiconductor layer 513 are sequentially formed on the first substrate 511. On this basis, the first trench 510 and the second trench 520 can penetrate the semiconductor layer 513 and stop at the second substrate 512.

[0132] In one feasible implementation, in the process of S120, refer to Fig.19 , a third trench 530 extending along the first direction X may also be formed, the third trench 530 intersecting the first trench 510 and the second trench 520, so that the semiconductor layer 513 is patterned into a plurality of semiconductor bodies 420 arranged in an array. In another feasible embodiment, the third trench 530 extending along the first direction X may be formed by a single etching process.

[0133] It should be noted that an insulating material is filled between two semiconductor bodies 420 adjacent to each other along the second direction Y, so that the two semiconductor bodies 420 adjacent to each other in the second direction Y are insulated.

[0134] S130: See Fig. 20 , an isolation layer 440 is formed on the substrate 500 .

[0135] In the above steps, the isolation layer 440 covers the first surface 500A of the substrate 500, and the bottom wall and the side wall of the first trench 510 and the second trench 520. The isolation layer 440 can be formed by a thin film deposition process, for example.

[0136] S140: See Fig. 20, a sacrificial layer 620 is formed in the first trench 510 and the second trench 520 .

[0137] In the above steps, the sacrificial layer 620 can, for example, first use a thin film deposition process to deposit sacrificial material on the entire surface so that the sacrificial material fills the first groove 510 and the second groove 520; then, a dry or wet etching process is used to remove the parts outside the first groove 510 and the second groove 520.

[0138] S150: See Fig. 20 , the sacrificial layer 620 located in the first trench 510 is removed.

[0139] In the above steps, a mask plate may be used to cover the sacrificial layer 620 in the second trench 520 , and then a dry or wet etching process may be used to remove the sacrificial layer 620 in the first trench 510 , and finally the mask plate may be peeled off.

[0140] It should be noted that the mask plate can be formed by, for example, sequentially adopting a coating process, an exposure process and a development process.

[0141] S200: See Fig.18 , an isolation structure 410 is formed in the first trench 510 .

[0142] In the above steps, the isolation structure 410 includes a conductor layer 411 and a twin inducing layer 412 . The twin inducing layer 412 is located between the conductor layer 411 and the sidewall of the first trench 510 , and is in contact with the conductor layer 411 .

[0143] For example, see Figure 7 , Fig.10 and Fig.18 The lattice type of the twin inducing layer 412 is a face-centered cubic lattice, and the crystal direction is

[111] . For example, the material of the twin inducing layer 412 includes aluminum oxide and / or hafnium oxide.

[0144] For example, see Fig.18 The crystal structure of the conductor layer 411 is a twin structure. For example, the material of the conductor layer 411 may include titanium nitride.

[0145] In some embodiments, see Fig.13 , S200 includes S210~S240.

[0146] S210: See Fig.18 , an initial isolation structure 410 ′ is formed in the first trench 510 .

[0147] In the above steps, the initial isolation structure 410' includes a twin inducing film 412' and a conductor film 411'. The twin inducing film 412' at least covers the sidewalls and the bottom wall of the first trench 510. The conductor film 411' is located on the side of the twin inducing film 412' away from the substrate 500 and contacts the twin inducing film 412'.

[0148] In some embodiments, see Fig.14 , S210 includes S211~S214.

[0149] S211: See Fig.18 , forming a twin-inducing film 412'.

[0150] In the above steps, the twin inducing film 412' covers the first surface 500A of the substrate 500 and the sidewalls and bottom wall of the first trench 510. The twin inducing film 412' can be formed by a thin film deposition process.

[0151] S212: See Fig.18 , a conductor film 411 ′ is formed on the twin inducing film 412 ′.

[0152] In the above steps, the conductor film 411' covers the twin inducing film 412' and fills the first trench 510. The conductor film 411' can be grown on the twin inducing film 412' by a deposition process, for example.

[0153] S213: See Fig.18 , the conductive film 411 ′ covering the first surface 500A of the substrate 500 and the conductive film 411 ′ located in the second predetermined portion of the first trench 510 are removed.

[0154] In the above steps, the second preset portion is the portion of the conductor film 411' that needs to be removed, which can be specifically determined according to the required height of the end of the conductor layer 411 formed in the subsequent process away from the second surface 500B of the substrate 500, so that the height of the end of the conductor layer 411 away from the second surface 500B is lower than the height of the end of the gate layer 431 formed subsequently away from the second surface 500B.

[0155] The second predetermined portion of the conductor film 411 ′ may be removed by, for example, adopting a dry or wet etching process and controlling the etching time.

[0156] S214: See Fig.18 , a portion of the twin inducing thin film 412 ′ covering the first surface 500A of the substrate 500 , a portion of the isolation layer 440 covering the first surface 500A of the substrate 500 , and the protective layer 610 are removed.

[0157] In the above steps, the portion of the twin inducing film 412 ′ covering the first surface 500A of the substrate 500 , the portion of the isolation layer 440 covering the first surface 500A of the substrate 500 , and the protective layer 610 may be removed by, for example, a dry etching process, a wet etching process, or a planarization process.

[0158] For example, the portion of the twin inducing film 412 ′ covering the first surface 500A of the substrate 500 , the portion of the isolation layer 440 covering the first surface 500A of the substrate 500 , and the protection layer 610 may be removed by chemical mechanical polishing.

[0159] In some embodiments, see Fig.18 In S213, the second predetermined portion of the conductor film 411' located in the first groove 510 is removed to form the first sub-groove 501. Fig.15 Before S214, the above S210 may further include S215.

[0160] S215: See Fig.18 , a first insulating film 413 ′ is formed in the first sub-groove 501 .

[0161] In the above steps, the first insulating film 413' covers the first surface 500A of the substrate 500 and fills the first sub-groove 501. The first insulating film 413' can be formed by, for example, a thin film deposition process.

[0162] At this time, in the process of S213, the portion of the first insulating film 413' covering the first surface 500A of the substrate 500 is also removed. Fig.15 S214 specifically includes: removing the portion of the first insulating film 413 ′ covering the first surface 500A of the substrate 500 , the portion of the twin inducing film 412 ′ covering the first surface 500A of the substrate 500 , the portion of the isolation layer 440 covering the first surface 500A of the substrate 500 , and the protective layer 610 .

[0163] Here, the first insulating film 413', the twin inducing film 412' and the isolation layer 440 covering the first surface 500A of the substrate 500 and the protective layer 610 can be removed by any one of a dry etching process, a wet etching process or a planarization process. For example, the first insulating film 413', the twin inducing film 412' and the isolation layer 440 covering the first surface 500A of the substrate 500 and the protective layer 610 can be removed by chemical mechanical polishing.

[0164] S220: See Fig.18 , a portion of the substrate 500 located at the twin inducing film 412 ′ away from the first surface 500A is removed, so that the twin inducing film 412 ′ is exposed.

[0165] In the above steps, the portion of the substrate 500 located at the twin inducing film 412 ′ away from the first surface 500A may be removed by, for example, using any one of a dry etching process, a wet etching process and a planarization process.

[0166] For example, Fig. 20 and Fig.21 As shown, the substrate 500 includes a first substrate 511, and a second substrate 512 and a semiconductor layer 513 are sequentially formed on the first substrate 511, and the first trench 510 can penetrate the semiconductor layer 513 and stop at the second substrate 512. On this basis, the substrate 500 is located at a portion of the twin inducing film 412' away from the first surface 500A, namely the first substrate 511 and the second substrate 512.

[0167] At this time, the portion of the substrate 500 located at the twin inducing film 412 ′ away from the first surface 500A, that is, the first base 511 and the second base 512 can be removed by chemical mechanical polishing.

[0168] S230: See Fig.18 , removing the exposed portion of the twin inducing film 412 ′, so that the conductor film 411 ′ is exposed.

[0169] In the above steps, the exposed portion of the twin inducing film 412' can be removed by a dry or wet etching process. Here, the conductor film 411' can serve as a stop layer for the etching process.

[0170] S240: See Fig.18 , remove the first preset portion of the conductor film 411'.

[0171] In the above steps, the first preset portion is the portion of the conductor film 411' that needs to be removed, which can be determined based on the required height of the end of the conductor layer 411 formed in the subsequent process close to the second surface 500B of the substrate 500, so that the height of the end of the conductor layer 411 close to the second surface 500B is higher than the height of the end of the gate layer 431 formed subsequently close to the second surface 500B.

[0172] The first predetermined portion of the conductor film 411 ′ may be removed by, for example, adopting a dry or wet etching process and controlling the etching time.

[0173] In some embodiments, see Fig.18 In S240, the first predetermined portion of the conductor film 411' is removed to form a second sub-groove 502. On this basis, refer to Fig.16 , after S240, the above S200 may further include S250.

[0174] S250: See Fig.18 , a second insulating layer 414 is formed in the second sub-groove 502 .

[0175] In the above steps, the second sub-groove 502 is a gap formed after removing the first preset portion of the conductor film 411 ′. The second insulating layer 414 can be formed by first depositing insulating material using a thin film deposition process, and then removing the portion covering the semiconductor layer 513 using a dry or wet etching process.

[0176] In some embodiments, see Fig.17 Before S220, the preparation method further includes S300 to S400.

[0177] S300: See Fig.21 , the sacrificial layer 620 located in the second trench 520 is removed.

[0178] In the above steps, the sacrificial layer 620 located in the second trench 520 can be removed by using a dry or wet etching process.

[0179] S400: See Fig.21 , a gate structure 430 is formed in the second trench 520 .

[0180] In the above steps, combined with Figure 6 The gate structure 430 may include, for example, a gate layer 431 , a gate dielectric layer 432 , and an insulating structure 433 . The insulating structure 433 may include, for example, a first insulating portion 4330 and a second insulating portion 4340 .

[0181] Fig. 22 is a block diagram of a storage system according to some embodiments. Fig.23 is a block diagram of a storage system according to some other embodiments.

[0182] See also Fig. 22 and Fig.23 Some embodiments of the present disclosure further provide a storage system 1000. The storage system 1000 includes a controller 20 and a memory 10 according to some embodiments above. The controller 20 is coupled to the memory 10 to control the memory 10 to store data.

[0183] The storage system 1000 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0184] In some embodiments, see Fig. 22 , the storage system 1000 includes a controller 20 and a memory 10, and the storage system 1000 can be integrated into a memory card.

[0185] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0186] In other embodiments, see Fig.23 The storage system 1000 includes a controller 20 and a plurality of memories 10, and the storage system 1000 is integrated into a solid state drive (SSD).

[0187] In the storage system 1000, in some embodiments, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0188] In other embodiments, the controller 20 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

[0189] In some embodiments, the controller 20 may be configured to manage data stored in the memory 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 may also be configured to control operations of the memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 may also be configured to manage various functions regarding data stored or to be stored in the memory 10, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 20 is also configured to process error correction codes regarding data read from or written to the memory 10.

[0190] Of course, the controller 20 may also perform any other suitable functions, such as formatting the memory 10; for example, the controller 20 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0191] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0192] Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0193] The electronic device may include the storage system 1000 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0194] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: A plurality of first transistors, at least two of which are arranged along a first direction; an isolation structure, located between two first transistors adjacent to each other in the first direction; The isolation structure includes a twin inducing layer and a conductor layer, wherein the twin inducing layer is located between the conductor layer and the first transistor and contacts the conductor layer.

2. The semiconductor structure according to claim 1, characterized in that: The lattice type of the twin inducing layer is face-centered cubic lattice, and the crystal direction is [111].

3. The semiconductor structure according to claim 2, characterized in that: The material of the twin inducing layer includes aluminum oxide and / or hafnium oxide.

4. The semiconductor structure according to claim 1, characterized in that The crystal structure of the conductor layer is a twin structure.

5. The semiconductor structure according to claim 1, characterized in that: The material of the conductor layer includes titanium nitride.

6. The semiconductor structure according to claim 1, characterized in that The isolation structure also includes: A first insulating layer, along a third direction, the first insulating layer is located on one side of the conductive layer; the third direction is perpendicular to the first direction; The second insulating layer is located on the other side of the conductive layer along the third direction.

7. The semiconductor structure according to claim 6, characterized in that: The twin inducing layer comprises: A first portion, located between the conductor layer and the first transistor; The second portion is located between the first insulating layer and the first transistor, and between the second insulating layer and the first transistor.

8. The semiconductor structure according to claim 7, characterized in that: The thickness of the second portion is smaller than the thickness of the first portion.

9. The semiconductor structure according to any one of claims 1 to 8, characterized in that: The plurality of first transistors are divided into a plurality of first transistor groups, each of the first transistor groups includes two first transistors arranged in the first direction, and at least two first transistor groups are arranged along the first direction; The isolation structure is located between two adjacent first transistor groups; the first transistor group includes a gate structure and a semiconductor body, and along the first direction, the semiconductor body is arranged on two opposite sides of the gate structure.

10. The semiconductor structure according to claim 9, characterized in that: Also includes: An isolation layer is located between the gate structure and the semiconductor body, and between the isolation structure and the semiconductor body.

11. The semiconductor structure according to claim 9, characterized in that: The gate structure comprises: A gate dielectric layer is disposed on the sidewall of the semiconductor body; A gate layer, disposed on a side of the gate dielectric layer away from the semiconductor body; The insulating structure at least covers two ends of the gate layer in a third direction; the third direction is perpendicular to the first direction.

12. The semiconductor structure according to claim 11, characterized in that: Two ends of the conductor layer in the third direction are located between two ends of any adjacent gate layer in the third direction.

13. A method for preparing a semiconductor structure, characterized in that: include: forming an intermediate semiconductor structure; The intermediate semiconductor structure comprises a substrate and a plurality of first trenches. Along a third direction, the substrate has a first surface and a second surface that are oppositely disposed. The first trenches are disposed on the first surface of the substrate and extend along the second direction. The plurality of first grooves are arranged in a first direction; the second direction intersects with the first direction and are both perpendicular to the third direction; An isolation structure is formed in the first trench; the isolation structure includes a twin inducing layer and a conductor layer, the twin inducing layer is located between the conductor layer and the sidewall of the first trench and is in contact with the conductor layer.

14. The preparation method according to claim 13, characterized in that: The forming of the intermediate semiconductor structure comprises: forming a protective layer on the first surface of the substrate; Forming a first groove and a second groove on the first surface of the substrate; the first groove and the second groove extend along the second direction and are alternately arranged in the first direction; forming an isolation layer on the substrate; the isolation layer covers the first surface of the substrate, and the bottom wall and side wall of the first trench and the second trench; forming a sacrificial layer in the first trench and the second trench; The sacrificial layer in the first trench is removed.

15. The preparation method according to claim 14, characterized in that: The forming of an isolation structure in the first trench comprises: forming an initial isolation structure in the first trench; the initial isolation structure comprises a twin-inducing film and a conductor film, the twin-inducing film at least covers the sidewall and the bottom wall of the first trench, and the conductor film is located on a side of the twin-inducing film away from the substrate and in contact with the twin-inducing film; removing a portion of the substrate located away from the first surface and away from the twin-inducing film, so that the twin-inducing film is exposed; removing the exposed portion of the twin inducing film so that the conductor film is exposed; A first predetermined portion of the conductor film is removed.

16. The preparation method according to claim 15, characterized in that: The forming of an initial isolation structure in the first trench comprises: forming a twinning inducing film; the twinning inducing film covers the first surface of the substrate and the sidewalls and bottom walls of the first trench; forming a conductor film on the twin-inducing film; the conductor film covers the twin-inducing film and fills the first trench; removing the conductive film covering the first surface of the substrate and the conductive film located in the second preset portion of the first groove; The portion of the twinning inducing thin film covering the first surface of the substrate, the portion of the isolation layer covering the first surface of the substrate, and the protective layer are removed.

17. The preparation method according to claim 16, characterized in that: removing a second preset portion of the conductor film located in the first trench to form a first sub-trench; before removing the portion of the twin inducing film covering the first surface of the substrate, the portion of the isolation layer covering the first surface of the substrate, and the protective layer, forming an initial isolation structure in the first trench, further comprising: forming a first insulating film in the first sub-groove; the first insulating film covers the first surface of the substrate and fills the first sub-groove; In the process of removing the portion of the twin inducing film covering the first surface of the substrate, the portion of the isolation layer covering the first surface of the substrate, and the protective layer, the portion of the first insulating film covering the first surface of the substrate is also removed.

18. The preparation method according to any one of claims 14 to 17, characterized in that: The lattice type of the twin inducing layer is face-centered cubic lattice, and the crystal direction is [111].

19. The preparation method according to claim 18, characterized in that: The material of the twin inducing layer includes aluminum oxide and / or hafnium oxide.

20. The preparation method according to any one of claims 14 to 17, characterized in that: The crystal structure of the conductor layer is a twin structure.

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