Semiconductor structure and method of manufacturing the same

Abstract

The disclosure provides a semiconductor structure and a preparation method thereof, and relates to the technical field of semiconductor chips, and aims to solve the problem of how to reduce electromagnetic interference generated between transistors. The semiconductor structure comprises a plurality of first transistors and an isolation structure. At least two first transistors are arranged along a first direction. The isolation structure is located between two first transistors adjacent in the first direction. The isolation structure comprises a twin-induced layer and a conductor layer, the twin-induced layer is located between the conductor layer and the first transistor, and is in contact with the conductor layer. The above semiconductor structure is used to realize the read and write operations of data.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor chip, and particularly relates to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] A dynamic random access memory (DRAM) is composed of a plurality of memory cells, each of which is composed of a capacitor controlled by a transistor, that is, the DRAM is a memory cell of 1 transistor and 1 capacitor (1T1C).

[0003] With the improvement of the integration of the memory array, the distance between the transistors is closer and closer, and how to reduce the electromagnetic interference generated between the transistors is a problem to be solved at present. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor structure, a preparation method thereof and a storage system, and aim to solve the problem of how to reduce the electromagnetic interference generated between the transistors.

[0005] To achieve the above-mentioned purpose, embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, a semiconductor structure is provided. The semiconductor structure includes a plurality of first transistors and an isolation structure. At least two first transistors are arranged along a first direction. The isolation structure is located between two first transistors adjacent in the first direction. The isolation structure includes a twin-induced layer and a conductor layer, the twin-induced layer is located between the conductor layer and the first transistor, and is in contact with the conductor layer.

[0007] The semiconductor structure provided by the present disclosure has low crystal energy and high stability due to the twin structure, and the risk of grain crystallization of the conductor layer is reduced under high-temperature process, which can reduce the voids generated inside due to the grain recombination of the conductor layer. In this way, when the etching depth is controlled by controlling the etching time, the accuracy of the etching depth can be improved, which is beneficial to improve the uniformity of the height of the end of the conductor layer close to the bonding surface, and is beneficial to improve the accurate control of the height of the two ends of the conductor layer in the third direction.

[0008] At this time, the accurate control of the height of the two ends of the conductor layer in the third direction can effectively block the interference between the two first transistors located on the opposite sides of the isolation structure and adjacent to each other on the basis of avoiding the conductor layer from causing the first transistor to generate a leakage current.

[0009] In some embodiments, the lattice type of the twin-induced layer is a face-centered cubic lattice, and the crystal direction is

[111] .

[0010] In some embodiments, the material of the twin inducing layer comprises aluminum oxide and / or hafnium oxide.

[0011] In some embodiments, the crystal structure of the conductor layer is a twin structure.

[0012] In some embodiments, the material of the conductor layer comprises titanium nitride.

[0013] In some embodiments, the isolation structure further comprises a first insulating layer and a second insulating layer. The first insulating layer is located on one side of the conductor layer along a third direction. The third direction is perpendicular to the first direction. The first insulating layer is located on the other side of the conductor layer along the third direction.

[0014] In some embodiments, the twin inducing layer comprises a first portion and a second portion. The first portion is located between the conductor layer and the first transistor. The second portion is located between the first insulating layer and the first transistor, and between the second insulating layer and the first transistor.

[0015] In some embodiments, the thickness of the second portion is less than the thickness of the first portion.

[0016] In some embodiments, the plurality of first transistors are divided into a plurality of first transistor groups. Each of the first transistor groups comprises two first transistors arranged along the first direction. At least two first transistor groups are arranged along the first direction. The isolation structure is located between two adjacent first transistor groups. The first transistor group comprises a gate structure and a semiconductor body. The semiconductor body is arranged on opposite sides of the gate structure along the first direction.

[0017] In some embodiments, the semiconductor structure further comprises an isolation layer. The at least one isolation layer is located between the gate structure and the semiconductor body, and between the isolation structure and the semiconductor body.

[0018] In some embodiments, the gate structure comprises a gate dielectric layer, a gate layer, and an insulating structure. The gate dielectric layer is arranged on the sidewall of the semiconductor body. The gate layer is arranged on the side of the gate dielectric layer away from the semiconductor body. The insulating structure covers at least two ends of the gate layer along a third direction. The third direction is perpendicular to the first direction.

[0019] In some embodiments, the two ends of the conductor layer along the third direction are located between the two ends of any adjacent gate layer along the third direction.

[0020] In another aspect, a method for fabricating a semiconductor structure is provided. The method includes forming an intermediate semiconductor structure. The intermediate semiconductor structure includes a substrate and a plurality of first trenches. The substrate has a first surface and a second surface disposed opposite to each other. The first trenches are disposed on the first surface of the substrate and extend along a second direction. The plurality of first trenches are arranged in a first direction. The second direction and the first direction are perpendicular to a third direction. An isolation structure is formed in the first trenches. The isolation structure includes a twin-induced layer and a conductor layer. The twin-induced layer is between the conductor layer and sidewalls of the first trenches and in contact with the conductor layer.

[0021] In some embodiments, the forming the intermediate semiconductor structure includes forming a protection layer on the first surface of the substrate. The first trenches and the second trenches are formed on the first surface of the substrate. The first trenches and the second trenches extend along the second direction and are arranged in the first direction alternately. An isolation layer is formed on the substrate. The isolation layer covers the first surface of the substrate and bottom walls and sidewalls of the first trenches and the second trenches. A sacrificial layer is formed in the first trenches and the second trenches. The sacrificial layer in the first trenches is removed.

[0022] In some embodiments, the forming the isolation structure in the first trenches includes forming an initial isolation structure in the first trenches. The initial isolation structure includes a twin-induced film and a conductor film. The twin-induced film covers at least the sidewalls and the bottom walls of the first trenches. The conductor film is on a side of the twin-induced film away from the substrate and in contact with the twin-induced film. A portion of the substrate on the side of the twin-induced film away from the first surface is removed so that the twin-induced film is exposed. A portion of the twin-induced film exposed is removed so that the conductor film is exposed. A first predetermined portion of the conductor film is removed.

[0023] In some embodiments, the forming the initial isolation structure in the first trenches includes forming a twin-induced film. The twin-induced film covers the first surface of the substrate and the sidewalls and the bottom walls of the first trenches. A conductor film is formed on the twin-induced film. The conductor film covers the twin-induced film and fills the first trenches. The conductor film covering the first surface of the substrate and a second predetermined portion of the conductor film in the first trenches are removed. A portion of the twin-induced film covering the first surface of the substrate, a portion of the isolation layer covering the first surface of the substrate, and the protection layer are removed.

[0024] In some embodiments, the removing the conductor thin film from the second preset portion of the first trench forms a first sub-trench. Before the removing the portion of the twin-induced thin film covering the first surface of the substrate, the portion of the isolation layer covering the first surface of the substrate, and the protection layer, the forming the initial isolation structure in the first trench further comprises: forming a first insulating thin film in the first sub-trench. The first insulating thin film covers the first surface of the substrate and fills the first sub-trench. In the process of removing the portion of the twin-induced thin film covering the first surface of the substrate, the portion of the isolation layer covering the first surface of the substrate, and the protection layer, the portion of the first insulating thin film covering the first surface of the substrate is also removed.

[0025] In some embodiments, the lattice type of the twin-induced layer is face-centered cubic lattice, and the crystal direction is

[111] .

[0026] In some embodiments, the material of the twin-induced layer comprises aluminum oxide and / or hafnium oxide.

[0027] In some embodiments, the crystal structure of the conductor layer is twin structure.

[0028] It can be understood that the semiconductor structure preparation method provided by the above-mentioned embodiments of the present disclosure can achieve the beneficial effects of the semiconductor structure, which will not be described here again. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description are only some drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual time sequence, etc. of the products involved in the embodiments of the present disclosure.

[0030] Figure 1 is a perspective view of a memory according to some embodiments;

[0031] Figure 2 is a sectional view of a memory according to some embodiments;

[0032] Figure 3 is Figure 1 is a structural diagram of a memory cell;

[0033] Figure 4 is Figure 3 is an equivalent circuit diagram of the memory cell shown in FIG. 8;

[0034] Figure 5This is a top view of a semiconductor structure according to some embodiments;

[0035] Figure 6 for Figure 5 A sectional view along section line AA;

[0036] Figure 7 This is a structural diagram of a face-centered cubic lattice according to some embodiments;

[0037] Figure 8 This is a structural diagram of a crystal with a crystal orientation of

[100] according to some embodiments;

[0038] Figure 9 This is a structural diagram of a crystal with a crystal orientation of

[110] according to some embodiments;

[0039] Figure 10 This is a structural diagram of a crystal with a crystal orientation of

[111] according to some embodiments;

[0040] Figures 11-17 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0041] Figure 18 This is a process step diagram of a method for fabricating a semiconductor structure according to some embodiments;

[0042] Figure 19 A top view of a substrate according to some embodiments;

[0043] Figure 20 and Figure 21 This is a process step diagram of a method for fabricating a semiconductor structure according to some embodiments;

[0044] Figure 22 This is a block diagram of a storage system according to some embodiments;

[0045] Figure 23 This is a block diagram of a storage system according to some other embodiments. Detailed Implementation

[0046] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0047] In the description of the disclosure, it needs to be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the disclosure.

[0048] Unless the context clearly requires otherwise, throughout the description and the claims, the term "comprise" is to be construed as an open, inclusive meaning, i.e. as "comprising, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "exemplarily" or "some examples" and the like are intended to mean that a particular feature, structure, material or characteristic included in at least one embodiment or example of the disclosure. The illustrative representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0049] Hereinafter, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the embodiments of the disclosure, unless otherwise stated, the meaning of "multiple" is two or more.

[0050] In describing some embodiments, "coupled" and "connected" and their derivatives can be used. For example, the term "connected" can be used to describe some embodiments to indicate that two or more components have direct physical or electrical contact with each other. For another example, the term "coupled" can be used to describe some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" can also mean that two or more components have no direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited by the content herein.

[0051] "A, B and C at least one of them" has the same meaning as "at least one of A, B or C", which includes the following combinations of A, B and C: only A, only B, only C, combination of A and B, combination of A and C, combination of B and C, and combination of A, B and C.

[0052] "A and / or B" includes the following three combinations: only A, only B, and combination of A and B.

[0053] The use of "adapted to" or "configured to" herein is meant as open and inclusive language that does not foreclose devices adapted to or configured to perform additional tasks or steps. Conjunctive language such as the

[0054] Additionally, the use of "based on" is meant to mean "based, at least in part, on" which is open and inclusive language that does not foreclose additional based on items.

[0055] In the subject disclosure, the meaning of "on," "over," and "above" should be interpreted in the broadest sense, such that "on" means not only "directly on," but also "on" with intervening features or layers therebetween, and "over" or "above" means not only "over" or "above" with no intervening features or layers therebetween, but also "over" or "above" with intervening features or layers therebetween (i.e., directly on).

[0056] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. In this regard, the thicknesses of layers and regions are exaggerated in the drawings for clarity. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Therefore, exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

[0057] As used herein, the term "substrate" refers to a material on which subsequent layers of material can be added. The substrate itself can be patterned. The material added on the substrate can be patterned or can remain unpatterned. Further, the substrate can include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0058] Figure 1 A perspective view of a memory according to some embodiments, Figure 2 A cross-sectional view of a memory according to some embodiments, Figure 3 A perspective view of a memory according to some embodiments, Figure 1 A perspective view of a memory according to some embodiments, Figure 4 A perspective view of a memory according to some embodiments, Figure 3 An equivalent circuit diagram of the memory cell shown.

[0059] It is noted that in the following description, the term "memory" is used to refer to a memory device, such as a DRAM, SRAM, or other memory device. Figure 1 A perspective view of a memory according to some embodiments, Figure 2In some embodiments, the memory 10 extends in an X-Y plane, and the first direction X and the second direction Y are, for example, two orthogonal directions in the plane in which the memory 10 lies (e.g., the plane in which the common layer GD lies): the first direction X is, for example, the direction of extension of the bit lines BL, and the second direction Y is, for example, the direction of extension of the word lines WL. The third direction Z is perpendicular to the plane in which the memory 10 lies, i.e., perpendicular to the X-Y plane.

[0060] Referring to Figure 1 and Figure 2 Some embodiments of the present disclosure provide a memory 10 including a semiconductor device 100 and a peripheral device 200. The peripheral device 200 can be disposed on one side of the semiconductor device 100.

[0061] As shown in Figure 2 , the semiconductor device 100 can include a memory cell array 110 and a common layer GD. The peripheral device 200 can be disposed, for example, on a side of the memory cell array 110 that is away from the common layer GD.

[0062] Referring to Figure 2 and Figure 3 The common layer GD can be connected to a first reference voltage, which can be a ground voltage or another voltage. The material of the common layer GD can be, for example, a conductive material, such as one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or another suitable material.

[0063] Referring to Figure 1 and Figure 2 The memory cell array 110 includes a plurality of memory cells 111 arranged in an array along a first direction X and a second direction Y.

[0064] As shown in Figure 3 and Figure 4 , the memory cell 111 includes a first transistor T1 and a capacitor C. The first electrode of the first transistor T1 is connected to a bit line BL, the second electrode of the first transistor T1 is connected to one plate of the capacitor C, and the other plate of the capacitor C can be connected to the common layer GD. The gate of the first transistor T1 is connected to a word line WL. In this way, the first transistor T1 can be controlled to be turned on or turned off by applying a voltage to the word line WL, and the bit line BL can perform a read or write operation on the first transistor T1 when the first transistor T1 is turned on.

[0065] In some embodiments, referring to Figure 1 and Figure 2 The semiconductor device 100 can further include an array interconnection layer 120.

[0066] The array interconnection layer 120 can be coupled with the memory cells 111 to enable transmission of electrical signals between the memory cells 111 and external circuits (e.g., the peripheral circuitry described below).

[0067] As shown in Figure 2 , the array interconnection layer 120 can include one or more first interconnection conductor layers 121, one or more first interlayer insulating layers 122, and a plurality of first contacts 123 insulated from each other by the first interlayer insulating layers 122. The different first interconnection conductor layers 121 can be coupled with each other through the first contacts 123.

[0068] The first interconnection conductor layers 121 and the first contacts 123 can be made of conductive materials, such as one or more of tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials.

[0069] The first interlayer insulating layers 122 can be made of insulating materials, such as one or more of silicon oxide, silicon nitride, and high-k insulating materials, or other suitable materials.

[0070] As shown in Figure 2 , the peripheral device 200 can include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry to support operation of the array device, including but not limited to page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components (e.g., transistors, diodes, resistors, or capacitors) of the circuitry. The peripheral circuitry can also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random-access memory (SRAM)).

[0071] In some embodiments, as shown in Figure 2 , the peripheral device 200 can include a substrate 210, a second transistor T2 disposed on the substrate 210, and a peripheral interconnection layer 220 disposed on the substrate 210. The peripheral circuitry can include the second transistor T2.

[0072] The substrate 210 can be made of single-crystal silicon or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator films. The peripheral interconnection layer 220 is coupled with the second transistor T2 to enable transmission of electrical signals between the transistor T2 and the peripheral interconnection layer 220.

[0073] As shown in Figure 2 exemplarily, the peripheral interconnection layer 220 can include one or more second interconnection conductor layers 231, one or more second interlayer insulating layers 232, and a plurality of second contacts 233 insulated from each other by the second interlayer insulating layers 232. Among them, the different second interconnection conductor layers 231 can be coupled by the second contacts 233.

[0074] The material of the second interconnection conductor layer 231 and the second contact 233 can be a conductive material, for example, tungsten, cobalt, copper, aluminum, and a combination of one or more of metal silicides, and can also be other suitable materials.

[0075] The material of the second interlayer insulating layer 232 is an insulating material, for example, a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating material, and can also be other suitable materials.

[0076] The peripheral interconnection layer 220 can be coupled with the array interconnection layer 120, so that the semiconductor device 100 and the peripheral device 200 can be coupled. Specifically, since the peripheral interconnection layer 220 is coupled with the array interconnection layer 120, the peripheral circuit in the peripheral device 200 can be coupled with the storage unit 111 in the semiconductor device 100 to realize the transmission of electrical signals between the peripheral circuit and the storage unit 111.

[0077] In some possible implementations, the peripheral interconnection layer 220 and the array interconnection layer 120 are bonded, so that the second contact 233 in the peripheral interconnection layer 220 and the corresponding first contact 123 in the array interconnection layer 120 are in contact, so that the peripheral circuit in the peripheral device 200 can be coupled with the storage unit 111 in the semiconductor device 100. Among them, the surface of the peripheral interconnection layer 220 and the array interconnection layer 120 in contact can be referred to as a bonding surface S.

[0078] Referring to Figure 1 and Figure 2 some embodiments of the present disclosure provide a semiconductor structure 400. The memory 10 includes the semiconductor structure 400.

[0079] Exemplarily, the semiconductor structure 400 can be the memory 10, for example, the semiconductor structure 400 includes the semiconductor device 100 and the peripheral device 200. Exemplarily, the semiconductor structure 400 can also be part of the memory 10, for example, the semiconductor structure 400 is the semiconductor device 100 in the memory 10, and the embodiments of the present disclosure do not make specific limitations thereto.

[0080] In some embodiments, referring to Figure 2 and Figure 5The semiconductor structure 400 includes a plurality of first transistors T1 and an isolation structure 410.

[0081] As shown in Figure 5 , at least two first transistors T1 are arranged along a first direction X. Exemplarily, the plurality of first transistors T1 are arranged along the first direction X and a second direction Y.

[0082] Exemplarily, referring to Figure 5 and Figure 6 , the first transistor T1 includes a semiconductor body 420 and a gate layer 431. The semiconductor body 420 extends along a third direction Z, and includes a first pole 421, a channel 422 and a second pole 423 of the first transistor T1. The first pole 421 and the second pole 423 are opposite ends of the semiconductor body 420 in the third direction Z, and the channel 422 is located between the first pole 421 and the second pole 423. The gate layer 431 is disposed on the sidewall of the semiconductor body 420 to form a gate of the first transistor T1.

[0083] It should be noted that the material of the channel 422 includes a semiconductor material, and the materials of the first pole 421 and the second pole 423 can include a semiconductor material doped with P-type dopants or N-type dopants.

[0084] In addition, the orthogonal projection of the channel 422 on a reference surface is located within the range of the orthogonal projection of the gate layer 431 on the reference surface, so that the first pole 421 and the second pole 423 at both ends of the channel 422 can be turned on or turned off under the control of the voltage of the gate layer 431. The reference surface is perpendicular to the first direction X.

[0085] That is, when the gate layer 431 receives a voltage from the word line WL greater than the threshold voltage of the first transistor T1, the first transistor T1 is turned on. When the gate layer 431 receives a voltage from the word line WL less than or equal to the threshold voltage of the first transistor T1, the first transistor T1 is turned off.

[0086] As shown in Figure 5 , the isolation structure 410 extends along the second direction Y, and the isolation structure 410 is located between two first transistors T1 adjacent in the first direction X, so that the two first transistors T1 adjacent in the first direction X are insulated.

[0087] Exemplarily, referring to Figure 5 and Figure 6The isolation structure 410 includes a conductor layer 411, which can be connected to a second reference voltage, to isolate the gate layer 431 of one of the first transistors T1 from the semiconductor body 420 (channel 422) of the other first transistor T1, thereby reducing electromagnetic interference between the adjacent first transistors T1.

[0088] It should be noted that the second reference voltage can be a negative voltage, for example, and can also be other voltages. The material of the conductor layer 411 includes a conductive material; for example, the material of the conductor layer 411 includes titanium nitride.

[0089] It should be understood that, referring to Figure 5 and Figure 6 , the orthogonal projection of the conductor layer 411 on the reference surface at least partially overlaps the orthogonal projection of the adjacent gate layer 431 on the reference surface, so as to reduce the interference between the two first transistors T1 located on the opposite sides of the isolation structure 410.

[0090] In addition, when the orthogonal projection of the conductor layer 411 on the reference surface covers the gate layer 431, the conductor layer 411 will have an adverse effect on the conduction and cutoff of the channel 422, thereby increasing the risk of leakage current of the first transistor T1.

[0091] Based on this, as shown in Figure 5 and Figure 6 , the orthogonal projection of the conductor layer 411 on the reference surface is located within the range of the orthogonal projection of any adjacent gate layer 431 on the reference surface. That is, the two ends of the conductor layer 411 in the third direction Z are located between the two ends of any adjacent gate layer 431 in the third direction Z, so as to avoid the risk of leakage current of the first transistor T1 caused by the conductor layer 411.

[0092] In addition, in the case where the second reference voltage is fixed, the greater the overlapping area of the orthogonal projection of the conductor layer 411 on the reference surface and the orthogonal projection of the adjacent gate layer 431 on the reference surface, the better the shielding effect of the conductor layer 411. Therefore, the height (distance from the bonding surface S) of the two ends of the conductor layer 411 in the third direction Z is very important.

[0093] It should be understood that, when the height of the two ends of the conductor layer 411 in the third direction Z is directly controlled by etching the conductor layer 411, the conductor layer 411 needs to undergo at least two etching processes. The first etching is from the side of the conductor layer 411 away from the bonding surface S, so that the end of the conductor layer 411 away from the bonding surface S is lower than the end of the gate layer 431 away from the bonding surface S. The second etching is from the side of the conductor layer 411 close to the bonding surface S, so that the end of the conductor layer 411 close to the bonding surface S is higher than the end of the gate layer 431 close to the bonding surface S.

[0094] However, between the first etching and the second etching, there are other process steps, at least one of which has a process condition of high temperature, which can cause the grains of the conductor layer 411 to recombine, resulting in cavities inside the conductor layer 411. Due to the cavities inside the conductor layer 411, when the conductor layer 411 is directly etched in the second etching and the etching depth is controlled by controlling the etching time, the etching depth cannot be accurately controlled, resulting in difficulty in controlling the height of the end of the conductor layer 411 close to the bonding surface S.

[0095] Based on this, referring to Figure 7 and Figure 8 In the semiconductor structure 400 provided by the present disclosure, the isolation structure 410 further includes a twin-induced layer 412 located between the conductor layer 411 and the first transistor T1 and in contact with the conductor layer 411 to induce the growth direction of the crystal lattice of the conductor layer 411, so that the crystals of the conductor layer 411 form a twin structure.

[0096] In this case, since the crystals of the twin structure have low crystal energy and high stability, the risk of grain crystallization of the conductor layer 411 is reduced under high-temperature processes, and the cavities caused by the grain recombination of the conductor layer 411 can be reduced. Therefore, in the second etching, when the etching depth is controlled by controlling the etching time, the accuracy of the etching depth can be improved, which is conducive to improving the uniformity of the height of the end of the conductor layer 411 close to the bonding surface S, and is conducive to improving the accurate control of the height of the two ends of the conductor layer 411 in the third direction Z.

[0097] At this time, the accurate control of the height of the two ends of the conductor layer 411 in the third direction Z can make the overlapping area of the conductor layer 411 and the adjacent gate layer 431 larger on the basis of avoiding the conductor layer 411 causing the first transistor T1 to generate a leakage current, thereby effectively blocking the interference between the two first transistors T1 located on the opposite sides of the isolation structure 410 and adjacent to each other.

[0098] Figure 9 A structure diagram of a face-centered cubic lattice according to some embodiments; Figure 10 A structure diagram of a crystal with a crystal direction of

[100] according to some embodiments; Figure 7 A structure diagram of a crystal with a crystal direction of

[110] according to some embodiments; Figure 10 A structure diagram of a crystal with a crystal direction of

[111] according to some embodiments.

[0099] It should be understood that the twin-induced layer 412 is in contact with the conductor layer 411, and the conductor layer 411 can grow along the crystal grains of the twin-induced layer 412. At this time, the crystal structure of the conductor layer 411 depends on the lattice type and the crystal direction of the twin-induced layer 412.

[0100] Exemplarily, as shown in Figure 6 , the lattice type of the twin-induced layer 412 is a face-centered cubic lattice. And, as shown in Figure 6 , the crystal direction of the twin-induced layer 412 is

[111] . In this case, the conductor layer 411 can grow along the crystal grains of the twin-induced layer 412, thereby forming the conductor layer 411 with a crystal organization of a twin structure. Wherein, the material of the twin-induced layer 412 may, for example, include aluminum oxide and / or hafnium oxide.

[0101] In some embodiments, as shown in Figure 6 , the isolation structure 410 further includes a first insulating layer 413, which is located on one side of the conductor layer 411 along the third direction Z. For example, along the third direction Z, the first insulating layer 413 is located on the side of the conductor layer 411 away from the bonding surface S.

[0102] It should be noted that the material of the first insulating layer 413 includes any one of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating material, for example, the material of the first insulating layer 413 includes silicon nitride.

[0103] Wherein, the end of the first insulating layer 413 away from the conductor layer 411 is flush with the end of the semiconductor body 420, that is, the first insulating layer 413 fills the gap between the semiconductor body 420 on the upper side of the conductor layer 411, so as to play a role of flattening and supporting,

[0104] In some embodiments, as shown in Figure 6 , the isolation structure 410 further includes a second insulating layer 414, which is located on the other side of the conductor layer 411 along the third direction Z. For example, along the third direction Z, the second insulating layer 414 is located on the side of the conductor layer 411 close to the bonding surface S. That is, the first insulating layer 413 and the second insulating layer 414 are located on opposite sides of the conductor layer 411.

[0105] Wherein, the end of the second insulating layer 414 away from the conductor layer 411 is flush with the end of the semiconductor body 420, that is, the second insulating layer 414 fills the gap between the semiconductor body 420 on the lower side of the conductor layer 411, so as to play a role of flattening and supporting,

[0106] It should be noted that the material of the second insulating layer 414 includes any one of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating material; for example, the material of the second insulating layer 414 includes silicon nitride.

[0107] In some embodiments, as shown in Figure 18 the twin-induced layer 412 includes a first portion 4121 and a second portion 4122, the first portion 4121 is located between the conductor layer 411 and the first transistor T1, the second portion 4122 is located between the first insulating layer 413 and the first transistor T1, and between the second insulating layer 414 and the first transistor T1.

[0108] It should be noted that the thickness of the second portion 4122 of the twin-induced layer 412 is less than the thickness of the first portion 4121.

[0109] Exemplarily, as shown in Figure 5 the two ends of the twin-induced layer 412 in the third direction Z are flush with the two ends of the semiconductor body 420, so that the conductor thin film 411' (see Figure 5 ) with a twin structure can be formed in the gap between the semiconductor bodies 420 of the two adjacent first transistors T1, thereby forming the conductor layer 411 with a twin structure after removing the first and second predetermined portions mentioned below.

[0110] In some embodiments, referring to Figure 5 the plurality of first transistors T1 are divided into a plurality of transistor groups T10, each first transistor group T10 includes two first transistors T1 arranged in the first direction X, and at least two first transistor groups T10 are arranged along the first direction X.

[0111] On this basis, as shown in Figure 6 the isolation structure 410 can be located between the two adjacent first transistor groups T10, for example. And the first transistor group T10 includes the gate structure 430 and the semiconductor body 420, the gate structure 430 extends along the second direction Y, and the semiconductor body 420 is arranged on the opposite sides of the gate structure 430 along the first direction X.

[0112] That is, the isolation structure 410 and the gate structure 430 are alternately arranged in the first direction X. In this way, in combination with Figure 6 and Figure 6 the gate layer 431 and the gate dielectric layer 432 of the two first transistors T1 in the first transistor group T10 are located between the two adjacent semiconductor bodies 420, and the distance between the two semiconductor bodies 420 is large, which is beneficial to the preparation of the gate layer 431 and the gate dielectric layer 432, and the process difficulty is low, which is conducive to reducing the production cost.

[0113] In some embodiments, as shown in Figure 6As shown, the semiconductor structure 400 further includes an isolation layer 440 between the gate structure 430 and the semiconductor body 420, and between the isolation structure 410 and the semiconductor body 420, to protect the sidewall of the semiconductor body 420 from being damaged by etching.

[0114] It is to be noted that the material of the isolation layer 440 includes any one of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating material. For example, the material of the isolation layer 440 includes silicon oxide. The isolation layer 440 can be a single-layer structure or a multi-layer structure, which is not limited in the embodiments of the present disclosure.

[0115] In some embodiments, as shown in Figure 6 The gate structure 430 includes a gate layer 431 and a gate dielectric layer 432. The gate layer 431 is disposed on a side of the gate dielectric layer 432 away from the semiconductor body 420 to form a gate of the first transistor T1. The gate dielectric layer 432 is disposed on the sidewall of the semiconductor body 420 to insulate the gate layer 431 from the corresponding semiconductor body 420.

[0116] In some embodiments, as shown in Figure 6 The gate structure 430 further includes an insulating structure 433 covering at least two ends of the gate layer 431 in the third direction Z to provide support and reduce the risk of collapse of the semiconductor structure 400. Meanwhile, the insulating structure 433 can also provide insulation to avoid short-circuiting between the gate layer 431 and other conductive structures (e.g., the first electrode 421 of the semiconductor body 420).

[0117] For example, as shown in Figure 6 The insulating structure 433 includes a first insulating part 4330 and a second insulating part 4340.

[0118] As shown in Figure 6 The first insulating part 4330 includes a third part 4331 and a fourth part 4332. In the first direction X, the third part 4331 is between the gate layers 431 in the same gate structure 430 to reduce the risk of short-circuiting between the gate layers 431 in the same gate structure 430 and provide support. In the third direction Z, the fourth part 4332 covers one end of the gate layer 431 and the third part 4331, and is between the gate dielectric layers 432 in the same gate structure 430 to provide flatness and support.

[0119] As shown in Figure 6As shown, the second insulating portion 4340 is disposed between two adjacent semiconductor bodies 420. Along the third direction Z, the second insulating portion 4340 covers the gate layer 431, the gate dielectric layer 432, and the other end of the third portion 4331 away from the fourth portion 4332, in order to prevent the gate layer 431 from being short-circuited to the first electrode 421 of the semiconductor body 420 and to provide support.

[0120] In some embodiments, see Figure 11 The second insulating part 4340 includes a third insulating layer 4341 and a fourth insulating layer 4342.

[0121] like Figure 18 As shown, the third insulating layer 4341 is located between the fourth insulating layer 4342 and the semiconductor bodies 420 on both sides, and on the side of the fourth insulating layer 4342 away from the first insulating portion 4330. The portion of the third insulating layer 4341 located on the side of the fourth insulating layer 4342 away from the first insulating portion 4330 can be flush with the end of the semiconductor body 420.

[0122] Embodiments of this disclosure provide a method for fabricating a semiconductor structure 400, such as... Figure 20 As shown, the preparation method includes steps S100 to S200.

[0123] S100: See also Figure 20 and Figure 12 This forms an intermediate semiconductor structure of 400'.

[0124] In the above steps, the intermediate semiconductor structure 400' includes a substrate 500 and a plurality of first trenches 510. Along the third direction Z, the substrate 500 has a first surface 500A and a second surface 500B disposed opposite to each other, and the first trenches 510 are disposed on the first surface 500A of the substrate 500. Figure 20 The first groove 510 extends along the second direction Y, and the plurality of first grooves 510 are arranged in the first direction X.

[0125] In some embodiments, see Figure 20 S100 includes S110 to S150.

[0126] S110: See also Figure 20 A protective layer 610 is formed on the first surface 500A of the substrate 500.

[0127] In the above steps, the protective layer 610 covers the first surface 500A of the substrate 500 to protect the substrate and prevent damage to the first surface 500A of the substrate 500 from subsequent etching and stripping processes. The protective layer 610 can be formed by thin film deposition or coating processes.

[0128] It should be noted that the thin film deposition process includes any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0129] S120: Referring to Figure 19 The first trench 510 and the second trench 520 are formed on the first surface 500A of the substrate 500.

[0130] In the above step, the first trench 510 and the second trench 520 extend along the second direction Y and are alternately arranged in the first direction X. Moreover, the first trench 510 and the second trench 520 extend from the first surface 500A of the substrate 500 into the substrate 500 without penetrating through the substrate 500. The first trench 510 and the second trench 520 can be formed by a dry etching process or a wet etching process.

[0131] Exemplarily, as shown in Figure 20 The substrate 500 includes a first base 511, and a second base 512 and a semiconductor layer 513 are sequentially formed on the first base 511. On this basis, the first trench 510 and the second trench 520 can penetrate through the semiconductor layer 513 and stop at the second base 512.

[0132] In a feasible implementation, in the process of S120, referring to Figure 20 A third trench 530 extending along the first direction X can also be formed, and the third trench 530 intersects with the first trench 510 and the second trench 520, so that the semiconductor layer 513 is patterned into a plurality of semiconductor bodies 420 arranged in an array. In another feasible implementation, the third trench 530 extending along the first direction X can be formed by a single etching process.

[0133] It should be noted that the insulating material is filled between two semiconductor bodies 420 adjacent in the second direction Y to insulate the two semiconductor bodies 420 adjacent in the second direction Y.

[0134] S130: Referring to Figure 20 The isolation layer 440 is formed on the substrate 500.

[0135] In the above step, the isolation layer 440 covers the first surface 500A of the substrate 500, and the bottom wall and the side wall of the first trench 510 and the second trench 520. The isolation layer 440 can be formed by a thin film deposition process, for example.

[0136] S140: Referring to Figure 18A sacrifice layer 620 is formed in the first trench 510 and the second trench 520.

[0137] In the above step, the sacrifice layer 620 can be first deposited on the whole surface by a thin film deposition process, so that the sacrifice material fills the first trench 510 and the second trench 520; then, a dry or wet etching process is used to remove the sacrifice layer 620 outside the first trench 510 and the second trench 520.

[0138] S150: Refer to Figure 7 The sacrifice layer 620 located in the first trench 510 is removed.

[0139] In the above step, a mask plate can be used to cover the sacrifice layer 620 located in the second trench 520, and then a dry or wet etching process is used to remove the sacrifice layer 620 located in the first trench 510, and finally the mask plate is stripped.

[0140] It should be noted that the mask plate can be formed by a coating process, an exposure process and a developing process in sequence, for example.

[0141] S200: Refer to Figure 10 The isolation structure 410 is formed in the first trench 510.

[0142] In the above step, the isolation structure 410 includes a conductor layer 411 and a twin crystal inducing layer 412, the twin crystal inducing layer 412 is located between the conductor layer 411 and the sidewall of the first trench 510, and is in contact with the conductor layer 411.

[0143] Illustratively, refer to Figure 18 , Figure 18 and Figure 13 The lattice type of the twin crystal inducing layer 412 is face-centered cubic lattice, and the crystal direction is

[111] . For example, the material of the twin crystal inducing layer 412 includes aluminum oxide and / or hafnium oxide.

[0144] Illustratively, refer to Figure 18 The crystal structure of the conductor layer 411 is twin crystal structure. For example, the material of the conductor layer 411 can include titanium nitride.

[0145] In some embodiments, refer to Figure 14 S200 includes S210-S240.

[0146] S210: Refer to Figure 18 An initial isolation structure 410' is formed in the first trench 510.

[0147] In the step, the initial isolation structure 410' includes a twin-induced film 412' and a conductor film 411'. The twin-induced film 412' covers at least the sidewall and the bottom wall of the first trench 510. The conductor film 411' is located on the side of the twin-induced film 412' away from the substrate 500 and is in contact with the twin-induced film 412'.

[0148] In some embodiments, referring to Figure 18 , S210 includes S211-S214.

[0149] S211: referring to Figure 18 , forming a twin-induced film 412'.

[0150] In the step, the twin-induced film 412' covers the first surface 500A of the substrate 500 and the sidewall and the bottom wall of the first trench 510. The twin-induced film 412' can be formed by a thin film deposition process.

[0151] S212: referring to Figure 18 , forming a conductor film 411' on the twin-induced film 412'.

[0152] In the step, the conductor film 411' covers the twin-induced film 412' and fills the first trench 510. The conductor film 411' can be formed by a deposition process on the twin-induced film 412', for example.

[0153] S213: referring to Figure 18 , removing the conductor film 411' covering the first surface 500A of the substrate 500 and the conductor film 411' located in the second preset part of the first trench 510.

[0154] In the step, the second preset part is the part of the conductor film 411' to be removed, which can be determined according to the height of the end of the conductor layer 411 away from the second surface 500B required by the subsequent process, so that the height of the end of the conductor layer 411 away from the second surface 500B is lower than the height of the end of the gate layer 431 away from the second surface 500B formed subsequently.

[0155] The second preset part of the conductor film 411' can be removed by a dry or wet etching process and by controlling the etching time, for example.

[0156] S214: referring to Figure 15 , removing the part of the twin-induced film 412' covering the first surface 500A of the substrate 500, the part of the isolation layer 440 covering the first surface 500A of the substrate 500, and the protection layer 610.

[0157] In the above step, the part of the twin-induced film 412' covering the first surface 500A of the substrate 500, the part of the isolation layer 440 covering the first surface 500A of the substrate 500, and the protection layer 610 can be removed by any one of a dry etching process, a wet etching process, or a planarization process.

[0158] For example, the part of the twin-induced film 412' covering the first surface 500A of the substrate 500, the part of the isolation layer 440 covering the first surface 500A of the substrate 500, and the protection layer 610 can be removed by chemical mechanical polishing.

[0159] In some embodiments, referring to Figure 18 In S213, the conductor film 411' located at the second preset part of the first groove 510 is removed to form a first sub-groove 501. On this basis, referring to Figure 15 Before S214, the above S210 can further include S215.

[0160] S215: referring to Figure 18 The first insulating film 413' is formed in the first sub-groove 501.

[0161] In the above step, the first insulating film 413' covers the first surface 500A of the substrate 500 and fills the first sub-groove 501. The first insulating film 413' can be formed by a film deposition process, for example.

[0162] At this time, in the process of S213, the part of the first insulating film 413' covering the first surface 500A of the substrate 500 is also removed. That is, referring to Figure 20 S214 specifically includes: removing the part of the first insulating film 413' covering the first surface 500A of the substrate 500, the part of the twin-induced film 412' covering the first surface 500A of the substrate 500, the part of the isolation layer 440 covering the first surface 500A of the substrate 500, and the protection layer 610.

[0163] Here, the part of the first insulating film 413', the twin-induced film 412', and the isolation layer 440 covering the first surface 500A of the substrate 500, and the protection layer 610 can be removed by any one of a dry etching process, a wet etching process, or a planarization process. For example, the part of the first insulating film 413', the twin-induced film 412', and the isolation layer 440 covering the first surface 500A of the substrate 500, and the protection layer 610 can be removed by chemical mechanical polishing.

[0164] S220: referring to Figure 21 The part of the substrate 500 located away from the first surface 500A of the twin-induced film 412' is removed to expose the twin-induced film 412'.

[0165] In the above step, the part of the substrate 500 located away from the twin-induced film 412' of the first surface 500A can be removed by using any one of a dry etching process, a wet etching process and a planarization process.

[0166] Exemplarily, as shown in Figure 18 and Figure 18 , the substrate 500 includes a first base 511, and a second base 512 and a semiconductor layer 513 are sequentially formed on the first base 511, the first trench 510 can penetrate the semiconductor layer 513 and stop at the second base 512. On this basis, the part of the substrate 500 located away from the twin-induced film 412' of the first surface 500A is the first base 511 and the second base 512.

[0167] At this time, the part of the substrate 500 located away from the twin-induced film 412' of the first surface 500A, i.e., the first base 511 and the second base 512 can be removed by using chemical mechanical grinding.

[0168] S230: referring to Figure 18 , the part of the twin-induced film 412' exposed is removed so that the conductor film 411' is exposed.

[0169] In the above step, the part of the twin-induced film 412' exposed can be removed by using a dry etching process or a wet etching process. Here, the conductor film 411' can be used as a stop layer of the etching process.

[0170] S240: referring to Figure 16 , the first preset part of the conductor film 411' is removed.

[0171] In the above step, the first preset part is the part of the conductor film 411' to be removed, which can be determined according to the height required by the end of the conductor layer 411 close to the second surface 500B of the substrate 500, so that the height of the end of the conductor layer 411 close to the second surface 500B is higher than the height of the end of the gate layer 431 close to the second surface 500B.

[0172] For example, the first preset part of the conductor film 411' can be removed by using a dry etching process or a wet etching process and by controlling the etching time.

[0173] In some embodiments, referring to Figure 18 , in S240, the first preset part of the conductor film 411' is removed to form the second sub-trench 502. On this basis, referring to Figure 17 , after S240, the above S200 can further include S250.

[0174] S250: referring toFigure 21 A second insulating layer 414 is formed in the second sub-slot 502.

[0175] In the above steps, the second sub-groove 502 is the gap formed after the first preset portion of the conductor thin film 411' is removed. The second insulating layer 414 can be formed by first depositing insulating material using a thin film deposition process, and then removing the portion covering the semiconductor layer 513 using a dry or wet etching process.

[0176] In some embodiments, see Figure 21 Before S220, the above preparation method also includes S300 to S400.

[0177] S300: See Figure 6 Remove the sacrificial layer 620 located in the second trench 520.

[0178] In the above steps, the sacrificial layer 620 located in the second trench 520 can be removed by dry or wet etching processes.

[0179] S400: See Figure 22 A gate structure 430 is formed within the second trench 520.

[0180] In the above steps, combined Figure 23 The gate structure 430 may include, for example, a gate layer 431, a gate dielectric layer 432, and an insulating structure 433. The insulating structure 433 may include, for example, a first insulating portion 4330 and a second insulating portion 4340.

[0181] Figure 22 This is a block diagram of a storage system according to some embodiments. Figure 23 This is a block diagram of a storage system according to some other embodiments.

[0182] Please see Figure 22 and Figure 23 Some embodiments of this disclosure also provide a storage system 1000. The storage system 1000 includes a controller 20 and a memory 10 as described in some of the embodiments above, the controller 20 being coupled to the memory 10 to control the memory 10 to store data.

[0183] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 can be applied to and packaged into different types of electronic products, for example, a mobile phone (e.g., a cell phone), a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a game console, a printer, a positioning device, a wearable device, a smart sensor, a mobile power supply, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having a storage.

[0184] In some embodiments, referring to ​ , the storage system 1000 includes a controller 20 and one memory 10, and the storage system 1000 can be integrated into a memory card.

[0185] The memory card includes any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD) card, or a UFS.

[0186] In other embodiments, referring to ​ , the storage system 1000 includes a controller 20 and a plurality of memories 10, and the storage system 1000 is integrated into a Solid State Drive (SSD).

[0187] In the storage system 1000, in some embodiments, the controller 20 is configured to operate in a low duty cycle environment, for example, an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices for personal computers, digital cameras, mobile phones, etc.

[0188] In other embodiments, the controller 20 is configured to operate in a high duty cycle environment, for example, an SSD or an eMMC used for data storage of mobile devices such as smartphones, tablets, notebook computers, etc., and enterprise storage arrays.

[0189] In some embodiments, the controller 20 can be configured to manage data stored in the memory 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 can also be configured to control operations of the memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 can also be configured to manage various functions related to data stored in or to be stored in the memory 10, including at least one of bad block management, garbage collection, logical to physical address translation, wear leveling. In some embodiments, the controller 20 is also configured to process error correction codes related to data read from or written to the memory 10.

[0190] Of course, the controller 20 can also perform any other suitable functions, such as formatting the memory 10; for example, the controller 20 can communicate with an external device (e.g., a host) through at least one of various interface protocols.

[0191] It should be noted that the interface protocols include at least one of a USB protocol, a MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol.

[0192] Some embodiments of the present disclosure also provide an electronic device. The electronic device can be any one of a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0193] The electronic device can include the storage system 1000 described above, and can also include at least one of a Central Processing Unit (CPU) and a cache, etc.

[0194] The above only describes specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any changes or replacements within the technical scope disclosed by the present application can be easily thought of by those skilled in the art, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized by, The application relates to a semiconductor structure and a method for forming the same. The semiconductor structure comprises: a plurality of first transistors, at least two of which are arranged along a first direction; an isolation structure between two first transistors adjacent in the first direction; the isolation structure comprises a twin-induced layer and a conductor layer, the twin-induced layer is between the conductor layer and the first transistors and in contact with the conductor layer; the isolation structure further comprises: a first insulating layer along a third direction, the first insulating layer is on one side of the conductor layer; the third direction is perpendicular to the first direction; 2. The semiconductor structure of claim 1, wherein, a second insulating layer along the third direction, the second insulating layer is on the other side of the conductor layer.

3. The semiconductor structure of claim 2, wherein, The lattice type of the twin-induced layer is face-centered cubic lattice, and the crystal direction is [111].

4. The semiconductor structure of claim 1, wherein, The material of the twin-induced layer comprises aluminum oxide and / or hafnium oxide.

5. The semiconductor structure of claim 1, wherein, The crystal structure of the conductor layer is twin structure.

6. The semiconductor structure of claim 1, wherein, The material of the conductor layer comprises titanium nitride. The twin-induced layer comprises: a first part between the conductor layer and the first transistors; 7. The semiconductor structure of claim 6, wherein, a second part between the first insulating layer and the first transistors and between the second insulating layer and the first transistors.

8. The semiconductor structure of any one of claims 1-7, wherein, The thickness of the second part is less than that of the first part. The plurality of first transistors are divided into a plurality of first transistor groups, each of which comprises two first transistors arranged along the first direction, and at least two first transistor groups are arranged along the first direction; 9. The semiconductor structure of claim 8, wherein, wherein the isolation structure is between two adjacent first transistor groups; the first transistor group comprises a gate structure and a semiconductor body, along the first direction, the semiconductor body is arranged on the opposite sides of the gate structure. The application further comprises:

10. The semiconductor structure of claim 8, wherein, an isolation layer between the gate structure and the semiconductor body and between the isolation structure and the semiconductor body. The gate structure comprises: a gate dielectric layer arranged on the sidewall of the semiconductor body; a gate layer arranged on the side of the gate dielectric layer away from the semiconductor body; 11. The semiconductor structure of claim 10, wherein, an insulating structure covering at least two ends of the gate layer in the third direction; the third direction is perpendicular to the first direction.

12. A method of fabricating a semiconductor structure, characterized by, The two ends of the conductor layer in the third direction are between the two ends of any adjacent gate layer in the third direction. The application relates to a semiconductor structure and a method for forming the same. The semiconductor structure comprises: forming an intermediate semiconductor structure; the intermediate semiconductor structure comprises a substrate and a plurality of first trenches, along a third direction, the substrate has a first surface and a second surface arranged oppositely, the first trenches are arranged on the first surface of the substrate and extend along a second direction; the plurality of first trenches are arranged along a first direction; the second direction and the first direction intersect and are both perpendicular to the third direction; forming an isolation structure in the first trench; the isolation structure comprises a twin-induced layer and a conductor layer, the twin-induced layer is between the conductor layer and the sidewall of the first trench and in contact with the conductor layer; the isolation structure further comprises a first insulating layer and a second insulating layer, the first insulating layer is on one side of the conductor layer along a third direction; the third direction is perpendicular to the first direction; the second insulating layer is on the other side of the conductor layer along the third direction.

13. The method of claim 12, wherein, The forming the intermediate semiconductor structure comprises: forming a protection layer on the first surface of the substrate; forming a first trench and a second trench on the first surface of the substrate; the first trench and the second trench extend along the second direction and are arranged alternately along the first direction; forming an isolation layer on the substrate; the isolation layer covers the first surface of the substrate and the bottom wall and the sidewall of the first trench and the second trench; forming a sacrificial layer in the first trench and the second trench; removing the sacrificial layer in the first trench.

14. The method of claim 13, wherein, The forming the isolation structure in the first trench comprises: forming an initial isolation structure in the first trench; the initial isolation structure comprises a twin-induced film and a conductor film, the twin-induced film covers at least the sidewall and the bottom wall of the first trench, the conductor film is on the side of the twin-induced film away from the substrate and in contact with the twin-induced film; removing the part of the substrate on the side of the twin-induced film away from the first surface so that the twin-induced film is exposed; removing the exposed part of the twin-induced film so that the conductor film is exposed; removing a first preset part of the conductor film.

15. The preparation method according to claim 14, characterized in that, The forming the initial isolation structure in the first trench comprises: forming a twin-induced film; the twin-induced film covers the first surface of the substrate and the sidewall and the bottom wall of the first trench; forming a conductor film on the twin-induced film; the conductor film covers the twin-induced film and fills the first trench; removing the part of the conductor film covering the first surface of the substrate and the second preset part of the conductor film in the first trench; removing the part of the twin-induced film covering the first surface of the substrate, the part of the isolation layer covering the first surface of the substrate and the protection layer.

16. The method of claim 15, wherein, The removing the second preset part of the conductor film in the first trench forms a first sub-trench; before the removing the part of the twin-induced film covering the first surface of the substrate, the part of the isolation layer covering the first surface of the substrate and the protection layer, the forming the initial isolation structure in the first trench further comprises: forming a first insulating film in the first sub-trench; the first insulating film covers the first surface of the substrate and fills the first sub-trench; in the process of removing the part of the twin-induced film covering the first surface of the substrate, the part of the isolation layer covering the first surface of the substrate and the protection layer, the part of the first insulating film covering the first surface of the substrate is also removed.

17. The method of any one of claims 13-16, wherein, The lattice type of the twin-induced layer is a face-centered cubic lattice, and the crystal direction is [111].

18. The method of claim 17, wherein, The material of the twin-induced layer includes aluminum oxide and / or hafnium oxide.

19. The method of any one of claims 13-16, wherein, The crystal structure of the conductor layer is a twin structure.

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