Semiconductor device and method of manufacturing the same, storage system

Abstract

Embodiments of the present application provide a semiconductor device, a preparation method and a memory system. The semiconductor device comprises a semiconductor pillar, an isolation structure and a gate structure. The semiconductor pillar extends along a first direction and comprises at least one side surface; the isolation structure extends along a second direction, wherein the isolation structure is opposite to a part of the side surface of the semiconductor pillar in a third direction, and the first direction, the second direction and the third direction intersect with each other; and the gate structure surrounds the remaining side surface of the semiconductor pillar, wherein a plurality of gate structures adjacent to the same isolation structure are symmetrically distributed on both sides of the same isolation structure in the third direction.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and fabrication, and more specifically, to semiconductor devices, methods for fabricating semiconductor devices, and memory systems. Background Technology

[0002] Semiconductor devices may include memory cells composed of capacitors and transistors, wherein multiple memory cells may be arranged in a two-dimensional array. To further reduce the size of the two-dimensional array, the transistors may include vertical gate transistors (VGTs). In this structure, the transistor may include a semiconductor pillar, source and drain terminals located at both ends of the semiconductor pillar's extension direction, and a gate structure located on the sidewall of the semiconductor pillar.

[0003] The gate control capability of a transistor refers to its ability to form a channel between the source and drain along the extension direction of the semiconductor pillar by relying on the gate voltage applied to the gate structure. This channel can be formed when the gate voltage is higher than the threshold voltage of the vertical transistor.

[0004] How to further reduce the size of semiconductor devices while enhancing the gate control capability of the gate structure and improving the switching speed and reliability of the gate structure is one of the important research directions in the industry. Summary of the Invention

[0005] This application provides a method for fabricating a semiconductor device, a semiconductor device, and a memory system that can at least partially solve the above-mentioned problems in related technologies or other problems in the art.

[0006] This application provides a semiconductor device comprising: a semiconductor pillar extending along a first direction and including at least one side; an isolation structure extending along a second direction, wherein the isolation structure is opposite to a portion of the side of the semiconductor pillar in a third direction, and the first direction, the second direction, and the third direction intersect each other; and a gate structure surrounding the remaining side of the semiconductor pillar, wherein a plurality of the gate structures adjacent to the same isolation structure are symmetrically distributed on opposite sides of the same isolation structure in the third direction.

[0007] In one embodiment of this application, a plurality of gate structures adjacent to the same isolation structure are mirror-symmetrically distributed on both sides of the same isolation structure.

[0008] In one embodiment of this application, the isolation structure includes an isolation medium layer and an air gap surrounded by the isolation medium layer.

[0009] In one embodiment of the present application, the isolation structure includes an isolation dielectric layer and a conductive layer surrounded by the isolation dielectric layer.

[0010] In one embodiment of the present application, the gate structure includes a gate dielectric layer and a gate conductor layer, wherein the gate dielectric layer is between the side surface of the semiconductor pillar and the gate conductor layer.

[0011] In one embodiment of the present application, the gate conductor layer and the conductive layer include a conductive material layer of the same material.

[0012] In one embodiment of the present application, the gate structure includes a plurality of first parts and a plurality of second parts, wherein at least one of the plurality of first parts surrounds the side surface of the semiconductor pillar, and at least one of the plurality of second parts extends in the second direction and is connected to adjacent first parts in the second direction.

[0013] In one embodiment of the present application, at least one of the plurality of first parts includes a plurality of sub-parts connected to each other, wherein the number of the sub-parts is the same as the number of the remaining side surfaces of the semiconductor pillar, and the sub-parts are located on one of the remaining side surfaces of the semiconductor pillar.

[0014] In one embodiment of the present application, in a plane perpendicular to the first direction, a projection of the semiconductor pillar is located within a projection of the first part.

[0015] In one embodiment of the present application, a cross-sectional shape of the semiconductor pillar in a plane perpendicular to the first direction includes at least one of a rectangular shape, a trapezoidal shape, a circular shape, and an elliptical shape.

[0016] In one embodiment of the present application, the semiconductor pillar has a hexahedral shape and includes four side surfaces, wherein the isolation structure is opposite to one side surface of the semiconductor pillar in the third direction, and the gate structure surrounds the remaining three side surfaces of the semiconductor pillar.

[0017] Another aspect of the present application provides a method for fabricating a semiconductor device, the method comprising: forming a semiconductor pillar, wherein the semiconductor pillar extends along a first direction and comprises at least one side surface; forming an isolation sacrificial layer, wherein the isolation sacrificial layer extends along a second direction and is opposite to a portion of the side surface of the semiconductor pillar along a third direction, the first direction, the second direction and the third direction intersecting with each other; forming a gate structure surrounding the remaining side surface of the semiconductor pillar, wherein a second portion of the gate structure is in contact with the isolation sacrificial layer, the second portion being a portion of the gate structure between semiconductor pillars adjacent in the second direction; and removing the isolation sacrificial layer and forming an isolation structure in a first void formed after the removal of the isolation sacrificial layer.

[0018] In one embodiment of the present application, the forming of the semiconductor pillar comprises: forming a base structure, wherein the base structure comprises semiconductor layers and spacer layers alternatingly distributed along the second direction; forming a first trench and a second trench extending along the second direction in the base structure, respectively, wherein a plurality of the first trenches and a plurality of the second trenches are alternatingly distributed along the third direction to divide the semiconductor layers into a plurality of the semiconductor pillars.

[0019] In one embodiment of the present application, the forming of the isolation sacrificial layer comprises: forming an initial first isolation medium layer, wherein the initial first isolation medium layer is located at least on the sidewall and the bottom surface of the second trench; and filling the isolation sacrificial layer in the remaining space of the second trench.

[0020] In one embodiment of the present application, the forming of the gate structure surrounding the remaining side surface of the semiconductor pillar comprises: removing the spacer layers and a portion of the initial first isolation medium layer to form a second void and expose a portion of the isolation sacrificial layer, wherein the removed portion of the initial first isolation medium layer is between semiconductor pillars adjacent in the second direction; forming the gate structure on the side surface of the semiconductor pillar exposed in the second void and the exposed portion of the isolation sacrificial layer.

[0021] In one embodiment of the present application, the removing of the isolation sacrificial layer and the forming of an isolation structure in a first void formed after the removal of the isolation sacrificial layer comprises: removing the isolation sacrificial layer to form the first void; forming a first portion of an isolation medium layer in the first void, wherein the first portion covers at least the initial first isolation medium layer; forming a conductive layer in the remaining space of the first void; and covering a second portion of the isolation medium layer on the surface of the conductive layer to form the isolation structure, wherein the isolation structure comprises the first portion, the second portion and the conductive layer.

[0022] In one embodiment of the present application, removing the isolation sacrificial layer and forming an isolation structure in the first void formed after removing the isolation sacrificial layer comprises: removing the isolation sacrificial layer to form the first void; and forming an isolation dielectric layer covering at least the initial first isolation dielectric layer in the first void by using a deposition process, wherein the isolation dielectric layer comprises a first portion and a second portion; forming an air gap in the first void by using two different deposition rates to form the first portion and the second portion; and the isolation structure comprises the first portion, the second portion and the air gap.

[0023] In yet another aspect of the present application, a memory system is provided, which comprises the semiconductor device provided in an aspect of the present application and a controller coupled to the semiconductor device, wherein the controller is configured to store data into the semiconductor device.

[0024] According to the semiconductor device and the manufacturing method, the memory system provided in at least one embodiment of the present application, the semiconductor device can comprise a semiconductor pillar, an isolation structure and a gate structure, wherein the semiconductor pillar comprises at least one side surface, the isolation structure is opposite to a part of the side surface of the semiconductor pillar in a direction intersecting with the extending direction of the semiconductor pillar and the extending direction of the isolation structure, and the gate structure surrounds the rest of the side surface of the semiconductor pillar. In addition, a plurality of gate structures adjacent to the same isolation structure can be symmetrically distributed on the two sides opposite to the same isolation structure. In this way, the gate control capability of the gate structure can be improved by increasing the contact area between the gate structure and the semiconductor pillar, and on this basis, the isolation structure can reduce the interference between adjacent gate structures in the semiconductor device, improve the switching speed of the gate structure and the reliability of the semiconductor device; the plurality of gate structures adjacent to the same isolation structure can be symmetrically distributed on the two sides opposite to the same isolation structure, which can effectively reduce the size of the semiconductor device and improve the influence of structural differences on the performance of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0025] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments thereof as taken in conjunction with the accompanying drawings. In the drawings:

[0026] Figure 1A is a sectional view of a semiconductor device according to an exemplary embodiment of the present application;

[0027] Figure 1B is a sectional view of a semiconductor device according to an exemplary embodiment of the present application;

[0028] Figure 1C is Figure 1A is an enlarged schematic view of the semiconductor device at M;

[0029] Figure 1D isFigure 1B enlarged schematic view of the semiconductor device shown at N;

[0030] Figure 2 is Figure 1C schematic top view of the semiconductor device shown taken along line A-A';

[0031] Figure 3 is Figure 1C schematic top view of the semiconductor device shown taken along line B-B';

[0032] Figure 4 is a flowchart of a method of fabricating a semiconductor device according to an exemplary embodiment of the present application;

[0033] Figure 5 is a schematic cross-sectional view of a structure formed after forming a semiconductor layer according to the method of fabrication of one embodiment of the present application;

[0034] Figure 6 is Figure 5 schematic top view of the intermediate taken along line A-A' or line B-B';

[0035] Figure 7 is a schematic cross-sectional view of a structure formed after forming a semiconductor pillar according to the method of fabrication of one embodiment of the present application;

[0036] Figure 8 is Figure 7 schematic top view of the intermediate taken along line A-A' or line B-B';

[0037] Figure 9 is a schematic cross-sectional view of a structure formed after forming an initial first isolation dielectric layer according to the method of fabrication of one embodiment of the present application;

[0038] Figure 10 is Figure 9 schematic top view of the intermediate taken along line A-A' or line B-B';

[0039] Figure 11 is a schematic cross-sectional view of a structure formed after forming an isolation sacrificial layer according to the method of fabrication of one embodiment of the present application;

[0040] Figure 12 is Figure 11 schematic top view of the intermediate taken along line A-A' or line B-B';

[0041] Figure 13 is a schematic cross-sectional view of a structure formed after removing a portion of the initial first isolation dielectric layer according to the method of fabrication of one embodiment of the present application;

[0042] Figure 14 is Figure 13 schematic top view of the intermediate shown taken along line A-A' or line B-B'

[0043] Figure 15 is a schematic cross-sectional view of a structure formed after forming a gate structure according to a method of manufacturing according to an embodiment of the present application;

[0044] Figure 16 is Figure 15 schematic top view of the intermediate shown taken along line A-A';

[0045] Figure 17 is Figure 15 schematic top view of the intermediate shown taken along line B-B';

[0046] Figure 18 is a schematic cross-sectional view of a structure formed after forming a first void according to a method of manufacturing according to an embodiment of the present application;

[0047] Figure 19 is Figure 18 schematic top view of the intermediate shown taken along line A-A';

[0048] Figure 20 is Figure 18 schematic top view of the intermediate shown taken along line B-B'; and

[0049] Figure 21 is a schematic view of a memory system structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0050] For a better understanding of the present application, various aspects of the present application will be described in greater detail below with reference to the drawings. It should be understood that these detailed description is merely descriptive of illustrative embodiments of the present application and is not intended to limit the scope of the present application in any way. Throughout the specification, like reference numerals refer to like elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0051] It should be noted that in the present description, the expressions first, second, third and the like are used merely to differentiate one feature from another feature area, and do not represent any limitation on the features, especially do not represent any order of precedence. Thus, the first side discussed in the present application can also be referred to as the second side, and vice versa, without departing from the teachings of the present application.

[0052] In the drawings, the thicknesses of parts, sizes, and shapes are slightly adjusted for the convenience of explanation. The drawings are merely examples and are not strictly drawn to scale. As used in this document, the terms "substantially," "approximately," and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in a measuring device or measuring methodology which would be recognized by those of ordinary skill in the art.

[0053] It should also be understood that any reference to a method, including a claimed method, exists only for the purpose of the disclosure and that the claimed method is not limited to that method. Moreover, it is also understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," or "having" and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Although the terms "comprise," "comprises," "comprising," "contain," "contains," "containing," "include," "includes," "including" and / or "has" or "having" are used to describe and claim certain features, embodiments, methods, and / or processes, these terms are used herein as equivalent to the words "consist of" or "consisting of" and not as equivalent to "consisting essentially of" or "consisting of." Furthermore, the use of letters to identify elements in the figures is merely for convenience and any one element can be referred to by more than one letter and / or any one letter can identify more than one element. Additionally, when describing applications, the use of "may" indicates that one or more embodiments of the application. Also, the word "exemplary" is used herein to mean "an example or illustration." Although the application has been described and pictured in some embodiments, it is understood that various modifications and changes can be made without departing from the scope of the present application.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an overly formal or overly literal sense unless expressly so defined herein.

[0055] It should be noted that the embodiments and features of the application can be combined with each other as long as there is no conflict. In addition, the specific steps of the methods described in the present application are not necessarily limited to the order described, but can be performed in any order or in parallel, unless expressly limited or contradicted by the context.

[0056] Furthermore, "connected" or "coupled" as used in the present application can mean that the respective components are in direct contact or in indirect contact through other components, unless expressly defined otherwise or deduced from the context.

[0057] The present application will be described in detail below with reference to the accompanying drawings and embodiments.

[0058] Some embodiments of the present application provide a semiconductor device. Figure 1A is a cross-sectional view of a semiconductor device 1000 according to an exemplary embodiment of the present application. Figure 1B is a cross-sectional view of a semiconductor device 1000 according to an exemplary embodiment of the present application. Figure 1C is Figure 1AThe diagram shows an enlarged view of the semiconductor device 1000 at point M. Figure 1D yes Figure 1B The diagram shows an enlarged view of the semiconductor device 1000 at point N. Figure 2 yes Figure 1C The diagram shown is a top view of the semiconductor device 1000 taken along line A-A'. Figure 3 yes Figure 1C The diagram shown is a top view of the semiconductor device 1000 taken along line B-B'.

[0059] like Figures 1A to 3 As shown, the semiconductor device 1000 includes a semiconductor pillar 100, a gate structure 200, and an isolation structure 300. The semiconductor pillar 100 extends along a first direction (z-direction) and includes at least one side surface 130, such as a first side surface 131, a second side surface 132, a third side surface 133, and a fourth side surface 134. The isolation structure 300, such as a first isolation structure 301, extends along a second direction (x-direction), wherein the isolation structure 300 is opposite to a portion of the side surface of the semiconductor pillar 100 in a third direction (y-direction), and the x, y, and z directions intersect each other; the gate structure 200 surrounds the remaining side surface of the semiconductor pillar 100. Furthermore, multiple gate structures adjacent to the same isolation structure are symmetrically distributed on opposite sides of the same isolation structure in the y-direction. For example, multiple gate structures adjacent to the first isolation structure 301, namely the first gate structure 201, the second gate structure 202, the third gate structure 203, and the fourth gate structure 204, are symmetrically distributed on opposite sides of the first isolation structure 301 in the y-direction.

[0060] According to at least one embodiment of the semiconductor device provided in this application, the semiconductor device may include a semiconductor pillar, an isolation structure, and a gate structure. The semiconductor pillar includes at least one side surface. The isolation structure is positioned opposite a portion of the side surface of the semiconductor pillar in a direction intersecting both the extending direction of the semiconductor pillar and its own extending direction. The gate structure surrounds the remaining side surface of the semiconductor pillar. Furthermore, multiple gate structures adjacent to the same isolation structure may be symmetrically distributed on opposite sides of the same isolation structure. Thus, by increasing the contact area between the gate structure and the semiconductor pillar, the gate control capability of the gate structure can be improved. Based on this, the isolation structure can reduce interference between adjacent gate structures in the semiconductor device, improve the switching speed of the gate structure, and enhance the reliability of the semiconductor device. Symmetrically distributing multiple gate structures adjacent to the same isolation structure on opposite sides of the same isolation structure can effectively reduce the size of the semiconductor device and mitigate the impact of structural differences on the performance of the semiconductor device.

[0061] Optionally, to enhance the above effect, multiple gate structures adjacent to the same isolation structure are mirror-symmetrically distributed on opposite sides of the same isolation structure in the y-direction. For example, multiple gate structures adjacent to the first isolation structure 301, namely the first gate structure 201, the second gate structure 202, the third gate structure 203, and the fourth gate structure 204, are mirror-symmetrically distributed on opposite sides of the first isolation structure 301 in the y-direction.

[0062] Specifically, such as Figure 1A and Figure 1B As shown, in some embodiments of this application, the semiconductor device 1000 may include a plurality of memory cells (e.g., a memory array) and peripheral circuit structures connected to the plurality of memory cells. The plurality of memory cells may be located in a first semiconductor structure 1001 (which can be understood as a memory array wafer), and the peripheral circuit structures may be located in a second semiconductor structure 1002 (which can be understood as a peripheral circuit wafer). The peripheral circuit wafer may be bonded to the memory array wafer using processes such as wafer bonding, and the connection between the peripheral circuit wafer and the memory array wafer may be achieved through, for example, interconnecting wires. Alternatively, the plurality of memory cells and the peripheral circuit structures of the semiconductor device 1000 may also be disposed on the same wafer; this application does not limit this.

[0063] Optionally, a memory cell may include a transistor 1001-1 and a memory cell 1001-2 coupled to the transistor 1001-1, wherein multiple memory cells may be formed as a memory cell array. Taking DRAM (Dynamic Random Access Memory) as an example, the semiconductor device 1000 may include memory cells composed of capacitors (memory cells 1001-2) and transistors 1001-1, and multiple memory cells may be arranged in a two-dimensional array. In other words, in some embodiments, the memory cell 1001-2 may include a capacitor for storing charge as binary information stored by the corresponding DRAM cell.

[0064] Furthermore, in some embodiments, storage unit 1001-2 may include PCM elements (e.g., chalcogenide alloys) for storing binary information of the corresponding PCM unit based on the different resistivities of the PCM (Phase Change Memory) elements in the amorphous and crystalline phases.

[0065] Additionally, in some embodiments, the storage unit 1001-2 may include a ferroelectric capacitor for storing binary information of the corresponding FRAM (Ferroelectric Random Access Memory) unit based on the switching between two polarization states of the ferroelectric material under an external electric field.

[0066] Alternatively, the transistor 1001-1 is closer to the second semiconductor structure 1002 in the z direction relative to the memory cell 1001-2, so as to shorten the length of the connection line between the connection transistor and the peripheral circuit structure in the second semiconductor structure 1002; alternatively, the memory cell 1001-2 is closer to the second semiconductor structure 1002 in the z direction relative to the transistor 1001-1, which is not limited in the present application.

[0067] In addition, in order to further reduce the size of the two-dimensional array, the transistor 1001-1 can include a vertical gate transistor. In this structure, the extension direction of the channel of the transistor 1001-1 is perpendicular to the substrate surface, and the source 110 and the drain 120 of the transistor 1001-1 can be respectively formed at both ends of the channel extension direction, and the gate structure 200 of the transistor 1001-1 can be formed on at least one side of the channel.

[0068] In an embodiment of the present application, a vertical transistor such as a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) can be used as a transfer transistor of a memory cell instead of a conventional planar transistor, so as to reduce the area occupied by the transfer transistor, the coupling capacitance, and the interconnection wiring complexity.

[0069] Reference Figure 1C to 3 , wherein Figure 1C is an enlarged schematic view of the structure of Figure 1A after being flipped 180° at M, Figure 1D is an enlarged schematic view of the structure of Figure 1B after being flipped 180° at N. In some embodiments, unlike a planar transistor in which an active region is formed in a substrate, a vertical transistor can include a semiconductor pillar 100 extending vertically in the z direction above a substrate (not shown). The semiconductor pillar 100 can extend above the top surface of the substrate, exposing not only the top surface of the semiconductor pillar 100 but also one or more side surfaces 130 of the semiconductor pillar 100, such as a first side surface 131 and a second side surface 132.

[0070] Optionally, the cross-sectional shape of the semiconductor pillar 100 in a plane perpendicular to the z direction can include at least one of a rectangular shape, a trapezoidal shape, a circular shape, and an elliptical shape. For example, the shape of the semiconductor pillar 100 can be a hexahedral shape and include four side surfaces 130, a first side surface 131, a second side surface 132, a third side surface 133, and a fourth side surface 134.

[0071] In other words, the semiconductor pillar 100 can have a cubic shape to expose four of its side surfaces 130. However, it is understood by those skilled in the art that the semiconductor pillar 100 can have any suitable 3-dimensional shape, such as a polyhedral shape or a cylindrical shape. In other words, a cross-section of the semiconductor pillar 100 in a plane perpendicular to the z-direction can have a square shape, a rectangular shape, a trapezoidal shape, a circular shape, an elliptical shape, or any other suitable shape. It is understood that, consistent with the scope of the present disclosure, for a semiconductor pillar having a cross-section in the above-mentioned plane that has a circular or elliptical shape, the semiconductor pillar can still be considered to have multiple side surfaces such that the gate structure is in contact with more than one side surface of the semiconductor pillar. As described below with respect to fabrication, the semiconductor pillar 100 can be formed from a substrate by, for example, an etching or epitaxial process, and thus can have the same semiconductor material as the substrate.

[0072] As an option, the material of the substrate can include, but is not limited to, silicon (e.g., single-crystalline silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable semiconductor material. For example, the substrate can be a silicon substrate. Accordingly, the semiconductor pillar 100 can include at least one of the above-mentioned materials.

[0073] The vertical transistor can include a gate structure 200 in contact with one or more side surfaces 130 of the semiconductor pillar 100. For example, in the case where the semiconductor pillar 100 includes four side surfaces 130, the isolation structure 300 is opposite the first side surface 131 in the y-direction, and the gate structure 200 surrounds the remaining side surfaces of the semiconductor pillar 100, the second side surface 132, the third side surface 133, and the fourth side surface 134. In other words, in the case where the semiconductor pillar includes four side surfaces, the isolation structure is opposite one side surface of the semiconductor pillar, and the gate structure surrounds the remaining side surfaces of the semiconductor pillar, the vertical transistor is formed as a three-sided gate-all-around structure. In some embodiments, the vertical transistor can further include a source 110 and a drain 120 formed at two ends of the semiconductor pillar 100 in the z-direction, respectively, which can be understood as doped regions of the semiconductor pillar 100, and can also be referred to as source and drain electrodes. It is noted that, in the following description, the source 110 is disposed below the semiconductor pillar 100, and the drain 120 is disposed above the semiconductor pillar 100, however, the source 110 can also be disposed above the semiconductor pillar 100, and the drain 120 can also be disposed below the semiconductor pillar 100, as desired, which is not limited in the present disclosure. Figure 1C In the following description, the source 110 is disposed below the semiconductor pillar 100, and the drain 120 is disposed above the semiconductor pillar 100, however, the source 110 can also be disposed above the semiconductor pillar 100, and the drain 120 can also be disposed below the semiconductor pillar 100, as desired, which is not limited in the present disclosure.

[0074] As an option, the source 110 and the drain 120 can be doped with any suitable P-type dopant, which can include any one or combination of boron (B) or gallium (Ga). As another option, the source 110 and the drain 120 can be doped with any suitable N-type dopant, which can include any one or combination of phosphorus (P), arsenic (As), and antimony (Sb). The source 110 and the drain 120 can be separated in the z-direction by the gate structure 200. In other words, the gate structure 200 is formed between the source 110 and the drain 120 in the z-direction. Thus, one or more channels can be formed in the semiconductor pillar 100 in the z-direction between the source 110 and the drain 120 when a gate voltage applied to the gate structure 200 is higher than a threshold voltage of the vertical transistor (which can be understood as the gate control capability of the gate structure).

[0075] In some embodiments, the vertical transistor is a multi-gate transistor. In other words, the gate structure 200 can be in contact with more than one side of the semiconductor pillar 100 to form more than one gate, such that more than one channel can be formed between the source 110 and the drain 120 in operation. For example, the gate structure 200 can be located on one of the two x-directionally opposite sidewalls of the semiconductor pillar 100, and on the remaining sidewalls of the semiconductor pillar 100 other than the two x-directionally opposite sidewalls on this basis.

[0076] Unlike planar transistors that only include a single planar gate, due to the 3D structure of the semiconductor pillar 100 and the gate structure 200 surrounding multiple sides of the semiconductor pillar 100, the multi-gate vertical transistor has a larger gate control area compared to the planar transistor to achieve better channel control with smaller subthreshold swing.

[0077] Reference Figure 1C In one embodiment of the present application, the gate structure 200 includes a gate dielectric layer 230 and a gate conductor layer 12, where the gate dielectric layer 230 is located between the side 130 of the semiconductor pillar 100 and the gate conductor layer 12. Optionally, the gate conductor layer 12 can further include a gate adhesive layer 210 and a gate metal layer 220.

[0078] For example, the gate structure 200 can include a gate dielectric layer 230 on one or more sides 130 of the semiconductor pillar 100. In addition, the gate structure 200 can further include a gate adhesive layer 210 on and in contact with the gate dielectric layer 230, and a gate metal layer 220 on and in contact with the gate adhesive layer 210. In other words, the gate adhesive layer 210 is located between the side 130 of the semiconductor pillar 100 and the gate metal layer 220.

[0079] The gate dielectric layer 230 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 230 can include silicon oxide. Further, the gate adhesion layer 210 can include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. In addition, the gate metal layer 220 can include any suitable conductive material, such as the gate metal layer 220 can include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicide, etc. The gate adhesion layer 210 is used to block diffusion of the metal material in the gate metal layer 220, and also to improve adhesion between the gate metal layer 220 and the gate dielectric layer 230.

[0080] In addition, with reference to Figure 3 In one embodiment of the present application, the gate structure 200 includes a plurality of first portions 200-1 and a plurality of second portions 200-2, wherein at least one of the plurality of first portions 200-1 surrounds the side surface 130 of the semiconductor pillar 100, and at least one of the plurality of second portions 200-2 extends in the x direction and is connected to adjacent first portions 200-1 in the x direction. Optionally, at least one of the plurality of second portions 200-2 is in contact with the isolation structure 300.

[0081] Further, at least one of the plurality of first portions 200-1 includes a plurality of sub-portions, such as a first sub-portion 200-11 and a second sub-portion 200-12, connected to each other, wherein the number of sub-portions is the same as the number of the remaining side surfaces of the semiconductor pillar 100; and the sub-portions are located on one of the remaining side surfaces of the semiconductor pillar 100. For example, Figure 3 The semiconductor pillar 100 shown includes a first side surface 131, a second side surface 132, a third side surface 133, and a fourth side surface 134. Among them, the isolation structure 300 is opposite to the first side surface 131 in the y direction, and the remaining side surfaces of the semiconductor pillar 100 are the second side surface 132, the third side surface 133, and the fourth side surface 134. At least one of the plurality of first portions 200-1 includes a plurality of sub-portions, such as a first sub-portion 200-11, a second sub-portion 200-12, and a third sub-portion 200-13, connected to each other. The first sub-portion 200-11, the second sub-portion 200-12, and the third sub-portion 200-13 are located on the second side surface 132, the third side surface 133, and the fourth side surface 134, respectively.

[0082] Optionally, in a plane perpendicular to the z direction, the projection of the semiconductor pillar 100 is located within the projection of the first portion 200-1 of the gate structure 200. In other words, in a plane perpendicular to the z direction, the semiconductor pillar 100 is enclosed within the area surrounded by the first portion 200-1 of the gate structure 200 and the isolation structure 300; or in a direction perpendicular to the z direction, such as the x direction or the y direction, the extension size of the semiconductor pillar 100 is smaller than the extension size of the first portion 200-1 of the gate structure 200.

[0083] In other words, in at least one embodiment of the present application, the gate structure 200 continuously extends in a plane perpendicular to the z-direction and surrounds the side surface 130 of the plurality of semiconductor pillars 100 that is not opposite to the isolation structure 300, so that the gate control capability of the gate structure can be improved by increasing the contact area between the gate structure and the semiconductor pillars, and on this basis, the switching speed of the gate structure and the reliability of the semiconductor device can be improved.

[0084] Further, referring to Figure 1C to 3 , the semiconductor device 1000 can further include a dielectric fill layer 400 that at least fills between adjacent gate structures 200, between adjacent isolation structures 300 and gate structures 200, between adjacent isolation structures 300 and semiconductor pillars 100, between adjacent gate structures 200 and semiconductor pillars 100, and between adjacent semiconductor pillars 100.

[0085] Optionally, the dielectric fill layer 400 can be a composite structure having multiple layers and include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric. As an option, the gate dielectric layer 230 and the dielectric fill layer 400 can be made of the same material. In this case, there is no clear boundary between the portions of the gate dielectric layer 230 and the dielectric fill layer 400 that are in contact with each other.

[0086] Further, referring to Figure 1D and Figure 3 , as an option, the isolation structure 300 can include an isolation dielectric layer 320 and an air gap 310-1 surrounded by the isolation dielectric layer, to reduce interference between adjacent gate structures 200 in the semiconductor device 1000; referring to Figure 1C and Figure 3 , as another option, the isolation structure 300 can include an isolation dielectric layer 320 and a conductive layer 310-2 surrounded by the isolation dielectric layer 310. By applying a reference voltage (e.g., ground voltage) to the conductive layer 310-2, interference between adjacent gate structures 200 in the semiconductor device 1000 can be reduced.

[0087] Optionally, the isolation dielectric layer 320 can be a composite structure having multiple layers and include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric. For example, the isolation dielectric layer 320 can include silicon oxide. Further, the conductive layer 310-2 can include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0088] To simplify the fabrication process and save production cost, the isolation dielectric layer 320 can be formed in the process of forming the gate dielectric layer 230, and the gate dielectric layer 230 and the isolation dielectric layer 320 are fabricated by using the same material. In other words, the gate dielectric layer 230 and the isolation dielectric layer 320 can include an insulating material layer fabricated by using the same material.

[0089] Similarly, to simplify the fabrication process and save production cost, the conductive layer 310-2 and the gate adhesive layer 210 can be fabricated by using the same material. In other words, the gate adhesive layer 210 and the conductive layer 310-2 can include a conductive material layer fabricated by using the same material.

[0090] Alternatively, the gate dielectric layer 230, the isolation dielectric layer 320, and the dielectric filling layer 400 can be fabricated by using the same material. In this case, there is no obvious boundary between the portions of the gate dielectric layer 230, the isolation dielectric layer 320, and the dielectric filling layer 400 that are in contact with each other.

[0091] In addition, as shown in FIGS. 1A and 1B, in some embodiments of the present application, the semiconductor device 1000 further includes a bit line structure 500 extending in the x direction and in contact with the end portions 1 of the plurality of semiconductor pillars 100, so that the plurality of semiconductor pillars 100 are connected to each other through the bit line structure 500. Figure 1C 1B Alternatively, the bit line structure 500 can be a composite structure, for example, including a first bit line layer (not shown) and a second bit line layer (not shown) stacked in the z direction in sequence. Alternatively, the first bit line layer can include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicide, etc. The second bit line layer can include, but is not limited to, silicon (for example, single-crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other appropriate semiconductor material. Alternatively, the second bit line layer is located above the first bit line layer and in contact with the end portions of the plurality of semiconductor pillars 100.

[0092] In addition, in some embodiments of the present application, the gate structure 200 includes an upper surface and a lower surface opposite in the z direction, and the isolation structure 300 includes a top surface and a bottom surface opposite in the z direction. Among them, the upper surface of the gate structure 200 and the top surface of the isolation structure 300 can be located at different heights in the z direction. For example, the upper surface of the gate structure 200 is higher than the top surface of the isolation structure 300 in the z direction. The lower surface of the gate structure 200 and the bottom surface of the isolation structure 300 can be located at different heights in the z direction. For example, the lower surface of the gate structure 200 is higher than the bottom surface of the isolation structure 300 in the z direction. In this way, the gate control capability of the gate structure can be enhanced, and the anti-interference capability of the gate structure 200 can be improved.

[0093] In addition, in some embodiments of the present application, the gate structure 200 includes an upper surface and a lower surface opposite in the z direction, and the isolation structure 300 includes a top surface and a bottom surface opposite in the z direction. Among them, the upper surface of the gate structure 200 and the top surface of the isolation structure 300 can be located at different heights in the z direction. For example, the upper surface of the gate structure 200 is higher than the top surface of the isolation structure 300 in the z direction. The lower surface of the gate structure 200 and the bottom surface of the isolation structure 300 can be located at different heights in the z direction. For example, the lower surface of the gate structure 200 is higher than the bottom surface of the isolation structure 300 in the z direction. In this way, the gate control capability of the gate structure can be enhanced, and the anti-interference capability of the gate structure 200 can be improved. ​

[0094] This application provides a method for manufacturing a semiconductor device through some embodiments. Figure 4 This is a flowchart of a method 2000 for fabricating a semiconductor device according to an exemplary embodiment of this application. Figures 5 to 20 These are schematic diagrams of a semiconductor device fabrication method 2000 according to one embodiment of this application.

[0095] like Figure 4 As shown, this application provides a method for fabricating a semiconductor device 2000, comprising:

[0096] S1, forming a semiconductor pillar, wherein the semiconductor pillar extends along a first direction and includes at least one side.

[0097] S2, forming an isolation sacrificial layer, wherein the isolation sacrificial layer extends along a second direction and faces a portion of the side of the semiconductor pillar in a third direction, and the first direction, the second direction and the third direction intersect each other.

[0098] S3, forming a gate structure around the remaining sides of the semiconductor pillars, wherein a second part of the gate structure contacts the isolation sacrificial layer, and the second part is the portion of the gate structure located between adjacent semiconductor pillars in the second direction.

[0099] S4, remove the isolation sacrificial layer and form an isolation structure in the first void formed after removing the isolation sacrificial layer.

[0100] The following will combine Figures 4 to 20 The specific processes in each step of the above preparation method 2000 are described in detail.

[0101] Step S1

[0102] Figure 5 This is a cross-sectional schematic diagram of the structure formed after forming the semiconductor layer 100' according to a preparation method of one embodiment of this application. Figure 6 yes Figure 5 The diagram shows a top view of the intermediate body taken along line A-A' or line B-B'. Figure 7 This is a cross-sectional schematic diagram of the structure formed after forming the semiconductor pillar 100 according to one embodiment of the preparation method of this application. Figure 8 yes Figure 7 The diagram shows a top view of the intermediate body taken along line A-A' or line B-B'.

[0103] like Figures 4 to 8As shown, step S1 forms semiconductor pillars, wherein the semiconductor pillars extend along a first direction and include at least one side, and may include, for example, forming a base structure, wherein the base structure includes semiconductor layers 100' and spacer layers 101 alternately distributed along a second direction (x direction); forming first trenches 01 and second trenches 02 extending along the x direction in the base structure, wherein a plurality of first trenches 01 and a plurality of second trenches 02 are alternately distributed along a third direction (y direction) to divide the semiconductor layers 100' into a plurality of semiconductor pillars 100.

[0104] Specifically, in one embodiment of this application, the semiconductor layer 100' can be formed from a substrate (not shown). The material used to prepare the substrate can be any suitable semiconductor material, such as single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide, etc., which are group III-V compounds. Alternatively, the substrate can be single-crystal silicon.

[0105] In one embodiment of this application, the substrate may be, for example, a composite substrate, for supporting a device structure thereon. Multiple layers made of different materials may be sequentially deposited to form the substrate using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0106] In one embodiment of this application, the substrate may include a substrate sacrificial layer. Optionally, the substrate sacrificial layer may include a single layer, multiple layers, or a suitable composite layer. For example, the substrate sacrificial layer may include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Alternatively, the substrate sacrificial layer may be a high-dielectric-constant dielectric layer. Another option is that the substrate sacrificial layer may include a dielectric layer, a sacrificial layer, and a dielectric layer sequentially disposed therefrom, wherein the dielectric layer may be a silicon nitride layer, and the sacrificial layer may be a silicon oxide layer. Yet another option is that the substrate sacrificial layer may include any one or more of a dielectric material, a semiconductor material, and a conductive material. For example, the sacrificial layer may be silicon nitride.

[0107] Furthermore, a portion of the substrate may also form a well region doped with an N-type or P-type dopant via ion implantation or diffusion processes. The dopant may include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb); or any one or a combination of boron (B), gallium (Ga), or indium (In). In some embodiments of this application, the well regions may be prepared using the same or different dopants. Furthermore, the doping concentration of the well regions may be the same or different; this application does not limit this.

[0108] After the substrate is formed, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; alternatively, other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, to remove a portion of the substrate to form a plurality of openings (not shown) spaced apart along the x-direction, wherein the remaining portion of the substrate is also spaced apart along the x-direction, forming a plurality of semiconductor layers 100'. Then, as... Figures 5 to 6 As shown, a spacer layer 101 can be formed by filling multiple openings using a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. The spacer layer 101 can be formed using any suitable dielectric material. Optionally, the spacer layer 101 may comprise at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric.

[0109] like Figures 5 to 8 As shown, after the basic structure is formed, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, etc., to form a first trench 01 and a second trench 02 extending in the basic structure along a first direction (z direction), respectively, wherein a plurality of first trenches 01 and a plurality of second trenches 02 are alternately distributed in the y direction to divide the semiconductor layer 100' into a plurality of semiconductor pillars 100.

[0110] Optionally, the multiple first trenches 01 may have the same extension length in the z-direction. Similarly, the multiple second trenches 02 may have the same extension length in the z-direction. As described above, gate structures and isolation structures will subsequently be formed in the first and second trenches, thus enabling the multiple gate structures and the multiple isolation structures to have the same extension length in the z-direction. This improves the structural consistency of the memory cells in the semiconductor device and mitigates the impact of structural differences on the performance of the semiconductor device.

[0111] Step S2

[0112] Figure 9 is a cross-sectional view of a structure formed after forming the initial first isolation dielectric layer 102 according to the method of manufacturing of one embodiment of the present application. Figure 10 is Figure 9 is a top view of the intermediate shown taken along line A-A' or line B-B'. Figure 11 is a cross-sectional view of a structure formed after forming the isolation sacrificial layer 103 according to the method of manufacturing of one embodiment of the present application. Figure 12 is Figure 11 is a top view of the intermediate shown taken along line A-A' or line B-B'.

[0113] As shown in Figures 7 to 12 , the step S2 of forming the isolation sacrificial layer, wherein the isolation sacrificial layer extends along a second direction and opposes the portion of the side surface of the semiconductor pillar in a third direction, the first direction, the second direction and the third direction intersecting each other can comprise, for example: forming the initial first isolation dielectric layer 102, wherein the initial first isolation dielectric layer 102 is located at least on the sidewall and the bottom surface of the second trench 02; and filling the isolation sacrificial layer 103 in the remaining space 02' of the second trench.

[0114] Optionally, as shown in Figures 7 to 10 , in one embodiment of the present application, the initial first isolation dielectric layer 102 can be formed by one or more thin film deposition processes, which can include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof or any combination thereof. Among them, the initial first isolation dielectric layer 102 can be located on the sidewall and the bottom surface of the second trench 02, the sidewall and the bottom surface of the first trench 0 and the top surface of the semiconductor pillar 100. The initial first isolation dielectric layer 102 can include any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride or high-k dielectric. For example, the initial first isolation dielectric layer 102 can include silicon oxide.

[0115] Optionally, the initial first isolation dielectric layer 102 can be made of the same material as the spacer layer 101, so as to be removed in the subsequent same step.

[0116] As shown in Figures 9 to 11 , after forming the initial first isolation dielectric layer 102, the isolation sacrificial layer 103 can be filled in the remaining space 02' of the second trench by one or more thin film deposition processes, which can include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof or any combination thereof.

[0117] Alternatively, the isolation sacrificial layer 103 may be formed of a material with a high deposition rate to facilitate rapid filling of the remaining space 02' of the second trench, and the isolation sacrificial layer 103 should be any material with high dry etching selectivity relative to the initial first isolation dielectric layer 102 to facilitate removal in subsequent steps. In one embodiment of this application, the isolation sacrificial layer 103 may include a silicon nitride layer, etc. Furthermore, during the filling process, multiple gaps may be formed in the isolation sacrificial layer 103 by controlling the trench filling process to alleviate structural stress.

[0118] Step S3

[0119] Figure 13 This is a cross-sectional schematic diagram of the structure formed after removing part of the initial first isolation medium layer 102 according to a preparation method of one embodiment of this application. Figure 14 yes Figure 13 The diagram shows a top view of the intermediate body taken along line A-A' or line B-B'. Figure 15 This is a cross-sectional schematic diagram of the structure formed after forming the gate structure 200 according to a preparation method according to one embodiment of this application. Figure 16 yes Figure 15 The diagram shown is a top view of the intermediate body taken along line A-A'. Figure 17 yes Figure 15 The diagram shown is a top view of the intermediate body taken along line B-B'.

[0120] like Figures 11 to 17 As shown, step S3 forms a gate structure surrounding the remaining sides of the semiconductor pillars, wherein a second portion of the gate structure contacts the isolation sacrificial layer. The second portion, which is the part of the gate structure located between adjacent semiconductor pillars in the second direction, may include, for example, removing the spacer layer 101 and a portion of the initial first isolation dielectric layer 102 to form a second gap 03 and expose a portion of the isolation sacrificial layer 103, wherein the removed portion of the initial first isolation dielectric layer 102 is located between adjacent semiconductor pillars 100 in the x-direction; and forming a gate structure 200 on the sides of the semiconductor pillars 100 exposed in the second gap 03 and on the exposed portion of the isolation sacrificial layer 103.

[0121] Specifically, refer to Figures 11 to 14 In one embodiment of this application, the spacer layer 101 and a portion of the initial first isolation dielectric layer 102 can be formed, for example, by a dry etching process or a combination of dry and wet etching processes; alternatively, other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, to remove the spacer layer 101 and a portion of the initial first isolation dielectric layer 102. After this operation, the remaining portion of the initial first isolation dielectric layer 102 is formed as a first isolation dielectric layer 102', which is located between the isolation sacrificial layer 103 and the semiconductor pillar 100.

[0122] As Figure 14 indicated by the dashed-elliptical box, the removed portion of the first isolation dielectric layer 102 is located between the semiconductor pillars 100 adjacent in the x-direction, and thus, after the above operation, the exposed portion of the isolation sacrificial layer 103 can be exposed.

[0123] Thereafter, as Figures 13 to 17 indicated, the gate structure 200 can be formed on the side of the semiconductor pillars 100 exposed in the second void 03 and the exposed portion of the isolation sacrificial layer 103 by one or more thin film deposition processes, which can include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, or any combination thereof.

[0124] Optionally, the gate structure 200 includes a gate dielectric layer 230 and a gate conductor layer 12, wherein the gate dielectric layer 230 is located between the side 130 of the semiconductor pillar 100 and the gate conductor layer 12. Optionally, the gate conductor layer 12 can further include a gate adhesion layer 210 and a gate metal layer 220.

[0125] The gate dielectric layer 230 is formed on the side 130 of the semiconductor pillar 100 exposed in the second void 03 and the surface of the exposed portion of the isolation sacrificial layer 103; and the gate adhesion layer 210 and the gate metal layer 220 are sequentially formed on the surface of the gate dielectric layer 230.

[0126] Optionally, the gate dielectric layer 230 can include any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric. For example, the gate dielectric layer 230 can include silicon oxide. In addition, the gate adhesion layer 210 can include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. In addition, the gate metal layer 220 can include any suitable conductive material, for example, the gate metal layer 220 can include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicide, etc. The gate adhesion layer 210 is used to block the diffusion of the metal material in the gate metal layer 220, and also to improve the adhesion between the gate metal layer 220 and the gate dielectric layer 230.

[0127] As Figure 15 and Figure 17 indicated, the gate structure 200 continuously extends in a plane perpendicular to the z-direction (e.g., the x-y plane) and surrounds the side 130 of the plurality of semiconductor pillars 100 opposite to the isolation sacrificial layer 103, for example, the second side 132, the third side 133, and the fourth side 134, so that the gate control capability of the gate structure can be improved by increasing the contact area of the gate structure with the semiconductor pillars, and on this basis, the switching speed of the gate structure and the reliability of the semiconductor device can be improved.

[0128] In addition, as shown, a plurality of gate structures adjacent to the same isolation sacrificial layer 103 are symmetrically distributed on opposite sides of the same isolation structure in the y direction. For example, the first gate structure 201, the second gate structure 202, the third gate structure 203, and the fourth gate structure 204 are symmetrically distributed on opposite sides of the isolation sacrificial layer 103 in the y direction. Figure 17

[0129] In addition, in an embodiment of the present application, the gate structure 200 includes a plurality of first portions 200-1 and a plurality of second portions 200-2, wherein at least one of the plurality of first portions 200-1 surrounds the side surface 130 of the semiconductor pillar 100, and at least one of the plurality of second portions 200-2 extends in the x direction, contacts the isolation sacrificial layer 103, and is connected to adjacent first portions 200-1 in the x direction.

[0130] In addition, at least one of the plurality of first portions 200-1 includes a plurality of sub-portions connected to each other, such as a first sub-portion 200-11 and a second sub-portion 200-12, wherein the number of sub-portions is the same as the number of remaining side surfaces of the semiconductor pillar 100; and the sub-portions are located on one of the remaining side surfaces of the semiconductor pillar 100. For example, Figure 17 The semiconductor pillar 100 shown includes a first side surface 131, a second side surface 132, a third side surface 133, and a fourth side surface 134. Among them, the isolation sacrificial layer 103 is opposite to the first side surface 131 in the y direction, and the remaining side surfaces of the semiconductor pillar 100 are the second side surface 132, the third side surface 133, and the fourth side surface 134. At least one of the plurality of first portions 200-1 includes a plurality of sub-portions connected to each other, such as a first sub-portion 200-11, a second sub-portion 200-12, and a third sub-portion 200-13. The first sub-portion 200-11, the second sub-portion 200-12, and the third sub-portion 200-13 are located on the second side surface 132, the third side surface 133, and the fourth side surface 134, respectively.

[0131] Optionally, in a plane perpendicular to the z direction, a projection of the semiconductor pillar 100 is located within a projection of the first portion 200-1 of the gate structure 200.

[0132] In addition, after forming the gate structure 200, a first dielectric fill layer 104 can also be formed by one or more thin film deposition processes, which can include but are not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, or any combination thereof. The first dielectric fill layer 104 at least fills between adjacent gate structures 200, between adjacent semiconductor pillars 100, and on the top surface of the isolation sacrificial layer 103.

[0133] ​Optionally, the first dielectric fill layer 104 can be made of the same material as the initial first isolation dielectric layer 102, in which case there is no distinct boundary between the portions of the first dielectric fill layer 104 and the initial first isolation dielectric layer 102 that are in contact with each other.

[0134] Step S4

[0135] Figure 18 is a cross-sectional view of a structure formed after forming the first void 04 according to the method of making of one embodiment of the present application. Figure 19 is Figure 18 is a top view schematic of the intermediate body taken along line A-A'. Figure 20 is Figure 18 is a top view schematic of the intermediate body taken along line B-B'.

[0136] As an option, as shown in Figures 1C to 3 , Figures 15 to 20 removing the isolation sacrificial layer 103 to form the first void 04; forming a first portion 321 of an isolation dielectric layer 320 in the first void 04, wherein the first portion 321 covers at least the initial first isolation dielectric layer 102; forming a conductive layer 310-2 in the remaining space of the first void 04; and covering a surface of the conductive layer with a second portion 322 of the isolation dielectric layer 320 to form the isolation structure 300, wherein the isolation structure 300 comprises the first portion 321 of the isolation dielectric layer 320, the second portion 322 of the isolation dielectric layer 320, and the conductive layer 310-2.

[0137] In particular, as shown in Figures 15 to 20 , in one embodiment of the present application, the removal of the isolation sacrificial layer 103 to form the first void 04 can be performed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other fabrication processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc., can also be performed.

[0138] Referring to Figures 1C to 3 , Figures 15 to 20After the first void 04 is formed, a first portion 321 of the isolation dielectric layer 320 can be formed on the surface of the initial first isolation dielectric layer 102 by one or more thin film deposition processes, which can include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The first portion 321 of the isolation dielectric layer 320 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric. For example, the first portion 321 can include silicon oxide.

[0139] After the first portion 321 of the isolation dielectric layer 320 is formed, a conductive layer 310-2 can be formed in the remaining space of the first void 04 by one or more thin film deposition processes, which can include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The conductive layer 310-2 can include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0140] After the conductive layer 310-2 is formed, a second portion 322 of the isolation dielectric layer 320 can be formed on the surface of the conductive layer by one or more thin film deposition processes, which can include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The second portion 322 of the isolation dielectric layer 320 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric. For example, the isolation dielectric layer 320 can include silicon oxide.

[0141] Optionally, the first portion 321 of the isolation dielectric layer 320 and the second portion 322 of the isolation dielectric layer 320 can be fabricated using the same material, in which case there is no distinct boundary between the portions of the first portion 321 of the isolation dielectric layer 320 and the second portion 322 of the isolation dielectric layer 320 that are in contact with each other.

[0142] As another alternative, as Figures 1D to 3 , Figures 15 to 20As shown, the step S4 of removing the isolation sacrificial layer 103 and forming the isolation structure 300 in the first void 04 formed after removing the isolation sacrificial layer 103 can comprise, for example: removing the isolation sacrificial layer 103 to form the first void 04; forming an isolation dielectric layer 320 covering at least the initial first isolation dielectric layer 102 in the first void 04 using a deposition process, wherein the isolation dielectric layer 320 comprises a first portion 321 and a second portion 322; forming an air gap 310-1 in the first void 04 by forming the first portion 321 and the second portion 322 of the isolation dielectric layer 320 using two different deposition rates. The isolation structure 300 comprises the first portion 321 and the second portion 322 of the isolation dielectric layer 320, and the air gap 310-1.

[0143] In particular, as shown, in one embodiment of the present application, the isolation structure 300 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other fabrication processes can also be performed to remove the isolation sacrificial layer 103 to form the first void 04, such as, for example, patterning processes including photolithography, cleaning, and chemical mechanical polishing. Figures 15 to 20

[0144] Referring to Figures 1D to 3 , Figures 15 to 20 After forming the first void 04, the isolation dielectric layer 320 can be formed by one or more thin film deposition processes, which can include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, or any combination thereof.

[0145] The isolation dielectric layer 320 comprises a first portion 321 and a second portion 322. Both the first portion 321 and the second portion 322 can comprise any suitable dielectric material, such as, for example, silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric. For example, the first portion 321 and the second portion 322 can comprise silicon oxide. Alternatively, the first portion 321 of the isolation dielectric layer 320 and the second portion 322 of the isolation dielectric layer 320 can be made of the same material, in which case there is no distinct boundary between the portions of the first portion 321 and the second portion 322 of the isolation dielectric layer 320 that are in contact with each other.

[0146] ​The deposition process used to form the first portion 321 and the second portion 322 of the isolation medium layer 320 can include two different deposition rates to form the air gap 310-1. As an option, the first deposition rate and the second deposition rate can be used simultaneously to form the first portion 321 and the second portion 322 of the isolation medium layer 320 on the surface of the initial first isolation medium layer 102, wherein the first portion 321 is on top of the second portion 322, and the first deposition rate used to form the first portion 321 is greater than the second deposition rate used to form the second portion 322, so that the surface of the first portion 321 formed on top by the faster first deposition rate can seal off a portion of the space accordingly, thereby affecting the second portion 322 formed on the bottom by the slower first deposition rate to form the air gap 310-1. In this option, the isolation structure 300 includes the first portion 321 and the second portion 322 of the isolation medium layer 320, and the air gap 310-1.

[0147] According to the semiconductor device preparation method provided by at least one embodiment of the present application, the semiconductor device can include a semiconductor pillar, an isolation structure, and a gate structure, wherein the semiconductor pillar includes at least one side surface, the isolation structure is opposite to a portion of the side surface of the semiconductor pillar in a direction intersecting with the extension direction of the semiconductor pillar and the extension direction of the isolation structure, and the gate structure surrounds the remaining side surface of the semiconductor pillar. In addition, a plurality of gate structures adjacent to the same isolation structure can be symmetrically distributed on the two sides opposite to the same isolation structure. In this way, the gate control capability of the gate structure can be improved by increasing the contact area between the gate structure and the semiconductor pillar, and on this basis, the isolation structure can reduce the interference between adjacent gate structures in the semiconductor device, improve the switching speed of the gate structure, and improve the reliability of the semiconductor device; the plurality of gate structures adjacent to the same isolation structure can be symmetrically distributed on the two sides opposite to the same isolation structure, which can effectively reduce the size of the semiconductor device and improve the influence of structural differences on the performance of the semiconductor device.

[0148] In addition, Figure 21 is a structural schematic diagram of a storage system 30000 according to an embodiment of the present application.

[0149] As Figure 21 indicated, at least one embodiment of another aspect of the present application further provides a storage system 30000. The storage system 30000 can include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 can be the same as the semiconductor device described in any of the above embodiments, and the present application will not be repeated here. The semiconductor device 20000 can be a two-dimensional semiconductor device or a three-dimensional semiconductor device, or even a part of a two-dimensional semiconductor device or a part of a three-dimensional semiconductor device, and the following will be described taking a three-dimensional semiconductor device as an example.

[0150] As an option, the three-dimensional semiconductor device can include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0151] The storage system 30000 can include the semiconductor device 20000 and a controller 32000. The semiconductor device 20000 can be the same as the semiconductor device described in any of the embodiments above, and the description thereof will not be repeated here. The controller 32000 can control the semiconductor device 20000 through a channel CH, and the semiconductor device 20000 can perform an operation based on the control of the controller 32000 in response to a request from a host 31000. The semiconductor device 20000 can receive a command CMD and an address ADDR from the controller 32000 through the channel CH and access a region selected from the memory cell array in response to the address. In other words, the semiconductor device 20000 can perform an internal operation corresponding to the command on the region selected by the address.

[0152] In some embodiments, the three-dimensional storage system can be implemented as a Universal Flash Storage (UFS) device, a Solid State Disk (SSD), a Multimedia Card in the form of RS-MMC and micro-SD, a Secure Digital Card in the form of SD, mini-SD and micro-SD, a storage device of the Personal Computer Memory Card International Association (PCMCIA) card type, a storage device of the Peripheral Component Interconnect (PCI) type, a storage device of the Express PCI (PCI-E) type, a Compact Flash (CF) card, a smart media card or a memory stick, etc. The storage system provided by the present application has the same beneficial effects as the semiconductor device provided by the present application due to the provision of the semiconductor device provided by the present application, and the description thereof will not be repeated here.

[0153] Although exemplary methods of making and structures of the semiconductor device are described herein, it is understood that one or more features can be omitted, substituted, or added from the structure of the semiconductor device. In addition, the materials of the example layers are merely exemplary.

[0154] The above description is merely exemplary of the application and the application of the principles thereof. It is understood that variations in the described embodiments can be made by those skilled in the art without departing from the scope of the application. For example, the described features can be combined in any combination, and / or equivalent arrangements can be substituted for the described ones.

Claims

1. A semiconductor device, characterized by, comprises at least one side face; an isolation structure extending along a second direction, wherein the isolation structure opposes a portion of the side face of the semiconductor pillar in a third direction, the first direction, the second direction and the third direction being perpendicular to each other; a gate structure continuously extending in a plane perpendicular to the first direction and surrounding a remaining side face of the semiconductor pillar, wherein the gate structure comprises a gate dielectric layer and a gate conductor layer, wherein a plurality of the gate structures adjacent to a same isolation structure are symmetrically distributed on both sides of the same isolation structure in the third direction.

2. The semiconductor device of claim 1, wherein the plurality of the gate structures adjacent to the same isolation structure are mirror symmetrically distributed on the both sides of the same isolation structure.

3. The semiconductor device of claim 1, wherein the isolation structure comprises an isolation dielectric layer and an air gap surrounded by the isolation dielectric layer.

4. The semiconductor device of claim 1, wherein the isolation structure comprises an isolation dielectric layer and a conductive layer surrounded by the isolation dielectric layer.

5. The semiconductor device of claim 4, wherein the gate dielectric layer is located between the side face of the semiconductor pillar and the gate conductor layer.

6. The semiconductor device of claim 5, wherein the gate conductor layer and the conductive layer comprise a conductive material layer of the same material.

7. The semiconductor device of claim 1, wherein the gate structure comprises a plurality of first portions and a plurality of second portions, wherein at least one of the plurality of first portions surrounds a side face of the semiconductor pillar, and at least one of the plurality of second portions extends along the second direction and connects adjacent first portions in the second direction.

8. The semiconductor device of claim 7, wherein at least one of the plurality of first portions comprises a plurality of sub-portions connected to each other, wherein a number of the sub-portions is the same as a number of the remaining side faces of the semiconductor pillar; and the sub-portions are located on one of the remaining side faces of the semiconductor pillar.

9. The semiconductor device of claim 7, wherein a projection of the semiconductor pillar in a plane perpendicular to the first direction is located within a projection of the first portion.

10. The semiconductor device of claim 1, wherein a cross-sectional shape of the semiconductor pillar in a plane perpendicular to the first direction comprises at least one of a rectangular shape, a trapezoidal shape, a circular shape and an elliptical shape.

11. The semiconductor device of claim 1, wherein the semiconductor pillar has a hexahedral shape and comprises four side faces, wherein the isolation structure opposes one side face of the semiconductor pillar in the third direction; and the gate structure surrounds the remaining three side faces of the semiconductor pillar. comprises forming a semiconductor pillar, wherein the semiconductor pillar extends along a first direction and comprises at least one side face; 12. A method of manufacturing a semiconductor device, characterized by ​ ​ forming an isolation sacrificial layer, wherein the isolation sacrificial layer extends along a second direction and is opposite to a portion of side surfaces of the semiconductor pillars in a third direction, the first direction, the second direction and the third direction intersecting with each other; forming a gate structure surrounding remaining side surfaces of the semiconductor pillars, wherein a second portion of the gate structure is in contact with the isolation sacrificial layer, the second portion being a portion of the gate structure between semiconductor pillars adjacent in the second direction; and removing the isolation sacrificial layer and forming an isolation structure in a first void formed after removing the isolation sacrificial layer.

13. The method of claim 12, wherein, forming the semiconductor pillars comprises: forming a base structure, wherein the base structure comprises semiconductor layers and spacer layers alternatingly distributed along the second direction; forming first trenches and second trenches extending along the second direction in the base structure, wherein the first trenches and the second trenches are alternatingly distributed along the third direction to divide the semiconductor layers into the semiconductor pillars.

14. The method of claim 13, wherein, forming the isolation sacrificial layer comprises: forming an initial first isolation medium layer, wherein the initial first isolation medium layer is at least on sidewalls and a bottom surface of the second trenches; and filling the isolation sacrificial layer in remaining spaces of the second trenches.

15. The method of claim 14, wherein, forming the gate structure surrounding remaining side surfaces of the semiconductor pillars comprises: removing the spacer layers and a portion of the initial first isolation medium layer to form a second void and expose a portion of the isolation sacrificial layer, wherein the removed portion of the initial first isolation medium layer is between semiconductor pillars adjacent in the second direction; forming the gate structure on side surfaces of the semiconductor pillars exposed in the second void and the portion of the isolation sacrificial layer exposed.

16. The method of claim 14, wherein, removing the isolation sacrificial layer and forming an isolation structure in a first void formed after removing the isolation sacrificial layer comprises: removing the isolation sacrificial layer to form the first void; forming a first portion of an isolation medium layer in the first void, wherein the first portion covers at least the initial first isolation medium layer; forming a conductive layer in a remaining space of the first void; and covering a second portion of the isolation medium layer on a surface of the conductive layer to form the isolation structure, wherein the isolation structure comprises the first portion, the second portion and the conductive layer.

17. The method of claim 14, wherein, removing the isolation sacrificial layer and forming an isolation structure in a first void formed after removing the isolation sacrificial layer comprises: removing the isolation sacrificial layer to form the first void; and forming an isolation medium layer covering at least the initial first isolation medium layer in the first void by a deposition process, wherein the isolation medium layer comprises a first portion and a second portion; forming the first portion and the second portion by using two different sizes of deposition rates to form an air gap in the first void; and the isolation structure comprises the first portion, the second portion and the air gap.

18. A memory system, comprising: comprises: A controller coupled to the semiconductor device and configured to control the semiconductor device to store data.

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