Stacked semiconductor device and manufacturing method thereof

Abstract

The invention relates to a stacked semiconductor device and a manufacturing method thereof. The stacked semiconductor device includes a first semiconductor structure having a first integrated circuit layer and a first bonding layer and a second semiconductor structure having a second integrated circuit layer and a second bonding layer. The first integrated circuit layer has a first heat resistance on one surface of the first integrated circuit layer. A first bonding layer is formed over the first integrated circuit layer. The second integrated circuit layer has a second heat resistance on one surface of the second integrated circuit layer, the second heat resistance being lower than the first heat resistance. A second bonding layer is formed on the second integrated circuit layer and hybrid bonded to the first bonding layer. The third heat resistance is lower than the first heat resistance. The third integrated circuit layer is disposed to face at least one of the first integrated circuit layer and the second integrated circuit layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0142090 filed in the Korean Intellectual Property Office on October 23, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments generally relate to a semiconductor integrated circuit device, and more particularly, to a stacked semiconductor device and a method of manufacturing the stacked semiconductor device. Background Art

[0004] In order to meet customers' requirements for good performance and low cost, it is necessary to improve the integration of semiconductor devices.

[0005] The integration level of a semiconductor device can be an important factor in determining the price of an electronic component. Therefore, the integration level of a two-dimensional or planar semiconductor device can be determined based on the occupied area of ​​a unit memory cell.

[0006] In particular, there may be a limit to the increase in integration density in two-dimensional semiconductor devices because fine patterns that increase integration density may require expensive exposure equipment or an exposure device with high resolution.

[0007] Recently, in order to ensure higher integration of semiconductor devices, particularly semiconductor memory devices, a technology of stacking memory cells in a three-dimensional direction or stacking a memory cell array and a peripheral circuit in a vertical direction may be proposed.

[0008] A stacked semiconductor device may include layers having elements formed through various processes, so that maintenance of electrical characteristics between the elements may determine performance of the stacked semiconductor device. Summary of the invention

[0009] Example embodiments provide a stacked semiconductor device capable of ensuring electrical reliability.

[0010] Example embodiments also provide a method of manufacturing the above-mentioned stacked semiconductor device.

[0011] According to example embodiments, a stacked semiconductor device may be provided. The stacked semiconductor device may include a first semiconductor structure and a second semiconductor structure that are hybrid-bonded to each other. The first semiconductor structure may include a first integrated circuit layer and a first bonding layer. The first integrated circuit layer may have a first heat resistance on one surface of the first integrated circuit layer. The first bonding layer may be formed on the first integrated circuit layer. The second semiconductor structure may include a second integrated circuit layer and a second bonding layer. The second integrated circuit layer may have a second heat resistance on one surface of the second integrated circuit layer, and the second heat resistance may be lower than the first heat resistance. The second bonding layer may be formed on the second integrated circuit layer. The second bonding layer may be hybrid-bonded to the first bonding layer. The third heat resistance may be lower than the first heat resistance. The third integrated circuit layer is arranged to face at least one of the first integrated circuit layer and the second integrated circuit layer.

[0012] In example embodiments, the third heat resistance may be substantially equal to or lower than the second heat resistance.

[0013] In example embodiments, the first semiconductor structure may further include at least one through electrode formed through the first integrated circuit layer and the third integrated circuit layer.

[0014] In example embodiments, the first integrated circuit layer may include at least one capacitor. The capacitor may include a storage electrode, a dielectric layer, and a plate electrode stacked sequentially.

[0015] In example embodiments, the second integrated circuit layer may include a plurality of transistors and a plurality of interconnections connected between the transistors.

[0016] In example embodiments, the third integrated circuit layer may include at least one analog element that depends on temperature.

[0017] In example embodiments, the first bonding layer may include a plurality of first bonding pads electrically connected to the first integrated circuit layer. The second bonding layer may include a plurality of second bonding pads electrically connected to the second integrated circuit layer. The second bonding pads may be hybrid-bonded to the first bonding pads.

[0018] In example embodiments, the second heat resistance may be a thermal expansion temperature of the first bonding pad and the second bonding pad.

[0019] According to example embodiments, a stacked semiconductor device may be provided. The stacked semiconductor device may include a first semiconductor structure and a second semiconductor structure. The first semiconductor structure may include a first surface and a second surface opposite to the first surface. The first semiconductor structure may include at least one storage component integrated on the first surface and a logic circuit layer integrated on the second surface. The second semiconductor structure may include a third surface and a fourth surface opposite to the third surface. The second semiconductor structure may include a control circuit layer integrated on the third surface to control the storage component. The first semiconductor structure and the second semiconductor structure may be hybrid-bonded to each other so that the storage component and the control circuit layer face each other.

[0020] According to example embodiments, a method for manufacturing a stacked semiconductor device may be provided. In the method for manufacturing a stacked semiconductor device, a first integrated circuit layer may be formed on a first surface of a first semiconductor substrate at a first temperature. A first bonding layer may be formed on the first integrated circuit layer. The first bonding layer may include a plurality of first bonding pads electrically connected to the first integrated circuit layer and a first bonding insulating layer configured to electrically isolate the first bonding pads from each other. A second integrated circuit layer may be formed on a second semiconductor substrate. A second bonding layer may be formed on the second integrated circuit layer. The second bonding layer may include a plurality of second bonding pads electrically connected to the second integrated circuit layer and a second bonding insulating layer configured to electrically isolate the second bonding pads from each other. The first bonding layer and the second bonding layer may be mixed and bonded to each other at a second temperature lower than the first temperature. A third integrated circuit layer may be formed on a second surface of the first semiconductor substrate that may not be bonded to the second semiconductor substrate at a third temperature lower than the first temperature.

[0021] According to example embodiments, a memory layer formed by a high temperature process and a control circuit layer formed by a low temperature process may be formed at different substrates to prevent characteristics of the control circuit layer from being changed due to high temperature.

[0022] In addition, after bonding the first semiconductor substrate having the memory layer to the second semiconductor substrate having the control circuit layer, a logic circuit layer formed at a low temperature can be additionally formed on the back side of the first semiconductor substrate. Therefore, the heat burden applied to the control circuit layer and the logic circuit layer can be reduced to improve the characteristics of the stacked semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other aspects, features and advantages of the subject matter of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0024] Figure 1 is a cross-sectional view showing a stacked semiconductor device according to an embodiment of the present disclosure;

[0025] Figures 2 to 6is a cross-sectional view illustrating a method of manufacturing a stacked semiconductor device according to an embodiment of the present disclosure; and

[0026] Figure 7 is a flowchart illustrating a method of manufacturing a stacked semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] Various embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams of various embodiments (and intermediate structures). Therefore, due to, for example, manufacturing techniques and / or tolerances, variations in the illustrated configurations and shapes are to be expected. Therefore, the described embodiments should not be interpreted as limited to the specific configurations and shapes shown herein, but may include deviations in configurations and shapes that do not depart from the spirit and scope of the present disclosure as defined in the appended claims.

[0028] The present disclosure is described herein with reference to the cross-sectional views and / or plan views of the idealized embodiments of the present disclosure. However, the embodiments of the present disclosure should not be construed as limiting the concept of the present invention. Although some embodiments of the present disclosure will be shown and described, it will be understood by those of ordinary skill in the art that these embodiments may be changed without departing from the principles and spirit of the present disclosure.

[0029] As used herein, the term "configured" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device to facilitate operation of the one or more of the structure and device in a predetermined manner.

[0030] As used herein, the terms "vertical," "longitudinal," "horizontal," and "transverse" refer to the principal planes of a structure and are not necessarily defined by the Earth's gravitational field. A "horizontal" or "transverse" direction is a direction substantially parallel to the principal planes of a structure, while a "vertical" or "longitudinal" direction is a direction substantially perpendicular to the principal planes of a structure. The principal planes of a structure are defined by surfaces of the structure having a relatively large area compared to other surfaces of the structure. With reference to the accompanying drawings, a "horizontal" or "transverse" direction may be perpendicular to the indicated "Z" axis, and may be parallel to the indicated "X" axis and / or parallel to the indicated "Y" axis; a "vertical" or "longitudinal" direction may be parallel to the indicated "Z" axis, may be perpendicular to the indicated "X" axis, and may be perpendicular to the indicated "Y" axis.

[0031] As used herein, features (e.g., regions, structures, devices) described as being "adjacent" to each other mean and include features of the disclosed identity (or identities) that are closest to each other (e.g., closest). Additional features (e.g., additional regions, additional structures, additional devices) that do not match the identity (or identities) disclosed by the "adjacent" feature may be arranged between the "adjacent" features. In other words, the "adjacent" features may be positioned directly adjacent to each other so that no other features intervene between the "adjacent" features; or, the "adjacent" features may be positioned indirectly adjacent to each other so that at least one feature of an identity different from the identity associated with at least one "adjacent" feature is positioned between the "adjacent" features. Thus, features described as being "vertically adjacent" to each other mean and include features of the disclosed identity (or identities) that are closest to each other in the vertical direction (e.g., closest in the vertical direction). In addition, features described as being "horizontally adjacent" to each other mean and include features of the disclosed identity (or identities) that are closest to each other in the horizontal direction (e.g., closest in the horizontal direction).

[0032] As used herein, for ease of description, spatially related terms (e.g., "below," "below," "bottom," "above," "upper," "top," "front," "back," "left," "right," etc.) may be used to describe the relationship between an element or feature and another element or feature as shown. Unless otherwise indicated, spatially relative terms are intended to cover different orientations of materials in addition to the orientations depicted in the figures. For example, if the material in the figure is inverted, the element described as "below" or "below" or "under" or "bottom" of other elements or features will be oriented to be "above" or "on top of" other elements or features. Therefore, depending on the context in which the term "below" is used, the term can cover both the orientation of the top and the bottom, which will be apparent to one of ordinary skill in the art. The material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped) and the spatially relative descriptors used herein are interpreted accordingly.

[0033] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0034] As used herein, the phrases "coupled to" and "connected to" refer to structures that are operatively connected to one another, such as by a direct ohmic connection or by an indirect electrical connection (eg, through another structure).

[0035] As used herein, the term "substantially" in reference to a given parameter, property, or condition means and includes the degree to which a given parameter, property, or condition is satisfied with a certain degree of difference (e.g., within an acceptable tolerance range) as would be understood by one of ordinary skill in the art. For example, depending on the particular parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be at least 90.0% satisfied, at least 95.0% satisfied, at least 99.0% satisfied, at least 99.9% satisfied, or even 100.0% satisfied.

[0036] Figure 1 is a cross-sectional view showing a stacked semiconductor device according to an embodiment of the present disclosure.

[0037] Reference Figure 1 , the stacked semiconductor device 10 may include a first semiconductor structure 100 and a second semiconductor structure 200 hybrid-bonded to each other in a three-dimensional shape.

[0038] At least one of the first semiconductor structure 100 and the second semiconductor structure 200 may include a semiconductor wafer or a semiconductor chip. In the embodiment of the present disclosure, both the first semiconductor structure 100 and the second semiconductor structure 200 may include a semiconductor wafer. Alternatively, both the first semiconductor structure 100 and the second semiconductor structure 200 may include a semiconductor chip. In addition, the stacked semiconductor device 10 of the embodiment of the present disclosure may be part of a semiconductor package.

[0039] The first semiconductor structure 100 may include a first semiconductor substrate SUB1. The first semiconductor substrate SUB1 may have a first surface S1 and a second surface S2a opposite to the first surface S1. The first semiconductor substrate SUB1 may include a silicon substrate, a single crystal silicon substrate, an epitaxial semiconductor substrate, a silicon germanium substrate, etc. In addition, the first semiconductor substrate SUB1 may include, for example, an intrinsic semiconductor material, conductive impurities, etc.

[0040] In an embodiment of the present disclosure, the first surface S1 may be a front surface, a top surface, an upper surface, or a surface of the first semiconductor substrate SUB1. The second surface S2a may be a rear surface, a bottom surface, a lower surface, or another surface of the first semiconductor substrate SUB1. Alternatively, the first surface S1 may be a rear surface, a bottom surface, a lower surface, or another surface of the first semiconductor substrate SUB1. The second surface S2a may be a front surface, a top surface, an upper surface, or a surface of the first semiconductor substrate SUB1.

[0041] The first semiconductor structure 100 may include a first integrated circuit layer CL1 formed on a first surface S1 .

[0042] The first integrated circuit layer CL1 may include a memory layer ML. The memory layer ML may include a plurality of memory components formed at a first temperature (e.g., a high temperature of about 400° C. to about 700° C.). For example, the memory component may include a plurality of capacitors. The capacitors may be arranged in a memory cell array. The capacitors may be electrically isolated from each other. In addition, the memory component may be integrated on the first surface S1 of the first semiconductor substrate SUB1 through a front-end-of-line process (FEOL). FEOL may include a process for forming an element or component on a semiconductor substrate through a deposition process and a patterning process.

[0043] The first semiconductor structure 100 may include a first bonding layer BL1. The first bonding layer BL1 may be formed on a surface S11 of a storage layer ML corresponding to the first integrated circuit layer CL1. In an embodiment of the present disclosure, the first bonding layer BL1 may include a plurality of first bonding pads BP1 and a first bonding insulating layer Bl1. The first bonding pads BP1 may be electrically connected to a storage component of the storage layer ML. For example, a conductive component in the storage layer ML may be connected to the first bonding pads BP1 through at least one interconnect. The first bonding insulating layer Bl1 may be located between the first bonding pads BP1 to electrically isolate the first bonding pads BP1 from each other.

[0044] The second semiconductor structure 200 may include a second semiconductor substrate SUB2. The second semiconductor substrate SUB2 may have a third surface S3 and a fourth surface S4 opposite to the third surface S3. For example, the second semiconductor substrate SUB2 may include a single crystal silicon substrate, an epitaxial semiconductor substrate, a silicon germanium substrate, a polycrystalline silicon layer, a support layer including a semiconductor material, a silicon on insulator (SOI) substrate, etc., but is not limited thereto.

[0045] In an embodiment of the present disclosure, the third surface S3 may be a front surface, a top surface, an upper surface, or a surface of the second semiconductor substrate SUB2. The fourth surface S4 may be a rear surface, a bottom surface, a lower surface, or another surface of the second semiconductor substrate SUB2. Alternatively, the third surface S3 may be a rear surface, a bottom surface, a lower surface, or another side surface of the second semiconductor substrate SUB2. The fourth surface S4 may be a front surface, a top surface, an upper surface, or a surface of the second semiconductor substrate SUB2.

[0046] In an embodiment of the present disclosure, the second semiconductor structure 200 may include a second integrated circuit layer CL2 formed on the third surface S3. The second integrated circuit layer CL2 may include a plurality of transistors and a plurality of interconnections. The transistors and interconnections of the second integrated circuit layer CL2 may form a variety of control circuits. The control circuit may selectively input data into / output data from the storage component of the first semiconductor structure 100.

[0047] For example, the second integrated circuit layer CL2 may include a plurality of access transistors AA. The access transistors AA may be connected to a storage component, such as a capacitor, of the first semiconductor structure 100. The access transistors AA may be arranged in an array with the capacitors to form a stacked memory cell array.

[0048] In addition, the second integrated circuit layer CL2 may include a sense amplifier S / A configured to sense data in the storage component. The second integrated circuit layer CL2 may also include: a read / write circuit R / W configured to read data from the storage component or write data to the storage component; and a voltage generating circuit VG configured to generate a read voltage, a write voltage, and an operating voltage. The second integrated circuit layer CL2 may include a refresh circuit REF, which is configured to prevent leakage current of the storage component (i.e., the capacitor). Although not shown in the drawings, the second integrated circuit layer CL2 may include a plurality of word lines and a plurality of bit lines. The second integrated circuit layer CL2 may include a word line decoder configured to select any one of the plurality of word lines and a bit line decoder configured to select any one of the plurality of bit lines.

[0049] The transistors in the second integrated circuit layer CL2 may be formed by FEOL, but are not limited thereto.

[0050] The second semiconductor structure 200 may include a second bonding layer BL2. The second bonding layer BL2 may be bonded to the first bonding layer BL1 of the first semiconductor structure 100. The second bonding layer BL2 may be formed on a surface S31 of the second integrated circuit layer CL2. In an embodiment of the present disclosure, the second bonding layer BL2 may include a plurality of second bonding pads BP2 and a second bonding insulating layer Bl2.

[0051] The second bonding pads BP2 may be electrically connected to the conductive members of the second integrated circuit layer CL2. A second bonding insulating layer Bl2 may be located between the second bonding pads BP2 to electrically isolate the second bonding pads BP2 from each other.

[0052] The second bonding pad BP2 may be hybrid bonded to the first bonding pad BP1. The second bonding insulating layer Bl2 may be hybrid bonded to the first bonding insulating layer Bl1. In an embodiment of the present disclosure, hybrid bonding may be referred to as fusion bonding or direct bonding. For example, the first bonding insulating layer Bl1 and the second bonding insulating layer Bl2 may be bonded to each other through a compression process. The first bonding pad BP1 and the second bonding pad BP2 may be bonded to each other through thermal expansion in an annealing process. The annealing process may be performed at a second temperature lower than the first temperature. For example, the second temperature may be about 100°C to about 300°C. The second temperature may correspond to a hybrid bonding temperature.

[0053] The performance and electrical characteristics / properties of transistors and interconnects in the second integrated circuit layer CL2 may be guaranteed until the second temperature. Guarantee of performance or maintenance of electrical characteristics or properties may mean that the threshold voltage, output current, wiring resistance, operating speed, etc. of the MOS transistor may be maintained within an error range. The second temperature may be the heat resistance of the second integrated circuit layer CL2.

[0054] The first semiconductor structure 100 may further include a third integrated circuit layer CL3 on the second surface S2 a that is not bonded to the second semiconductor structure 200 .

[0055] The third integrated circuit layer CL3 may include a plurality of conductive patterns. The conductive patterns may include logic circuits. For example, the logic circuits may include an arithmetic logic calculation circuit LC1 for storing data in a component, a data pipeline operation circuit LC2, an interface circuit LC3 for receiving and processing external signals, and an analog element LC4.

[0056] The third integrated circuit layer CL3 may include temperature-dependent elements or components. For example, the performance or characteristics of the third integrated circuit layer CL3 may be guaranteed to be a third temperature lower than the first temperature. The third temperature may be substantially equal to or lower than the second temperature. For example, the third temperature may be room temperature to about 250°C.

[0057] In an embodiment of the present disclosure, although not shown in the drawings, the third integrated circuit layer CL3 may be formed on the fourth surface S4 of the second semiconductor substrate SUB2. The third integrated circuit layer CL3 may be connected to the second integrated circuit layer CL2 via a penetration electrode.

[0058] In an embodiment of the present disclosure, the first semiconductor structure 100 may include at least one through-electrode TSV formed through the first semiconductor substrate SUB1. The through-electrode TSV may electrically connect between the memory components of the memory layer ML and the conductive patterns of the third integrated circuit layer CL3.

[0059] According to an embodiment of the present disclosure, after the integrated circuit layers CL1, CL2, CL3 having different heat resistances are divided from each other, the integrated circuit layers CL1, CL2, CL3 may be formed sequentially in an order from high heat resistance to low heat resistance to ensure electrical reliability of the stacked semiconductor device 10.

[0060] Figures 2 to 6 is a cross-sectional view showing a method of manufacturing a stacked semiconductor device according to an embodiment of the present disclosure, Figure 7 is a flowchart illustrating a method of manufacturing a stacked semiconductor device according to an embodiment of the present disclosure.

[0061] Reference Figure 2 and Figure 7In step ST1, a memory layer ML corresponding to the first integrated circuit layer may be formed on a first surface S1 of a first semiconductor substrate 110. For example, the first semiconductor substrate 110 may include a silicon substrate, a single crystal silicon substrate, an epitaxial semiconductor substrate, a silicon germanium substrate, or the like.

[0062] The first surface S1 of the first semiconductor substrate 110 may be etched to form trenches t. The trenches t may be arranged according to a uniform rule. The uniform rule may correspond to the arrangement of the memory cell array.

[0063] The sidewall protection layer 115 may be formed on the inner wall of the trench t. The sidewall protection layer 115 may include an insulating material.

[0064] A conductive layer having a conformal thickness may be formed on the first surface S1 of the first semiconductor substrate 110. The conductive layer may be planarized to form a storage electrode 120 in the trench t. In an embodiment of the present disclosure, the conductive layer may include iridium (Ir), ruthenium (Ru), platinum (Pt), or a new metal having a work function. In addition, the conductive layer may include a metal nitride layer, such as a titanium nitride layer. The storage electrode 120 and the first semiconductor substrate 110 may be electrically isolated from each other by a sidewall protection layer 115.

[0065] The dielectric layer 130 may be formed on the storage electrode 120. The dielectric layer 130 may include a metal oxide layer having a high dielectric constant, such as HfO 2 , doped HfO 2 , HfZrO, doped HfZrO, Ta 2 O 5 、ZrO 2 、Al 2 O 5 、TiO 2 To ensure high capacitance, a high crystallization process may be performed on the dielectric layer 130 at a temperature of about 400° C. to about 700° C. Since the first semiconductor substrate 110 may not include other transistors except the storage electrode 120 , other electrical characteristics are not changed by the high crystallization process.

[0066] A conductive layer may be formed on the dielectric layer 130. The conductive layer may include a material substantially the same as or different from that of the storage electrode 120. The trench t may be completely filled with the conductive layer. The conductive layer and the dielectric layer 130 may be patterned to place the conductive layer on the trench t, ​​thereby forming the plate electrode 140. Therefore, a capacitor CAP including the storage electrode 120, the dielectric layer 130, and the plate electrode 140 may be formed in the trench t.

[0067] The storage electrode 120 , the dielectric layer 130 , and the plate electrode 140 may be formed through various processes to provide the capacitor CAP having various structures.

[0068] Reference Figure 3 and Figure 7 In step ST2 , a first bonding layer 150 may be formed on the memory layer ML of the first semiconductor substrate 110 .

[0069] In an embodiment of the present disclosure, a first bonding insulating layer 152 may be formed on the first semiconductor substrate 110 together with the memory layer ML. The first bonding insulating layer 152 may include at least one insulating layer. For example, the first bonding insulating layer 152 may include a silicon oxide layer. The first bonding insulating layer 152 may be etched to form a pad region. The pad region may be filled with a conductive material to form a first bonding pad 155. The conductive material may include, for example, copper, but is not limited thereto.

[0070] In an embodiment of the present disclosure, a portion of the first bonding pad 155 may be electrically connected to the plate electrode 140 of the capacitor CAP. In addition, although not shown in the drawings, another portion of the first bonding pad 155 may be electrically connected to the storage electrode 120 of the capacitor CAP.

[0071] In an embodiment of the present disclosure, a plurality of penetration electrodes 160 may be formed through the first bonding layer 150 and the first semiconductor substrate 110. For example, the penetration electrodes 160 may extend from the surface of the first bonding layer 150 to a depth set in the first semiconductor substrate 110. The set depth may be less than a length between the surface of the first bonding layer 150 and the second surface S2 of the first semiconductor substrate 110.

[0072] In an embodiment of the present disclosure, when forming the penetration electrode 160, the first bonding layer 150 and the first semiconductor substrate 110 may be etched to a set depth to form a deep trench. An insulating layer may be formed on the sidewalls of the deep trench. The deep trench may be filled with a conductive material. The first semiconductor substrate 110 and the penetration electrode 160 may be electrically isolated from each other by the insulating layer on the sidewalls of the deep trench.

[0073] Alternatively, the through electrode 160 may be formed before the capacitor CAP is formed. The through electrode 160 formed before the capacitor CAP is formed may be directly connected to the storage electrode 120 .

[0074] Reference Figure 4 and Figure 7 , a control circuit layer 250 and a second bonding layer 260 , which may correspond to the second integrated circuit layer CL2 , may be formed on the second semiconductor substrate 210 .

[0075] The second semiconductor substrate 210 may have a third surface S3 and a fourth surface S4 opposite to the third surface S3. The second semiconductor substrate 210 may include a single crystal silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a polycrystalline silicon layer, a support plate including a semiconductor material, an SOI substrate, etc. The second semiconductor substrate 210 may be substantially the same as or different from the first semiconductor substrate 110. In addition, the third surface S3 of the second semiconductor substrate 210 may be an upper surface of the second semiconductor substrate 210, but is not limited thereto. The fourth surface S4 may be a lower surface of the second semiconductor substrate 210, but is not limited thereto.

[0076] The control circuit layer 250 may be integrated on the third surface S3 of the second semiconductor substrate 210. The control circuit layer 250 may include a transistor 220 formed by FEOL. The control circuit layer 250 may include an interconnection 230 electrically connected to the transistor 220.

[0077] In an embodiment of the present disclosure, the transistor 220 may have at least one of a horizontal channel structure and a vertical channel structure. The horizontal channel may be parallel to the surface of the second semiconductor substrate 210. The vertical channel may extend in a direction substantially perpendicular to the surface of the second semiconductor substrate 210.

[0078] A portion of transistor 220 may be operated as an access transistor of a memory cell array. For example, the access transistor may be integrated at a location corresponding to a memory cell region of the memory cell array. Another portion of transistor 220 may form a sense amplifier electrically connected to the access transistor. Another portion of transistor 220 may form a memory peripheral circuit directly and indirectly connected to the access transistor. The memory peripheral circuit may include a read / write circuit, a refresh circuit, and a voltage generation circuit.

[0079] Interconnect 230 may be directly and indirectly connected to transistor 220. Interconnect 230 may include a plurality of vertical connections 232 and a plurality of horizontal connections 235. Vertical connections 232 may correspond to contact plugs or via plugs. Horizontal connections 235 may include conductive wiring.

[0080] A portion of the interconnect 230 may operate as an intermediate connection medium between the capacitor CAP and the access transistor connected in the first semiconductor substrate 110. A portion of the interconnect 230 may be connected between the transistors 220 to form a sense amplifier. In addition, a portion of the interconnect 230 may be connected between the access transistor and the sense amplifier. A portion of the interconnect 230 may be connected between the transistors 220 to form a memory peripheral circuit, such as a read / write circuit, a voltage generating circuit, a refresh circuit, a decoding circuit, etc. A portion of the interconnect 230 may be connected between the memory peripheral circuit and the access transistor, or between the memory peripheral circuit and an external terminal.

[0081] The control circuit layer 250 may further include at least one insulating interlayer 240 interposed between the transistor 220 and the interconnect 230 and between the interconnects 230. For example, the vertical connection 232 of the interconnect 230 may be formed through at least one layer of the insulating interlayer 240. The horizontal connection 235 may be placed on the lower surface or the upper surface of the insulating interlayer 240.

[0082] In an embodiment of the present disclosure, transistor 220 and interconnect 230 may be formed by various processes.

[0083] The second bonding insulating layer 262 may be formed on the second semiconductor substrate 210 together with the control circuit layer 250. The second bonding insulating layer 262 may include at least one insulating layer. The second bonding insulating layer 262 may include a silicon oxide layer. The second bonding insulating layer 262 may be etched to form a pad region. The pad region may be filled with a conductive material to form a second bonding pad 265. The second bonding pad 265 may be electrically connected to the interconnect 230.

[0084] Reference Figure 5 and Figure 7 In step ST4 , the first bonding layer 150 of the first semiconductor substrate 110 may be hybrid-bonded to the second bonding layer 260 of the second semiconductor substrate 210 .

[0085] For example, the first semiconductor substrate 110 may be turned over to face the first bonding layer 150 and the second bonding layer 260. The first bonding pad 155 of the first bonding layer 150 and the second bonding pad 265 of the second bonding layer 260 that may receive the same signal may be aligned with each other to perform a hybrid bonding process.

[0086] In an embodiment of the present disclosure, the first bonding insulating layer 152 and the second bonding insulating layer 262 may be pre-bonded to each other by a compression process. An annealing process may be performed so that the first bonding pad 155 and the second bonding pad 265 may be thermally expanded to thermally and chemically bond the first bonding pad 155 and the second bonding pad 265 to each other. The annealing process may be performed at a temperature of about 100° C. to about 300° C. The heat resistance of the transistor 220 and the conductive pattern in the control circuit layer 250 may be the temperature of the annealing process.

[0087] Reference Figure 6 and Figure 7 In an embodiment of the present disclosure, the second surface S2 of the first semiconductor substrate 110 that may not be bonded to the second semiconductor substrate 210 may be ground until the through electrode 160 may be exposed. Reference numeral S2a may correspond to the second surface of the thin first semiconductor substrate 110.

[0088] The logic circuit layer 170 may be formed on the second surface S2a. The logic circuit layer 170 may include a plurality of conductive patterns 172 and a plurality of insulating interlayers 175. The conductive patterns 172 may be located on the same plane. Alternatively, the conductive patterns 172 may be stacked to be located on different planes. The conductive patterns 172 on the same plane and on different planes may be electrically isolated from each other by the insulating interlayers 175.

[0089] A portion of the conductive pattern 172 may form an arithmetic logic circuit for calculating data in the capacitor CAP. A portion of the conductive pattern 172 may form a data pipeline operation circuit and an interface circuit. A portion of the conductive pattern 172 may form analog elements such as resistors and capacitors CAP. The logic circuit layer 170, in particular the analog elements, may depend on temperature. Therefore, it may be necessary to form the logic circuit layer 170 at a third temperature (e.g., from room temperature to about 250° C.) lower than the first temperature. The logic circuit layer 170 may be additionally formed after a process for forming the capacitor CAP at a high temperature such as the first temperature and a hybrid bonding process at an intermediate temperature such as the second temperature. Therefore, the logic circuit layer 170 may be formed without a thermal burden.

[0090] Furthermore, since the logic circuit layer 170 may be additionally formed at a low temperature such as the third temperature, bonding characteristics between the first bonding layer 150 and the second bonding layer 260 and electrical characteristics of the memory layer ML and the control circuit layer 250 may be maintained.

[0091] Thus, the stacked semiconductor device 1000 may be completed. The stacked semiconductor device 1000 may include a first semiconductor structure 100a and a second semiconductor structure 200a. The first semiconductor structure 100a may include a memory layer ML and a logic circuit layer 170 having different heat resistances. The second semiconductor structure 200a may include a control circuit layer 250.

[0092] According to an embodiment of the present disclosure, the memory layer ML formed by a high temperature process and the control circuit layer 250 formed by a low temperature process may be formed at different substrates to prevent characteristics of the control circuit layer 250 from being changed by high temperature.

[0093] In addition, after the first semiconductor substrate 110a having the memory layer ML may be bonded to the second semiconductor substrate 210 having the control circuit layer 250, the logic circuit layer 170 formed at a low temperature may be additionally formed on the other side of the first semiconductor substrate 110a. Therefore, the heat load applied to the control circuit layer 250 and the logic circuit layer 170 may be reduced to improve the characteristics of the stacked semiconductor device 1000.

[0094] The above embodiments of the present disclosure are intended to illustrate rather than limit the present disclosure. A variety of alternatives and equivalents are possible. The present disclosure is not limited to the embodiments described herein. The present disclosure is also not limited to any particular type of semiconductor device. In view of the present disclosure, other additions, reductions or modifications are obvious and are intended to fall within the scope of the appended claims.

Claims

1. A stacked semiconductor device, comprising: A first semiconductor structure, comprising a first integrated circuit layer and a first bonding layer, wherein the first bonding layer is formed on the first integrated circuit layer, and the first integrated circuit layer has a first heat resistance; as well as a second semiconductor structure comprising a second integrated circuit layer and a second bonding layer, wherein the second bonding layer is formed on the second integrated circuit layer, and the second bonding layer is hybrid-bonded to the first bonding layer, the second integrated circuit layer has a second heat resistance, and the second heat resistance is lower than the first heat resistance, wherein a third integrated circuit layer is integrated on at least one of the first semiconductor structure and the second semiconductor structure, and The third integrated circuit layer has a third heat resistance lower than the first heat resistance, and the third integrated circuit layer is arranged to face at least one of the first integrated circuit layer and the second integrated circuit layer.

2. The stacked semiconductor device according to claim 1, wherein: The third heat resistance is substantially equal to or lower than the second heat resistance.

3. The stacked semiconductor device according to claim 2, wherein: The first semiconductor structure further includes at least one through electrode, and the at least one through electrode electrically connects the first integrated circuit layer with the third integrated circuit layer.

4. The stacked semiconductor device according to claim 1, wherein: The first integrated circuit layer includes at least one capacitor including: a storage electrode, a dielectric layer, and a plate electrode stacked in sequence; and the first heat resistance is a crystallization temperature of the dielectric layer.

5. The stacked semiconductor device according to claim 1, wherein: The second integrated circuit layer includes: a plurality of transistors, and a plurality of interconnections connected between the plurality of transistors.

6. The stacked semiconductor device according to claim 1, wherein: The third integrated circuit layer includes at least one analog component.

7. The stacked semiconductor device according to claim 1, wherein: The first bonding layer includes: a plurality of first bonding pads electrically connected to the first integrated circuit layer; the second bonding layer includes: a plurality of second bonding pads, the plurality of second bonding pads being electrically connected to the second integrated circuit layer and hybrid-bonded to the plurality of first bonding pads; and the second heat resistance is the thermal expansion temperature of the plurality of first bonding pads and the plurality of second bonding pads.

8. The stacked semiconductor device according to claim 1, wherein: The first semiconductor structure includes a first substrate, the first substrate having a first surface and a second surface, the first integrated circuit layer and the first bonding layer are formed on the first surface, and the second surface is opposite to the first surface, The second semiconductor structure includes a second substrate, the second substrate has a third surface and a fourth surface, the second integrated circuit layer and the second bonding layer are formed on the third surface, and the fourth surface is opposite to the second surface, and The third integrated circuit layer is integrated on at least one of the second surface of the first substrate and the fourth surface of the second substrate.

9. A stacked semiconductor device, comprising: A first semiconductor structure having a first surface and a second surface opposite to the first surface, the first semiconductor structure comprising at least one storage component located on the first surface and a logic circuit layer located on the second surface; as well as a second semiconductor structure having a third surface and a fourth surface opposite to the third surface, the second semiconductor structure comprising a control circuit layer, the control circuit layer being integrated on the third surface to control the at least one storage component, The first semiconductor structure and the second semiconductor structure are hybrid-bonded so that the at least one storage component faces the control circuit layer.

10. The stacked semiconductor device according to claim 9, wherein: The at least one storage unit includes a plurality of capacitors, and the control circuit layer includes a plurality of access transistors that selectively transfer data to the plurality of capacitors.

11. The stacked semiconductor device according to claim 9, in, The first semiconductor structure further includes a first bonding layer, the first bonding layer being located on the at least one storage component and hybrid-bonded to the second semiconductor structure, and Wherein, the first bonding layer comprises: a plurality of first bonding pads electrically connected to the at least one memory component; and A first bonding insulation layer electrically isolates the plurality of first bonding pads from each other.

12. The stacked semiconductor device according to claim 11, in, The second semiconductor structure further includes a second bonding layer, wherein the second bonding layer is located on the control circuit layer, and Wherein, the second bonding layer comprises: a plurality of second bonding pads electrically connected to the control circuit layer and bonded to the plurality of first bonding pads; and A second bonding insulation layer electrically isolates the plurality of second bonding pads from each other.

13. The stacked semiconductor device according to claim 10, wherein: The logic circuit layer includes at least one of the following: an arithmetic logic circuit for calculating data in the at least one storage component; Data pipeline circuit; an interface circuit for receiving and processing external signals; and at least one analog element.

14. A method for manufacturing a stacked semiconductor device, the method comprising: forming a first integrated circuit layer on a first surface of a first semiconductor substrate at a first temperature; forming a first bonding layer on the first integrated circuit layer, the first bonding layer comprising a plurality of first bonding pads and a first bonding insulating layer, the plurality of first bonding pads being electrically connected to the first integrated circuit layer, and the first bonding insulating layer electrically isolating the first bonding pads from each other; forming a second integrated circuit layer on a second semiconductor substrate; forming a second bonding layer on the second integrated circuit layer, the second bonding layer comprising a plurality of second bonding pads and a second bonding insulating layer, the plurality of second bonding pads being electrically connected to the second integrated circuit layer, and the second bonding insulating layer electrically isolating the plurality of second bonding pads from each other; hybrid bonding the first bonding layer and the second bonding layer at a temperature lower than the first temperature; as well as A third integrated circuit layer is formed on a second surface of the first semiconductor substrate at a third temperature lower than the first temperature, the second surface not being bonded to the second semiconductor substrate.

15. The method according to claim 14, wherein: Forming the first integrated circuit layer includes: forming a storage electrode on the first surface of the first semiconductor substrate; forming a dielectric layer on the storage electrode; crystallizing the dielectric layer at the first temperature; and A plate electrode is formed on the dielectric layer.

16. The method according to claim 14, wherein: Hybrid bonding the first bonding layer and the second bonding layer comprises: directly bonding the first bonding insulating layer to the second bonding insulating layer; and An annealing process is performed to thermally expand the plurality of first bonding pads and the plurality of second bonding pads.

17. The method according to claim 14, wherein: The third temperature is substantially equal to or lower than the second temperature.

18. The method according to claim 14, further comprising: Before bonding the first bonding layer to the second bonding layer by a hybrid bonding process, a through electrode is formed from the first bonding layer to the first semiconductor substrate.

19. The method according to claim 18, further comprising: The exposed surface of the first semiconductor substrate is ground between the hybrid bonding process and the forming of the third integrated circuit layer until the through-electrode is exposed to provide the second surface of the first semiconductor substrate.

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