Semiconductor device and preparation method thereof, and storage system

Abstract

The invention discloses a semiconductor device, a preparation method thereof and a storage system. The semiconductor device includes: a first semiconductor structure including a first memory array and a first source structure located at one side of the first memory array along a first direction; the second semiconductor structure comprises a second storage array and a second source electrode structure located on one side of the second storage array in the first direction, and the first source electrode structure and the second source electrode structure are connected in a bonding mode. The preparation method comprises the following steps: forming a first semiconductor structure comprising a first storage array and a first source electrode structure, wherein the first source electrode structure is positioned on one side of the first storage array along a first direction; forming a second semiconductor structure comprising a second memory array and a second source structure, wherein the second source structure is located at one side of the second memory array along the first direction; and bonding the first source electrode structure and the second source electrode structure.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to semiconductor devices and methods for manufacturing the same, and storage systems. Background Art

[0002] As the feature size of semiconductor manufacturing processes becomes smaller and smaller, the storage density of memory devices becomes higher and higher, and three-dimensional memory applications are born. In order to increase the storage capacity per unit area of ​​three-dimensional memory, the number of stacked layers of the stacked structure of three-dimensional memory continues to increase. However, as the number of stacked layers increases, the aspect ratio of the channel hole increases, which in turn increases the difficulty of processes such as etching and filling of the channel hole, and the overlay accuracy becomes difficult to control, which requires the introduction of more advanced machines, resulting in a significant increase in costs.

[0003] At present, how to increase the storage capacity per unit area of ​​a three-dimensional memory without significantly increasing the cost is one of the technical problems that those skilled in the art need to solve urgently. Summary of the invention

[0004] The semiconductor device and its manufacturing method, and the storage system provided in the embodiments of the present application can solve or partially solve the above-mentioned deficiencies in the prior art or other deficiencies in the prior art.

[0005] The semiconductor device provided according to the first aspect of the present application includes:

[0006] A first semiconductor structure includes a first memory array and a first source structure located at one side of the first memory array along a first direction; and

[0007] The second semiconductor structure includes a second memory array and a second source structure located at one side of the second memory array along the first direction, and the first source structure and the second source structure are bonded and connected.

[0008] According to the second aspect of the present application, a method for preparing a semiconductor device includes:

[0009] forming a first semiconductor structure including a first memory array and a first source structure, wherein the first source structure is located at one side of the first memory array along a first direction;

[0010] forming a second semiconductor structure including a second memory array and a second source structure, wherein the second source structure is located at one side of the second memory array along the first direction; and

[0011] The first source structure and the second source structure are bonded together.

[0012] According to the storage system provided in the third aspect of the present application, the storage system includes a controller and the semiconductor device described above, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0013] The semiconductor device provided in the embodiment of the present application is achieved by bonding the first source structure of the first semiconductor structure to the second source structure of the second semiconductor structure. In other words, by achieving a common source connection between the first semiconductor structure and the second semiconductor structure, not only can the number of stacking layers of the entire semiconductor device be increased, thereby improving the storage capacity per unit area of ​​the entire semiconductor device, but also the first semiconductor structure and the second semiconductor structure are bonded to each other, and the formation processes of each other can be independent of each other. Compared with the entire semiconductor device, the first semiconductor structure and the second semiconductor structure each have fewer stacking layers, so that the process difficulty of each of the first semiconductor structure and the second semiconductor structure is relatively small. Under the premise of ensuring the overlay accuracy, the first semiconductor structure and the second semiconductor structure can be formed with the help of an existing machine without the need to introduce a more advanced machine. In addition, bonding the first semiconductor structure to the second semiconductor structure can also achieve stress balance between the various semiconductor structures.

[0014] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Other features, purposes and advantages of the present application will become more apparent by reading the detailed description of the non-limiting embodiments made with reference to the following drawings. The drawings are used to better understand the present solution and do not constitute a limitation of the present application. In the drawings:

[0016] Figures 1 to 14 They are respectively process schematic diagrams of a method for preparing a semiconductor device according to an embodiment of the present application;

[0017] Fig.15 is a partial schematic diagram of a first source structure (a second source structure) according to an embodiment of the present application;

[0018] Fig.16 is a schematic flow chart of a method for preparing a semiconductor device according to one embodiment of the present application;

[0019] Fig.17 is a block diagram of a system having a semiconductor device according to one embodiment of the present application;

[0020] Fig.18 is a schematic diagram of a memory card having a semiconductor device according to an embodiment of the present application; and

[0021] Fig.19 is a schematic diagram of a solid-state drive having a semiconductor device according to one embodiment of the present application.

[0022] Reference numerals:

[0023] 100, a first semiconductor structure; 200, a second semiconductor structure;

[0024] 301, first storage array; 302, second storage array; 310, channel structure;

[0025] 311, functional layer; 312, channel layer; 313, channel dielectric layer;

[0026] 320, first contact structure; 330, second contact structure; 331, contact conductive layer;

[0027] 332, contact dielectric layer; 340, third contact structure; 350, fourth contact structure;

[0028] 400, first source layer; 410, first bonding layer; 411, first bonding contact;

[0029] 412, a first conductive barrier layer; 413, a first insulating layer; 414, a first dielectric barrier layer;

[0030] 500, first interconnect layer; 510, first substrate; 610, first conductive structure;

[0031] 611, first connecting portion; 612, first conductive protrusion; 620, second conductive structure;

[0032] 621, second connecting portion; 622, second conductive protrusion; 630, insulating portion;

[0033] 700, second source layer; 710, second bonding layer; 711, second bonding contact;

[0034] 712, second conductive barrier layer; 713, second insulating layer; 714, second dielectric barrier layer;

[0035] 801, a third semiconductor structure; 802, a fourth semiconductor structure; 810, a second interconnect layer;

[0036] 820, second substrate; 830, trench isolation structure; 840, source; 850, drain;

[0037] 860, channel; 871, gate dielectric layer; 872, gate conductive layer; 880, well region;

[0038] 890, fifth contact structure; 900, system; 901, memory system;

[0039] 902, semiconductor device; 903, memory controller; 904, host;

[0040] 910, memory card; 911, memory card connector; 920, SSD;

[0041] 921.SSD connector. DETAILED DESCRIPTION

[0042] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature region, but do not represent any limitation on the features, and especially do not represent any order of precedence.

[0044] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0045] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0046] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0047] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in the present application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0048] In addition, in the present application, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. A layer may extend horizontally, vertically and / or along an inclined surface. A layer may include multiple sublayers. In addition, in the present application, when "connected" or "coupled" is used, it may indicate direct contact or indirect contact between corresponding parts, unless otherwise clearly defined or inferred from the context.

[0049] In order to increase the storage capacity per unit area of ​​3D memory, multiple deck technology is usually used to prepare 3D memory. However, as the number of stacking layers increases, the aspect ratio of the channel hole increases, resulting in increased difficulty in processes such as etching and filling of the channel hole, and overlay accuracy becomes difficult to control. Taking a stacked structure including N sub-stacked structures as an example, a preparation method of a three-dimensional memory includes: stacking a first sub-stacked structure on one side of a substrate; forming M first sub-channel holes penetrating the first sub-stacked structure and extending into the substrate in the first sub-stacked structure; filling the first sub-channel holes with a sacrificial material; forming a second sub-stacked structure on a side of the first sub-stacked structure away from the substrate; forming M second sub-channel holes penetrating the second sub-stacked structure and corresponding to the first sub-channel holes in the second sub-stacked structure; filling the second sub-channel holes with a sacrificial material; continuing to form subsequent sub-stacked structures and sub-channel holes in the same manner until an Nth sub-stacked structure and M Nth sub-channel holes penetrating the Nth sub-stacked structure are formed; removing the sacrificial material filled in the remaining sub-channel holes based on the Nth sub-channel hole, so that the upper and lower adjacent sub-channel holes in the N sub-stacked structures are at least partially aligned with each other to obtain M channel holes; forming a functional layer, a channel layer and a channel dielectric layer in the channel holes in sequence to form a channel structure, wherein the functional layer may include an ONO structure. In the above steps, the deposition process of the sub-stack structure involves heat treatment, and as the sub-stack structure increases, the heat treatment will cause the previously formed sub-stack structure to bend, thereby affecting the overlay accuracy (OVL) of the overlay process of the subsequently formed sub-channel holes, thereby increasing the alignment error of two adjacent sub-channel holes. In addition, in order to achieve the connection between the functional layer of each channel structure and the subsequently formed source layer, the subsequent process needs to remove the substrate and part of the ONO structure of the channel structure to expose part of the channel layer of the channel structure, and the reduction in the overlay accuracy of the sub-channel hole may cause problems such as over-etching or leakage when removing the substrate and part of the ONO structure. At present, the introduction of more advanced machines is usually used to improve the overlay accuracy, thereby solving the above problems, but this will lead to a significant increase in costs.

[0050] In order to solve at least part of the above problems, an embodiment of the present application provides a semiconductor device. Figures 12 to 15 Schematic diagrams of the structures of semiconductor devices according to different embodiments of the present application are shown. The semiconductor device includes a first semiconductor structure 100 and a second semiconductor structure 200, wherein the first semiconductor structure 100 includes a first storage array 301 and a first source structure located at one side of the first storage array 301 along a first direction (z direction), and the second semiconductor structure 200 includes a second storage array 302 and a second source structure located at one side of the second storage array 302 along the first direction (z direction), and the first source structure and the second source structure are bonded to each other.

[0051] The embodiment of the present application bonds the first source structure of the first semiconductor structure 100 to the second source structure of the second semiconductor structure 200. In other words, by realizing the common source connection of the first semiconductor structure 100 and the second semiconductor structure 200, not only the number of stacking layers of the entire semiconductor device can be increased, thereby improving the storage capacity per unit area of ​​the entire semiconductor device, but also the first semiconductor structure 100 and the second semiconductor structure 200 are bonded and connected, and the formation processes of each other can be independent of each other. Compared with the entire semiconductor device, the first semiconductor structure 100 and the second semiconductor structure 200 each have fewer stacking layers, so that the process difficulty of each of the first semiconductor structure 100 and the second semiconductor structure 200 is relatively small. Under the premise of ensuring the overlay accuracy, the first semiconductor structure 100 and the second semiconductor structure 200 can be formed with the help of an existing machine without introducing a more advanced machine. In addition, bonding the first semiconductor structure 100 and the second semiconductor structure 200 can also achieve stress balance between each semiconductor structure.

[0052] It should be noted that, in the embodiment of the present application, the first source structure and the second source structure may be completely the same or different. The first source structure may include a first source layer 400, and the second source structure may include a second source layer 700. The first source layer 400 and the second source layer 700 may be directly bonded or bonded based on a bonding layer. If the first source layer 400 and the second source layer 700 are directly bonded, then the first source structure and the second source structure are both single-layer structures; if the first source layer 400 and the second source layer 700 are bonded based on a bonding layer, then the first source structure and / or the second source structure are multi-layer structures. Compared with other methods, the direct bonding method can make the first semiconductor structure 100 and the second semiconductor structure 200 have a lower degree of deformation, a smaller connection spacing and less residual stress.

[0053] As an example, Figure 5 and Figure 7 As shown, the first source structure includes a first source layer 400 and a first bonding layer 410, and a first bonding contact 411 is arranged in the first bonding layer 410. The second source structure includes a second source layer 700 and a second bonding layer 710, and a second bonding contact 711 is arranged in the second bonding layer 710. The first bonding layer 410 contacts the second bonding layer 710, and the first bonding contact 411 contacts the second bonding contact 711. The material of the first source layer 400 and the second source layer 700 may include, but is not limited to, polysilicon. The material of the first bonding contact 411 and the second bonding contact 711 may include, but is not limited to, at least one of tungsten, cobalt, copper, aluminum and silicide. The first bonding layer 410 and the second bonding layer 710 may be a single-layer structure or a multi-layer structure, and the two may be the same or different, which is not limited in the present application.

[0054] For example, Figure 5 As shown, when the first bonding contact 411 is a metal contact such as a copper contact, in order to prevent the metal particles of the first bonding contact 411 from diffusing into the first source layer 400, the first bonding layer 410 may include a first conductive barrier layer 412 and a first insulating layer 413, the first conductive barrier layer 412 is located on a side of the first source layer 400 away from the first storage array 301, and the first insulating layer 413 is located on a side of the first conductive barrier layer 412 away from the first source layer 400. In other words, the first conductive barrier layer 412 is located between the first source layer 400 and the first insulating layer 413, and the first bonding contact 411 penetrates the first insulating layer 413 along a first direction (z direction) and extends into the first conductive barrier layer 412. Thus, after the first bonding layer 410 and the second bonding layer 710 are bonded and connected, the first bonding surface of the first bonding layer 410 overlaps with the second bonding surface of the second bonding layer 710, the first bonding surface is the surface of the first insulating layer 413 away from the first conductive barrier layer 412, and the second bonding surface is the surface of the second bonding layer 710 away from the second memory array 302. The material of the first conductive barrier layer 412 may include, but is not limited to, metal silicide and / or metal. If the first conductive barrier layer 412 includes a metal material, the metal material is different from the metal material of the first bonding contact 411.

[0055] For another example, when the first bonding contact 411 is a metal contact such as a copper contact, in order to prevent metal particles of the first bonding contact 411 from diffusing on the bonding interface between the first bonding layer 410 and the second bonding layer 710, the first bonding layer 410 may include a first insulating layer 413 and a first dielectric barrier layer 414, the first insulating layer 413 is located on a side of the first source layer 400 away from the first storage array 301, the first dielectric barrier layer 414 is located on a side of the first insulating layer 413 away from the first source layer 400, and the first bonding contact 411 penetrates the first dielectric barrier layer 414 and the first insulating layer 413 along a first direction (z direction). Thus, after the first bonding layer 410 and the second bonding layer 710 are bonded, the first bonding surface of the first bonding layer 410 overlaps with the second bonding surface of the second bonding layer 710, the first bonding surface is the surface of the first dielectric barrier layer 414 away from the first insulating layer 413, and the second bonding surface is the surface of the second bonding layer 710 away from the second storage array 302. The material of the first dielectric barrier layer 414 may include, but is not limited to, silicon nitride and / or doped silicon nitride.

[0056] For another example, when the first bonding contact 411 is a metal contact such as a copper contact, in order to prevent the metal particles of the first bonding contact 411 from diffusing into the first source layer 400 while also preventing the metal particles of the first bonding contact 411 from diffusing on the bonding interface between the first bonding layer 410 and the second bonding layer 710, the first bonding layer 410 may include a first conductive barrier layer 412, a first insulating layer 413 and a first dielectric barrier layer 414, the first conductive barrier layer 412 is located on a side of the first source layer 400 away from the first storage array 301, the first insulating layer 413 is located on a side of the first conductive barrier layer 412 away from the first source layer 400, and the first dielectric barrier layer 414 is located on a side of the first insulating layer 413 away from the first conductive barrier layer 412. In other words, the first insulating layer 413 is located between the first conductive barrier layer 412 and the first dielectric barrier layer 414. The first bonding contact 411 sequentially penetrates the first dielectric barrier layer 414 and the first insulating layer 413 along the first direction (z direction) and extends into the first conductive barrier layer 412. Therefore, after the first bonding layer 410 and the second bonding layer 710 are bonded and connected, the first bonding surface of the first bonding layer 410 coincides with the second bonding surface of the second bonding layer 710, the first bonding surface is the surface of the first dielectric barrier layer 414 away from the first insulating layer 413, and the second bonding surface is the surface of the second bonding layer 710 away from the second storage array 302.

[0057] Similarly, for example, when the second bonding contact 711 is a metal contact such as a copper contact, in order to prevent the metal particles of the second bonding contact 711 from diffusing into the second source layer 700, the second bonding layer 710 may include a second conductive barrier layer 712 and a second insulating layer 713, the second conductive barrier layer 712 is located on the side of the second source layer 700 away from the second storage array 302, and the second insulating layer 713 is located on the side of the second conductive barrier layer 712 away from the second source layer 700. In other words, the second conductive barrier layer 712 is located between the second source layer 700 and the second insulating layer 713, and the second bonding contact 711 penetrates the second insulating layer 713 along the first direction (z direction) and extends into the second conductive barrier layer 712. Thus, after the first bonding layer 410 and the second bonding layer 710 are bonded, the first bonding surface of the first bonding layer 410 overlaps with the second bonding surface of the second bonding layer 710, the first bonding surface is the surface of the first bonding layer 410 away from the first source layer 400, and the second bonding surface is the surface of the second insulating layer 713 away from the second conductive barrier layer 712. The material of the second conductive barrier layer 712 may include but is not limited to metal silicide and / or metal. If the second conductive barrier layer 712 includes a metal material, the metal material is different from the metal material of the second bonding contact 711.

[0058] For another example, when the second bonding contact 711 is a metal contact such as a copper contact, in order to prevent metal particles of the second bonding contact 711 from diffusing on the bonding interface between the first bonding layer 410 and the second bonding layer 710, the second bonding layer 710 may include a second insulating layer 713 and a second dielectric barrier layer 714, the second insulating layer 713 is located on a side of the second source layer 700 away from the second storage array 302, the second dielectric barrier layer 714 is located on a side of the second insulating layer 713 away from the second source layer 700, and the second bonding contact 711 penetrates the second dielectric barrier layer 714 and the second insulating layer 713 along a first direction (z direction). Thus, after the first bonding layer 410 and the second bonding layer 710 are bonded, the first bonding surface of the first bonding layer 410 overlaps with the second bonding surface of the second bonding layer 710, the first bonding surface is the surface of the first bonding layer 410 away from the first source layer 400, and the second bonding surface is the surface of the second dielectric barrier layer 714 away from the second insulating layer 713. The material of the second dielectric barrier layer 714 may include, but is not limited to, silicon nitride and / or doped silicon nitride.

[0059] For another example, when the second bonding contact 711 is a metal contact such as a copper contact, in order to prevent the metal particles of the second bonding contact 711 from diffusing into the second source layer 700 while also preventing the metal particles of the second bonding contact 711 from diffusing on the bonding interface between the first bonding layer 410 and the second bonding layer 710, the second bonding layer 710 may include a second conductive barrier layer 712, a second insulating layer 713 and a second dielectric barrier layer 714, the second conductive barrier layer 712 is located on a side of the second source layer 700 away from the second storage array 302, the second insulating layer 713 is located on a side of the second conductive barrier layer 712 away from the second source layer 700, and the second dielectric barrier layer 714 is located on a side of the second insulating layer 713 away from the second conductive barrier layer 712. In other words, the second insulating layer 713 is located between the second conductive barrier layer 712 and the second dielectric barrier layer 714. The second bonding contact 711 sequentially penetrates the second dielectric barrier layer 714 and the second insulating layer 713 along the first direction and extends into the second conductive barrier layer 712. Therefore, after the first bonding layer 410 and the second bonding layer 710 are bonded, the first bonding surface of the first bonding layer 410 coincides with the second bonding surface of the second bonding layer 710, the first bonding surface is the surface of the first bonding layer 410 away from the first source layer 400, and the second bonding surface is the surface of the second dielectric barrier layer 714 away from the second insulating layer 713.

[0060] It should be noted that the various forms of the first source structure and the second source structure mentioned above can be combined arbitrarily, as long as the expected results of the technical solution disclosed in this application can be achieved, and this application does not impose any restrictions on this.

[0061] The above mainly illustrates the structural forms that the first source structure and the second source structure can adopt when the first source layer 400 and the second source layer 700 are bonded based on the bonding layer. The following describes the structural forms that the first source structure and the second source structure can adopt when the first source layer 400 and the second source layer 700 are directly bonded.

[0062] For example, Fig.11 , Fig.15 As shown in (a) and 15(b), the first source structure includes a first source layer 400 and a first conductive structure 610 located in the first source layer 400, and the first conductive structure 610 extends along a second direction (x direction) perpendicular to the first direction. The first conductive structure 610 includes a first connecting portion 611 extending along the second direction (x direction) and at least one first conductive protrusion 612 connected to the first connecting portion 611, and the first conductive protrusion 612 is located on a side of the first connecting portion 611 facing the first storage array 301, and a side of the first connecting portion 611 away from the first storage array 301 is exposed to the surface of the first source layer 400. In other words, along the first direction (z direction), the first connecting portion 611 penetrates the first source layer 400 in a direction away from the first conductive protrusion 612. The first conductive protrusion 612 can be as shown in FIG. Fig.15 (a) penetrates the first source layer 400 in a direction away from the first connection portion 611, or Fig.15 (b) does not penetrate the first source layer 400. Similarly, the second source structure includes a second source layer 700 and a second conductive structure 620 located in the second source layer 700, the second conductive structure 620 extends along the second direction (x direction), the second conductive structure 620 includes a second connecting portion 621 extending along the second direction (x direction) and at least one second conductive protrusion 622 connected to the second connecting portion 621, the second conductive protrusion 622 is located on the side of the second connecting portion 621 facing the second storage array 302, and the side of the second connecting portion 621 away from the second storage array 302 is exposed to the surface of the second source layer 700. In other words, along the first direction, the second connecting portion 621 penetrates the second source layer 700 in the direction away from the second conductive protrusion 622. The second conductive protrusion 622 can be as shown in FIG. Fig.15 (a) penetrates the second source layer 700 in a direction away from the second connection portion 621, or Fig.15(b) does not penetrate the second source layer 700. Therefore, after the first source layer 400 and the second source layer 700 are bonded and connected, the surface of the first source layer 400 away from the first memory array 301 and the surface of the second source layer 700 away from the second memory array 302 overlap, and the surface of the first connecting portion 611 exposed to the first source layer 400 and the surface of the second connecting portion 621 exposed to the second source layer 700 at least partially overlap. The materials of the first connecting portion 611, the second connecting portion 621, the first conductive protrusion 612 and the second conductive protrusion 622 may include, but are not limited to, at least one of tungsten, cobalt, copper, aluminum and silicide.

[0063] For example, Fig.15 As shown in FIGS. 15(c) to 15(f), the first conductive structure 610 includes a plurality of first connection portions 611 and first conductive protrusions 612 corresponding to the first connection portions 611. The plurality of first connection portions 611 are spaced apart in the first source layer 400 along the second direction (x direction). A side of the first connection portion 611 away from the first memory array 301 is exposed to the surface of the first source layer 400. A side of the first connection portion 611 facing the first memory array 301 is provided with at least one first conductive protrusion 612. The first conductive protrusion 612 may be as follows: Fig.15 (c) penetrates the first source layer 400 in a direction away from the first connection portion 611, or Fig.15 (d) does not penetrate the first source layer 400. Fig.15 (e) and Fig.15 As shown in (f), an insulating portion 630 may be further provided between two adjacent first connection portions 611. Similarly, the second conductive structure 620 includes second connection portions 621 corresponding to the first connection portions 611 one by one and second conductive protrusions 622 corresponding to the second connection portions 621. The plurality of second connection portions 621 are spaced apart along the second direction (x direction). The side of the second connection portion 621 away from the second storage array 302 is exposed to the surface of the second source layer 700. The side of the second connection portion 621 facing the second storage array 302 is provided with at least one second conductive protrusion 622. The second conductive protrusion 622 may be as follows: Fig.15 (c) penetrates the second source layer 700 in a direction away from the second connection portion 621, or Fig.15 (d) does not penetrate the second source layer 700. Fig.15 (e) and Fig.15As shown in (f), an insulating portion 630 may be further provided between two adjacent second connection portions 621. Thus, after the first source layer 400 and the second source layer 700 are bonded and connected, the surface of the first source layer 400 away from the first storage array 301 and the surface of the second source layer 700 away from the second storage array 302 overlap, and the surface of the first connection portion 611 exposed to the first source layer 400 and the surface of the corresponding second connection portion 621 exposed to the second source layer 700 at least partially overlap. In the embodiment of the present application, by providing a plurality of first connection portions 611 spaced apart and distributed along the second direction (x direction) in the first source layer 400, and correspondingly providing a plurality of second connection portions 621 in the second source layer 700, the internal stress of the first source structure and the second source structure can be reduced. In addition, since the stress generated by the insulating material is a negative value and the stress generated by the metal material is a positive value, when the first connecting part 611 and the second connecting part 621 are metal structures, setting an insulating part 630 between two adjacent first connecting parts 611 and between two adjacent second connecting parts 621 can achieve stress balance with the help of the insulating part 630.

[0064] In some embodiments, Figure 5 As shown, a third semiconductor structure 801 is disposed on one side of the first memory array 301 away from the first source structure, and the third semiconductor structure 801 includes a first peripheral circuit connected to the first memory array 301. As an example, Figure 4 and Figure 5 As shown, the first storage array 301 includes a first contact structure 320, one end of the first contact structure 320 is connected to the first source structure, and the other end is connected to the first peripheral circuit. In the embodiment of the present application, the first source structure of the first semiconductor structure 100 is bonded to the second source structure of the second semiconductor structure 200, so that the first semiconductor structure 100 and the second semiconductor structure 200 can share the first peripheral circuit through the first contact structure 320.

[0065] In some embodiments, a fourth semiconductor structure 802 is disposed on a side of the second storage array 302 away from the second source structure, and the fourth semiconductor structure 802 includes a second peripheral circuit connected to the second storage array 302. As an example, the second storage array 302 includes a second contact structure 330, one end of the second contact structure 330 is connected to the second source structure, and the other end is connected to the second peripheral circuit. In the embodiment of the present application, by bonding the first source structure of the first semiconductor structure 100 to the second source structure of the second semiconductor structure 200, the first semiconductor structure 100 and the second semiconductor structure 200 can share the second peripheral circuit through the second contact structure 330.

[0066] The first peripheral circuit and the second peripheral circuit may include, but are not limited to, at least one of a high voltage device, a low voltage device, and an ultra low voltage device. The high voltage device may include, but are not limited to, at least one of a row decoder, a column decoder, a word line driver, and a bit line driver, the low voltage device may include, but are not limited to, a page buffer or a logic device, and the ultra low voltage device may include, but are not limited to, an I / O circuit. The operating voltage of a high-voltage device is generally greater than 3.3V, such as 5V to 30V. As an example, the operating voltage of a high-voltage device may be 5V, 10V, 15V, 20V, 25V or 30V; the operating voltage of a low-voltage device is generally between 1.3V and 3.3V. As an example, the operating voltage of a low-voltage device may be 1.3V, 1.8V, 2.3V, 2.8V or 3.3V; the operating voltage of an ultra-low-voltage device is generally lower than 1.3V, such as 0.9V to 1.2V; as an example, the operating voltage of an ultra-low-voltage device may be 0.9V, 0.95V, 1V, 1.05V, 1.1V, 1.15V or 1.2V. It should be noted that the operating voltage of a high-voltage device, a low-voltage device or an ultra-low-voltage device may also be any value between any two of the above voltage values. Those skilled in the art should understand that the description of the operating voltage ranges of high-voltage devices, low-voltage devices and ultra-low-voltage devices above is for a better understanding of the present solution and does not constitute a limitation on the present application.

[0067] In some embodiments, the first storage array 301 and the second storage array 302 may both include a stacked structure and a channel structure 310, and the channel structure 310 penetrates the stacked structure along the first direction (z direction). Since it is usually necessary to etch a channel hole in the process of forming the channel structure 310, and based on the characteristics of the etching process, the size of the channel hole along the etching direction, that is, the aperture, will gradually decrease during the etching process, so the sizes of the two ends of the channel structure 310 finally formed are different, that is, the channel structure 310 includes a first end and a second end arranged oppositely along the first direction (z direction), and the size of the first end of the channel structure 310 in the direction perpendicular to the first direction (z direction) is smaller than the size of the second end thereof, in other words, on a plane perpendicular to the first direction (z direction), the projection area of ​​the first end of the channel structure 310 is smaller than the projection area of ​​the second end thereof. It can be seen that the relative sizes of the two ends of the channel structure 310 can characterize the etching direction of the channel hole, that is, the formation direction of the channel structure 310. The channel structures 310 of the first memory array 301 and the channel structures 310 of the second memory array 302 may be formed in the same direction or in different directions.

[0068] For example, Fig. 9 As shown, the first end of the channel structure 310 of the first memory array 301 is closer to the first source structure than the second end thereof, and the first end of the channel structure 310 of the second memory array 302 is also closer to the first source structure than the second end thereof. Fig. 9Taking the orientation shown as a reference, in order to form the above-mentioned channel structure 310, when etching the channel holes, the channel holes of the first memory array 301 are etched from top to bottom along the negative direction of the z-axis, and the channel holes of the second memory array 302 are etched from bottom to top along the positive direction of the z-axis. Fig.10 As shown, the first end of the channel structure 310 of the first memory array 301 is farther away from the first source structure than the second end thereof, and the first end of the channel structure 310 of the second memory array 302 is also farther away from the first source structure than the second end thereof. Fig.10 Taking the orientation shown as a reference, in order to form the above-mentioned channel structure 310, when etching the channel holes, the channel holes of the first memory array 301 are etched from bottom to top along the positive direction of the z-axis, and the channel holes of the second memory array 302 are etched from top to bottom along the negative direction of the z-axis. It can be seen that Fig. 9 and Fig.10 The channel structures 310 of the first memory array 301 and the channel structures 310 of the second memory array 302 are formed in opposite directions.

[0069] For example, the first end of the channel structure 310 of the first memory array 301 is close to the first source structure relative to the second end thereof, while the first end of the channel structure 310 of the second memory array 302 is far away from the first source structure relative to the second end thereof. In order to form the above-mentioned channel structure 310, when etching the channel hole, the channel hole of the first memory array 301 is etched along the negative direction of the z-axis, that is, from top to bottom, and the channel hole of the second memory array 302 is etched along the negative direction of the z-axis, that is, from top to bottom. For another example, the first end of the channel structure 310 of the first memory array 301 is far away from the first source structure relative to the second end thereof, and the first end of the channel structure 310 of the second memory array 302 is close to the first source structure relative to the second end thereof. When etching the channel hole to form the above-mentioned channel structure 310, the channel hole of the first memory array 301 is etched along the positive direction of the z-axis, that is, from bottom to top, and the channel hole of the second memory array 302 is etched along the positive direction of the z-axis, that is, from bottom to top. It can be seen that in the above situation, the channel structures 310 of the first memory array 301 and the channel structures 310 of the second memory array 302 are formed in the same direction.

[0070] In some embodiments, the stacking structure may include a connection area and a core area having a plurality of channel structures 310 formed therein, wherein the connection area is located on at least one side of the core area along the second direction (x direction). The connection area may be a stepped structure or a non-stepped structure. For example, under the SCT (Staircase Contact) architecture, the connection area does not need to be stepped. The stacking structure may include gate layers and third insulating layers alternately stacked along a first direction, and the gate layers and the third insulating layers may be arranged in pairs or not. As an example, the stacking structure may include, but is not limited to, 64 pairs, 128 pairs or more than 128 pairs of gate layers and third insulating layers, which is not limited in the present application. Figure 4 As shown, the channel structure 310 may include a functional layer 311 and a channel layer 312, and the functional layer 311 may include a blocking layer, a charge capture layer and a tunneling layer sequentially arranged along the second direction (x direction). Among them, the material of the channel layer 312 may include but is not limited to semiconductor materials such as amorphous silicon, polycrystalline silicon or single crystal silicon, the materials of the blocking layer and the tunneling layer may be but are not limited to silicon oxide, and the material of the charge capture layer may be but is not limited to silicon nitride. In other words, the functional layer 311 may have an ONO structure. In the embodiment of the present application, both the functional layer 311 and the channel layer 312 can be formed by a thin film deposition process, and the thin film deposition process may be but is not limited to a physical vapor deposition (Physical Vapor Deposition, referred to as PVD) process, a chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD) process, an atomic layer deposition (Atomic Layer Deposition, referred to as ALD) process or a combination of any of the above processes.

[0071] Among them, the functional layer 311 and the channel layer 312 of the channel structure 310 and the corresponding part of the gate layer of the stacked structure and a part of the gate layer together constitute a memory cell, and multiple memory cells are connected in series along the stacking direction of the stacked structure, that is, the first direction (z direction) to form a memory string, and the memory cells located in the same row, that is, distributed along the second direction (x direction) can be connected to the same word line, and the remaining part of the gate layer can be used as the word line of multiple memory cells in the corresponding memory string, and each memory string, that is, the memory cells in the same column, can be connected to the same bit line. Under the voltage control of the corresponding word line, the carriers in the channel layer 312 of the memory cell enter the charge capture layer of the functional layer 311, or the carriers in the charge capture layer of the functional layer 311 retreat to the channel layer 312, thereby realizing the programming or erasing of the memory cell. In the case where the first peripheral circuit and / or the second peripheral circuit include a page buffer, a word line driver and an I / O circuit, the page buffer is connected to the bit line to apply a bit line voltage to the bit line, and the bit line voltage corresponds to the data DATA to be programmed, and the data DATA may include multi-bit data. In a read operation, the page buffer can sense the data DATA stored in the selected memory cell through the bit line and output the sensed data DATA to the I / O circuit. The word line driver is connected to the word line through the word line contact to apply a word line voltage to the word line, thereby performing an erase operation on the memory cell corresponding to the word line.

[0072] In some embodiments, Figure 1 As shown, the first storage array 301 includes a third contact structure 340 arranged corresponding to its gate layer, one end of the third contact structure 340 is connected to the corresponding gate layer, and the other end is connected to the first peripheral circuit; and / or, the second storage array 302 includes a fourth contact structure 350 arranged corresponding to its gate layer, one end of the fourth contact structure 350 is connected to the corresponding gate layer, and the other end is connected to the second peripheral circuit.

[0073] In addition, if Fig.16 As shown, the embodiment of the present application further provides a method 1000 for preparing a semiconductor device, the method comprising:

[0074] S100, forming a first semiconductor structure 100 including a first memory array 301 and a first source structure, wherein the first source structure is located at one side of the first memory array 301 along a first direction (z direction);

[0075] S200, forming a second semiconductor structure 200 including a second memory array 302 and a second source structure, wherein the second source structure is located at one side of the second memory array 302 along a first direction (z direction);

[0076] S300, bonding the first source structure and the second source structure.

[0077] The following is a detailed introduction to each step in the method for preparing a semiconductor device in an embodiment of the present application.

[0078] Step S100

[0079] In step S100, a first semiconductor structure 100 is formed, and the first semiconductor structure 100 includes a first memory array 301 and a first source structure. The first source structure may be a single-layer structure or a multi-layer structure.

[0080] In some embodiments, step S100 may include: Figure 1 As shown, a first storage array 301 is formed; as Figure 4 As shown, a first source layer 400 is formed on one side of the first memory array 301; Figure 5 As shown, a first bonding layer 410 is formed on a side of the first source layer 400 away from the first memory array 301 ; and a first bonding contact 411 is formed in the first bonding layer 410 from a side of the first bonding layer 410 away from the first source layer 400 .

[0081] In addition to the above-mentioned method, the first semiconductor structure 100 may also be formed by other methods. For example, the step of forming the first semiconductor structure 100, i.e., S100, may include: forming a first memory array 301; forming a first source layer 400 on one side of the first memory array 301; forming a first conductive structure 610 (see FIG. 6 ) from a side of the first source layer 400 away from the first memory array 301; Fig.11 ).

[0082] As an example, the step of forming the first storage array 301 may include: forming a stacked structure (not shown) on one side of the first substrate 510, and the stacked structure may include a third insulating layer and a sacrificial layer alternately stacked along a first direction (z direction). The third insulating layer and the sacrificial layer may be formed on one side of the first substrate 510 by a thin film deposition process, and the thin film deposition process may be, but not limited to, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a combination of any of the above processes. Among them, the first substrate 510 may include, but is not limited to, single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI) or III-V compounds such as gallium arsenide. The material of the third insulating layer may include, but is not limited to, silicon oxide, silicon oxynitride or silicon nitride, and the material of the third insulating layer may also include high-K materials such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, etc. The material of the sacrificial layer may include, but is not limited to, silicon oxynitride, silicon nitride, polysilicon or polycrystalline germanium. As an example, in the embodiment of the present application, the material of the third insulating layer is silicon oxide, and the material of the sacrificial layer is silicon nitride. A channel hole is etched along a first direction (z direction) on a side of the stacked structure away from the first substrate 510, and the channel hole penetrates the stacked structure and extends into the first substrate 510. The channel hole can be formed by a dry etching process, a combination of dry and wet etching processes, or a patterning process, wherein the patterning process includes photolithography, cleaning, and chemical mechanical polishing processes; a blocking layer is formed on the inner wall of the channel hole to block the outflow of charge; wherein the material of the blocking layer may include, but is not limited to, silicon oxide, silicon nitride, a high-K dielectric material, or a combination of any of the above. A charge capture layer is formed on the side of the blocking layer away from the inner wall of the channel hole to store charges; wherein the material of the charge capture layer may include but is not limited to silicon nitride, silicon oxynitride, silicon or any combination of the above. A tunneling layer is formed on the side of the charge capture layer away from the blocking layer; wherein the material of the tunneling layer may include but is not limited to silicon oxide or silicon nitride. A channel layer 312 is formed on the side of the tunneling layer away from the charge capture layer to transport the required carriers, i.e., electrons or holes; wherein the material of the channel layer 312 may include but is not limited to amorphous silicon, polycrystalline silicon or single crystal silicon. A dielectric material is filled in the pores formed by the channel layer 312 to form a channel dielectric layer 313; wherein the material of the channel dielectric layer 313 may include but is not limited to silicon oxide, silicon nitride, silicon oxynitride, spin-on glass, carbon-doped oxide, etc.A channel plug (not shown) in contact with the channel layer 312 is formed on the side of the channel dielectric layer 313 away from the first substrate 510, and the material of the channel plug can be the same as the material of the channel layer 312; a gate line slit (GLS) is etched along the first direction (z direction) on the side of the stacked structure away from the first substrate 510; the sacrificial layer is replaced with the gate layer through the gate line slit to form a stacked structure. The material of the gate layer can include but is not limited to polysilicon, tungsten, aluminum, titanium, copper, cobalt, tungsten nitride, or any combination of the above.

[0083] In addition, the step of forming the first storage array 301 may also include: etching a first contact hole along a first direction (z direction) on a side of the stack structure away from the first substrate 510, the first contact hole at least passing through the stack structure, in other words, the first contact hole may also extend into the first substrate 510, or may not extend into the first substrate 510; forming a contact dielectric layer 332 on the inner wall of the first contact hole; filling a conductive material in a gap formed by the contact dielectric layer 332 to form a contact conductive layer 331. The first contact structure 320 includes a contact conductive layer 331 and a contact dielectric layer 332.

[0084] As an example, Figure 3 and Figure 4 As shown, the step of forming the first source layer 400 on one side of the first storage array 301 may include: removing the first substrate 510 to expose the portion of the channel structure 310 extending to the first substrate 510; wherein the first substrate 510 may be removed by dry etching and / or wet etching process; removing the functional layer 311 of the exposed channel structure 310 to expose part of the channel layer 312; forming the first source layer 400 on the side of the stacked structure where the first substrate 510 is removed; the first source layer 400 may be formed by a thin film deposition process, and the thin film deposition process may be but is not limited to a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a combination of any of the above processes. The portion of the channel layer 312 exposed to one side of the stack structure contacts the first source layer 400, thereby increasing the contact area between the channel layer 312 and the first source layer 400 and reducing the contact resistance between the two. Since the functional layer 311 of the channel structure 310 and the portion of the channel layer 312 corresponding to the gate layer of the stack structure and a portion of the gate layer together constitute a storage unit, a plurality of storage units are connected in series along the stacking direction of the stack structure, i.e., the first direction (z direction) to form a storage string, and therefore all storage strings in the same storage block can be electrically connected to the first source layer 400.

[0085] As an example, Figure 5 As shown, the step of forming the first bonding layer 410 may include: forming a first conductive barrier layer 412 on a side of the first source layer 400 away from the first memory array 301; forming a first insulating layer 413 on a side of the first conductive barrier layer 412 away from the first source layer 400; and forming a first dielectric barrier layer 414 on a side of the first insulating layer 413 away from the first conductive barrier layer 412. It should be noted that the step of forming the first conductive barrier layer 412 and / or the first dielectric barrier layer 414 may be omitted during the process of forming the first bonding layer 410. In other words, the first bonding layer 410 may not include the first conductive barrier layer 412 and / or the first dielectric barrier layer 414. When the first bonding layer 410 includes a first conductive barrier layer 412, a first insulating layer 413 and a first dielectric barrier layer 414, the step of forming a first bonding contact 411 may include: forming a first contact hole that sequentially penetrates the first dielectric barrier layer 414 and the first insulating layer 413 and extends to the first conductive barrier layer 412; and filling the first contact hole with a conductive material to form the first bonding contact 411.

[0086] As an example, the step of forming the first conductive structure 610 may include: forming a first conductive hole extending along the first direction (z direction) in the second region of the first source layer 400, the first conductive hole may penetrate the first source layer 400, or may not penetrate the first source layer 400; forming a first conductive groove in the first region of the first source layer 400, the depth of the first conductive groove along the first direction is less than the depth of the first conductive hole along the first direction; filling the first conductive hole and the first conductive groove with a conductive material to form the first conductive structure 610. The first region and the second region are regions of the first source layer 400 away from the surface of the first memory array 301, and the second region is located in the first region.

[0087] Step S200

[0088] In step S200, a second semiconductor structure 200 is formed, and the second semiconductor structure 200 includes a second memory array 302 and a second source structure. The second source structure may be a single-layer structure or a multi-layer structure.

[0089] In some embodiments, step S200 may include: Figure 1 As shown, a second storage array 302 is formed; Figure 4 As shown, a second source layer 700 is formed on one side of the second memory array 302; Figure 5 As shown, a second bonding layer 710 is formed on a side of the second source layer 700 away from the second memory array 302 ; and a second bonding contact 711 is formed in the second bonding layer 710 from a side of the second bonding layer 710 away from the second source layer 700 .

[0090] In addition to the above-mentioned method, the second semiconductor structure 200 may also be formed by other methods. For example, the step of forming the second semiconductor structure 200, i.e., S200, may include: forming a second memory array 302; forming a second source layer 700 on one side of the second memory array 302; and forming a second conductive structure 620 on a side of the second source layer 700 away from the second memory array 302.

[0091] As an example, the step of forming the second memory array 302 may include: forming a stacked structure on one side of the first substrate 510 , the stacked structure may include third insulating layers and sacrificial layers alternately stacked along the first direction (z direction). A channel hole is etched along a first direction on a side of the stacked structure away from the first substrate 510, and the channel hole penetrates the stacked structure and extends into the first substrate 510; a barrier layer is formed on the inner wall of the channel hole to block the outflow of charges; a charge capture layer is formed on the side of the barrier layer facing away from the inner wall of the channel hole to store charges; a tunneling layer is formed on the side of the charge capture layer facing away from the barrier layer; a channel layer 312 is formed on the side of the tunneling layer facing away from the charge capture layer to transport required carriers, i.e., electrons or holes; a dielectric material is filled in the pores formed by the channel layer 312 to form a channel dielectric layer 313; a channel plug (not shown) in contact with the channel layer 312 is formed on the side of the channel dielectric layer 313 away from the first substrate 510; a gate line slit (GLS) is etched along the first direction on the side of the stacked structure away from the first substrate 510; and a sacrificial layer is replaced with a gate layer through the gate line slit to form a stacked structure.

[0092] In addition, the step of forming the second storage array 302 may also include: etching a second contact hole along the first direction on a side of the stack structure away from the first substrate 510, the second contact hole at least passing through the stack structure, in other words, the second contact hole may extend into the first substrate 510, or may not extend into the first substrate 510; forming a contact dielectric layer 332 on the inner wall of the second contact hole; filling a conductive material in the gap formed by the contact dielectric layer 332 to form a contact conductive layer 331. The second contact structure 330 includes a contact conductive layer 331 and a contact dielectric layer 332 (see Figure 3 ).

[0093] As an example, the step of forming the second source layer 700 on one side of the second storage array 302 may include: removing the first substrate 510 to expose the portion of the channel structure 310 extending to the first substrate 510; wherein the first substrate 510 may be removed by dry etching and / or wet etching process; removing the functional layer 311 of the exposed channel structure 310 to expose a portion of the channel layer 312; forming the second source layer 700 on the side of the stacked structure where the first substrate 510 is removed; the second source layer 700 may be formed by a thin film deposition process, and the thin film deposition process may be but is not limited to a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a combination of any of the above processes. The portion of the channel layer 312 exposed to one side of the stacked structure contacts the second source layer 700 , thereby increasing the contact area between the channel layer 312 and the second source layer 700 and reducing the contact resistance therebetween.

[0094] As an example, Figure 5 As shown, the step of forming the second bonding layer 710 may include: forming a second conductive barrier layer 712 on a side of the second source layer 700 away from the second memory array 302; forming a second insulating layer 713 on a side of the second conductive barrier layer 712 away from the second source layer 700; and forming a second dielectric barrier layer 714 on a side of the second insulating layer 713 away from the second conductive barrier layer 712. It should be noted that the step of forming the second conductive barrier layer 712 and / or the second dielectric barrier layer 714 may be omitted in the process of forming the second bonding layer 710. In other words, the second bonding layer 710 may not include the second conductive barrier layer 712 and / or the second dielectric barrier layer 714. In the case where the second bonding layer 710 includes a second conductive barrier layer 712, a second insulating layer 713 and a second dielectric barrier layer 714, the step of forming a second bonding contact 711 may include: forming a second contact hole that sequentially penetrates the second dielectric barrier layer 714 and the second insulating layer 713 and extends to the second conductive barrier layer 712; and filling the second contact hole with a conductive material to form the second bonding contact 711.

[0095] As an example, the step of forming the second conductive structure 620 may include: forming a second conductive hole extending along the first direction in the second region of the second source layer 700, the second conductive hole may penetrate the second source layer 700, or may not penetrate the second source layer 700; forming a second conductive groove in the first region of the second source layer 700, the depth of the second conductive groove along the first direction is less than the depth of the second conductive hole along the first direction; filling the second conductive hole and the second conductive groove with conductive material to form the second conductive structure 620. The first region and the second region are regions of the second source layer 700 away from the surface of the second memory array 302, and the second region is located in the first region.

[0096] In some embodiments, Figure 1 As shown, the preparation method may also include: forming a first interconnection layer 500 on a side of the stacked structure of the first memory array 301 and / or the second memory array 302 away from the first substrate 510; forming a first interconnection structure, a second interconnection structure, and a third interconnection structure that penetrate the first interconnection layer 500 along a first direction in the first interconnection layer 500. The first interconnection structure of the first semiconductor structure 100 is connected to the channel plug of its channel structure 310, the second interconnection structure is connected to the first contact structure 320, and the third interconnection structure is connected to the third contact structure 340. The first interconnection structure of the second semiconductor structure 200 is connected to the channel plug of its channel structure 310, the second interconnection structure is connected to the second contact structure 330, and the third interconnection structure is connected to the fourth contact structure 350.

[0097] Step S300

[0098] In step S300, the first source structure and the second source structure are bonded. As an example, the first source structure and the second source structure can be bonded by an Xtacking bonding process. The Xtacking bonding process refers to the alignment bonding of bonding structures between different devices in the same process step, thereby achieving electrical connection between the two devices. Figure 6 and Figure 7 As shown, in the case where the first source structure includes the first source layer 400, the first conductive barrier layer 412, the first insulating layer 413, the first dielectric barrier layer 414 and the first bonding contact 411, and the second source structure includes the second source layer 700, the second conductive barrier layer 712, the second insulating layer 713, the second dielectric barrier layer 714 and the second bonding contact 711, after the first source structure and the second source structure are bonded, the surface of the first dielectric barrier layer 414 away from the first insulating layer 413 overlaps with the surface of the second dielectric barrier layer 714 away from the second insulating layer 713, and the first bonding contact 411 contacts the corresponding second bonding contact 711. Fig.11 and Fig.12As shown, in the case where the first source structure includes the first source layer 400 and the first conductive structure 610, and the second source structure includes the second source layer 700 and the second conductive structure 620, after the first source structure and the second source structure are bonded together, the surface of the first source layer 400 away from the first storage array 301 and the surface of the second source layer 700 away from the second storage array 302 overlap, and the first conductive structure 610 is in contact with the corresponding second conductive structure 620.

[0099] In addition, if Figures 2 to 9 As shown, the preparation method may also include: forming a third semiconductor structure 801; bonding the third semiconductor structure 801 to a side of the first semiconductor structure 100 away from the second semiconductor structure 200; and / or, forming a fourth semiconductor structure 802; bonding the fourth semiconductor structure 802 to a side of the second semiconductor structure 200 away from the first semiconductor structure 100.

[0100] As an example, Figure 2 As shown, the steps of forming the third semiconductor structure 801 may include: forming a plurality of transistors on the second substrate 820, wherein at least a portion of the transistors are located in the second substrate 820; forming a trench isolation structure 830 surrounding an active region of the transistor on the second substrate; forming a second interconnect layer 810 on the second substrate 820, wherein the second interconnect layer 810 covers a side of the second substrate 820 where the transistors are formed and a side of the transistors away from the second substrate 820; forming a fourth interconnect structure and a fifth interconnect structure (not shown) that penetrate the second interconnect layer 810 in the second interconnect layer 810, wherein an end of the fourth interconnect structure close to the second substrate 820 is connected to the transistor, and an end of the fourth interconnect structure and the fifth interconnect structure that are away from the second substrate 820 are in contact with the first interconnect structure, the second interconnect structure or the third interconnect structure of the first interconnect layer 500, respectively.

[0101] As an example, the step of forming a transistor on the second substrate 820 may include: forming a well region 880 in the second substrate 820; for example, if the transistor is an N-type transistor, an ion implantation or diffusion process may be used to form a P-type doped well, i.e., a P-well, in the second substrate 820, and the dopant may be a P-type dopant with a lower concentration such as boron (B); if the transistor is a P-type transistor, an ion implantation or diffusion process may be used to form an N-type doped well, i.e., an N-well, in the second substrate 820, and the dopant may be a N-type dopant with a lower concentration such as phosphorus (P), arsenic (As) and antimony (Sb). A drain 850 and a source 840 are formed in the well region 880. For example, if the transistor is an N-type transistor, the source 840 and the drain 850 are formed in the second substrate 820 using N-type dopants such as phosphorus (P), arsenic (As) and antimony (Sb); if the transistor is a P-type transistor, the source 840 and the drain 850 are formed in the second substrate 820 using P-type dopants such as boron (B), and the portion of the well region 880 between the source 840 and the drain 850 constitutes a channel 860; a gate dielectric layer 871 and a gate conductive layer 872 are formed on one side of the second substrate 820. The gate structure, for example, can form a gate dielectric layer 871 on one side of the second substrate 820 by a thin film deposition process, and remove part of the gate dielectric layer 871 by an etching process, so that the remaining gate dielectric layer 871 is located between the source 840 and the drain 850, that is, covers the surface of the channel 860; a gate conductive layer 872 is formed on the side of the gate dielectric layer 871 facing away from the second substrate 820 by a thin film deposition process, and remove part of the gate conductive layer 872 by an etching process, so that the remaining gate conductive layer 872 is located between the source 840 and the drain 850 and covers the gate dielectric layer 871. The material of the gate dielectric layer 871 includes dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, zirconium oxide, aluminum oxide, magnesium oxide, and tantalum oxide, and the material of the gate conductive layer 872 includes polysilicon, conductive metal or conductive alloy. As an example, the material of the gate conductive layer 872 includes at least one of tungsten (W), titanium nitride (TiN), copper (Cu) and silver (Ag). It should be noted that the source 840 and the drain 850 of the above transistor may also be directly formed in the second substrate 820 . In other words, the above steps may not include the step of forming the well region 880 .

[0102] In some embodiments, Fig. 9 As shown, the step of forming the third semiconductor structure 801 may also include: etching a fifth contact hole corresponding to the fifth interconnect structure along the first direction on a side of the second substrate 820 away from the second interconnect layer 810, the fifth contact hole passing through the second substrate 820; forming a dielectric layer on the inner wall of the fifth contact hole; and filling a conductive material in the gap formed by the dielectric layer 332 to form a fifth contact structure 890.

[0103] It should be noted that the method of forming the fourth semiconductor structure 802 is similar to the method of forming the third semiconductor structure 801 , and will not be described in detail herein.

[0104] In addition, an embodiment of the present application further provides a storage system, which includes a controller and the above-mentioned semiconductor device, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0105] Fig.17 1 shows a block diagram of a system having a semiconductor device according to an embodiment of the present application. The system 900 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device located therein. Fig.17 As shown in , the system 900 may include a host 904 and a memory system 901, the memory system 901 having one or more semiconductor devices 902 and a memory controller 903. The host 904 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system on chip 900 (SoC), such as an application processor (AP). The host 904 may be configured to send or receive data to or from the semiconductor device 902.

[0106] The semiconductor device 902 may be any semiconductor device disclosed in this application, for example Fig.13 or Fig.14 The semiconductor device shown. According to some embodiments, the memory controller 903 is coupled to the semiconductor device 902 and the host 904, and is configured to control the semiconductor device 902. The memory controller 903 can manage the data stored in the semiconductor device 902 and communicate with the host 904. For example, the memory controller 903 can be coupled to the semiconductor device 902, and the memory controller 903 can be configured to control the operation of the first storage array 301 and the second storage array 302 through the first peripheral circuit and the second peripheral circuit. In the embodiment of the present application, by bonding the first source structure of the first semiconductor structure 100 to the second source structure of the second semiconductor structure 200, the first semiconductor structure 100 and the second semiconductor structure 200 can share the first peripheral circuit through the first contact structure 320, and can also share the second peripheral circuit through the second contact structure 330.

[0107] In some embodiments, the memory controller 903 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 903 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smart phones, tablets, laptops, etc. and enterprise storage arrays. The memory controller 903 can be configured to control the operation of the semiconductor device 902, such as read, erase, and program operations. The memory controller 903 can also be configured to manage various functions related to data stored in or to be stored in the semiconductor device 902, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the memory controller 903 is further configured to process error correction code (ECC) related to data read from or written to the semiconductor device 902. Any other suitable functions may also be performed by the memory controller 903, for example, formatting the semiconductor device 902. The memory controller 903 may communicate with an external device (e.g., the host 904) according to a specific communication protocol. For example, the memory controller 903 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, etc.

[0108] The memory controller 903 and the one or more semiconductor devices 902 may be integrated into various types of storage devices, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 901 may be implemented and packaged into different types of final electronic products. Fig.18 In one example shown, the memory controller 903 and the single semiconductor device 902 may be integrated into a memory card 910. The memory card 910 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 910 may further include a processor that connects the memory card 910 to a host (e.g., Fig.17 The memory card connector 911 is coupled to the host 904 in FIG. Fig.19 In another example shown, the memory controller 903 and the plurality of semiconductor devices 902 may be integrated into a solid state drive, or SSD 920. The SSD 920 may further include a processor that connects the SSD 920 to a host (eg, Fig.17 In some embodiments, the storage capacity and / or operating speed of the SSD 920 is higher than the storage capacity and / or operating speed of the memory card 910.

[0109] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. As an example, the steps recorded in the disclosure of the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution disclosed in the present application can be achieved, and this document does not limit this.

[0110] The above specific implementations do not constitute a limitation on the protection scope of this application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of this application should be included in the protection scope of this application.

Claims

1. A semiconductor device, characterized in that: include: A first semiconductor structure includes a first memory array and a first source structure located at one side of the first memory array along a first direction; as well as The second semiconductor structure includes a second memory array and a second source structure located at one side of the second memory array along the first direction, and the first source structure and the second source structure are bonded and connected.

2. The semiconductor device according to claim 1, wherein The first source structure includes a first source layer and a first bonding layer located on a side of the first source layer away from the first storage array, and a first bonding contact is arranged in the first bonding layer. The second source structure includes a second source layer and a second bonding layer located on a side of the second source layer away from the second storage array, and a second bonding contact is arranged in the second bonding layer. The first bonding contact is in contact with the second bonding contact.

3. The semiconductor device according to claim 2, wherein: The first bonding layer includes a first conductive barrier layer and a first insulating layer, the first conductive barrier layer is located between the first source layer and the first insulating layer, and the first bonding contact penetrates the first insulating layer along the first direction and extends into the first conductive barrier layer; and / or The second bonding layer includes a second conductive barrier layer and a second insulating layer, the second conductive barrier layer is located between the second source layer and the second insulating layer, and the second bonding contact penetrates the second insulating layer along the first direction and extends into the second conductive barrier layer.

4. The semiconductor device according to claim 3, wherein: The material of the first conductive barrier layer and / or the second conductive barrier layer includes metal silicide and / or metal.

5. The semiconductor device according to claim 2, wherein: The first bonding layer includes a first insulating layer and a first dielectric barrier layer, the first dielectric barrier layer is located on a side of the first insulating layer away from the first source layer, and the first bonding contact penetrates the first dielectric barrier layer and the first insulating layer along the first direction; and / or The second bonding layer includes a second insulating layer and a second dielectric barrier layer, the second dielectric barrier layer is located on a side of the second insulating layer away from the second source layer, and the second bonding contact penetrates the second dielectric barrier layer and the second insulating layer along the first direction.

6. The semiconductor device according to claim 5, wherein: The material of the first dielectric barrier layer and / or the second dielectric barrier layer includes silicon nitride and / or doped silicon nitride.

7. The semiconductor device according to claim 1, wherein The first source structure includes a first source layer and a first conductive structure located in the first source layer, the first conductive structure extends along a second direction perpendicular to the first direction, the second source structure includes a second source layer and a second conductive structure located in the second source layer, the second conductive structure extends along a second direction perpendicular to the second direction, and the first conductive structure is in contact with the second conductive structure.

8. The semiconductor device according to claim 7, wherein: The first conductive structure includes a first connecting portion extending along the second direction and at least one first conductive protrusion connected to the first connecting portion, the first conductive protrusion is located on a side of the first connecting portion facing the first memory array, and a side of the first connecting portion away from the first memory array is exposed to a surface of the first source layer; and / or The second conductive structure includes a second connecting portion extending along the second direction and at least one second conductive protrusion connected to the second connecting portion, the second conductive protrusion is located on a side of the second connecting portion facing the second storage array, and a side of the second connecting portion away from the second storage array is exposed to the surface of the second source layer.

9. The semiconductor device according to claim 8, wherein: Along the first direction, the first conductive protrusion penetrates the first source layer in a direction away from the first connecting portion; and / or Along the first direction, the second conductive protrusion penetrates the second source layer in a direction away from the second connecting portion.

10. The semiconductor device according to claim 8, wherein A plurality of first connection portions are spaced apart and distributed along the second direction in the first source layer, and / or a plurality of second connection portions are spaced apart and distributed along the second direction in the second source layer.

11. The semiconductor device according to claim 10, wherein: An insulating portion is disposed between two adjacent first connecting portions and / or between two adjacent second connecting portions.

12. The semiconductor device according to any one of claims 1 to 11, wherein: The first storage array and the second storage array both include: stacked structure; and A channel structure penetrates the stack structure along the first direction, the channel structure comprises a first end and a second end arranged opposite to each other along the first direction, and a size of the first end of the channel structure along a direction perpendicular to the first direction is smaller than a size of the second end thereof.

13. The semiconductor device according to claim 12, wherein: The first ends of the channel structures of the first storage array and the second storage array are both closer to or farther from the first source structure relative to their second ends; or, The first end of one of the channel structures of the first storage array and the channel structures of the second storage array is closer to the first source structure than the second end thereof, and the first end of the other one is farther from the first source structure than the second end thereof.

14. The semiconductor device according to claim 12, wherein: A third semiconductor structure is disposed on a side of the first storage array away from the first source structure, and the third semiconductor structure includes a first peripheral circuit connected to the first storage array; and / or A fourth semiconductor structure is disposed on a side of the second memory array away from the second source structure. The fourth semiconductor structure includes a second peripheral circuit connected to the second memory array.

15. The semiconductor device according to claim 14, wherein: The first storage array includes a first contact structure, one end of the first contact structure is connected to the first source structure, and the other end of the first contact structure is connected to the first peripheral circuit; and / or The second storage array includes a second contact structure, one end of the second contact structure is connected to the second source structure, and the other end of the second contact structure is connected to the second peripheral circuit.

16. The semiconductor device according to claim 14, wherein The stacked structure comprises a third insulating layer and a gate layer alternately stacked along the first direction; The first storage array includes a third contact structure arranged corresponding to the gate layer thereof, one end of the third contact structure is connected to the corresponding gate layer, and the other end is connected to the first peripheral circuit; and / or The second storage array includes a fourth contact structure arranged corresponding to the gate layer thereof, one end of the fourth contact structure is connected to the corresponding gate layer, and the other end of the fourth contact structure is connected to the second peripheral circuit.

17. A method for preparing a semiconductor device, characterized in that: include: forming a first semiconductor structure including a first memory array and a first source structure, wherein the first source structure is located at one side of the first memory array along a first direction; forming a second semiconductor structure including a second memory array and a second source structure, wherein the second source structure is located at one side of the second memory array along the first direction; as well as The first source structure and the second source structure are bonded together.

18. The method for preparing a semiconductor device according to claim 17, wherein: Forming a first semiconductor structure including a first memory array and a first source structure and / or forming a second semiconductor structure including a second memory array and a second source structure includes: forming a storage array; forming a source layer on one side of the memory array; forming a bonding layer on a side of the source layer away from the memory array; and A bonding contact is formed in the bonding layer from a side of the bonding layer away from the source layer.

19. The method for preparing a semiconductor device according to claim 18, wherein: Forming a bonding layer on a side of the source layer away from the memory array includes: forming a conductive barrier layer on a side of the source layer away from the memory array; and forming an insulating layer on a side of the conductive barrier layer away from the source layer; Wherein, the bonding contact extends into the conductive barrier layer.

20. The method for preparing a semiconductor device according to claim 18, wherein: Forming a bonding layer on a side of the source layer away from the memory array includes: forming an insulating layer on a side of the source layer away from the memory array; and forming a dielectric barrier layer on a side of the insulating layer away from the source layer; Wherein, the bonding contact penetrates the dielectric barrier layer and the insulating layer.

21. The method for preparing a semiconductor device according to claim 16, wherein: Forming a first semiconductor structure including a first memory array and a first source structure and / or forming a second semiconductor structure including a second memory array and a second source structure includes: forming a storage array; forming a source layer on one side of the memory array; and A conductive structure is formed from a side of the source layer away from the memory array.

22. The method for preparing a semiconductor device according to claim 21, wherein: The surface of the source layer away from the memory array includes a first region and at least one second region located in the first region; Wherein, forming a conductive structure from a side of the source layer away from the memory array comprises: forming a conductive hole extending along the first direction in the second region; forming a conductive groove in the first region, wherein a depth of the conductive groove along the first direction is smaller than a depth of the conductive hole along the first direction; and The conductive hole and the conductive groove are filled with conductive material to form the conductive structure.

23. A storage system, characterized in that: The storage system comprises a controller and the semiconductor device according to any one of claims 1 to 16, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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