Semiconductor device, method for manufacturing the same, and electronic apparatus

Abstract

The semiconductor device, a method for manufacturing the same, and an electronic device according to the present disclosure include: an N+ substrate; a first N- buffer layer located on and in contact with the N+ substrate; an N- drift layer located on a side of the first N- buffer layer away from the N+ substrate; a P- well layer embedded in the N- drift layer on a side of the N- drift layer away from the N+ substrate; a P+ cathode in contact with the P- well layer on a side of the P- well layer away from the N+ substrate; and a P- layer located between the N- drift layer and the first N- buffer layer and in contact with the first N- buffer layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0002] In a bipolar power device, both holes and electrons participate in conduction during conduction, and the number of minority carriers in the drift layer is much higher than the background doping concentration. Therefore, the conductivity modulation effect will occur in the drift layer, greatly reducing the on-resistance of the drift layer. Therefore, bipolar power devices are widely used in application fields that require high voltage and large current.

[0003] Conventional bipolar devices such as bipolar junction transistors IGBTs, thyristors GTOs, MOS-controlled thyristors MCTs, etc. do not have reverse conduction capabilities. However, in most applications, it is necessary to freewheel the reverse current. Therefore, an external anti-parallel diode is often used to achieve freewheeling. If the freewheeling diode can be integrated inside the bipolar device, not only can the parasitic inductance and parasitic resistance of the connection leads be reduced, but also the device power density can be increased by saving the terminal area, the device performance can be improved, and the system volume can be reduced. In addition, there may be a voltage jump phenomenon in which the on-voltage drop decreases sharply during the forward conduction process of the device, which may cause local overcurrent of the device and failure. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor device, a manufacturing method thereof, and an electronic device, for preparing an N-type IGBT based on an N-type substrate, integrating a freewheeling diode inside the device, and the introduction of the freewheeling diode will not cause a voltage jump phenomenon in the device.

[0005] Embodiments of the present disclosure provide a semiconductor device, a manufacturing method thereof, and an electronic device, and the specific solutions are as follows:

[0006] On the one hand, embodiments of the present disclosure provide a semiconductor device, including:

[0007] An N+ substrate;

[0008] A first N- buffer layer, located above the N+ substrate and in contact with the first N- buffer layer;

[0009] An N- drift layer, located on a side of the first N- buffer layer away from the N+ substrate;

[0010] A P- well layer, embedded in the N- drift layer on a side of the N- drift layer away from the N+ substrate;

[0011] A P+ cathode, in contact with the P- well layer on a side of the P- well layer away from the N+ substrate;

[0012] The P-layer is located between the N-drift layer and the first N-buffer layer, and the P-layer is in contact with the first N-buffer layer.

[0013] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, a second N-buffer layer and a P+ anode are further included, wherein the second N-buffer layer is in contact with the N-drift layer on a side of the N-drift layer close to the N+ substrate, and the P+ anode is embedded in the second N-buffer layer on a side of the second N-buffer layer close to the N+ substrate.

[0014] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the P-layer is in contact with the second N-buffer layer.

[0015] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the P-layer is in contact with the N-drift layer.

[0016] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, an anode conductive layer and a trench are further included, wherein the trench penetrates through the N+ substrate, the first N-buffer layer, and the P-layer, and extends to a plane where the lower surface of the P+ anode is located, and the anode conductive layer is in contact with the P+ anode in the trench and is spaced apart from the side wall of the trench.

[0017] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, an anode dielectric layer is further included, and the anode dielectric layer fills a gap between the anode conductive layer and the side wall of the trench.

[0018] On the other hand, the embodiments of the present disclosure provide a method for manufacturing the above semiconductor device, including:

[0019] Epitaxially growing a first N-buffer layer, a P-layer, and an N-drift layer on an N+ substrate in sequence;

[0020] Selectively forming a P-well layer and a P+ cathode on the surface of the N-drift layer by using ion implantation technology.

[0021] In some embodiments, in the above manufacturing method provided by the embodiments of the present disclosure, after epitaxially growing the P-layer and before epitaxially growing the N-drift layer, it further includes: epitaxially growing a second N-buffer layer;

[0022] After selectively forming a P-well layer and a P+ cathode on the surface of the N-drift layer by using ion implantation technology, it further includes:

[0023] Forming a trench that penetrates through the N+ substrate, the first N-buffer layer, and the P-layer, and at most partially penetrates the second N-buffer layer;

[0024] At the trench, P-type impurities are implanted into the second N-buffer layer to form a P+ anode.

[0025] In some embodiments, in the above preparation method provided by the embodiments of the present disclosure, after forming a P-well layer and a P+ cathode by selective area formation on the surface of the N-drift layer using ion implantation technology, the method further includes:

[0026] Forming a trench that penetrates through the N+ substrate, the first N-buffer layer, and the P-layer, and at most partially penetrates the N-drift layer;

[0027] At the trench, N-type impurities are implanted into the N-drift layer to form a second N-buffer layer;

[0028] At the trench, P-type impurities are implanted into the second N-buffer layer to form a P+ anode.

[0029] On the other hand, the embodiments of the present disclosure provide an electronic device including the above semiconductor device provided by the embodiments of the present disclosure.

[0030] The beneficial effects of the present disclosure are as follows:

[0031] The semiconductor device, its preparation method, and the electronic device provided by the embodiments of the present disclosure include: an N+ substrate; a first N-buffer layer located above and in contact with the N+ substrate; an N-drift layer located on a side of the first N-buffer layer away from the N+ substrate; a P-well layer embedded in the N-drift layer on a side of the N-drift layer away from the N+ substrate; a P+ cathode in contact with the P-well layer on a side of the P-well layer away from the N+ substrate; and a P-layer located between the N-drift layer and the first N-buffer layer, and the P-layer is in contact with the first N-buffer layer. Thus, a PNPN freewheeling diode structure including a P+ cathode, a P-well layer, an N-drift layer, a P-layer, a first N-buffer layer, and an N+ substrate is integrated inside the device, so that there is no need to anti-parallel a diode externally to achieve the freewheeling function, which can increase the power density and reduce the system volume. Description of the Drawings

[0032] Figure 1 It is a schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure;

[0033] Figure 2 is Figure 1 a schematic diagram of the current distribution when the reverse conduction of the semiconductor device shown;

[0034] Figure 3 is Figure 1 a schematic diagram of the current distribution when the forward conduction of the semiconductor device shown;

[0035] Figure 4Another structural schematic diagram of the semiconductor device provided by the embodiments of the present disclosure;

[0036] Figure 5 Another structural schematic diagram of the semiconductor device provided by the embodiments of the present disclosure;

[0037] Figure 6 Another structural schematic diagram of the semiconductor device provided by the embodiments of the present disclosure;

[0038] Figure 7 Flowchart of the manufacturing method of the semiconductor device provided by the embodiments of the present disclosure;

[0039] Figure 8(a) is Figure 1 A structural schematic diagram of the semiconductor device shown during the manufacturing process;

[0040] Figure 8(b) is Figure 1 Another structural schematic diagram of the semiconductor device shown during the manufacturing process;

[0041] Figure 8(c) is Figure 1 Another structural schematic diagram of the semiconductor device shown during the manufacturing process;

[0042] Figure 8(d) is Figure 1 Another structural schematic diagram of the semiconductor device shown during the manufacturing process;

[0043] Figure 8(e) is Figure 1 Another structural schematic diagram of the semiconductor device shown during the manufacturing process;

[0044] Figure 8(f) is Figure 1 Another structural schematic diagram of the semiconductor device shown during the manufacturing process;

[0045] Figure 8(g) is Figure 1 Another structural schematic diagram of the semiconductor device shown during the manufacturing process;

[0046] Figure 9(a) is Figure 4 A structural schematic diagram of the semiconductor device shown during the manufacturing process;

[0047] Figure 9(b) is Figure 4 Another structural schematic diagram of the semiconductor device shown during the manufacturing process;

[0048] Figure 9(c) is Figure 4 Another structural schematic diagram of the semiconductor device shown during the manufacturing process;

[0049] Figure 9(d) is Figure 4 Another structural schematic diagram of the semiconductor device shown during the manufacturing process;

[0050] Figure 9(e) isFigure 4 Another schematic structural diagram of the semiconductor device during the manufacturing process;

[0051] Figure 9(f) is Figure 4 Another schematic structural diagram of the semiconductor device during the manufacturing process;

[0052] Figure 9(g) is Figure 4 Another schematic structural diagram of the semiconductor device during the manufacturing process;

[0053] Figure 9(h) is Figure 4 Another schematic structural diagram of the semiconductor device during the manufacturing process;

[0054] Figure 9(i) is Figure 4 Another schematic structural diagram of the semiconductor device during the manufacturing process;

[0055] Figure 9(j) is Figure 4 Another schematic structural diagram of the semiconductor device during the manufacturing process. Detailed implementation manners

[0056] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It should be noted that the sizes and shapes of the various figures in the drawings do not reflect the actual proportions, and the purpose is only to schematically illustrate the content of the present disclosure. Also, the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components are omitted in the present disclosure.

[0057] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings understood by those of ordinary skill in the field to which the present disclosure belongs. The "first", "second", and similar terms used in the specification and claims of the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "include" or "comprise" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. The terms such as "inside", "outside", "above", "below", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0058] Based on this, the embodiments of the present disclosure provide a semiconductor device, which can be manufactured based on semiconductor materials such as silicon, silicon carbide, gallium nitride, etc. through processes such as epitaxy and ion implantation. In some embodiments, as Figure 1 shown, the semiconductor device provided by the present disclosure may include:

[0059] An N+ substrate 101, which can be relatively thick to keep the device with sufficient mechanical strength.

[0060] A first N- buffer layer 102, located on the N+ substrate 101 and in contact with the first N- buffer layer 102. In other words, the lower surface of the first N- buffer layer 102 is in contact with the upper surface of the N+ substrate 101.

[0061] An N- drift layer 103, located on the side of the first N- buffer layer 102 away from the N+ substrate 101.

[0062] A P- well layer 104, embedded in the N- drift layer 103 on the side of the N- drift layer 103 away from the N+ substrate 101. That is, the lower surface and the side surface of the P- well layer 104 are in contact with the N- drift layer 103.

[0063] A P+ cathode 105, in contact with the P- well layer 104 on the side of the P- well layer 104 away from the N+ substrate 101, such that the lower surface of the P+ cathode 105 is in contact with the upper surface of the P- well layer 104.

[0064] A P- layer 106, located between the N- drift layer 103 and the first N- buffer layer 102, and the P- layer 106 is in contact with the first N- buffer layer 102. Specifically, the lower surface of the P- layer 106 is in contact with the upper surface of the first N- buffer layer 102.

[0065] In the above semiconductor device provided by the embodiments of the present disclosure, by adding a P- layer 106 in contact with the first N- buffer layer 102 between the N- drift layer 103 and the first N- buffer layer 102, a PNPN diode structure including a P+ cathode 105, a P- well layer 104, an N- drift layer 103, a P- layer 106, a first N- buffer layer 102, and an N+ substrate 101 is integrated inside the device. As Figure 2 shown, in the reverse conduction mode, the cathode of the device is connected to zero potential, the anode of the device is connected to negative potential, and the gate voltage is zero potential or negative potential. The PNPN diode structure including a P+ cathode 105, a P- well layer 104, an N- drift layer 103, a P- layer 106, a first N- buffer layer 102, and an N+ substrate 101 inside the device will conduct, thereby realizing the freewheeling function. Therefore, a freewheeling diode is integrated inside the device in the present disclosure, so that there is no need to anti-parallel a diode externally for freewheeling, which can increase the power density and reduce the system volume.

[0066] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, as Figure 1As shown, it may further include a second N-buffer layer 107 and a P+ anode 108. The second N-buffer layer 107 is in contact with the N-drift layer 103 on the side of the N-drift layer 103 close to the N+ substrate 101, and the P+ anode 108 is embedded in the second N-buffer layer 107 on the side of the second N-buffer layer 107 close to the N+ substrate 101. That is to say, the upper surface of the second N-buffer layer 107 is in contact with the lower surface of the N-drift layer 103, and the upper surface and side surfaces of the P+ anode 108 are in contact with the second N-buffer layer 107. As Figure 3 shown, in the forward conduction mode, the cathode of the device is connected to zero potential and the anode of the device is connected to positive potential. When the gate voltage changes from zero potential or negative potential to positive potential, an electron channel is formed by the inversion of the surface of the P-well layer 104 under the gate dielectric layer. Since the PN junction between the P-layer 106 and the first N-buffer layer 102 is in the reverse bias state, the N+ substrate 101 will not conduct, while the PN junction between the P+ anode 108 and the second N-buffer layer 107 is in the forward bias state, and this PN junction between the P+ anode 108 and the second N-buffer layer 107 will gradually turn on, and the device enters the bipolar conduction mode. Therefore, the presence of the N+ substrate 101 will not affect the normal forward conduction process of the device, and there is no voltage jump phenomenon in which the conduction voltage drop decreases sharply, thus avoiding the problem that the device fails due to local overcurrent caused by the voltage jump phenomenon.

[0067] In addition, due to the high defects of the SiC P-type substrate, the defect density of the epitaxial wafer grown based on the P-type substrate is high. Therefore, the performance and reliability of the bipolar device prepared therefrom are poor. And due to the high defects of the P-type substrate, its resistivity is relatively large. A relatively thick P-type substrate will result in an additional on-resistance. If the overall thickness of the substrate is reduced, the mechanical strength of the substrate will be reduced, resulting in an increased probability of fragmentation. Therefore, currently, bipolar power devices are usually fabricated based on N-type substrates. However, devices fabricated based on N-type substrates, such as IGBT devices, are usually P-type IGBTs, which have opposite electrode polarities to the currently common N-type IGBTs. The application circuit and the drive circuit are relatively complex and are not compatible with the common application circuits, which affects the application of the device. The present disclosure can form a P+ anode 108 or form a P+ anode 108 and a second N-buffer layer 107 by grooving and digging through the N+ substrate 101, the first N-buffer layer 102, and the P-layer 106, and then through an ion implantation process, so as to form an N-type IGBT structure based on the N+ substrate 101, and a relatively thick N+ substrate 101 can be retained to keep the device with sufficient mechanical strength.

[0068] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, as Figure 1As shown, the upper surface of the P-layer 106 may be in contact with the lower surface of the second N-buffer layer 107. At this time, the second N-buffer layer 107 not only wraps the P+ anode 108 but also covers the P-layer 106. The freewheeling diode of the present disclosure further includes the second N-buffer layer 107; or, as Figure 4 shown, the upper surface of the P-layer 106 is in contact with the lower surface of the N-drift layer 103. At this time, the second N-buffer layer 107 only wraps the P+ anode 108, and the freewheeling diode of the present disclosure does not include the second N-buffer layer 107, and the freewheeling diode can be turned on more easily. In some embodiments, the P+ anode 108 of the present disclosure may be formed by ion implantation. Figure 1 The second N-buffer layer 107 in Figure 4 may be formed by epitaxial growth.

[0069] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, as Figure 1 and Figure 4 shown, it may further include an anode conductive layer 109 and a trench T. Wherein, the trench T penetrates through the N+ substrate 101, the first N-buffer layer 102 and the P-layer 106 and extends to the plane where the lower surface of the P+ anode 108 is located. The anode conductive layer 109 is in contact with the P+ anode 108 in the trench T and is spaced from the side wall of the trench T, and at the same time covers the lower surface of the N+ substrate 101. In this way, the anode conductive layer 109 can be insulated from the first N-buffer layer 102, the P-layer 106, and the second N-buffer layer 107, avoiding the mutual influence between the forward conduction current and the reverse conduction current of the device. In some embodiments, the gap between the anode conductive layer 109 and the side wall of the trench T may be filled with an anode dielectric layer 110, so that the side wall of the anode conductive layer 109 is separated from the side walls of the second N-buffer layer 107, the first N-buffer layer 102, the P-layer 106, and the N+ substrate 101 by the anode dielectric layer 110, and the anode conductive layer 109 can be led out as the device anode.

[0070] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, as Figure 1 and Figure 4As shown, it may further include an N+ cathode 111, a cathode conductive layer 112, a gate dielectric layer 113, a gate conductive layer 114, and an isolation dielectric layer 115. Among them, a cell may include multiple P-well layers 104, multiple N+ cathodes 111, and multiple P+ cathodes 105. The N+ cathode 111 is embedded in the P-well layer 104, the P+ cathode 105 is embedded in the N+ cathode 111, and the lower surfaces of both the P+ cathode 105 and the N+ cathode 111 are in contact with the upper surface of the P-well layer 104. The lower surface of the cathode conductive layer 112 is simultaneously in contact with the upper surfaces of the N+ cathode 111 and the P+ cathode 105. The gate dielectric layer 113 is in contact with the upper surface of the P-well layer 104 and the upper surface of the N+ cathode 111. The gate conductive layer 114 is located on the upper surface of the gate dielectric layer 113. The upper surface and the side surfaces of the gate conductive layer 114 are in contact with the isolation dielectric layer 115. The upper surface and the side surfaces of the isolation dielectric layer 115 are in contact with the cathode conductive layer 112. The isolation dielectric layer 115 and the gate dielectric layer 113 completely wrap the gate conductive layer 114. The gate conductive layer 114 can be led out as a device gate, and the cathode conductive layer 112 can be led out as a device cathode.

[0071] In some embodiments, the P-well layer 104, N+ cathode 111, P+ cathode 105, and cathode conductive layer 112 of the present disclosure may belong to the cathode region, the gate dielectric layer 113, gate conductive layer 114, and isolation dielectric layer 115 may belong to the gate region, and the N-drift layer 103 belongs to the drift region. The N+ substrate 101, first N-buffer layer 102, P-layer 106, second N-buffer layer 107, P+ anode 108, anode conductive layer 109, and anode dielectric layer 110 belong to the anode region. Figure 1 and Figure 4 shows that one drift region, one cathode region, and one gate region are provided on one anode region. In some embodiments, multiple repeated drift regions, cathode regions, and gate regions may be provided on one anode region according to process capabilities and required device performance. As Figure 5 and Figure 6 shows that two drift regions, two cathode regions, and two gate regions are provided on one anode region. Among them, the two drift regions are integrally provided, the P-well layers 104 on the adjacent sides of the two cathode regions are integrally provided, the P+ cathodes 105 are integrally provided, and the cathode conductive layer 112 is integrally provided. The two gate regions are spaced apart by the cathode conductive layer 112.

[0072] Based on the same inventive concept, the embodiments of the present disclosure provide a method for manufacturing the above semiconductor device. Since the principle of solving problems by this manufacturing method is similar to the principle of solving problems by the above semiconductor device, therefore, the implementation of this manufacturing method provided by the embodiments of the present disclosure can refer to the implementation of the above semiconductor device provided by the embodiments of the present disclosure, and the repeated parts will not be described again.

[0073] In some embodiments, in the above preparation method provided by the embodiments of the present disclosure, as Figure 7 shown, the following steps may be included:

[0074] S701: Epitaxially grow a first N-buffer layer, a P-layer, and an N-drift layer on the N+ substrate in sequence;

[0075] S702: Selectively form a P-well layer and a P+ cathode on the surface of the N-drift layer by using ion implantation technology.

[0076] To better understand the above preparation method provided by the embodiments of the present disclosure, the following Figure 1 and Figure 4 detailed description will be given to the manufacturing process of the semiconductor device shown.

[0077] In some embodiments, Figure 1 the manufacturing process of the semiconductor device shown may include the following steps:

[0078] Step (1): As shown in FIG. 8(a), epitaxially grow a first N-buffer layer 102, a P-layer 106, a second N-buffer layer 107, and an N-drift layer 103 on the N+ substrate 101 in sequence.

[0079] Step (2): As shown in FIG. 8(b), selectively form a P-well layer 104, an N+ cathode 111, and a P+ cathode 105 on the surface of the N-drift layer 103 in sequence by using ion implantation technology.

[0080] Step (3): As shown in FIG. 8(c), form a hard mask HM on the back of the N+ substrate 101, and then selectively etch. Use dry etching to etch the N+ substrate 101, the first N-buffer layer 102, and the P-layer 106 until at least the second N-buffer layer 107 is exposed, so as to form a trench T that penetrates the N+ substrate 101, the first N-buffer layer 102, and the P-layer 106 and at most partially penetrates the second N-buffer layer 107.

[0081] Step (4): As shown in FIG. 8(d), keep the hard mask HM in place, inject P-type impurities from the back of the N+ substrate 101 into the second N-buffer layer 107 at the trench T, so as to form a P+ anode 108. Then, strip the hard mask HM. Subsequently, perform annealing treatment to activate the implanted ions and repair the lattice damage.

[0082] Step (5): As shown in FIG. 8(e), form a gate dielectric layer 113, a gate conductive layer 114, an isolation dielectric layer 115, and a cathode conductive layer 112 on the surface of the device in sequence.

[0083] Step (6): As shown in FIG. 8(f), deposit an anode dielectric layer 110 on the back of the device.

[0084] Step (7): As shown in FIG. 8(g), on the back surface of the device, using a reactive ion ICP etching method, etch away the anode dielectric layer 110 in the middle region of the lower surface of the N+ substrate 101 and the lower surface of the P+ anode 108, leaving only the anode dielectric layer 110 on the sidewalls of the trench T.

[0085] Step (8): As Figure 1 shown, on the back surface of the device, use a sputtering method to fill and form the anode conductive layer 109.

[0086] Thus far, the fabrication of the Figure 1 shown semiconductor device is completed.

[0087] In some embodiments, Figure 4 the fabrication process of the shown semiconductor device may include the following steps:

[0088] Step (1): As shown in FIG. 9(a), sequentially epitaxially grow a first N- buffer layer 102, a P- layer 106, and an N- drift layer 103 on the N+ substrate 101.

[0089] Step (2): As shown in FIG. 9(b), on the surface of the N- drift layer 103, use ion implantation technology to sequentially form a P- well layer 104, an N+ cathode 111, and a P+ cathode 105 by selective area.

[0090] Step (3): As shown in FIG. 9(c), form a first hard mask HM1 on the back surface of the N+ substrate 101, and then perform selective area etching. Use dry etching to etch the N+ substrate 101, the first N- buffer layer 102, and the P- layer 106 until at least the N- drift layer 103 is exposed, thereby forming a trench T that penetrates the N+ substrate 101, the first N- buffer layer 102, and the P- layer 106 and at most partially penetrates the N- drift layer 103.

[0091] Step (4): As shown in FIG. 9(d), while maintaining the state of the first hard mask HM1, inject N-type impurities from the back surface of the N+ substrate 101 into the N- drift layer 103 at the trench T, thereby forming a second N- buffer layer 107.

[0092] Step (5): As shown in FIG. 9(e), while maintaining the state of the first hard mask HM1, grow a second hard mask HM2 on the back surface.

[0093] Step (6): As shown in FIG. 9(f), use a reactive ion ICP etching method to etch the second hard mask HM2 on the back surface until the second hard mask HM2 in the middle of the surface of the second N- buffer layer 107 is removed.

[0094] Step (7): As shown in Fig. 9(g), P-type impurities are implanted into the second N-buffer layer 107 at the trench T from the back surface of the N+ substrate 101, thereby forming the P+ anode 108. Subsequently, the first hard mask HM1 on the back surface of the N+ substrate 101 and the second hard mask HM2 on the sidewalls of the trench T are stripped. Then, annealing treatment is performed to activate the implanted ions and repair lattice damage.

[0095] Step (8): As shown in Fig. 9(h), a gate dielectric layer 113, a gate conductive layer 114, an isolation dielectric layer 115, and a cathode conductive layer 112 are sequentially formed on the device surface.

[0096] Step (9): As shown in Fig. 9(i), an anode dielectric layer 110 is deposited on the back surface of the device.

[0097] Step (10): As shown in Fig. 9(j), using a reactive ion ICP etching method on the back surface of the device, the anode dielectric layer 110 in the middle region of the lower surface of the N+ substrate 101 and the lower surface of the P+ anode 108 is etched away, leaving only the anode dielectric layer 110 on the sidewalls of the trench T.

[0098] Step (11): As Figure 4 shown, an anode conductive layer 109 is formed by filling on the back surface of the device using a sputtering method.

[0099] So far, the fabrication of the Figure 4 shown semiconductor device is completed.

[0100] Based on the same inventive concept, the embodiments of the present disclosure provide an electronic device, including the above semiconductor device provided by the embodiments of the present disclosure. Since the principle of the electronic device to solve problems is similar to that of the above semiconductor device to solve problems, therefore, the implementation of the electronic device provided by the embodiments of the present disclosure can refer to the implementation of the above semiconductor device provided by the embodiments of the present disclosure, and the repeated parts will not be described again.

[0101] In some embodiments, the above electronic device provided by the embodiments of the present disclosure may include, but is not limited to: radio frequency amplifiers, mixers, radars, satellites, power supplies, automotive electronics, energy-saving lamps, home appliances, etc. Of course, in addition to including semiconductor devices, the electronic device provided by the present disclosure may also include other structures. For example, when the electronic device is a radar, it further includes: a transmitter, an antenna, a receiver, etc.; when the electronic device is a mixer, it may further include: input ports and output ports, etc.

[0102] As can be seen from the above, the present disclosure achieves the purpose of fabricating an N-type IGBT based on an N+ substrate, which can retain a relatively thick N+ substrate to keep the device with sufficient mechanical strength. In addition, by introducing a P- layer above the N+ substrate, a PNPN diode structure including a P+ cathode, a P- well layer, an N- drift layer, a second N- buffer layer (optional), a P- layer, a first N- buffer layer, and an N+ substrate is formed inside the device, so that a freewheeling diode is integrated in the device to achieve the freewheeling function, and the introduction of this freewheeling diode will not cause the voltage jump phenomenon existing in the conventional reverse-conducting IGBT.

[0103] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present disclosure.

[0104] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure is also intended to include these modifications and variations.

Claims

1. A semiconductor device, characterized in that: include: N+ substrate; A first N-buffer layer, located on the N+ substrate and in contact with the N+ substrate; An N-drift layer, located on a side of the first N-buffer layer away from the N+ substrate; A P-well layer embedded in the N-drift layer on a side of the N-drift layer away from the N+ substrate; A P+ cathode, contacting the P-well layer at a side of the P-well layer away from the N+ substrate; A P-layer, located between the N-drift layer and the first N-buffer layer, and the P-layer is in contact with the first N-buffer layer; It also includes a second N-buffer layer, a P+ anode, an anode conductive layer, a groove and an anode dielectric layer, wherein the second N-buffer layer contacts the N-drift layer on a side of the N-drift layer close to the N+ substrate, the P+ anode is embedded in the second N-buffer layer on a side of the second N-buffer layer close to the N+ substrate, the groove runs through the N+ substrate, the first N-buffer layer and the P-layer, and extends to the plane where the lower surface of the P+ anode is located, the anode conductive layer is in direct contact with the P+ anode in the groove and is spaced from the side wall of the groove, and the anode dielectric layer fills the gap between the anode conductive layer and the side wall of the groove.

2. The semiconductor device according to claim 1, wherein The P-layer contacts the second N-buffer layer.

3. The semiconductor device according to claim 1, wherein The P-layer is in contact with the N-drift layer.

4. A method for preparing a semiconductor device according to any one of claims 1 to 3, characterized in that: include: epitaxially growing a first N-buffer layer, a P-layer and an N-drift layer in sequence on an N+ substrate; A P-well layer and a P+ cathode are selectively formed on the surface of the N-drift layer by using ion implantation technology.

5. The preparation method according to claim 4, characterized in that: After epitaxially growing the P-layer and before epitaxially growing the N-drift layer, the method further includes: epitaxially growing a second N-buffer layer; After selectively forming a P-well layer and a P+ cathode on the surface of the N-drift layer by ion implantation technology, the method further comprises: forming a trench penetrating the N+ substrate, the first N-buffer layer and the P-layer, and penetrating at most partially the second N-buffer layer; At the trench, P-type impurities are implanted into the second N-buffer layer to form a P+ anode.

6. The preparation method according to claim 4, characterized in that: After selectively forming a P-well layer and a P+ cathode on the surface of the N-drift layer by ion implantation technology, the method further comprises: forming a trench penetrating the N+ substrate, the first N-buffer layer and the P-layer, and penetrating at most partially the N-drift layer; In the trench, injecting N-type impurities into the N-drift layer to form a second N-buffer layer; At the trench, P-type impurities are implanted into the second N-buffer layer to form a P+ anode.

7. An electronic device, characterized in that: Comprising a semiconductor device as described in any one of claims 1 to 3.

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