MOS device and forming method thereof

Abstract

The invention relates to an MOS device and a forming method thereof. According to the MOS device and the forming method thereof, a source end halo region and a drain end halo region are formed on one side of a source region and one side of a drain region of the MOS device respectively, the source end halo region and the drain end halo region enable the drain end doping concentration on the surface of a channel region to be smaller than the source end doping concentration, and the doping concentration of the drain end halo region on the surface of the channel region is reduced, so that the doping concentration of the drain end halo region on the surface of the channel region is reduced, and the doping concentration of the drain end halo region on the surface of the channel region is reduced. The electric field intensity of the surface of the channel region near the drain PN junction is weakened, so that the hot carrier effect can be inhibited; moreover, the source end halo region and the drain end halo region can act together to inhibit the depletion regions of the source PN junction and the drain PN junction from expanding to the channel region, and the effect of effectively inhibiting the short channel effect can be achieved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a MOS device and a forming method thereof. Background Art

[0002] As the characteristic size of MOSFET (hereinafter referred to as MOS device) is reduced to nanometer scale, the short channel effect such as drain induced barrier lowering (DIBL) has an increasingly prominent impact on device performance. In order to effectively suppress the short channel effect, the lateral non-uniform doping ring implantation (hereinafter referred to as Halo ion implantation) of the channel region with the opposite type to the source / drain is widely used in the manufacture of nanometer scale MOS devices.

[0003] The angle of Halo ion implantation is the angle between the implantation direction and the substrate normal direction. Currently, the industry often performs Halo ion implantation at the same large angle from the source side and the drain side, so that the ion concentration in the channel region of the MOS device presents a distribution with high concentrations at both ends and low concentrations in the middle along the channel length direction. Among them, the highly doped regions formed near the source PN junction and the drain PN junction can effectively inhibit the lateral expansion of the corresponding depletion region to the channel region, reduce charge sharing, and prevent source-drain punch-through, thereby inhibiting the short channel effect.

[0004] The study found that although the short channel effect can be suppressed by the above-mentioned Halo ion implantation, the highly doped Halo ion implantation will also increase the electric field strength near the source PN junction and the drain PN junction. The carriers in the drain region can easily obtain sufficiently high energy, which enhances the hot carrier effect and reduces the reliability of the device.

[0005] In order to avoid enhancing the hot carrier effect, one method proposed by the industry is to implement Halo ion implantation only on the source side to reduce the electric field strength near the drain PN junction, thereby weakening the hot carrier effect at the drain end. However, when the channel length is small, this method cannot effectively control the short channel effect. Another method is to perform Halo ion implantation between the lightly doped region at the source end and the lightly doped region at the drain end to form a halo injection region in the channel region. The halo injection region can not only suppress the short channel effect, but also reduce the peak electric field near the drain PN junction by optimizing the concentration, thereby improving the hot carrier effect. However, the halo injection region will cause the doping concentration in the channel region to increase, enhance the scattering effect of channel carriers, reduce carrier mobility, and affect device performance.

[0006] Therefore, how to suppress the short channel effect while avoiding the enhancement of the hot carrier effect is still a problem that needs to be solved. Summary of the invention

[0007] In order to suppress the short channel effect by using Halo ion implantation and avoid enhancing the hot carrier effect, the present invention provides a method for forming a MOS device and a MOS device.

[0008] In one aspect, the present invention provides a method for forming a MOS device, the method comprising:

[0009] Forming a gate structure on a semiconductor substrate, wherein the semiconductor substrate includes a channel region located below the gate structure, one side of the channel region is used to form a source region, and the other side of the channel region is used to form a drain region;

[0010] Performing halo ion implantation and annealing, a source end halo region located on one side of the source region and a drain end halo region located on one side of the drain region are respectively formed in the semiconductor substrate, wherein the source end halo region and the drain end halo region make the drain end doping concentration on the surface of the channel region less than the source end doping concentration.

[0011] Optionally, a position of a maximum doping concentration in the source end halo region is closer to a surface of the channel region than a position of a maximum doping concentration in the drain end halo region.

[0012] Optionally, performing the halo ion implantation includes:

[0013] Performing source-end halo ion implantation from one side of the source region at a first implantation angle;

[0014] Drain end halo ion implantation is performed from one side of the drain region at a second implantation angle, wherein the first implantation angle is greater than the second implantation angle.

[0015] Optionally, when performing the source-end halo ion implantation, a first mask layer is used to cover the semiconductor substrate surface on the drain region side and the gate structure surface facing the drain region; when performing the drain-end halo ion implantation, a second mask layer is used to cover the semiconductor substrate surface on the source region side and the gate structure surface facing the source region.

[0016] Optionally, the source end halo ion implantation and the drain end halo ion implantation have the same implantation energy and implantation dose.

[0017] Optionally, the first injection angle ranges from 35° to 55°.

[0018] Optionally, the second injection angle ranges from 15° to 35°.

[0019] In one aspect, the present invention provides a MOS device, comprising:

[0020] Semiconductor substrate;

[0021] a gate structure formed on the semiconductor substrate, the semiconductor substrate including a channel region located below the gate structure;

[0022] A source halo region and a drain halo region are formed in the semiconductor substrate, wherein the source halo region and the drain halo region make the drain end doping concentration on the surface of the channel region lower than the source end doping concentration.

[0023] A sidewall formed on a side of the gate structure;

[0024] The source region and the drain region are respectively formed on both sides of the channel region, the source region and the source end halo region are located on one side of the channel region, and the drain region and the drain end halo region are located on the other side of the channel region.

[0025] Optionally, the gate structure includes a gate dielectric layer formed on the surface of the semiconductor substrate, a gate stacked on the gate dielectric layer, a gate oxide layer formed on the top surface of the gate, and an offset sidewall covering the gate dielectric layer, the gate and the side of the gate oxide layer.

[0026] Optionally, the MOS device further includes a source LDD region and a drain LDD region respectively formed on both sides of the gate structure, the source LDD region extends from the source region to under the gate structure, and the drain LDD region extends from the drain region to under the gate structure.

[0027] In the MOS device and the method for forming the MOS device provided by the present invention, a source end halo region located on one side of the source region and a drain end halo region located on one side of the drain region are formed in a semiconductor substrate, and the source end halo region and the drain end halo region make the drain end doping concentration on the surface of the channel region less than the source end doping concentration. Among them, by increasing the source end doping concentration on the surface of the channel region by using the source end halo region, the depletion region of the source PN junction can be effectively suppressed from expanding to the channel region. At the same time, the drain end doping concentration on the surface of the channel region is made less than the source end doping concentration, the purpose is to make the electric field strength on the surface of the channel region near the drain PN junction weaker, so that the hot carrier effect is suppressed, and the drain end halo region can suppress the depletion region of the drain PN junction from expanding to the channel region in the region where its doping concentration is relatively large (the region far away from the surface of the channel region), that is, the source end halo region and the drain end halo region can work together to effectively suppress the depletion region of the source PN junction and the drain PN junction from expanding to the channel region, and achieve the effect of effectively suppressing the short channel effect as a whole. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic flow chart of a method for forming a MOS device according to an embodiment of the present invention.

[0029] Figures 2A to 2G is a cross-sectional schematic diagram of a method for forming a MOS device according to an embodiment of the present invention.

[0030] Figure 3 FIG. 4 is a cross-sectional schematic diagram of a MOS device according to an embodiment of the present invention.

[0031] Figure 4 It is a simulation result of the ion doping concentration near the surface of the channel region of the MOS device according to an embodiment of the present invention and the MOS device obtained by the prior art process.

[0032] Figure 5 It is a simulation result of the electric field strength near the surface of the channel region of the MOS device according to an embodiment of the present invention and the MOS device obtained by the conventional process.

[0033] Figure 6 It is the simulation result of the substrate current of the MOS device according to an embodiment of the present invention and the MOS device obtained by the existing process.

[0034] Figure 7 It is the simulation result of the transfer characteristics of the MOS device according to an embodiment of the present invention and the existing MOS device. DETAILED DESCRIPTION

[0035] The MOS device and the method for forming the same of the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be understood that the drawings of the specification are all in a very simplified form and are all in non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be noted that the order of the steps in the method presented herein is not necessarily the only order for performing these steps, some of the steps described may be omitted and / or some other steps not described herein may be added to the method. It should be understood that spatial relative terms are intended to include different orientations in use or operation in addition to the orientation of the device described in the figure. For example, if the structure in the figure is inverted or positioned in other different ways (such as rotation), the exemplary term "on..." may also include "under..." and other orientation relationships.

[0036] The following combination Figure 1 and Figures 2A to 2G A method for forming a MOS device according to an embodiment of the present invention is introduced.

[0037] Reference Figure 1 and Figure 2A, perform step S1, form a gate structure 10 on a semiconductor substrate 100, the semiconductor substrate 100 includes a channel region CH located below the gate structure 10, one side of the channel region CH is used to form a source region, and the other side of the channel region CH is used to form a drain region.

[0038] The semiconductor substrate 100 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon on insulator (SOI) substrate, a germanium on insulator substrate, a silicon germanium on insulator substrate, or a III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate), or may be other substrates known to those skilled in the art for carrying MOS devices, and a doped region and / or an isolation structure may be formed in the semiconductor substrate 100. Specifically, in this embodiment, at least one doped well region may be formed in the semiconductor substrate 100, and at least one active region may be defined on the top of the doped well region by an isolation region (e.g., a shallow trench isolation (STI)), and the MOS device is formed corresponding to the corresponding active region. Before forming the gate structure, ion implantation may be performed on the active region to adjust the threshold voltage of the MOS device.

[0039] like Figure 2A As shown, in this embodiment, the gate structure 10 includes a gate dielectric layer 101 formed on the surface of a semiconductor substrate 100, a gate 102 stacked on the gate dielectric layer 101, and a gate oxide layer 103 formed on the top surface of the gate 102. It may also include an offset sidewall 104 covering the gate dielectric layer 101, the gate 102, and the side of the gate oxide layer 103. By adjusting the thickness of the offset sidewall 104, the relative position of the gate 102 and the subsequently formed Halo region and LDD region can be adjusted. The present invention is not limited to this. In another embodiment, the gate structure 10 may include a gate dielectric layer 101 formed on the surface of a semiconductor substrate 100, a gate 102 stacked on the gate dielectric layer 101, and a gate oxide layer 103 formed on the top surface of the gate 102, but no offset sidewall is formed on the side of the gate 102.

[0040] The channel region CH is used to form a channel connecting the source region and the drain region of the MOS device on the lower surface of the gate structure 10 when the MOS device is turned on. The channel region CH is, for example, located directly below the gate structure 10. As an example, Figure 2A The left side of the middle channel region CH is used to form a source region, and the right side is used to form a drain region.

[0041] Reference Figure 1 , execute step S2, perform halo ion implantation and annealing, and form a source end halo region located on one side of the source region and a drain end halo region located on one side of the drain region in the semiconductor substrate 100, respectively, wherein the source end halo region and the drain end halo region make the drain end doping concentration on the surface of the channel region CH less than the source end doping concentration.

[0042] The halo ion implantation is performed from both sides of the gate structure 10. For example, the halo ion implantation is performed from the side where the source region is to be formed, and then the halo ion implantation is performed from the side where the drain region is to be formed, but the order of the two can also be reversed.

[0043] As an example, halo ion implantation is first performed from one side of the source region where the MOS device is to be formed, and then halo ion implantation is performed from one side of the drain region where the MOS device is to be formed. Step S2 includes the following process.

[0044] First, in order to prevent ions from entering from the drain region when performing halo ion implantation from the source region, Figure 2B As shown, a patterned first mask layer 105 is first formed, so that the first mask layer 105 covers the surface of the semiconductor substrate 100 and the shallow trench isolation (STI) surface on the drain region side, and also covers the surface of the gate structure 10 facing the drain region side. The first mask layer 105 can be a photoresist or a hard mask (the hard mask can include a silicon nitride layer and / or a silicon oxide layer).

[0045] Next, refer to Figure 2B , source-end halo ion implantation is performed from one side of the source region at a first implantation angle to form the source-end halo region 110. The source-end halo region 110 is formed after the source-end halo ion implantation is completed and an annealing process is performed. The source-end halo ion implantation is obliquely incident to the semiconductor substrate 100. The first implantation angle refers to the angle between the ion implantation direction of the source-end halo ion implantation and the normal direction of the surface of the semiconductor substrate 100. In this embodiment, the range of the first implantation angle is, for example, 35° (in "degrees") to 55°, the implantation energy is, for example, in the range of 5KeV to 50KeV, and the implantation dose is, for example, 2E14 atoms / cm 3 To 3E14 atoms / cm 3 range.

[0046] Afterwards, the first mask layer 105 is removed.

[0047] Next, in order to prevent ions from being injected from the source region when performing halo ion injection from the drain region, as shown in FIG. Figure 2C As shown, a patterned second mask layer 106 is formed, so that the second mask layer 106 covers the surface of the semiconductor substrate 100 and the shallow trench isolation (STI) surface on the source region side, and also covers the surface of the gate structure 10 facing the source region side. The second mask layer 106 can be a photoresist or a hard mask (the hard mask can include a silicon nitride layer and / or a silicon oxide layer). The first mask layer 105 and the second mask layer 106 are, for example, conformally covered in the corresponding area.

[0048] Afterwards, still refer to Figure 2C , drain end halo ion implantation is performed from one side of the drain region at a second implantation angle to form a drain end halo region 120, and the drain end halo region 120 is formed after completing the drain end halo ion implantation and undergoing an annealing process. The drain end halo ion implantation is obliquely incident to the semiconductor substrate 100. The second implantation angle refers to the angle between the ion implantation direction of the drain end halo ion implantation and the normal direction of the surface of the semiconductor substrate 100. In this embodiment, the second implantation angle is smaller than the first implantation angle. The range of the second implantation angle is, for example, 15° to 35°, the implantation energy is, for example, in the range of 5KeV to 50KeV, and the implantation dose is, for example, 2E14 atoms / cm 3 To 3E14 atoms / cm 3 As an example, the source end halo ion implantation has the same implantation energy and the same implantation dose as the drain end halo ion implantation. However, the present invention is not limited thereto, and the source end halo ion implantation and the drain end halo ion implantation may also be different.

[0049] Next, the second mask layer 106 is removed, as shown in FIG. Figure 2D shown.

[0050] By using the above process, a source Halo region 110 and a drain Halo region 120 are respectively formed in the semiconductor substrate 100 (specifically in the corresponding active region), and the two are asymmetrically located on both sides of the channel region CH. The doping concentrations of the source Halo region 110 and the drain Halo region 120 in the semiconductor substrate 100 are not uniform, for example, but are regions with a maximum doping concentration and regions with a smaller doping concentration around the region with the maximum doping concentration. Optionally, the maximum doping concentration position of the source halo region 110 is closer to the surface of the channel region CH than the maximum doping concentration position of the drain halo region 120. The maximum doping concentration position of the source halo region 110 is, for example, located on the surface of the channel region CH or in a region below the surface of the channel region CH and adjacent to the surface of the channel region CH, and the maximum doping concentration position of the drain halo region 120 is, for example, located below the surface of the channel region CH and lower than the maximum doping concentration position of the source halo region 110. Figure 2D The ranges of the source Halo region 110 and the drain Halo region 120 are shown for illustration only. Depending on specific settings, the ranges of the source Halo region 110 and the drain Halo region 120 may be different.

[0051] By forming the source end halo region 110 and the drain end halo region 120, the doping concentration on the surface of the channel region CH can be adjusted. Specifically, by controlling the doping concentration distribution and / or coverage area of ​​the source end halo region 110 and the drain end halo region 120, the doping concentration on the surface of the channel region CH adjacent to the source PN junction (i.e., the source end doping concentration on the surface of the channel region CH) and / or the doping concentration on the surface of the channel region CH adjacent to the drain PN junction (i.e., the drain end doping concentration on the surface of the channel region CH) can be adjusted.

[0052] In the present embodiment, by controlling the formation areas of the source end halo region 110 and the drain end halo region 120, the influence of the source end halo region 110 on the source end doping concentration on the surface of the channel region CH is greater than the influence of the drain end halo region 120 on the drain end doping concentration on the surface of the channel region CH; specifically, the source end halo region 110 is used to increase the source end doping concentration on the surface of the channel region CH, while the drain end halo region 120 does not substantially change or increases the drain end doping concentration on the surface of the channel region CH to a small extent, so that the drain end doping concentration on the surface of the channel region CH is less than the source end doping concentration.

[0053] In this embodiment, in order to make the source end halo region 110 have a greater influence on the source end doping concentration on the surface of the channel region CH than the drain end halo region 120 has on the drain end doping concentration on the surface of the channel region CH, the first injection angle used to form the source end halo region 110 is greater than the second injection angle used to form the drain end halo region 120, and the injection energy and injection dose of the source end halo ion injection and the drain end halo ion injection are the same. However, the present invention is not limited to this. In other embodiments, other means may be used, such as controlling the injection energy, injection dose, injection angle, and injection times of the source end halo ion injection and the drain end halo ion injection, so that the drain end doping concentration on the surface of the channel region CH is less than the source end doping concentration.

[0054] After completing the above step S2, refer to Figure 2E , LDD implantation can be performed to form source end LDD regions (such as Figure 2E "LDD1" shown) and the drain LDD region (such as Figure 2E The LDD implantation type is opposite to the source end halo ion implantation and the drain end halo ion implantation. The LDD implantation direction is, for example, along the normal direction of the surface of the semiconductor substrate 100.

[0055] Reference Figure 2F, a sidewall spacer may be further formed on the side of the gate structure 10. In this embodiment, the gate structure 10 includes an offset sidewall spacer 104, and a main sidewall spacer 107 may be formed on the outer side of the offset sidewall spacer 104. The thickness of the main sidewall spacer 107 may be adjusted as needed.

[0056] Reference Figure 2G , source and drain implantation is performed on the semiconductor substrate 100 to form a source region S and a drain region D on both sides of the gate structure 10, respectively. The source region S and the above-mentioned source terminal halo region 110 are located on one side of the channel region CH, and the drain region D and the above-mentioned drain terminal halo region 120 are located on the other side of the channel region CH. The implantation type of the source and drain implantation is the same as the implantation type of the above-mentioned LDD implantation, and the implantation dose is greater than the implantation dose of the above-mentioned LDD implantation. The implantation direction of the source and drain implantation is, for example, along the normal direction of the surface of the semiconductor substrate 100. When performing the above-mentioned halo ion implantation, LDD implantation and source and drain implantation, annealing may be performed after the implantation is completed to activate the implanted ions. According to specific needs, annealing may be performed after a single implantation is completed, or after multiple implantations are completed.

[0057] By using the method for forming a MOS device described in the above embodiment, the source end Halo region 110 formed increases the source end doping concentration on the surface of the channel region CH, which can effectively inhibit the depletion region of the source PN junction of the MOS device from extending to the channel region CH; since during the operation of the transistor, a voltage is usually applied to the drain end, but no voltage is applied to the source end, the source end carriers are less affected by the source PN junction electric field, and thus the source end doping concentration on the surface of the channel region CH does not affect the hot carrier effect. In this embodiment, the drain end doping concentration on the surface of the channel region CH is less than the source end doping concentration, which helps to reduce the hot carrier effect. The electric field strength on the surface of the channel region CH near the weak drain PN junction reduces the electric field on the drain surface, thereby suppressing the hot carrier effect. Moreover, since the depletion region of the drain PN junction also extends below the channel region CH, the drain end halo region 120 can also play a role in suppressing the diffusion of the drain PN junction depletion region far away from the surface of the channel region CH to the channel region CH. It can be seen that the source end halo region 110 and the drain end halo region 120 can work together to suppress the diffusion of the depletion region to suppress the short channel effect, thereby ensuring that the short channel effect and the related drain induced barrier lowering effect (DIBL) will not deteriorate.

[0058] The embodiment of the present invention also relates to a MOS device. The MOS device is formed by, for example, the method for forming the MOS device described in the above embodiment. Figure 3 , the MOS device comprises:

[0059] A semiconductor substrate 100;

[0060] A gate structure 10 formed on the semiconductor substrate 100, wherein the semiconductor substrate 100 includes a channel region CH located below the gate structure 10;

[0061] A source halo region 110 and a drain halo region 120 are formed in the semiconductor substrate 100, wherein the source halo region 110 and the drain halo region 120 make the drain end doping concentration on the surface of the channel region CH lower than the source end doping concentration;

[0062] A sidewall spacer (eg, a main sidewall spacer 107 ) formed on a side surface of the gate structure 10 ;

[0063] The source region S and the drain region D are respectively formed on both sides of the channel region CH, the source region S and the source end halo region 110 are located on one side of the channel region CH, and the drain region D and the drain end halo region 120 are located on the other side of the channel region CH.

[0064] The semiconductor substrate includes an active region defined by shallow trench isolation STI, and the channel region CH, the source end halo region 110, the drain end halo region 120, the source region S and the drain region D are, for example, located on the surface of the active region.

[0065] like Figure 3 As shown, optionally, the gate structure 10 may include a gate dielectric layer 101 formed on the surface of a semiconductor substrate 100, a gate 102 stacked on the gate dielectric layer 101, a gate oxide layer 103 formed on the top surface of the gate 102, and an offset sidewall 104 covering the gate dielectric layer 101, the gate 102 and the side of the gate oxide layer 103. The MOS device may also include a source LDD region (such as a source LDD region) formed in the semiconductor substrate 100 on both sides of the gate structure 10. Figure 3 "LDD1" shown) and the drain LDD region (such as Figure 3 As shown in “LDD2”, the source end LDD region extends from the source region S to below the gate structure 10, and the drain end LDD region extends from the drain region D to below the gate structure 10.

[0066] The doping concentration distribution and / or coverage area of ​​the source halo region 110 and the drain halo region 120 can be adjusted, and the drain doping concentration on the surface of the channel region CH can be made lower than the source doping concentration by using the source halo region 110 and the drain halo region 120. For example, the maximum doping concentrations of the source halo region 110 and the drain halo region 120 can be located at different heights in the active region by adjusting the injection angle, and specifically, the maximum doping concentration position of the source halo region 110 can be closer to the surface of the channel region than the maximum doping concentration position of the drain halo region 120, thereby having different effects on the doping concentration on the surface of the channel region CH. The source doping concentration is, for example, greater than the doping concentration in the middle region of the surface of the channel region CH, and the drain doping concentration is, for example, greater than or equal to the doping concentration in the middle region of the surface of the channel region CH.

[0067] Figures 4 to 7 The results of simulating the characteristics of a MOS device (marked as "MOS1") of an embodiment of the present invention and a MOS device (marked as "MOS2") obtained by using the existing process for comparison, wherein in the MOS device of the embodiment of the present invention, the first injection angle is 45°, and the second injection angle is 15°. In the MOS device manufactured by the existing process, the injection angles of the halo ion injection from the source region side and the drain region side are both 45°. In addition, the injection parameters (including injection energy and injection dose) of the halo ion injection of the MOS device of the embodiment of the present invention and the MOS device manufactured by the existing process are the same.

[0068] Figure 4 The simulation results of ion doping concentration of two MOS devices are shown, where the ion doping concentration shown is the net doping concentration. Figure 4 The curve with high sides and low center in the middle area represents the net doping concentration in the surface area of ​​the channel region (the test depth is 10 nm). Figure 5 The simulation results of the electric field strength in the surface area of ​​the channel region of two MOS devices are shown. Figure 4 It can be seen that the net doping concentration of the channel region CH surface near the drain PN junction of MOS1 is less than the net doping concentration of the channel region CH surface near the drain PN junction of MOS2, while the net doping concentrations of the two near the source PN junction are basically the same, indicating that the source end halo region increases the source end doping concentration of the channel region CH surface, and the change in the drain end doping concentration of the drain end halo region of MOS1 to the channel region CH surface is less than the change in the drain end doping concentration of the drain end halo region of MOS2 to the channel region CH surface. Figure 5 It can be seen that the peak electric field on the surface of the channel region CH near the drain PN junction of MOS1 is also significantly reduced compared to MOS2.

[0069] Figure 6 The simulation results of substrate current of two MOS devices are shown. Figure 6 It can be seen that the substrate current of MOS1 is small, indicating that when the maximum doping concentration position of the drain halo region 120 moves downward, the drain doping concentration on the surface of the channel region CH decreases, and the substrate current decreases, further proving that the MOS device using the embodiment of the present invention can improve the hot carrier effect.

[0070] Figure 7 The figure shows the simulation results of the transfer characteristics of two MOS devices, where the drain-source voltage Vds corresponding to the lower gate voltage-drain current curve is 0.05V, and the drain-source voltage Vds corresponding to the upper gate voltage-drain current curve is 1.1V. Figure 7 As shown, the transfer characteristics of the two MOS devices are basically the same, indicating that when the method described in this embodiment is used to make the drain end doping concentration on the surface of the channel region CH less than the source end doping concentration, the transfer characteristics of the MOS device do not change significantly, and the drain-induced barrier lowering effect does not change significantly, indicating that the MOS device using this embodiment will not aggravate the short channel effect and can achieve the same effect of suppressing the short channel effect as the existing process.

[0071] In addition, during the operation of the transistor, voltage is usually applied only to one end of the drain region D, while no voltage is applied to the source region S. The carriers in the source region S are less affected by the electric field of the source PN junction. Therefore, the source end halo region 110 is used to increase the source end doping concentration on the surface of the channel region CH, which will not affect the hot carrier effect. Moreover, although the doping concentration on the surface of the channel region CH near the drain PN junction is relatively low, the doping concentration of the drain end halo region 120 is increased in the deep part of the drain PN junction below the channel region CH, which can also play a role in suppressing the extension of the depletion region of the drain PN junction to the channel region CH. Therefore, short channel effects such as the drain induced barrier lowering effect (DIBL) will not be aggravated, and the hot carrier effect can be significantly suppressed. On the whole, the short channel effect can still be suppressed, ensuring that the short channel effect and the related drain induced barrier lowering effect (DIBL) will not deteriorate.

[0072] In the MOS device of the embodiment of the present invention, the source end halo region 110 and the drain end halo region 120 make the drain end doping concentration on the surface of the channel region CH lower than the source end doping concentration. The source end halo region 110 and the drain end halo region 120 form an asymmetric halo injection region structure at both ends of the channel region CH, which can suppress the short channel effect while weakening the electric field strength on the surface of the channel region CH near the drain PN junction, thereby suppressing the hot carrier effect.

[0073] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0074] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for forming a MOS device, characterized in that: include: Forming a gate structure on a semiconductor substrate, wherein the semiconductor substrate includes a channel region located below the gate structure, one side of the channel region is used to form a source region, and the other side of the channel region is used to form a drain region; Performing halo ion implantation and annealing, a source end halo region located on one side of the source region and a drain end halo region located on one side of the drain region are respectively formed in the semiconductor substrate, wherein the source end halo region and the drain end halo region make the drain end doping concentration on the surface of the channel region less than the source end doping concentration.

2. The forming method according to claim 1, characterized in that: The maximum doping concentration position of the source end halo region is closer to the surface of the channel region than the maximum doping concentration position of the drain end halo region.

3. The forming method according to claim 1, characterized in that: The halo ion implantation comprises: Performing source-end halo ion implantation from one side of the source region at a first implantation angle; Drain end halo ion implantation is performed from one side of the drain region at a second implantation angle, wherein the first implantation angle is greater than the second implantation angle.

4. The forming method according to claim 3, characterized in that: When performing the source-end halo ion implantation, a first mask layer is used to cover the semiconductor substrate surface on the drain region side and the gate structure surface facing the drain region; when performing the drain-end halo ion implantation, a second mask layer is used to cover the semiconductor substrate surface on the source region side and the gate structure surface facing the source region.

5. The forming method according to claim 3, characterized in that: The injection energy and injection dose of the source end halo ion injection and the drain end halo ion injection are the same.

6. The forming method according to claim 3, characterized in that: The first injection angle ranges from 35° to 55°.

7. The forming method according to claim 3, characterized in that: The second injection angle ranges from 15° to 35°.

8. A MOS device, characterized in that: The MOS device comprises: Semiconductor substrate; a gate structure formed on the semiconductor substrate, the semiconductor substrate including a channel region located below the gate structure; A source halo region and a drain halo region formed in the semiconductor substrate, wherein the source halo region and the drain halo region make the drain end doping concentration on the surface of the channel region lower than the source end doping concentration; A sidewall formed on a side of the gate structure; The source region and the drain region are respectively formed on both sides of the channel region, the source region and the source end halo region are located on one side of the channel region, and the drain region and the drain end halo region are located on the other side of the channel region.

9. The MOS device according to claim 8, characterized in that: The gate structure includes a gate dielectric layer formed on the surface of the semiconductor substrate, a gate stacked on the gate dielectric layer, a gate oxide layer formed on the top surface of the gate, and an offset sidewall covering the gate dielectric layer, the gate and the side of the gate oxide layer.

10. The MOS device according to claim 8, characterized in that: Also includes: A source LDD region and a drain LDD region are respectively formed on both sides of the gate structure, wherein the source LDD region extends from the source region to below the gate structure, and the drain LDD region extends from the drain region to below the gate structure.

Images