Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a first surface; forming an epitaxial layer on the first surface; forming a first photoresist layer on the epitaxial layer; etching the epitaxial layer by taking the first photoresist layer as a mask to form a groove located in the first region; forming a first doped column in the groove and a second doped column in the second region, wherein the first doped column and the second doped column are arranged along a second direction; forming a second photoresist layer with a body region pattern on the epitaxial layer; and injecting ions into the epitaxial layer by taking the second photoresist layer as a mask to form body regions, and arranging the body regions along the first direction. The body region, the first doped column and the second doped column are located in the different directions of the epitaxial layer respectively, the situation that the space size of the super-junction MOS tube device is limited by the existence of the first doped column and the second doped column is avoided, the channel length of the super-junction MOS tube device is not limited by the space size, and then the channel length is increased.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Superjunction MOS tube is a new type of high-voltage MOS tube. Its advantage is that it can provide an on-resistance that is one order of magnitude smaller than that of traditional high-voltage MOS tubes while being able to withstand high-voltage operation. In addition to low on-resistance, it also has the advantages of low power consumption and low switching time.

[0003] However, there are still many problems in the formation process of existing super junction MOS tube devices. Summary of the invention

[0004] The technical problem solved by the present invention is how to improve the performance of super junction MOS tube devices.

[0005] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first surface; using an epitaxial process to form an epitaxial layer on the first surface, the epitaxial layer comprising a plurality of first regions and second regions located between adjacent first regions, the first regions and the second regions being arranged along a second direction; forming a first photoresist layer having a first region pattern on the epitaxial layer, the first photoresist layer exposing a surface of the first region; using the first photoresist layer as a mask, etching the epitaxial layer to form a groove located in the first region; forming a first doped column in the groove, and a second doped column located in the first region; The second doped column in the second region, the first doped column and the second doped column are arranged along the second direction; a second photoresist layer with a body region pattern is formed on the epitaxial layer, the second photoresist layer is arranged along the first direction, the first direction and the second direction are parallel to the substrate surface, and the first direction is perpendicular to the second direction; using the second photoresist layer as a mask, ions are injected into the epitaxial layer to form a body region, and the body region is arranged along the first direction; a gate material layer is formed on the epitaxial layer; using a photolithography process, the gate material layer is etched until the body region is exposed to form a plurality of gates, and each of the gates is separately located on an adjacent body region.

[0006] Optionally, the step of forming the body region further includes: injecting first ions into the body region; and injecting second ions into the epitaxial layer between adjacent body regions to form a JFET region.

[0007] Optionally, the type of the first doped column is opposite to the type of the second doped column, the type of the first ion is opposite to the type of the second ion, and the implantation concentration range of the first ion in the body region is 1E12 ions / cm 2 To 1E16 ions / cm2 The implantation concentration of the second ion in the JFET region is in the range of 1E12 ions / cm 2 To 1E16ions / cm 2 .

[0008] Optionally, after the step of forming a plurality of gates, the method further includes: using the gates as masks, injecting second ions into the body regions on both sides of the gates to form source regions.

[0009] Optionally, the implantation concentration of the second ions in the source region is in the range of 1E12 ions / cm 2 To 1E16 ions / cm 2 .

[0010] Optionally, the substrate further includes a second surface, and after the step of forming a plurality of gates, further includes: depositing a source metal layer on the plurality of gates; and depositing a drain metal layer on the second surface.

[0011] Correspondingly, the present invention also provides a semiconductor structure, comprising: a substrate, the substrate comprising a first surface; an epitaxial layer, located on the first surface, the epitaxial layer comprising a plurality of first regions, and a second region located between adjacent first regions, the first region and the second region being arranged along a second direction; a first doped column, located in the first region; a second doped column, located in the second region, the first doped column and the second doped column being arranged along the second direction; a plurality of body regions, separately located in the epitaxial layer, and the body regions being arranged along a first direction, the first direction and the second direction being parallel to the substrate surface, and the first direction being perpendicular to the second direction; a plurality of gates, each of the gates being separately located on adjacent body regions.

[0012] Optionally, the semiconductor structure further includes: a JFET region located in the epitaxial layer between adjacent body regions, wherein the JFET region has second ions and the body region has first ions.

[0013] Optionally, a type of the first doping column is opposite to a type of the second doping column, and a type of the first ion is opposite to a type of the second ion.

[0014] Optionally, the semiconductor structure further includes: a source region located in the body region on both sides of the gate, and the source region has second ions.

[0015] Optionally, the substrate further includes a second surface, and the semiconductor structure further includes: a source metal layer located on the plurality of gates; and a drain metal layer located on the second surface.

[0016] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0017] In the semiconductor structure of the technical solution of the present invention, the epitaxial layer includes a first doped column and a second doped column, and the first doped column and the second doped column are arranged along the second direction. The epitaxial layer also includes a body region, and the body region is arranged along the first direction. Compared with the solution in the prior art solution in which the first doped column and the second doped column are still present on the lower surface of the body region, the body region and the first doped column and the second doped column in the present invention are respectively located in different directions of the epitaxial layer, avoiding the existence of the first doped column and the second doped column to limit the spacing size of the super junction MOS tube device, so that the channel length of the super junction MOS tube device is not affected by the spacing size, thereby achieving an increase in the channel length and improving the performance of the super junction MOS tube device.

[0018] In the method for forming a semiconductor structure of the technical solution of the present invention, a first doped column and a second doped column are formed in the epitaxial layer, and the first doped column and the second doped column are arranged along the second direction, and a body region is formed in the epitaxial layer, and the body region is arranged along the first direction. Compared with the prior art solution which further includes forming the first doped column and the second doped column on the lower surface of the body region before forming the body region, the body region and the first doped column and the second doped column in the present invention are respectively located in different directions of the epitaxial layer, avoiding the existence of the first doped column and the second doped column to limit the spacing size of the super junction MOS tube device, so that the channel length of the super junction MOS tube device is not affected by the spacing size, thereby achieving an increase in the channel length and improving the performance of the super junction MOS tube device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the structure of a semiconductor structure;

[0020] Figure 2 It is a schematic diagram of the structure of another semiconductor structure;

[0021] Figure 3 is a schematic diagram of test results for a semiconductor structure;

[0022] Figures 4 to 14 is a schematic diagram of a process for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0023] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0024] Please refer to the current structure of super junction MOS tube device Figure 1, comprising: a substrate, the substrate comprising a first surface a; an epitaxial layer 100, located on the first surface a; a first doped column 101, located on the epitaxial layer 100; a second doped column 102, adjacent to the first doped column 101; a body region 103, located on the first doped column 101; and a plurality of gates 104, each of the gates 104 being separately located on an adjacent body region 103.

[0025] It can be seen that the gate 104 in the super junction MOS transistor device is located on the body region 103, so the super junction MOS transistor device is a Planner gate structure, and the channel is located in the body region 103 under the gate 104 and is a horizontal channel, that is, Figure 1 The red circle part 105, but the spacing dimension P1 of the super junction MOS tube device in the above scheme is the sum of the widths of the first doped column 101 and the second doped column 102, and thus under the limitation of the spacing dimension, the channel lengths on both sides are also limited, resulting in a reduction in the channel length, an increase in resistance, and a slowdown in the switching speed of the device, thereby reducing the performance of the super junction MOS tube device.

[0026] At present, in order to solve the above problems, the technical solution of the present invention provides another structure of super junction MOS tube device. Please refer to Figure 2 , substrate, the substrate comprising a first surface a; an epitaxial layer 200, located on the first surface a; a first doped column 201, located on the epitaxial layer 200; a second doped column 202, adjacent to the first doped column 201; a body region 203, located on the first doped column 201; and a plurality of gates 204, located in the epitaxial layer 200 and adjacent to the body region 203.

[0027] In the above scheme, the gate 204 in the super junction MOS transistor device is located in the epitaxial layer 200, and the gate 204 is adjacent to the body region 203, so the super junction MOS transistor device is a Trench gate structure, and the channel is located in the body region 203 connected to the side wall of the gate 204, and at this time the channel is a vertical channel, that is, Figure 2 The red circle portion 205 in the middle, and the pitch size P2 of the super junction MOS transistor device in the above scheme is the sum of the widths of the first doped column 201 and the second doped column 202. Therefore, under the limitation of the pitch size, the length of the vertical channel is relative to Figure 1 The length of the horizontal channel in the embodiment is increased.

[0028] In addition, please refer to Figure 3 , Figure 3 Figure (a) shows the test results of the Planner gate structure. Figure 3 Figure (b) shows the test results of the Trench gate structure, where: Figure 3 Figure (a) and Figure 3 The horizontal axis of Figure (b) is the gate voltage. Figure 3 Figure (a) and Figure 3 The vertical axis of Figure (b) is the gate current. Figure 3 The gate voltage range in (a) is -60V to 80V. Figure 3 The gate voltage range of Figure (b) is -50V to 40V, so the leakage current of the Trench gate structure is greater than the leakage current of the Plannergate structure. That is, the Trench gate structure has a large leakage problem due to the problem of the device structure itself, which will also affect the performance of the super junction MOS tube device.

[0029] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same, wherein the epitaxial layer includes a first doped column and a second doped column, and the first doped column and the second doped column are arranged along the second direction, and the epitaxial layer also includes a body region, and the body region is arranged along the first direction. Compared with the solution in the prior art solution in which the first doped column and the second doped column are still present on the lower surface of the body region, the body region and the first doped column and the second doped column in the present invention are respectively located in different directions of the epitaxial layer, thereby avoiding the existence of the first doped column and the second doped column to limit the spacing size of the super junction MOS tube device, so that the channel length of the super junction MOS tube device is not affected by the spacing size, thereby achieving an increase in the channel length and improving the performance of the super junction MOS tube device.

[0030] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0031] Please refer to Figure 4 as well as Figure 5 , Figure 4 It is a stereogram. Figure 5 yes Figure 4 In the cross-sectional view along the AA1 direction, a substrate 300 is provided, and the substrate 300 includes a first surface a; an epitaxial layer 301 is formed on the first surface a by using an epitaxial process.

[0032] In this embodiment, the material of the substrate 300 is silicon.

[0033] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0034] In one embodiment, the epitaxial layer 301 is formed by a vapor phase epitaxy process, and the thickness of the epitaxial layer 301 is in a range of 50 micrometers to 60 micrometers.

[0035] Please refer to Figure 6 , Figure 6 It is a three-dimensional diagram, the epitaxial layer 301 includes a plurality of first regions I and second regions II located between adjacent first regions I, the first regions I and the second regions II are arranged along a second direction Y, a first photoresist layer (not shown in the figure) having a pattern of the first regions I is formed on the epitaxial layer 301, the first photoresist layer exposes the surface of the first region I; the epitaxial layer 301 is etched using the first photoresist layer as a mask to form a groove located in the first region I; a first doped column 3011 and a second doped column 3012 located in the second region II are formed in the groove (not shown in the figure), the first doped column 3011 and the second doped column 3012 are arranged along the second direction Y.

[0036] In some embodiments of the present invention, the first doped column 3011 is a P column, and the second doped column 3012 is an N column.

[0037] In other embodiments, the first doped column is an N column, and the second doped column is a P column.

[0038] In some embodiments of the present invention, after the step of forming the first doped column 3011 in the trench, the step further includes: planarizing the top surface of the first doped column 3011 until the top surface of the first doped column 3011 is flush with the second doped column 3012 .

[0039] In a specific embodiment, the planarization method includes: a chemical mechanical polishing process.

[0040] Please refer to Figure 7 , Figure 7 yes Figure 6 In the cross-sectional view along the AA1 direction, a second photoresist layer 3021 having a body region pattern is formed on the epitaxial layer 301, and the second photoresist layer 3021 is arranged along a first direction X. The first direction X and the second direction Y are parallel to the surface of the substrate 300, and the first direction X is perpendicular to the second direction Y.

[0041] Please refer to Figure 8 , Figure 8 The viewing direction and Figure 7 Consistently, using the second photoresist layer as a mask, ions are implanted into the epitaxial layer 301 to form a body region 302 , and the body region 302 is arranged along the first direction X.

[0042] In some embodiments of the present invention, the ions in the body region 302 are first ions, and the implantation concentration of the first ions in the body region 302 is in the range of 1E12 ions / cm 2 To 1E16 ions / cm 2 .

[0043] In the above scheme, a first doping column 3011 and a second doping column 3012 are formed in the epitaxial layer 301, and the first doping column 3011 and the second doping column 3012 are arranged along the second direction Y, and a body region 302 is formed in the epitaxial layer 301, and the body region 302 is arranged along the first direction X. Compared with the scheme in the prior art that further includes forming the first doping column and the second doping column on the lower surface of the body region before forming the body region, the body region 302 and the first doping column 3011 and the second doping column 3012 in the present invention are respectively located in different directions of the epitaxial layer 301, thereby avoiding the existence of the first doping column and the second doping column to limit the spacing size of the super junction MOS tube device, so that the channel length of the super junction MOS tube device is not affected by the spacing size, thereby achieving an increase in the channel length and improving the performance of the super junction MOS tube device.

[0044] Please refer to Fig. 9 , Fig. 9 The viewing direction and Figure 8 Consistently, second ions are implanted into the epitaxial layer 301 between the adjacent body regions 302 to form a JFET region 303 .

[0045] In some embodiments of the present invention, the type of the first ions is opposite to the type of the second ions, and the implantation concentration of the first ions in the body region 302 is in the range of 1E12 ions / cm 2 To 1E16 ions / cm 2 The implantation concentration of the second ions in the JFET region 303 is in the range of 1E12 ions / cm 2 To 1E16 ions / cm 2 .

[0046] In some embodiments of the present invention, the type of the first ion is P type, and the type of the second ion is N type.

[0047] In other embodiments, the type of the first ion is N-type, and the type of the second ion is P-type.

[0048] Please refer to Fig.10 , Fig.10 The viewing direction and Fig. 9Consistently, a gate material layer is formed on the epitaxial layer 301 ; a photolithography process is used to etch the gate material layer until the body region 302 is exposed, thereby forming a plurality of gates 304 , each of which is separately located on an adjacent body region 302 .

[0049] In a specific embodiment, a gate oxide layer 3042 is formed on the epitaxial layer 301 ; a gate material layer is formed on the epitaxial layer 301 ; a photolithography process is used to etch the gate material layer until the body region 302 is exposed to form a plurality of gate layers 3041 , and each gate 304 is separately located on an adjacent body region 302 .

[0050] In this embodiment, the process of forming the gate oxide layer 3042 is a growth process.

[0051] In this embodiment, the thickness of the gate oxide layer 3042 ranges from 800 angstroms to 1000 angstroms.

[0052] In this embodiment, the material of the gate oxide layer 3042 is silicon nitride, silicon oxide or borophosphosilicate glass.

[0053] In this embodiment, the material of the gate layer 3041 is single crystal silicon or polycrystalline silicon.

[0054] Please refer to Fig.11 , Fig.11 The viewing direction and Fig.10 Consistently, a third photoresist layer (not shown in the figure) is formed on the substrate, and the third photoresist layer exposes a portion of the surface of the gate oxide layer 3042; using the third photoresist layer as a mask, second ions are injected into the body region 302 on both sides of the gate layer 3041 to form a source region 305.

[0055] In some embodiments of the present invention, the implantation concentration of the second ions in the source region 305 is in the range of 1E12 ions / cm 2 To 1E16 ions / cm 2 .

[0056] Please refer to Fig.12 , Fig.12 The viewing direction and Fig.11 Consistently, an interlayer dielectric layer 3043 is formed on the sidewall surface and the top surface of the gate layer 3041 .

[0057] In some embodiments of the present invention, the process for forming the interlayer dielectric layer 3043 is a chemical vapor deposition process.

[0058] In this embodiment, the material of the interlayer dielectric layer 3043 is silicon nitride or borophosphosilicate glass, and the thickness of the interlayer dielectric layer 3043 is in the range of 0.5 micrometer to 1 micrometer.

[0059] Please refer to Fig.13 , Fig.13 The viewing direction and Fig.12 Consistently, a dry etching process is used to etch away the gate oxide layer 3042 until the body region 302 is exposed.

[0060] In some embodiments of the present invention, the parameters of the dry etching process include: the chamber pressure is 5.5mT to 50mT, the source power is 180W to 1000W, the etching gas contains one or more combinations of CH2F2, Cl2, HBr, He and O2, the gas flow rate is 20sccm to 200sccm, and the etching time is 6s to 40s.

[0061] In other embodiments, after removing the gate oxide layer on the body region, the method further includes: forming a conductive layer on a portion of the body region.

[0062] Wherein, the material of the conductive layer includes titanium and titanium nitride.

[0063] Please refer to Fig.14 , Fig.14 It is a three-dimensional diagram, and after the step of forming a plurality of gates 304 , the step further includes: depositing a source metal layer 306 on the plurality of gates 304 .

[0064] In some embodiments of the present invention, the method for forming the source metal layer 306 is a physical vapor deposition process, the parameters of the physical vapor deposition process are a deposition rate of 350 angstroms to 450 angstroms per minute, a deposition time of 12 seconds to 20 seconds, the material of the source metal layer 306 is AlCu, and the thickness of the source metal layer 306 ranges from 80 angstroms to 130 angstroms.

[0065] In some embodiments of the present invention, the substrate 300 further includes a second surface b, and a drain metal layer 307 is deposited on the second surface b.

[0066] In some embodiments of the present invention, the method for forming the drain metal layer 307 is a physical vapor deposition process, the parameters of the physical vapor deposition process are a deposition rate of 350 angstroms to 450 angstroms per minute, a deposition time of 12 seconds to 20 seconds, the material of the drain metal layer 307 is AlCu, and the thickness of the drain metal layer 307 ranges from 80 angstroms to 130 angstroms.

[0067] Accordingly, please continue to refer to Fig.14The present invention also provides a semiconductor structure, including: a substrate 300, the substrate 300 includes a first surface a; an epitaxial layer 301, located on the first surface a, the epitaxial layer includes a plurality of first regions, and a second region located between adjacent first regions, the first region and the second region are arranged along a second direction; a first doped column, located in the first region; a second doped column, located in the second region, the first doped column and the second doped column are arranged along the second direction; a plurality of body regions 302, separately located in the epitaxial layer 301, and the body regions are arranged along a first direction, the first direction and the second direction are parallel to the substrate surface, and the first direction is perpendicular to the second direction; a plurality of gates 304, each of the gates 304 is separately located on adjacent body regions 302.

[0068] In a specific embodiment, the gate 304 includes a gate layer 3041 , a gate oxide layer 3042 located on the bottom surface of the gate layer 3041 , and an interlayer dielectric layer 3043 located on the sidewall surface and the top surface of the gate layer 3041 .

[0069] In a specific embodiment, the thickness of the gate oxide layer 3042 ranges from 800 angstroms to 1000 angstroms, and the thickness of the interlayer dielectric layer 3043 ranges from 0.5 micrometers to 1 micrometer.

[0070] In this embodiment, the material of the gate oxide layer 3042 is silicon nitride or silicon oxide.

[0071] In this embodiment, the material of the gate layer 3041 is single crystal silicon or polycrystalline silicon.

[0072] In this embodiment, the material of the interlayer dielectric layer 3043 is silicon nitride or borophosphosilicate glass.

[0073] In some embodiments of the present invention, the first doped column is a P column, and the second doped column is an N column.

[0074] In other embodiments, the first doped column is an N column, and the second doped column is a P column.

[0075] In some embodiments of the present invention, the semiconductor structure further includes: a JFET region 303 located in the epitaxial layer 301 between adjacent body regions 302 , wherein the JFET region 303 has second ions and the body region 302 has first ions.

[0076] In one embodiment, the type of the first ion is opposite to the type of the second ion.

[0077] In a specific embodiment, the type of the first ion is P type, and the type of the second ion is N type.

[0078] In some embodiments of the present invention, the type of the first ion is opposite to the type of the second ion.

[0079] In some embodiments of the present invention, the semiconductor structure further includes: a source region 305 located in the body region 302 on both sides of the gate 304 , and the source region 305 has second ions.

[0080] In some embodiments of the present invention, the substrate 300 further includes a second surface b, and the semiconductor structure further includes: a source metal layer 306 located on the plurality of gates 304; and a drain metal layer 307 located on the second surface b.

[0081] In the above scheme, the epitaxial layer 301 includes a first doping column 3011 and a second doping column 3012, and the first doping column 3011 and the second doping column 3012 are arranged along the second direction Y. The epitaxial layer 301 also includes a body region 302, and the body region 302 is arranged along the first direction X. Compared with the scheme in the prior art scheme in which the first doping column and the second doping column are still present on the lower surface of the body region, the body region 302 and the first doping column 3011 and the second doping column 3012 in the present invention are respectively located in different directions of the epitaxial layer 301, thereby avoiding the existence of the first doping column and the second doping column to limit the spacing size of the super junction MOS tube device, so that the channel length of the super junction MOS tube device is not affected by the spacing size, thereby achieving an increase in the channel length and improving the performance of the super junction MOS tube device.

[0082] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first surface; Using an epitaxial process, forming an epitaxial layer on the first surface, wherein the epitaxial layer includes a plurality of first regions and second regions located between adjacent first regions, and the first regions and the second regions are arranged along a second direction; forming a first photoresist layer having a first region pattern on the epitaxial layer, wherein the first photoresist layer exposes a surface of the first region; Using the first photoresist layer as a mask, etching the epitaxial layer to form a groove in the first region; forming a first doped column in the trench and a second doped column in the second region, wherein the first doped column and the second doped column are arranged along a second direction; Forming a second photoresist layer having a body region pattern on the epitaxial layer, wherein the second photoresist layer is arranged along a first direction, the first direction and the second direction are parallel to a substrate surface, and the first direction is perpendicular to the second direction; Using the second photoresist layer as a mask, ions are implanted into the epitaxial layer to form a body region, wherein the body region is arranged along a first direction; forming a gate material layer on the epitaxial layer; The gate material layer is etched by photolithography until the body region is exposed, thereby forming a plurality of gates, each of which is independently located on an adjacent body region.

2. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the body region further comprises: implanting first ions into the body region; Second ions are implanted into the epitaxial layer between adjacent body regions to form a JFET region.

3. The method for forming a semiconductor structure according to claim 2, wherein: The type of the first doped column is opposite to the type of the second doped column, the type of the first ion is opposite to the type of the second ion, and the implantation concentration range of the first ion in the body region is 1E12 ions / cm 2 To 1E16 ions / cm 2 The implantation concentration of the second ion in the JFET region is in the range of 1E12 ions / cm 2 To 1E16 ions / cm 2 .

4. The method for forming a semiconductor structure according to claim 1, wherein: After the step of forming a plurality of gates, the method further comprises: Using the gate as a mask, second ions are implanted into the body regions on both sides of the gate to form source regions.

5. The method for forming a semiconductor structure according to claim 4, wherein: The implantation concentration of the second ion in the source region is in the range of 1E12 ions / cm 2 To 1E16 ions / cm 2 .

6. The method for forming a semiconductor structure according to claim 1, wherein: The substrate further includes a second surface, and after the step of forming a plurality of gates, further includes: Depositing a source metal layer on the plurality of gates; A drain metal layer is deposited on the second surface.

7. A semiconductor structure, characterized in that: include: a substrate, the substrate comprising a first surface; an epitaxial layer, located on the first surface, the epitaxial layer comprising a plurality of first regions and second regions located between adjacent first regions, the first regions and the second regions being arranged along a second direction; a first doped column located in the first region; A second doped column is located in the second region, wherein the first doped column and the second doped column are arranged along a second direction; A plurality of body regions are separately located in the epitaxial layer, and the body regions are arranged along a first direction, the first direction and the second direction are parallel to the substrate surface, and the first direction is perpendicular to the second direction; A plurality of gates are disposed separately on adjacent body regions.

8. The semiconductor structure according to claim 7, wherein: Also includes: The JFET region is located in the epitaxial layer between the adjacent body regions, and the JFET region has second ions, and the body region has first ions.

9. The semiconductor structure according to claim 8, characterized in that The type of the first doped column is opposite to the type of the second doped column, and the type of the first ions is opposite to the type of the second ions.

10. The semiconductor structure according to claim 7, wherein: Also includes: The source region is located in the body region at both sides of the gate, and the source region has second ions.

11. The semiconductor structure according to claim 7, wherein: The substrate further includes a second surface, and the semiconductor structure further includes: a source metal layer located on the plurality of gates; and a drain metal layer located on the second surface.

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