SiC epitaxial wafer
By forming a SiC epitaxial layer on the SiC substrate and controlling the stacking fault density, the problem of difficulty in grasping the position and number of base surface dislocations in the SiC substrate is solved, and the quality of SiC substrate and the improvement of device reliability are achieved.
Patent Information
- Application Number
- CN202411428227.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-25
- Filing Date
- 2024-10-14
- Publication Date
- 2025-04-25
AI Technical Summary
When making SiC devices, it is difficult to non-destructively grasp the position and number of base surface dislocations in the SiC substrate, especially after layering the SiC epitaxial layer.
By forming a SiC epitaxial layer on the SiC substrate and controlling the density of the double-shockley stacking faults to be above 4/cm2 and below 10/cm2, the position and number of the base surface dislocations are estimated.
The position and number of base surface dislocations in the SiC substrate are estimated in the SiC epitaxial wafer, ensuring the quality of the SiC substrate and the reliability of the device.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention relates to a SiC epitaxial wafer. Background Art
[0002] Compared with silicon (Si), silicon carbide (SiC) has an insulation breakdown electric field that is one order of magnitude larger and a band gap that is three times larger. In addition, silicon carbide (SiC) has characteristics such as a thermal conductivity that is about three times higher than that of silicon (Si). Therefore, silicon carbide (SiC) is expected to be used in power devices, high-frequency devices, high-temperature working devices, etc. Therefore, in recent years, SiC epitaxial wafers have been used in semiconductor devices such as the above.
[0003] SiC epitaxial wafers are obtained by stacking SiC epitaxial layers on the surface of SiC substrates. Hereinafter, the substrate before stacking the SiC epitaxial layer is referred to as SiC substrate, and the substrate after stacking the SiC epitaxial layer is referred to as SiC epitaxial wafer. SiC substrates are made by cutting out from SiC ingots. SiC devices such as power devices, high-frequency devices, and high-temperature working devices are obtained by forming devices on the SiC epitaxial layer of the SiC epitaxial wafer and then chipping the SiC epitaxial wafer.
[0004] In SiC epitaxial wafers, there are usually crystal defects. Among the crystal defects, there are defects that have adverse effects on subsequent processes and hinder the normal operation of SiC devices. Such defects are called killer defects. For example, basal plane dislocation (BPD) is considered to be the cause of stacking faults, which are one of the killer defects (for example, Patent Document 1).
[0005] In addition, Patent Document 2 discloses that there are a plurality of stacking faults, and discloses a method of reducing the total amount of stacking faults or double Shockley stacking faults therein.
[0006] Prior Art Literature
[0007] Patent Document 1: Japanese Patent No. 5961357
[0008] Patent Document 2: Japanese Patent No. 6824088 Summary of the invention
[0009] Problems to be solved by the invention
[0010] As mentioned above, when making SiC devices, it is important to understand the location and number of basal plane dislocations (BPDs) that are the cause of fatal defects. However, after stacking SiC epitaxial layers, it is difficult to non-destructively understand the location and number of basal plane dislocations in the SiC substrate where basal plane dislocations are more concentrated.
[0011] The present invention has been made in view of the above-mentioned problems, and an object thereof is to provide a SiC epitaxial wafer capable of estimating positions where basal plane dislocations are concentrated and the number of basal plane dislocations in a SiC substrate even after SiC epitaxial layers are stacked.
[0012] Means for solving problems
[0013] (1) The SiC epitaxial wafer according to the first technical solution comprises a SiC substrate and a SiC epitaxial layer formed on the SiC substrate. The SiC substrate has a basal plane dislocation density of 1 / cm 2 Above and 3000 pieces / cm 2 In the SiC epitaxial layer, the density of double Shockley (2SSF) type stacking faults is 4 / cm 2 More than 10 / cm 2 Hereinafter, the density of stacking faults other than the double Shockley (2SSF) type stacking faults is 2 / cm 2 the following.
[0014] (2) The SiC epitaxial wafer involved in the above technical solution can have a diameter of more than 145 mm.
[0015] (3) The SiC epitaxial wafer involved in the above technical solution can have a diameter of more than 195 mm.
[0016] (4) In the SiC epitaxial wafer involved in the above technical solution, the density of double Shockley (2SSF) type stacking faults can be 6 / cm 2 More than 10 / cm 2 the following.
[0017] (5) In the SiC epitaxial wafer involved in the above technical solution, the density of double Shockley (2SSF) type stacking faults can be 8 / cm 2 More than 10 / cm 2 the following.
[0018] (6) In the SiC epitaxial wafer involved in the above technical solution, the density of double Shockley (2SSF) type stacking faults can be 4 / cm 2 More than 6 / cm 2 the following.
[0019] Effects of the Invention
[0020] The SiC epitaxial wafer according to the above-mentioned technical solution can estimate the positions where basal plane dislocations are concentrated and the number of basal plane dislocations in the SiC substrate even after the SiC epitaxial layers are stacked. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 It is a cross-sectional view of a SiC epitaxial wafer according to the present embodiment.
[0022] Figure 2 It is a top view of the SiC epitaxial wafer according to the present embodiment.
[0023] Description of Reference Numerals
[0024] 1 SiC epitaxial wafer
[0025] 2 SiC substrate
[0026] 3 SiC epitaxial layer
[0027] 4. Incision DETAILED DESCRIPTION
[0028] Hereinafter, the SiC epitaxial wafer and the like of the present embodiment will be described in detail with reference to the accompanying drawings as appropriate. In order to facilitate the understanding of the features of the present embodiment, the accompanying drawings used in the following description sometimes enlarge the features and sometimes the dimensional ratios of the components are different from the actual ones. The materials, dimensions, etc. illustrated in the following description are only examples, and the present invention is not limited thereto, and can be implemented with appropriate changes within the scope of not changing the gist thereof.
[0029] In this specification, individual orientations are indicated by [], and collective orientations are indicated by <>. Regarding negative indices, in crystallography, "-" (bar) is added to the numbers, but in this specification, a negative sign is added before the numbers.
[0030] Figure 1 It is a cross-sectional view of the SiC epitaxial wafer 1 according to the present embodiment. Figure 2 It is a top view of the SiC epitaxial wafer 1 according to the present embodiment.
[0031] The SiC epitaxial wafer 1 includes a SiC substrate 2 and a SiC epitaxial layer 3. The SiC epitaxial wafer 1 is substantially circular in plan view. The SiC epitaxial wafer 1 may have a notch 4 for grasping the crystal axis direction. In addition, the SiC substrate 2 may have an orientation flat surface instead of the notch 4.
[0032] The diameter of the SiC epitaxial wafer 1 is, for example, 145 mm or more, preferably 149 mm or more. In addition, the diameter of the SiC epitaxial wafer 1 is preferably 155 mm or less, more preferably 151 mm or less. In addition, the diameter of the SiC epitaxial wafer 1 is, for example, 195 mm or more, preferably 199 mm or more. In addition, the diameter of the SiC epitaxial wafer 1 is preferably 205 mm or less, more preferably 201 mm or less.
[0033] The SiC substrate 2 is composed of, for example, n-type SiC. The polycrystalline type of the SiC substrate 2 is not particularly limited, and may be any of 2H, 3C, 4H, and 6H. The SiC substrate 2 is, for example, 4H-SiC.
[0034] The density of basal plane dislocation (BPD) of SiC substrate 2 is 1 / cm 2 Above and 3000 pieces / cm 2 Below. If the basal plane dislocation in the SiC substrate 2 is inherited by the SiC epitaxial layer 3, stacking faults, which are one of the fatal defects, may sometimes occur. Therefore, it is ideal that there is no basal plane dislocation in the SiC substrate 2. However, it is difficult to stably manufacture a SiC substrate without basal plane dislocations. In contrast, if the SiC substrate 2 has a basal plane dislocation density within a desired range, it can be manufactured relatively stably. That is, the basal plane dislocation density is 1 / cm 2 Above and 3000 pieces / cm 2 The following SiC substrates 2 can satisfy the required quality and can be obtained stably.
[0035] After laminating the SiC epitaxial layer 3, the SiC epitaxial wafer 1 of the present disclosure can estimate the positions where basal plane dislocations of the SiC substrate 2 are more concentrated and the number of basal plane dislocations, so it is not necessary to always measure the density of basal plane dislocations of the SiC substrate 2. When it is necessary to evaluate the density of basal plane dislocations in the SiC substrate 2, for example, the photoluminescence method can be used for measurement.
[0036] The SiC epitaxial layer 3 is stacked on one surface of the SiC substrate 2. The density of double Shockley (2SSF) stacking faults in the SiC epitaxial layer 3 is 4 / cm 2 More than 10 / cm 2 The density of double Shockley (2SSF) stacking faults is more preferably 6 / cm 2 More than 10 / cm 2 Below, more preferably 7 pieces / cm 2 More than 10 / cm 2 Below, particularly preferably 8 pieces / cm 2 More than 10 / cm 2 If the density is within this range, it is easier to understand the positions where basal plane dislocations are more concentrated (i.e., positions with high basal plane dislocation density) and the number of basal plane dislocations in the SiC substrate. In addition, the density of double Shockley (2SSF) type stacking faults is more preferably 4 / cm 2 More than 8 / cm 2 Below, more preferably 4 / cm 2 More than 6 / cm 2If the density range is within this range, the positions where basal plane dislocations are more concentrated (i.e., positions where the basal plane dislocation density is high) and the number of basal plane dislocations can be understood in the SiC substrate, and the occurrence of device defects can be suppressed. Double Shockley (2SSF) type stacking faults are caused by basal plane dislocations.
[0037] The density of stacking faults other than double Shockley (2SSF) type stacking faults in the SiC epitaxial layer 3 is 2 / cm 2 The density of stacking faults other than double Shockley (2SSF) type stacking faults is preferably 1 / cm 2 Below, more preferably 0.5 pieces / cm 2 By lowering the density of stacking faults other than double Shockley (2SSF) type stacking faults, device failures caused by stacking faults other than double Shockley (2SSF) type stacking faults can be further suppressed.
[0038] There are various types of stacking faults. Stacking faults include Frank type, Shockley type, and mixed types thereof. In addition, Frank type, Shockley type, and mixed types thereof are further classified according to the number of layers in which the defect occurs. Table 1 shows the classification of stacking faults. Table 1 corresponds to Table 1 of Kamata et al., Appl. Phys. Lett. 97, 172107 (2010).
[0039]
[0040] The classification of stacking faults can be determined by the following steps. First, the stacking fault map of the SiC epitaxial wafer 1 is measured using a photoluminescence method. The stacking fault density in the SiC epitaxial layer 3 is, for example, 4 / cm 2 More than 12 pieces / cm 2 At this time, it is not possible to classify each stacking fault, and it is not clear what type of stacking fault it is.
[0041] Then, a spectrum measurement is performed on each mapped stacking fault. The spectrum measurement is performed using MiPLATO manufactured by EtaMax. In the spectrum measurement, the SiC epitaxial layer 3 is irradiated with light of an excitation wavelength of 355nm, and the fluorescence wavelength generated by each stacking fault is measured. The fluorescence wavelength is measured by using a spectrometer to measure the intensity of each wavelength of light generated by the stacking fault, and the peak wavelength with the maximum luminous intensity is obtained. The band gap of the stacking fault varies depending on the number of layers in the stacking direction where the defect occurs, and the peak wavelength of the luminescence from the stacking fault also varies depending on the difference in the band gap. Therefore, it is possible to classify each stacking fault according to the peak wavelength of the spectral measurement.
[0042] The peak wavelength of the double Shockley stacking fault is 500nm. The double Shockley stacking fault is one of the fatal defects, and it is ideal that this defect does not exist. The double Shockley stacking fault is caused by the basal plane dislocation of the SiC substrate 2. In the case where the SiC substrate 2 has more than a certain number of basal plane dislocations, it is difficult to make the double Shockley stacking fault zero. The SiC substrate 2 in the present disclosure has more than a certain number of basal plane dislocations, so the SiC epitaxial layer 3 has a double Shockley stacking fault caused by the basal plane dislocation.
[0043] Stacking faults other than the double Shockley type are located outside the peak wavelength of 500nm. Stacking faults other than the double Shockley type can also become fatal defects. The fewer stacking faults other than the double Shockley type, the better. The density is preferably 2 / cm 2 In the following, it is considered that stacking faults other than the double Shockley type stacking faults are generated due to causes other than basal plane dislocations.
[0044] The SiC epitaxial layer 3 of the SiC epitaxial wafer 1 of the present embodiment has almost no stacking faults other than the double Shockley type stacking faults. Therefore, it can be inferred that the stacking faults confirmed after stacking the SiC epitaxial layer 3 are mostly caused by the basal plane dislocations of the SiC substrate 2. Therefore, the SiC epitaxial wafer 1 of the present embodiment, by measuring the stacking faults after the SiC epitaxial layer 3 is formed by photoluminescence, can infer the position where the basal plane dislocations are more concentrated in the SiC substrate 2 and the number of basal plane dislocations. In the case where the SiC epitaxial layer 3 has multiple stacking faults other than the double Shockley type stacking faults, the estimation accuracy decreases. However, the SiC epitaxial layer 3 of the SiC epitaxial wafer 1 of the present embodiment has almost no stacking faults other than the double Shockley type stacking faults, so the estimation accuracy is high. Information such as the density, position, and number of basal plane dislocations in the SiC substrate 2 is important information in the quality assurance of the SiC epitaxial wafer 1.
[0045] As described above, the SiC epitaxial wafer 1 of the present embodiment can non-destructively estimate the position where the basal plane dislocations in the SiC substrate 2 are more concentrated and the number of basal plane dislocations even after the SiC epitaxial layer 3 is stacked. Therefore, the SiC epitaxial wafer 1 of the present embodiment also guarantees the quality of the SiC substrate 2 and is a SiC epitaxial wafer with high reliability. In addition, in the SiC substrate 2, the position where the basal plane dislocations are more concentrated (i.e., the position where the basal plane dislocation density is high) has a high possibility of device failure. The SiC epitaxial wafer 1 of the present embodiment can grasp the position of the part where the possibility of device failure is high in advance.
[0046] Next, a method for manufacturing the SiC epitaxial wafer 1 according to the present embodiment will be described.
[0047] First, a SiC substrate 2 is prepared. The SiC substrate 2 has a basal plane dislocation density of 1 / cm 2 Above and 3000 pieces / cm 2 Although it is difficult to obtain and manufacture a SiC substrate having no basal plane dislocation, a SiC substrate 2 having a basal plane dislocation within a predetermined range can be obtained relatively easily.
[0048] Next, the SiC epitaxial layer 3 is stacked on the SiC substrate 2. The SiC epitaxial layer 3 is formed by, for example, a chemical vapor deposition method (CVD method).
[0049] The SiC epitaxial layer 3 of this embodiment needs to selectively control the density of predetermined defects in the stacking faults, so stricter control is required compared to the case of controlling the overall density of the stacking faults. The crystal growth conditions for making the density of predetermined defects in the stacking faults fall within a predetermined range are sometimes different in each film forming apparatus, and need to be adjusted accordingly for each film forming apparatus.
[0050] Therefore, first, as a preliminary process, the growth conditions of the SiC epitaxial layer 3 are adjusted. In the preliminary process, the growth conditions of the SiC epitaxial layer 3 suitable for a specific film forming device are determined. This preliminary process is performed for each film forming device. In addition, when the film forming device is cleaned, the preliminary process is performed again. In the preliminary process, the film formation is adjusted repeatedly until the growth conditions of the SiC epitaxial layer 3 are determined. In the preliminary process, it is divided into three stages: the initial stage, the middle stage, and the final stage of crystal growth, and the parameters of temperature, C / Si ratio, and growth rate are changed.
[0051] For example, if only the double Shockley stacking fault is to be reduced, this can be achieved by setting the C / Si ratio in the three stages of the initial, middle, and final stages of crystal growth within a preferred range, as described in Patent Document 2. On the other hand, if the number of stacking faults other than the double Shockley type is to be reduced while limiting the number of double Shockley type stacking faults within a predetermined range, this cannot be achieved by simply setting an optimal range. It is necessary to determine the conditions in the pre-process in consideration of the inherent characteristics of each device.
[0052] First, in the first adjustment film formation, the temperature, C / Si ratio, and growth rate of each of the three growth stages are set as the first condition to form a SiC epitaxial layer 3. Then, after the first adjustment film formation, the SiC epitaxial layer 3 is subjected to photoluminescence measurement to determine the predetermined stacking fault density in the SiC epitaxial layer 3.
[0053] Next, in the second adjustment film formation, the SiC epitaxial layer 3 is formed under the second condition in which at least one of the temperature, C / Si ratio, and growth rate of each of the three growth stages is changed from the first condition. Then, after the second adjustment film formation, the SiC epitaxial layer 3 is subjected to photoluminescence measurement to determine the predetermined stacking fault density in the SiC epitaxial layer 3.
[0054] Then, the results of the first and second film adjustment are fed back to determine the conditions for the third film adjustment. In the third film adjustment, at least one of the temperature, C / Si ratio, and growth rate of each of the three growth stages is changed from the first and second conditions.
[0055] The film formation adjustment and the feedback of the measurement results are repeated to determine the final growth conditions of the SiC epitaxial layer 3. The film formation adjustment and the feedback of the measurement results are repeated by slightly changing the growth conditions, and the final growth conditions of the SiC epitaxial layer 3 are precisely determined in accordance with the inherent characteristics of each film formation device.
[0056] The temperature conditions for film formation were adjusted in each of the three growth stages within a range of 1500° C. to 1700° C. The temperature conditions were finally adjusted within a range of 1° C.
[0057] The C / Si ratio of the film formation is adjusted in each of the three growth stages within a range of 0.8 to 1.5. The C / Si ratio is finally adjusted within a range of 0.05. C / Si is the ratio of the C raw material gas to the Si raw material gas in the growth plane of the SiC epitaxial layer 3.
[0058] The growth rate of the film formation was adjusted to be changed within the range of 5 μm / h to 100 μm / h in each of the three growth stages. The growth rate was finally adjusted within the range of 5 μm / h.
[0059] Next, the actual film formation of the SiC epitaxial layer 3 is performed under the film formation conditions determined in the previous step. According to such a procedure, the SiC epitaxial wafer 1 of the present embodiment can be manufactured.
[0060] As described above, the SiC epitaxial wafer 1 of the present embodiment can be manufactured by determining the conditions in consideration of the characteristics inherent to each device. The SiC epitaxial wafer 1 of the present embodiment has almost no stacking faults other than the double Shockley type stacking faults, so by determining the double Shockley type stacking faults, the number of basal plane dislocations in the SiC substrate 2 and the positions where the basal plane dislocations are concentrated can also be estimated. That is, the SiC epitaxial wafer 1 of the present embodiment can ensure the quality of the SiC substrate 2 even after the SiC epitaxial layer 3 is stacked.
[0061] Although preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims.
[0062] Example
[0063] Example 1
[0064] First, a SiC substrate 2 with a diameter of 150 mm was prepared. The SiC substrate 2 was selected to have a basal plane dislocation of 1 / cm 2 Above and 3000 pieces / cm 2 The following substrate.
[0065] Next, a SiC epitaxial layer 3 was formed on the SiC substrate 2. The growth conditions of the SiC epitaxial layer 3 were set in advance by repeatedly adjusting the film formation and feedback. The defects on the surface of the SiC epitaxial layer 3 were observed by photoluminescence. The stacking fault density of the SiC epitaxial layer 3 was 5.33 / cm 2 In addition, the density of double Shockley stacking faults caused by basal plane dislocations in the SiC epitaxial layer 3 is 4.05 pieces / cm 2 In addition, the density of stacking faults other than the double Shockley type stacking faults is 1.29 / cm 2 Furthermore, the stacking fault density of the SiC epitaxial layer 3, the double Shockley type stacking fault density caused by basal plane dislocations, and the stacking fault density other than the double Shockley type stacking faults are rounded values, and the stacking fault density of the SiC epitaxial layer 3 is not necessarily consistent with the total density of the double Shockley type stacking faults and the stacking fault density other than the double Shockley type stacking faults.
[0066] Next, the cross section of the position where the stacking fault was confirmed in the SiC epitaxial wafer 1 was measured. In the SiC epitaxial wafer 1 of Example 1, most of the defects identified as stacking faults were double Shockley stacking faults. In addition, in the SiC substrate 2 where the double Shockley stacking fault was confirmed, many basal plane dislocations were confirmed.
[0067] As can be seen from the above, the SiC epitaxial wafer 1 of Example 1 can estimate the information of the basal plane dislocation in the SiC substrate 2 based on the information of the stacking fault measured after the SiC epitaxial layer 3 is formed.
[0068] Example 2
[0069] In Example 2, a SiC epitaxial wafer 1 was produced under the same conditions as in Example 1. Then, defects on the surface of the SiC epitaxial layer 3 were observed using a photoluminescence method. The stacking fault density of the SiC epitaxial layer 3 was 9.17 pieces / cm 2 In addition, the density of double Shockley stacking faults caused by basal plane dislocations in the SiC epitaxial layer 3 is 7.35 pieces / cm 2 In addition, the density of stacking faults other than the double Shockley type stacking faults is 1.81 / cm 2 . In addition, in the SiC epitaxial wafer 1, the cross section at the position where the stacking fault was confirmed was measured. In the SiC epitaxial wafer 1 of Example 2, most of the defects determined to be stacking faults were double Shockley type stacking faults. In addition, in the SiC substrate 2 where the double Shockley type stacking fault was confirmed, more basal plane dislocations were confirmed. That is, based on the information of the stacking faults measured after the SiC epitaxial layer 3 was formed, the information of the basal plane dislocations in the SiC substrate 2 can be inferred.
[0070] Comparative Example 1
[0071] A SiC substrate 2 with a diameter of 150 mm was prepared in the same manner as in Example 1. The SiC substrate 2 was selected to have a basal plane dislocation density of 1 / cm 2 Above and 3000 pieces / cm 2 The following substrate.
[0072] Next, a SiC epitaxial layer 3 was formed on the SiC substrate 2. The growth conditions of the SiC epitaxial layer 3 were different from those in Example 1. The defects on the surface of the SiC epitaxial layer 3 were observed by photoluminescence. The stacking fault density of the SiC epitaxial layer 3 was 3.09 pieces / cm 2 In addition, the density of double Shockley stacking faults caused by basal plane dislocations in the SiC epitaxial layer 3 is 0.72 pieces / cm 2 In addition, the density of stacking faults other than the double Shockley type stacking faults is 2.37 / cm 2 .
[0073] In the SiC epitaxial wafer of Comparative Example 1, the number of stacking faults other than the double Shockley type stacking faults is large, and if the stacking faults are not classified one by one, it is impossible to estimate the basal plane dislocations of the SiC substrate 2. The SiC epitaxial wafer of Comparative Example 1 takes time to estimate the positions where the basal plane dislocations are concentrated and the number of basal plane dislocations. In addition, the number of other stacking faults in the SiC epitaxial wafer of Comparative Example 1 is large, and the estimation accuracy of the positions where the basal plane dislocations are concentrated and the number of basal plane dislocations is also low.
[0074] In addition, the results for the SiC epitaxial wafer 1 using the SiC substrate 2 with a diameter of 150 mm have been shown so far, but the same study was also conducted on the SiC epitaxial wafer 1 using the SiC substrate 2 with a diameter of 200 mm. In the case of the diameter of 200 mm, the same tendency as that in the case of the diameter of 150 mm was confirmed.
Claims
1. A SiC epitaxial wafer comprising a SiC substrate and a SiC epitaxial layer formed on the SiC substrate, The density of basal plane dislocations of the SiC substrate is 1 / cm 2 Above and 3000 pieces / cm 2 the following, In the SiC epitaxial layer, the density of double Shockley, i.e., 2SSF type stacking faults is 4 / cm 2 More than 10 / cm 2 Hereinafter, the density of stacking faults other than the double Shockley, i.e., 2SSF type stacking faults is 2 / cm 2 the following.
2. The SiC epitaxial wafer according to claim 1, The diameter is 145mm or more.
3. The SiC epitaxial wafer according to claim 1, The diameter is 195mm or more.
4. The SiC epitaxial wafer according to claim 1, The density of the double Shockley, 2SSF, stacking faults is 6 / cm 2 More than 10 / cm 2 the following.
5. The SiC epitaxial wafer according to claim 1, The density of the double Shockley, 2SSF, stacking faults is 8 / cm 2 More than 10 / cm 2 the following.
6. The SiC epitaxial wafer according to claim 1, The density of the double Shockley, 2SSF, stacking faults is 4 / cm 2 More than 8 / cm 2 the following.
7. The SiC epitaxial wafer according to claim 1, The density of the double Shockley, 2SSF, stacking faults is 4 / cm 2 More than 6 / cm 2 the following.