Semiconductor device and forming method thereof

Abstract

A method of forming a semiconductor device includes forming a device layer including a nanostructure and a gate structure around the nanostructure; forming a first interconnection structure on the front side of the device layer; and forming a second interconnect structure on the backside of the device layer, including: forming a dielectric layer along the backside of the device layer using a first dielectric material; forming a first conductive feature and a second conductive feature in the dielectric layer; forming an opening in the dielectric layer between the first conductive feature and the second conductive feature; forming a first barrier layer and a second barrier layer along a first sidewall of the first conductive feature and along a second sidewall of the second conductive feature, respectively; and forming a second dielectric material different from the first dielectric material in the opening between the first barrier layer and the second barrier layer. The embodiment of the invention also relates to a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that should be addressed. Summary of the invention

[0004] Some embodiments of the present application provide a method for forming a semiconductor device, the method comprising: forming a device layer comprising a nanostructure and a gate structure located around the nanostructure; forming a first interconnect structure on the front side of the device layer; and forming a second interconnect structure on the back side of the device layer opposite to the front side of the device layer, comprising: forming a dielectric layer along the back side of the device layer using a first dielectric material; forming a first conductive component and a second conductive component in the dielectric layer; forming an opening in the dielectric layer by removing a portion of the dielectric layer disposed between the first conductive component and the second conductive component; forming a first barrier layer and a second barrier layer respectively along a first side wall of the first conductive component facing the second conductive component and along a second side wall of the second conductive component facing the first conductive component; and forming a second dielectric material different from the first dielectric material in the opening between the first barrier layer and the second barrier layer.

[0005] Some other embodiments of the present application provide a method for forming a semiconductor device, the method comprising: forming a device layer including a nanostructure and a gate structure located around the nanostructure; forming a first interconnect structure on a first side of the device layer; and forming a second interconnect structure on a second side of the device layer opposite to the first side of the device layer, comprising: forming a dielectric layer along the second side of the device layer using a first dielectric material; forming a first conductive component surrounded by a first barrier layer in the dielectric layer; forming a second conductive component surrounded by a second barrier layer in the dielectric layer; removing a portion of the dielectric layer disposed between the first conductive component and the second conductive component to form an opening in the dielectric layer, the opening exposing a first sidewall of the first barrier layer and a second sidewall of the second barrier layer; forming a second dielectric material different from the first dielectric material along the first sidewall of the first barrier layer and along the second sidewall of the second barrier layer; after forming the second dielectric material, lining the sidewalls and bottom of the opening with a third barrier layer; and after forming the third barrier layer, filling the opening with a conductive material.

[0006] Some other embodiments of the present application provide a semiconductor device, comprising: a device layer, comprising a nanostructure and a gate structure located around the nanostructure; a first interconnect structure, located on a first side of the device layer; and a second interconnect structure, located on a second side of the device layer opposite to the first side of the device layer, comprising: a dielectric layer, along the second side of the device layer, wherein the dielectric layer comprises a first dielectric material; a first conductive component and a second conductive component, embedded in the dielectric layer; and a metal-insulator-metal (MIM) capacitor, located in the dielectric layer, comprising: a first barrier layer, along a first sidewall of the first conductive component facing the second conductive component; a second barrier layer, along a second sidewall of the second conductive component facing the first conductive component; and a second dielectric material, located in the dielectric layer between the first barrier layer and the second barrier layer, wherein the second dielectric material is different from the first dielectric material. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 An example of a nanostructured field effect transistor (nanoFET) in a three-dimensional view is shown in accordance with some embodiments.

[0009] Figures 2 to 5 , Fig. 6A、 Figure 6B 、 Figure 6C 、 Fig. 7A 、 Figure 7B 、 Figure 7C 、 Fig. 8A 、 Figure 8B 、 Figure 8C 、 Fig.9A 、 Fig. 9B 、 Fig. 9C 、 Fig. 10A 、 Fig. 10B 、 Fig. 10C 、 Fig.11A 、 Fig. 11B 、 Fig. 11C 、 Fig.11D 、 Fig. 12A 、 Fig. 12B 、 Fig. 12C 、 Fig.12D 、 Fig.12E 、 Fig.13A 、 Fig. 13B 、 Fig. 13C 、 Fig.14A 、 Fig. 14B 、 Fig. 14C 、 Fig.15A 、 Fig. 15B 、 Fig. 15C 、 Fig.16A 、 Fig. 16B 、 Fig. 16C 、 Fig.17A 、 Fig. 17B 、 Fig. 17C 、 Fig.18A 、 Fig.18B 、 Fig. 18C 、 Fig.19A 、 Fig.19B 、 Fig.19C 、 Fig. 20A 、 Fig. 20B 、 Fig. 20C 、 Fig.21A 、 Fig.21B 、 Fig. 21C 、 Fig.22A 、 Fig. 22B 、 Fig. 22C 、 Fig.23A 、 Fig. 23B 、 Fig.23C 、 Fig.24A 、 Fig. 24B 、 Fig.24C 、 Fig.25A 、 Fig.25B 、 Fig.25C 、 Fig.26A 、 Fig.26B 、 Fig.26C 、 Fig.27A 、 Fig.27B 、 Fig.27C 、 Fig.27D 、 Figures 28 to 33 、 Fig.34A 、 Fig.34B , Fig.35A , Fig.35B , Fig.36A , Fig.36B and Fig.36C Various views of a nanometer field effect transistor (FET) device at different stages of fabrication are shown in accordance with an embodiment.

[0010] Figures 37 to 43 Cross-sectional views of a nanoFET device at different fabrication stages according to another embodiment are shown.

[0011] Fig.44 and Fig.45 Cross-sectional views of a semiconductor package at different manufacturing stages in an embodiment are shown.

[0012] Fig.46 A flow chart of a method for forming a semiconductor device in an embodiment is shown. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact.

[0014] In addition, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Throughout the discussion herein, unless otherwise specified, the same or similar numbers in different figures refer to the same or similar components formed using the same or similar materials by the same or similar formation methods.

[0015] Various embodiments provide methods for forming a metal-insulator-metal (MIM) capacitor in a back-end-of-line (BEOL) process of a semiconductor device and a semiconductor device including a MIM capacitor. In some embodiments, the MIM capacitor is formed in one or more dielectric layers of an interconnect structure on the back side of a semiconductor die. The backside interconnect structure can be wired for power lines and electrical ground lines. In an embodiment, the MIM capacitor is formed by: removing a portion of a dielectric layer disposed between two adjacent wires in the dielectric layer to form an opening; forming a barrier layer along the sidewalls of the two adjacent wires exposed by the opening; and filling the opening with a high-k dielectric material. In another embodiment, the MIM capacitor is formed by: forming a wire with a barrier layer in a dielectric layer; removing a portion of a dielectric layer disposed between two adjacent wires to form an opening; lining the sidewalls of the two adjacent wires exposed by the opening with a high-k dielectric material; and forming a new wire with a barrier layer to fill the opening. The MIM capacitor can stabilize the power line and the electrical ground line, resulting in improved device performance. Forming a MIM capacitor including a high-k dielectric material allows the decoupling capacitor to hold a larger charge while minimizing the size of the MIM capacitor.

[0016] Some embodiments discussed herein are described in the context of dies including nanoFETs. However, various embodiments may be applicable to dies including other types of transistors (eg, fin field effect transistors (FinFETs), planar transistors, etc.) instead of or in combination with nanoFETs.

[0017] Figure 1 An example of a nanoFET (e.g., a nanowire FET, a nanosheet FET, etc.) in a three-dimensional view according to some embodiments is shown. The nanoFET includes a nanostructure 55 (e.g., a nanosheet, a nanowire, etc.) above a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 is used as a channel region for the nanoFET. The nanostructure 55 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. A shallow trench isolation (STI) region 68 is disposed between adjacent fins 66, and the fins 66 may protrude above and from between adjacent STI regions 68. In addition, although the bottom portion of the fin 66 is shown as a single, continuous material with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 66 refers to the portion extending between adjacent STI regions 68.

[0018] Gate dielectric layer 100 is located over the top surface of fin 66 and along the top surface, sidewalls and bottom surface of nanostructure 55. Gate electrode 102 is located over gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on fin 66 on opposite sides of gate dielectric layer 100 and gate electrode 102.

[0019] Figure 1 Reference cross sections used in later figures are also shown. Cross section AA' is along the longitudinal axis of gate electrode 102, and in a direction, e.g., perpendicular to the direction of current flow between epitaxial source / drain regions 92 of the nanoFETs. Cross section BB' is parallel to cross section AA' and extends through epitaxial source / drain regions 92 of multiple nanoFETs. Cross section CC' is perpendicular to cross section AA' and parallel to the longitudinal axis of fins 66 of the nanoFETs, and in the direction of current flow, e.g., between epitaxial source / drain regions 92 of the nanoFETs. For clarity, subsequent figures refer to these reference cross sections.

[0020] Some embodiments discussed herein are discussed in the context of nano FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects used in planar devices such as planar FETs or fin field effect transistors (FinFETs).

[0021] Figures 2 to 36C are various views (eg, cross-sectional views, top views) of nanoFET device 180 at different stages of fabrication, according to an embodiment. Figures 2 to 5 , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.23A , Fig.24A , Fig.25A , Fig.26A , Fig.27A , Figure 28 to Figure 33 , Fig.34A , Fig.35A , Fig.35B and Fig.36A Shows Figure 1 Reference section AA' shown in . Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig.12D , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig.21B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.25B , Fig.26B , Fig.27B and Fig.36B Shows Figure 1 Reference section BB' shown in . Figure 6C , Figure 7C , Figure 8C , Fig. 9C , Fig. 10C , Fig. 11C , Fig.11D , Fig. 12C , Fig.12E , Fig. 13C , Fig. 14C , Fig. 15C , Fig. 16C , Fig. 17C , Fig. 18C , Fig.19C , Fig. 20C , Fig. 21C , Fig. 22C , Fig.23C , Fig.24C , Fig.25C , Fig.26C , Fig.27C , Fig.27D and Fig.36C Shows Figure 1 Reference section CC' shown in . Fig.34B yes Fig.34A Top view of the structure.

[0022] exist Figure 2 In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. An insulating layer is provided on a substrate, which is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0023] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type nano FET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type nano FET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by the separator 20), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be arranged between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0024] In addition, Figure 2 In the embodiment of the present invention, a multilayer stack 64 is formed over the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-53C (collectively referred to as second semiconductor layers 53). For the purpose of illustration and as discussed in more detail below, the first semiconductor layer 51 will be removed and the second semiconductor layer 53 will be patterned to form a channel region of the nanoFET in the n-type region 50N and the p-type region 50P. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of the nanoFET in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanoFET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanoFET in the n-type region 50N, and the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of the nanoFET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanoFET in the n-type region 50N and the p-type region 50P.

[0025] For the purpose of illustration, the multilayer stack 64 is shown as including three layers of each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each of the layers of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for a p-type nanoFET, such as silicon germanium, etc., and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for an n-type nanoFET, such as silicon, silicon carbon, etc. For the purpose of illustration, the multilayer stack 64 is shown as having a bottommost semiconductor layer suitable for a p-type nanoFET. In some embodiments, the multilayer stack 64 may be formed such that the bottommost layer is a semiconductor layer suitable for an n-type nanoFET.

[0026] The first semiconductor material and the second semiconductor material can be materials with high etching selectivity to each other. Therefore, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the nanoFET. Similarly, in an embodiment where the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form the channel region, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the nanoFET.

[0027] Reference now Figure 3 According to some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching grooves in multilayer stack 64 and substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. Etching can be anisotropic. Forming nanostructure 55 by etching multilayer stack 64 can further define first nanostructures 52A-52C (collectively referred to as first nanostructures 52) by first semiconductor layer 51, and define second nanostructures 54A-54C (collectively referred to as second nanostructures 54) by second semiconductor layer 53. First nanostructure 52 and second nanostructure 54 can be collectively referred to as nanostructure 55.

[0028] The fins 66 and nanostructures 55 can be patterned by any suitable method. For example, the fins 66 and nanostructures 55 can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a pitch that is smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0029] For illustration purposes, Figure 3 The fins 66 in the n-type region 50N and the p-type region 50P are shown as having substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater than or thinner than the width of the fins 66 in the p-type region 50P. In addition, although each of the fins 66 and the nanostructures 55 are shown as having a uniform width throughout, in other embodiments, the fins 66 and / or the nanostructures 55 may have tapered sidewalls such that the width of each of the fins 66 and / or the nanostructures 55 increases continuously in a direction toward the substrate 50. In such embodiments, each of the nanostructures 55 may have different widths and be trapezoidal in shape.

[0030] exist Figure 4 In the embodiment, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material over the substrate 50, the fin 66 and the nanostructure 55 and between adjacent fins 66. The insulating material can be an oxide, such as silicon oxide, nitride, etc., or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be implemented. In an embodiment, the insulating material is formed so that excess insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) can be first formed along the surface of the substrate 50, the fin 66 and the nanostructure 55. Thereafter, a filling material such as those discussed above can be formed over the liner.

[0031] A removal process is then applied to the insulating material to remove excess insulating material above the nanostructures 55. In some embodiments, a planarization process may be utilized, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. The planarization process exposes the nanostructures 55 so that the top surfaces of the nanostructures 55 and the insulating material are flush after the planarization process is completed.

[0032] The insulating material is then recessed to form STI regions 68. The insulating material is recessed so that the upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude from between adjacent STI regions 68. In addition, the top surface of the STI region 68 can have a flat surface (as shown), a convex surface, a concave surface (such as a depression), or a combination thereof. The top surface of the STI region 68 can be formed to be flat, convex, and / or concave by appropriate etching. The STI region 68 can be recessed using an acceptable etching process, such as an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fin 66 and the nanostructure 55). For example, oxide removal can be used, using, for example, dilute hydrofluoric (dHF) acid.

[0033] Above about Figures 2 to 4 The process described is merely one example of how the fin 66 and nanostructure 55 may be formed. In some embodiments, the fin 66 and / or nanostructure 55 may be formed using a mask and an epitaxial growth process. For example, a dielectric layer may be formed above the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the epitaxial structure protrudes from the dielectric layer to form the fin 66 and / or nanostructure 55. The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially grown epitaxial structures, the epitaxially grown material may be doped in situ during growth, which may avoid prior and / or subsequent implantation, but in situ doping and implantation doping may be used together.

[0034] In addition, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are shown and discussed herein as including the same material in the p-type region 50P and the n-type region 50N for illustration purposes only. Therefore, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials or formed in a different order in the p-type region 50P and the n-type region 50N.

[0035] In addition, Figure 4In the embodiment with different well types, a photoresist or other mask (not shown separately) can be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, a photoresist can be formed over the fins 66 and STI regions 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed by using a spin coating technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent the n-type impurity from being implanted into the n-type region 50N. The n-type impurity can be implanted in the region from about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 Phosphorus, arsenic, antimony, etc., at concentrations within a range of 0.1 to 0.1. After implantation, the photoresist is removed, such as by an acceptable ashing process.

[0036] After or before implanting the p-type region 50P, a photoresist or other mask (not separately shown) is formed over the fins 66, nanostructures 55, and STI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist may be formed using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region 50N, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity may be implanted in the region from about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 Boron, boron fluoride, indium, etc., at concentrations within a range of 0.1 to 0.1. After implantation, the photoresist may be removed, such as by an acceptable ashing process.

[0037] After implanting n-type region 50N and p-type region 50P, annealing may be performed to repair implant damage and activate implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin may be in-situ doped during growth, which may avoid implantation, but in-situ doping and implantation doping may be used together.

[0038] exist Figure 5In the embodiment of the present invention, a pseudo dielectric layer 70 is formed on the fin 66 and / or the nanostructure 55. The pseudo dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to an acceptable technique. A pseudo gate layer 72 is formed above the pseudo dielectric layer 70, and a mask layer 74 is formed above the pseudo gate layer 72. The pseudo gate layer 72 may be deposited above the pseudo dielectric layer 70, and then planarized such as by CMP. The mask layer 74 may be deposited above the pseudo gate layer 72. The pseudo gate layer 72 may be a conductive or non-conductive material, and may be selected from a group including amorphous silicon, polycrystalline silicon (poly silicon), and polycrystalline silicon germanium (poly-SiGe). The pseudo gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The pseudo gate layer 72 may be made of other materials having high etching selectivity relative to the etching of the isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. It should be noted that the dummy dielectric layer 70 is shown to cover only the fin 66 and the nanostructure 55 for illustration purposes only. In some embodiments, the dummy dielectric layer 70 can be deposited such that the dummy dielectric layer 70 covers the STI region 68, so that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0039] 6A to 18C Various additional steps in fabricating example devices are shown. 6A to 18C Components in either the n-type region 50N or the p-type region 50P are shown. FIG. 6A to FIG. 6C In the embodiment, the mask layer 74 (see Figure 5 ) can be patterned using acceptable photolithography and etching techniques to form a mask 78. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and to the dummy dielectric layer 70 to form a dummy gate 76 and a dummy gate dielectric 71, respectively. The dummy gate 76 covers the corresponding channel region of the fin 66. The pattern of the mask 78 can be used to physically separate each of the dummy gates 76 from the adjacent dummy gates 76. The dummy gates 76 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the corresponding fin 66.

[0040] exist FIG. 7A to FIG. 7C in FIG. 6A to FIG. 6C A first spacer layer 80 and a second spacer layer 82 are formed over the structure shown in FIG. The first spacer layer 80 and the second spacer layer 82 will then be patterned to serve as spacers for forming self-aligned source / drain regions. FIG. 7A to FIG. 7C, a first spacer layer 80 is formed on the top surface of the STI region 68; the top surface and sidewalls of the fin 66, the nanostructure 55, and the mask 78; and the sidewalls of the dummy gate 76 and the dummy gate dielectric 71. A second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. using a technique such as thermal oxidation, or may be deposited by CVD, ALD, etc. The second spacer layer 82 may be formed of a material having a different etch rate from the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and may be deposited by CVD, ALD, etc.

[0041] After forming the first spacer layer 80 and before forming the second spacer layer 82, an implant for lightly doped source / drain (LDD) regions (not shown separately) may be performed. In embodiments with different device types, similar to the above, Figure 4 As discussed in the implantation, a mask, such as a photoresist, can be formed over the n-type region 50N while exposing the p-type region 50P, and impurities of the appropriate type (e.g., p-type) can be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask can then be removed. Subsequently, a mask, such as a photoresist, can be formed over the p-type region 50P while exposing the n-type region 50N, and impurities of the appropriate type (e.g., n-type) can be implanted into the exposed fins 66 and nanostructures 55 in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the n-type impurities discussed previously, and the p-type impurity can be any of the p-type impurities discussed previously. The lightly doped source / drain regions can have a density ranging from about 1×10 15 Atom / cm 3 About 1×10 19 Atom / cm 3 Annealing can be used to repair implantation damage and activate implanted impurities.

[0042] exist FIG. 8A to FIG. 8C, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 are used to self-align the subsequently formed source / drain regions, and to protect the sidewalls of the fin 66 and / or the nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), etc. In some embodiments, the material of the second spacer layer 82 has a different etching rate than the material of the first spacer layer 80, so that the first spacer layer 80 can be used as an etching stop layer when patterning the second spacer layer 82, and so that the second spacer layer 82 can be used as a mask when patterning the first spacer layer 80. For example, the second spacer layer 82 may be etched using an anisotropic etching process, wherein the first spacer layer 80 serves as an etch stop layer, wherein the remaining portion of the second spacer layer 82 forms the second spacer 83, such as Figure 8B Thereafter, the second spacer 83 is used as a mask when etching the exposed portion of the first spacer layer 80, thereby forming the first spacer 81, as shown in FIG. Figure 8B and Figure 8C as shown in .

[0043] like Figure 8B As shown in FIG. 1 , the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8C As shown in , in some embodiments, the second spacer layer 82 can be removed from above the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric 71. In other embodiments, a portion of the second spacer layer 82 can remain above the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71.

[0044] It should be noted that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, different step sequences may be used (e.g., the first spacer 81 may be patterned before the second spacer layer 82 is deposited), additional spacers may be formed and removed, etc. In addition, n-type and p-type devices may be formed using different structures and steps.

[0045] exist 9A to 9CIn some embodiments, a first recess 86 and a second recess 87 are formed in the fin 66, the nanostructure 55, and the substrate 50. An epitaxial source / drain region will be subsequently formed in the first recess 86, and a first epitaxial material and an epitaxial source / drain region will be subsequently formed in the second recess 87. The first recess 86 and the second recess 87 may extend through the first nanostructure 52 and the second nanostructure 54 and extend into the substrate 50. Fig. 9B As shown in , the top surface of the STI region 68 can be flush with the bottom surface of the first recess 86. In various embodiments, the fin 66 can be etched so that the bottom surface of the first recess 86 is disposed below the top surface of the STI region 68, etc. The bottom surface of the second recess 87 can be disposed below the bottom surface of the first recess 86 and the top surface of the STI region 68. The first recess 86 and the second recess 87 can be formed by etching the fin 66, the nanostructure 55 and the substrate 50 using an anisotropic etching process (such as RIE, NBE, etc.). During the etching process for forming the first recess 86 and the second recess 87, the first spacer 81, the second spacer 83 and the mask 78 mask the fin 66, the nanostructure 55 and the substrate 50. Each layer of the nanostructure 55 and / or the fin 66 can be etched using a single etching process or multiple etching processes. After the first recess 86 and the second recess 87 reach the desired depth, a timed etching process can be used to stop etching. The second recess 87 may be etched by the same process used to etch the first recess 86 and an additional etching process before or after etching the first recess 86. In some embodiments, a region corresponding to the first recess 86 may be masked when the additional etching process for the second recess 87 is performed.

[0046] exist FIG. 10A to FIG. 10C In the embodiment, the portion of the sidewall of the layer formed of the first semiconductor material of the multilayer stack 64 exposed by the first groove 86 and the second groove 87 (e.g., the first nanostructure 52) is etched to form a sidewall groove 88. Although the sidewall of the first nanostructure 52 adjacent to the sidewall groove 88 is Fig. 10C The sidewalls are shown as being straight, but the sidewalls may be concave or convex. The sidewalls may be etched using an isotropic etching process such as a wet etch. In embodiments where the first nanostructures 52 include, for example, SiGe and the second nanostructures 54 include, for example, Si or SiC, a etchant having tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 The sidewall of the first nanostructure 52 is etched by a dry etching process such as OH.

[0047] exist FIG. 11A to FIG. 11D In the embodiment, a first inner spacer 90 is formed in the sidewall groove 88. The first inner spacer 90 can be formed by FIG. 10A to FIG. 10C86 and 87, and the first nanostructure 52 is replaced with a corresponding gate structure.

[0048] The inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, etc. The inner spacer layer may include a material such as silicon nitride or silicon oxynitride, but any suitable material may be utilized, such as a low dielectric constant (low-k) material having a k value of less than about 3.5. The inner spacer layer may then be anisotropically etched to form a first inner spacer 90. Although the outer sidewalls of the first inner spacer 90 are shown flush with the sidewalls of the second nanostructure 54, the outer sidewalls of the first inner spacer 90 may extend beyond the sidewalls of the second nanostructure 54 or be recessed from the sidewalls of the second nanostructure 54.

[0049] In addition, although the outer side wall of the first inner partition 90 is Fig. 11C , but the outer sidewall of the first inner spacer 90 may be concave or convex. As an example, Fig.11D An embodiment is shown in which the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the second nanostructure 54. The inner spacer layer can be etched by an anisotropic etching process, such as RIE, NBE, etc. The first inner spacer 90 can be used to prevent subsequent etching processes (such as etching processes used to form gate structures) from affecting subsequently formed source / drain regions (such as epitaxial source / drain regions 92, which are described below). FIG. 12A to FIG. 12E discussion) damage.

[0050] exist FIG. 12A to FIG. 12E In the embodiment, the first epitaxial material 91 is formed in the second recess 87, and the epitaxial source / drain region 92 is formed in the first recess 86 and the second recess 87. In some embodiments, the first epitaxial material 91 may be subsequently removed to form a backside via (such as backside via 130, described below with respect to FIG. 26A to FIG. 26C Discussion) of sacrificial materials. FIG. 12B to FIG. 12EAs shown in , the top surface of the first epitaxial material 91 can be flush with the bottom surface of the first recess 86. However, in some embodiments, the top surface of the first epitaxial material 91 can be disposed above or below the bottom surface of the first recess 86. The first epitaxial material 91 can be epitaxially grown in the second recess 87 using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. The first epitaxial material 91 can include any acceptable material, such as silicon germanium, etc. The first epitaxial material 91 can be formed by epitaxially bonding the epitaxial source / drain regions 92, the substrate 50, and the dielectric layer (such as the STI region 68 and the second dielectric layer 125, which are described below). FIG. 24A to FIG. 24C Therefore, the first epitaxial material 91 can be removed and replaced with a backside via without significantly removing the epitaxial source / drain regions 92 and the dielectric layer.

[0051] Then, epitaxial source / drain regions 92 are formed over the first epitaxial material 91 in the first recess 86 and in the second recess 87. In some embodiments, the epitaxial source / drain regions 92 may exert stress on the second nanostructure 54, thereby improving performance. Fig. 12C As shown in FIG. 1 , epitaxial source / drain regions 92 are formed in first recess 86 and second recess 87 such that each dummy gate 76 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 92. In some embodiments, first spacers 81 are used to separate epitaxial source / drain regions 92 from dummy gates 76, and first internal spacers 90 are used to separate epitaxial source / drain regions 92 from nanostructures 55 by an appropriate lateral distance such that epitaxial source / drain regions 92 are not short-circuited with a subsequently formed gate of the resulting nanoFET.

[0052] The epitaxial source / drain region 92 in the n-type region 50N (e.g., NMOS region) can be formed by masking the p-type region 50P (e.g., PMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first groove 86 and the second groove 87 in the n-type region 50N. The epitaxial source / drain region 92 may include any acceptable material suitable for n-type nanoFETs. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 may include a material that applies tensile strain on the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 92 may have a surface protruding from the corresponding upper surface of the nanostructure 55, and may have a small facet.

[0053] The epitaxial source / drain region 92 in the p-type region 50P (e.g., a PMOS region) can be formed by masking the n-type region 50N (e.g., an NMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 and the second recess 87 in the p-type region 50P. The epitaxial source / drain region 92 may include any acceptable material suitable for a p-type nanoFET. For example, if the first nanostructure 52 is silicon germanium, the epitaxial source / drain region 92 may include a material that applies compressive strain on the first nanostructure 52, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain region 92 may also have a surface that protrudes from the corresponding surface of the multilayer stack 56 and may have a small facet.

[0054] The epitaxial source / drain regions 92, the first nanostructures 52, the second nanostructures 54, and / or the substrate 50 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The source / drain regions may have a dopant density of about 1×10 19 Atom / cm 3 and about 1×10 21 Atom / cm 3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 may be doped in situ during growth.

[0055] Due to the epitaxial process used to form epitaxial source / drain regions 92 in n-type region 50N and p-type region 50P, the upper surface of epitaxial source / drain regions 92 has facets that extend laterally outward beyond the sidewalls of nanostructures 55. In some embodiments, these facets allow adjacent epitaxial source / drain regions 92 of the same nanoFET to merge, such as Fig. 12B In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, such as Fig.12D As shown in Fig. 12B and Fig.12D In the embodiment shown in , the first spacer 81 can be formed to the top surface of the STI region 68, thereby blocking epitaxial growth. In some other embodiments, the first spacer 81 can cover a portion of the sidewall of the nanostructure 55, further blocking epitaxial growth. In some other embodiments, the spacer etch used to form the first spacer 81 can be adjusted to remove the spacer material to allow the epitaxial growth region to extend to the surface of the STI region 68.

[0056] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration that is less than the second semiconductor material layer 92B and greater than the third semiconductor material layer 92C. In an embodiment where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited above the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited above the second semiconductor material layer 92B.

[0057] Fig.12E An embodiment is shown in which the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the second nanostructure 54. Fig.12E As shown in , the epitaxial source / drain regions 92 may be formed in contact with the first inner spacers 90 and may extend beyond the sidewalls of the second nanostructures 54 .

[0058] exist FIG. 13A to FIG. 13C in FIG. 12A to FIG. 12C A first interlayer dielectric (ILD) 96 is deposited over the structure shown in FIG. The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the mask 78, and the first spacer 81. The CESL 94 may include a dielectric material having a different etch rate than the material of the first ILD 96 above, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0059] exist FIG. 14A to FIG. 14CIn the process, a planarization process, such as CMP, may be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and the portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush within process variations. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 may remain, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0060] exist FIG. 15A to FIG. 15C In one embodiment, the dummy gate 76 and the mask 78 (if present) are removed in one or more etching steps to form a third recess 98. The portion of the dummy gate dielectric 71 located in the third recess 98 is also removed. In some embodiments, the dummy gate 76 and the dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 76 at a faster rate than the first ILD 96 or the first spacer 81. Each of the third recesses 98 exposes a portion of the nanostructure 55 and / or is located above a portion of the nanostructure 55 that is used as a channel region in a subsequently completed nanoFET. The portion of the nanostructure 55 used as a channel region is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, when etching the dummy gate 76, the dummy gate dielectric 71 may be used as an etch stop layer. Then, after removing the dummy gate 76, the dummy gate dielectric 71 may be removed.

[0061] exist FIG. 16A to FIG. 16C In the embodiment, first nanostructure 52 is removed and third recess 98 is extended. First nanostructure 52 can be removed by performing an isotropic etching process (such as wet etching) using an etchant that is selective to the material of first nanostructure 52, while second nanostructure 54, substrate 50, and STI region 68 remain relatively unetched compared to first nanostructure 52. In an embodiment where first nanostructure 52 includes, for example, SiGe and second nanostructures 54A-54C include, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH) etc. to remove the first nanostructure 52.

[0062] exist FIG. 17A to FIG. 17C, a gate dielectric layer 100 and a gate electrode 102 for replacing the gate are formed. The gate dielectric layer 100 is conformally deposited in the third recess 98. The gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric layer 100 may also be deposited on the top surfaces of the first ILD 96, the CESL 94, the first spacer 81, and the STI region 68 and on the sidewalls of the first spacer 81 and the first inner spacer 90.

[0063] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, etc., or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. The formation method of the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0064] The gate electrode 102 is deposited over the gate dielectric layer 100 and fills the remaining portion of the third recess 98. The gate electrode 102 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Fig.17A and Fig. 17C , a single-layer gate electrode 102 is shown, but the gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and filler materials. Any combination of layers constituting the gate electrode 102 may be deposited in the n-type region 50N between adjacent second nanostructures 54 and between the second nanostructure 54A and the substrate 50, and may be deposited in the p-type region 50P between adjacent first nanostructures 52.

[0065] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may occur simultaneously, so that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 may occur simultaneously, so that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region may be formed by a different process, so that the gate dielectric layer 100 may be a different material and / or have a different number of layers, and / or the gate electrode 102 in each region may be formed by a different process, so that the gate electrode 102 may be a different material and / or have a different number of layers. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0066] After filling the third recess 98, a planarization process, such as CMP, may be performed to remove excess portions of the gate dielectric layer 100 and the gate electrode 102 material that are located above the top surface of the first ILD 96. Thus, the remaining portions of the gate electrode 102 and the gate dielectric layer 100 material form a replacement gate structure of the resulting nanoFET. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as a "gate structure".

[0067] exist 18A to 18C In the process, the gate structure (including the gate dielectric layer 100 and the corresponding gate electrode 102 thereon) is recessed to form a groove directly above the gate structure and between the opposite portion of the first spacer 81. A gate mask 104 including one or more dielectric material layers (such as silicon nitride, silicon oxynitride, etc.) is filled in the groove, followed by a planarization process to remove the excess portion of the dielectric material extending above the first ILD 96. A gate contact (such as gate contact 114, described below) is subsequently formed. FIG. 20A to FIG. 20C Discussion) penetrates the gate mask 104 to contact the top surface of the recessed gate electrode 102.

[0068] like 18A to 18C As further shown, a second ILD 106 is deposited over the first ILD 96 and over the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method, such as CVD, PECVD, etc.

[0069] exist FIG. 19A to FIG. 19C, the second ILD 106, the first ILD 96, the CESL 94, and the gate mask 104 are etched to form a fourth recess 108 exposing the surface of the epitaxial source / drain region 92 and / or the gate structure. The fourth recess 108 may be formed by etching using an anisotropic etching process (such as RIE, NBE, etc.). In some embodiments, the fourth recess 108 may be etched through the second ILD 106 and the first ILD 96 using a first etching process; etched through the gate mask 104 using a second etching process; and then etched through the CESL 94 using a third etching process. A mask such as a photoresist may be formed and patterned over the second ILD 106 to mask portions of the second ILD 106 from the first etching process and the second etching process. In some embodiments, the etching process may over-etch, and therefore, the fourth recess 108 extends into the epitaxial source / drain region 92 and / or the gate structure, and the bottom of the fourth recess 108 may be flush with the epitaxial source / drain region 92 and / or the gate structure (e.g., at the same level, or at the same distance from the substrate 50), or lower than the epitaxial source / drain region 92 and / or the gate structure (e.g., closer to the substrate 50). Although Fig.19C The fourth recess 108 is shown as exposing the epitaxial source / drain regions 92 and the gate structure in the same cross section, but in various embodiments, the epitaxial source / drain regions 92 and the gate structure may be exposed in different cross sections, thereby reducing the risk of shorting subsequently formed contacts.

[0070] After forming the fourth recess 108, a first silicide region 110 is formed over the epitaxial source / drain region 92. In some embodiments, the first silicide region 110 is formed by: first depositing a metal (not shown separately) that can react with the semiconductor material (e.g., silicon, silicon germanium, germanium) of the underlying epitaxial source / drain region 92 to form a silicide or germanide region over the exposed portion of the epitaxial source / drain region 92, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof; and then performing a thermal annealing process to form the first silicide region 110. Then, the unreacted portion of the deposited metal is removed, for example, by an etching process. Although the first silicide region 110 is referred to as a silicide region, the first silicide region 110 may also be a germanide region or a silicon germanide region (e.g., a region including silicide and germanide).

[0071] exist FIG. 20A to FIG. 20CIn the fourth recess 108, source / drain contacts 112 and gate contacts 114 (also referred to as contact plugs) are formed. The source / drain contacts 112 and gate contacts 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, the source / drain contacts 112 and gate contacts 114 each include a barrier layer and a conductive material, and each is electrically coupled to the underlying conductive component (e.g., the gate electrode 102 and / or the first silicide region 110). The gate contact 114 is electrically coupled to the gate electrode 102, and the source / drain contacts 112 are electrically coupled to the first silicide region 110. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process, such as CMP, may be performed to remove excess material from the surface of the second ILD 106. The epitaxial source / drain regions 92, the second nanostructure 54, and the gate structure (including the gate dielectric layer 100 and the gate electrode 102) may be collectively referred to as a transistor structure 109. The transistor structure 109 may be formed in a device layer, with a first interconnect structure (such as a front-side interconnect structure 120, described below) formed over its front side. FIG. 21A to FIG. 21C ), and forming a second interconnect structure over its back side (such as backside interconnect structure 136, discussed below) FIG. 36A to FIG. 36C Discussion.) Although the device layer is described as having nano FETs, other embodiments may include device layers having different types of transistors (eg, planar FETs, fin FETs, thin film transistors (TFTs), etc.).

[0072] Although FIG. 20A to FIG. 20C Source / drain contacts 112 are shown extending to each of the epitaxial source / drain regions 92, but source / drain contacts 112 may be omitted from some of the epitaxial source / drain regions 92. For example, as explained in more detail below, a conductive feature (e.g., a backside via or power rail) may be subsequently attached through the back side of one or more of the epitaxial source / drain regions 92. For these particular epitaxial source / drain regions 92, source / drain contacts 112 may be omitted or may not be electrically connected to any overlying conductive lines (such as first conductive feature 122, discussed below with respect to FIG. 21A to FIG. 21C Discussion) of the pseudo contact.

[0073] FIG. 21A to FIG. 36C An intermediate step is shown in which a frontside interconnect structure and a backside interconnect structure are formed on the transistor structure 109. The frontside interconnect structure and the backside interconnect structure may each include conductive features electrically connected to the nanoFETs formed on the substrate 50. FIG. 21A to FIG. 36CThe process steps described in can be applied to both the n-type region 50N and the p-type region 50P. As noted above, the backside conductive features (e.g., backside vias or power rails) can be connected to one or more of the epitaxial source / drain regions 92. Therefore, the source / drain contacts 112 can be optionally omitted from the epitaxial source / drain regions 92.

[0074] exist FIG. 21A to FIG. 21C In the embodiment, a front side interconnect structure 120 is formed on the second ILD 106. The front side interconnect structure 120 may be referred to as a front side interconnect structure because it is formed on the front side of the transistor structure 109 (eg, the side of the transistor structure 109 on which active devices are formed).

[0075] The front-side interconnect structure 120 may include one or more layers of first conductive features 122 formed in one or more stacked first dielectric layers 124. Each of the stacked first dielectric layers 124 may include a dielectric material, such as a low-k dielectric material, an ultra-low-k (ELK) dielectric material, etc. The first dielectric layer 124 may be deposited using a suitable process, such as CVD, ALD, PVD, PECVD, etc.

[0076] The first conductive component 122 may include conductive wires and conductive vias interconnecting the conductive wire layers. The conductive vias may extend through the corresponding first dielectric layer 124 to provide vertical connections between the conductive wire layers. The first conductive component 122 may be formed by any acceptable process, such as a damascene process, a dual damascene process, etc.

[0077] In some embodiments, the first conductive component 122 can be formed using a damascene process, in which a combination of photolithography and etching techniques is used to pattern the corresponding first dielectric layer 124 to form a groove corresponding to the desired pattern of the first conductive component 122. An optional diffusion barrier layer and / or an optional adhesion layer can be deposited, and then the groove can be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, combinations thereof, and the like, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, and the like. In an embodiment, the first conductive component 122 can be formed by depositing a seed layer of copper or a copper alloy and filling the groove by electroplating. A chemical mechanical planarization (CMP) process or the like can be used to remove excess conductive material from the surface of the corresponding first dielectric layer 124, and to planarize the surfaces of the first dielectric layer 124 and the first conductive component 122 for subsequent processing.

[0078] FIG. 21A to FIG. 21CFive layers of first conductive features 122 and first dielectric layers 124 in the front side interconnect structure 120 are shown. However, it should be understood that the front side interconnect structure 120 may include any number of first conductive features 122 disposed in any number of first dielectric layers 124. The front side interconnect structure 120 may be electrically connected to the gate contact 114 and the source / drain contacts 112 to form a functional circuit. In some embodiments, the functional circuit formed by the front side interconnect structure 120 may include a logic circuit, a memory circuit, an image sensor circuit, etc.

[0079] exist FIG. 22A to FIG. 22C In the embodiment, the carrier substrate 150 is bonded to the top surface of the front-side interconnect structure 120 by a first bonding layer 152A and a second bonding layer 152B (collectively referred to as bonding layers 152). The carrier substrate 150 may be a glass carrier substrate, a ceramic carrier substrate, a wafer (e.g., a silicon wafer), etc. The carrier substrate 150 may provide structural support during subsequent processing steps and in the completed device.

[0080] In various embodiments, the carrier substrate 150 may be bonded to the front side interconnect structure 120 using a suitable technique such as dielectric-to-dielectric bonding, etc. The dielectric-to-dielectric bonding may include depositing a first bonding layer 152A on the front side interconnect structure 120. In some embodiments, the first bonding layer 152A includes silicon oxide (e.g., high density plasma (HDP) oxide, etc.) deposited by CVD, ALD, PVD, etc. The second bonding layer 152B may also be an oxide layer formed on the surface of the carrier substrate 150 prior to bonding using, for example, CVD, ALD, PVD, thermal oxidation, etc. Other suitable materials may be used for the first bonding layer 152A and the second bonding layer 152B.

[0081] The dielectric to dielectric bonding process may also include applying surface treatment to one or more of the first bonding layer 152A and the second bonding layer 152B. The surface treatment may include plasma treatment. The plasma treatment may be implemented in a vacuum environment. After the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water, etc.) that may be applied to one or more of the bonding layers 152. Then, the carrier substrate 150 is aligned with the front side interconnect structure 120, and the two are pressed against each other to start the pre-bonding of the carrier substrate 150 to the front side interconnect structure 120. The pre-bonding may be implemented at room temperature (e.g., between about 21°C and about 25°C). After the pre-bonding, an annealing process may be applied by, for example, heating the front side interconnect structure 120 and the carrier substrate 150 to a temperature of about 170°C.

[0082] In addition, FIG. 22A to FIG. 22CIn the embodiment, after the carrier substrate 150 is bonded to the front side interconnect structure 120, the device can be flipped so that the back side of the transistor structure 109 faces upward. The back side of the transistor structure 109 can refer to the side opposite to the front side of the transistor structure 109 on which active devices are formed.

[0083] exist FIG. 23A to FIG. 23C In the embodiment, a thinning process may be applied to the back side of the substrate 50. The thinning process may include a planarization process (e.g., mechanical grinding, CMP, etc.), an etch-back process, a combination thereof, etc. The thinning process may expose a surface of the first epitaxial material 91 opposite to the front-side interconnect structure 120. In addition, after the thinning process, a portion of the substrate 50 may remain above the gate structure (e.g., the gate electrode 102 and the gate dielectric layer 100) and the nanostructure 55. FIG. 23A to FIG. 23C As shown in FIG. 5 , after the thinning process, the backside surfaces of substrate 50 , first epitaxial material 91 , STI regions 68 , and fins 66 may be flush with each other.

[0084] exist FIG. 24A to FIG. 24C , the remaining portions of the fins 66 and the substrate 50 are removed and replaced with the second dielectric layer 125. The fins 66 and the substrate 50 can be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), etc. The etching process can be a process that is selective to the materials of the fins 66 and the substrate 50 (e.g., etches the materials of the fins 66 and the substrate 50 at a faster rate than the STI regions 68, the gate dielectric layer 100, the epitaxial source / drain regions 92, and the first epitaxial material 91). After etching the fins 66 and the substrate 50, the surfaces of the STI regions 68, the gate dielectric layer 100, the epitaxial source / drain regions 92, and the first epitaxial material 91 can be exposed.

[0085] Then, a second dielectric layer 125 is deposited on the back side of the transistor structure 109 in the recess formed by removing the fin 66 and the substrate 50. The second dielectric layer 125 can be deposited over the STI region 68, the gate dielectric layer 100, and the epitaxial source / drain region 92. The second dielectric layer 125 can physically contact the surfaces of the STI region 68, the gate dielectric layer 100, the epitaxial source / drain region 92, and the first epitaxial material 91. The second dielectric layer 125 can be substantially similar to the above description of 18A to 18C For example, the second dielectric layer 125 may be formed of a material similar to that of the second ILD 106 and using a process similar to that of the second ILD 106. FIG. 24A to FIG. 24CAs shown in , the material of the second dielectric layer 125 can be removed using a CMP process or the like, so that the top surface of the second dielectric layer 125 is flush with the top surfaces of the STI regions 68 and the first epitaxial material 91. It should be noted that in the discussion herein, the term "similar material" (or "similar process") is used to refer to the same or similar material (or process).

[0086] exist FIG. 25A to FIG. 25C , the first epitaxial material 91 is removed to form a fifth recess 128, and a second silicide region 129 is formed in the fifth recess 128. The first epitaxial material 91 can be removed by a suitable etching process, which can be an isotropic etching process, such as a wet etching process. The etching process can have a high etching selectivity to the material of the first epitaxial material 91. Therefore, the first epitaxial material 91 can be removed without significantly removing the material of the second dielectric layer 125, the STI region 68, or the epitaxial source / drain region 92. The fifth recess 128 can expose the sidewalls of the STI region 68, the backside surface of the epitaxial source / drain region 92, and the sidewalls of the second dielectric layer 125.

[0087] Then, a second silicide region 129 may be formed in the fifth recess 128 on the back side of the epitaxial source / drain region 92. The second silicide region 129 may be similar to the one described above with respect to FIG. 19A to FIG. 19C For example, the second silicide region 129 may be formed of a similar material and using a similar process as the first silicide region 110 .

[0088] exist FIG. 26A to FIG. 26C In the embodiment, a backside via 130 is formed in the fifth recess 128. The backside via 130 can extend through the second dielectric layer 125 and the STI region 68, and can be electrically coupled to the epitaxial source / drain region 92 through the second silicide region 129. The backside via 130 can be similar to the above description of FIG. 20A to FIG. 20C For example, the backside via 130 can be formed of similar materials and using similar processes as the source / drain contacts 112 .

[0089] Next, in FIG. 27A to FIG. 36C In the embodiment of the present invention, a backside interconnect structure 136 having an embedded metal-insulator-metal (MIM) capacitor 147 (also referred to as a decoupling capacitor 147) is formed. In some embodiments, the backside interconnect structure 136 is used to distribute power to the formed semiconductor device and can be referred to as a backside power distribution network (PDN). In addition to distributing power, the disclosed backside interconnect structure 136 includes an integrated MIM capacitor and achieves approximately 100 fF / μm 2The integrated MIM capacitors may be used to form power supply circuits and / or to stabilize reference voltages in a PDN, thus achieving improved performance for the formed device.

[0090] exist FIG. 27A to FIG. 27D , a conductive line 134 and a third dielectric layer 132 are formed over the second dielectric layer 125, the STI region 68, and the backside via 130. The third dielectric layer 132 can be similar to the second dielectric layer 125. For example, the third dielectric layer 132 can be formed of a similar material and using a similar process as the second dielectric layer 125.

[0091] The wire 134 is formed in the third dielectric layer 132. Forming the wire 134 may include, for example, patterning a groove in the third dielectric layer 132 using a combination of photolithography and etching processes. The pattern of the groove in the third dielectric layer 132 may correspond to the pattern of the wire 134. Then, the wire 134 is formed by depositing a conductive material in the groove. In some embodiments, the wire 134 includes a metal layer, which may be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the wire 134 includes copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, etc. Before filling the groove with the conductive material, an optional diffusion barrier layer and / or an optional adhesion layer may be deposited. Suitable materials for the barrier layer / adhesion layer include titanium, titanium nitride, tantalum, tantalum nitride, etc. The wire 134 may be formed using, for example, CVD, ALD, PVD, plating, etc. The wire 134 is physically and electrically coupled to the epitaxial source / drain region 92 through the backside via 130 and the second silicide region 129. A planarization process (eg, CMP, grinding, etch-back, etc.) may be performed to remove excess portions of the conductive line 134 formed over the third dielectric layer 132 .

[0092] In some embodiments, the conductor 134 is a power rail, which is a conductor that electrically connects the epitaxial source / drain region 92 to a reference voltage, a supply voltage, etc. Advantages can be achieved by placing the power rail on the back side of the resulting semiconductor die rather than on the front side of the semiconductor die. For example, the gate density of the nanoFET and / or the interconnect density of the front side interconnect structure 120 can be increased. In addition, the back side of the semiconductor die can accommodate a wider power rail, thereby reducing resistance and increasing the efficiency of power delivery to the nanoFET. For example, the width of the conductor 134 can be at least twice the width of the first level conductor (e.g., the first conductive component 122) of the front side interconnect structure 120.

[0093] Fig.27DAn embodiment is shown in which the epitaxial source / drain region 92 to which the backside via 130 is electrically coupled has a height greater than the epitaxial source / drain region 92 that is not electrically coupled to the backside via 130. The height of the epitaxial source / drain region 92 can be selected by controlling the depth of the first recess 86 and the second recess 87 and / or controlling the thickness of the first epitaxial material 91. Forming the epitaxial source / drain region 92 that is not electrically coupled to the backside via 130 to have a height less than the epitaxial source / drain region 92 that is electrically coupled to the backside via 130 results in the epitaxial source / drain region 92 that is not electrically coupled to the backside via 130 being separated from the conductive line 134 by a larger thickness of the second dielectric layer 125. This provides better isolation of the epitaxial source / drain region 92 that is not electrically coupled to the backside via 130 from the conductive line 134 and improves device performance.

[0094] exist Figures 28 to 36C , the remaining portion of the backside interconnect structure 136 is formed over the third dielectric layer 132 and the conductive line 134. The backside interconnect structure 136 may be referred to as a backside interconnect structure because it is formed on the back side of the transistor structure 109 (e.g., the side of the transistor structure 109 opposite to the side of the transistor structure 109 on which the active devices are formed). The backside interconnect structure 136 (see, e.g., Fig.35A ) may include a third dielectric layer 132 and a conductive line 134. The backside interconnect structure 136 may also include conductive lines 140A-140C (collectively referred to as conductive lines 140) and conductive vias 139A-139C (collectively referred to as conductive vias 139) formed in fourth dielectric layers 138A-138F (collectively referred to as fourth dielectric layers 138). In addition, the backside interconnect structure 136 may include etch stop layers 141A-141F (collectively referred to as etch stop layers 141) formed between adjacent dielectric layers of the backside interconnect structure 136. The conductive vias 139 (which may be referred to as vias 139) may extend through the respective fourth dielectric layers 138 and the respective etch stop layers 141 to provide vertical connections between the layers of the conductive lines 140.

[0095] The power supply voltage V can be routed via conductor 140 DD (which may be a positive supply voltage) and the supply voltage V SS(which may be an electrical ground or a negative power supply voltage), and a MIM capacitor 147 (e.g., a decoupling capacitor) may be formed in the backside interconnect structure 136. The MIM capacitor 147 may be formed in any of the fourth dielectric layers 138. In addition, the MIM capacitor 147 may be formed in the third dielectric layer 132. In some embodiments, the process of forming the MIM capacitor 147 in the third dielectric layer 132 or in the fourth dielectric layer 138 having the through hole 139 may be more complicated than the process of forming the MIM capacitor 147 in the fourth dielectric layer 138 having the conductive line 140, and therefore, the MIM capacitor 147 is formed only in the fourth dielectric layer 138 having the conductive line 140. These and other variations are fully intended to be included within the scope of the disclosed embodiments.

[0096] In some embodiments, the fourth dielectric layer 138 is formed of a low-k dielectric material or an ultra-low-k (ELK) dielectric material. Examples of low-k or ultra-low-k dielectric materials include fluorine-doped silicon oxide, carbon-doped silicon oxide (CDO), porous silicon oxide, etc. The fourth dielectric layer 138 can be deposited using an appropriate process, such as CVD, ALD, PVD, PECVD, etc. The use of low-k or ultra-low-k dielectric materials can advantageously reduce the parasitic capacitance of the formed device, thereby reducing RC delay and improving device performance. As will be discussed below, in the region where the MIM capacitor 147 is formed, a portion of the low-k or ultra-low-k dielectric material is replaced with a high-k dielectric material because the high-k dielectric material increases the capacitance density of the formed MIM capacitor 147. By using low-k (or ultra-low-k) dielectric materials and high-k dielectric materials in the fourth dielectric layer 138 with the MIM capacitor 147, a balance of performance requirements between reduced RC delay and higher capacitance density is achieved.

[0097] To avoid clutter and to illustrate the details of the backside interconnect structure 136, Figures 28 to 35B Other parts of the semiconductor device (for example, FIG. 27A to FIG. 27D The backside interconnect structure 136 is shown in the case of the portion below the third dielectric layer 132 in FIG.

[0098] Reference now Fig.28 and Fig.29 .exist Fig.28 In the embodiment, an etch stop layer 141A and a fourth dielectric layer 138A are successively formed on the third dielectric layer 132. A through hole 139A is formed to extend through the fourth dielectric layer 138A and the etch stop layer 141A and to be electrically coupled to the corresponding conductive line 134. Next, in Fig.29In the embodiment of the present invention, an etch stop layer 141B and a fourth dielectric layer 138B are successively formed on the fourth dielectric layer 138A, and a conductive line 140A is formed in the fourth dielectric layer 138B. At least some of the conductive lines 140A extend through the fourth dielectric layer 138B and the etch stop layer 141B and are electrically coupled to corresponding vias 139A. Some of the conductive lines 140A may not be coupled to the underlying vias 139A and may be used to route electrical signals within the fourth dielectric layer 138B.

[0099] The etch stop layer 141 (e.g., 141A or 141B) can be formed of a suitable material (such as silicon nitride, silicon oxynitride, silicon carbide, etc.) using a suitable formation method (such as CVD, PECVD, ALD, etc.). The fourth dielectric layer 138 (e.g., 138A or 138B) is formed on the corresponding etch stop layer 141 using a low-k or ultra-low-k dielectric material.

[0100] The conductive via 139 and the conductive line 140 can be formed using any acceptable process, such as a damascene process, a dual damascene process, etc. In some embodiments, the conductive via 139 (or the conductive line 140) can be formed using a damascene process, wherein the corresponding fourth dielectric layer 138 and the corresponding etch stop layer 141 are patterned using a combination of photolithography and etching techniques to form a groove corresponding to the desired pattern of the conductive via 139 (or the conductive line 140). An optional diffusion barrier layer and / or an optional adhesion layer can be deposited, and then the groove can be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, tantalum, tantalum nitride, combinations thereof, etc., and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, etc. In an embodiment, the conductive via 139 (or the conductive line 140) can be formed by depositing a seed layer of copper or a copper alloy and filling the groove by electroplating. A chemical mechanical planarization (CMP) process or the like may be used to remove excess conductive material from the surface of the corresponding fourth dielectric layer 138 and planarize the surfaces of the fourth dielectric layer 138 and the conductive via 139 (or conductive line 140 ) for subsequent processing.

[0101] Next, in Fig.30 In the embodiment of the present invention, the portion of the fourth dielectric layer 138B located in the region 142 of the fourth dielectric layer 138B is removed, for example, by a suitable etching process (such as an anisotropic etching process). An etching mask (not shown) may be used to cover the region of the fourth dielectric layer 138B located outside the region 142 and to expose the region of the fourth dielectric layer 138B located inside the region 142. The portion of the fourth dielectric layer 138B exposed by the etching mask is removed. Fig.30As shown in FIG. 1 , after removing a portion of the fourth dielectric layer 138B, an opening 149 is formed in the region 142 of the fourth dielectric layer 138. The opening 149 exposes the upper surface and sidewalls of some of the conductive lines 140A in the region 142 of the fourth dielectric layer 138B. Fig.30 In the example, the etch stop layer 141B is exposed at the bottom of the opening 149, for example, because the etching process used to remove the fourth dielectric layer 138B is selective to (eg, has a higher etching rate for) the material of the fourth dielectric layer 138B.

[0102] Next, in Fig.31 in Fig.30 A barrier material 143 is formed over the structure in (eg, conformally). The barrier material 143 may be tantalum nitride, titanium nitride, tantalum, titanium, etc., and may be formed by a suitable formation method, such as CVD, PVD, PECVD, ALD, etc. Fig.31 As shown in FIG. 1 , the barrier material 143 extends along the sidewalls and upper surface of the conductive line 140A in the region 142 and along the upper surface of the fourth dielectric layer 138B.

[0103] Next, in Fig.32 In the embodiment, the blocking material 143 is etched by, for example, an anisotropic etching process. In some embodiments, the anisotropic etching process removes portions of the blocking material 143 from the upper surface of the fourth dielectric layer 138B and from the bottom of the opening 149. In some embodiments, the anisotropic etching process also removes portions of the etch stop layer 141B located at the bottom of the opening 149. The remaining portions of the blocking material 143 (which extend along the sidewalls of the conductive line 140A in the region 142 or along the sidewalls of the fourth dielectric layer 138B exposed by the opening 149) form the blocking layer 143. ... Fig.32 In the example of FIG. 1 , since the conductive line 140A has an inclined sidewall (e.g., having a trapezoidal cross section) and due to the anisotropy of the anisotropic etching process, some horizontal portions of the barrier material 143 (and the etch stop layer 141B) at the bottom of the opening 149 adjacent to the conductive line 104A remain after the anisotropic etching process. Therefore, the barrier layer 143 along the sidewall of the conductive line 104A has an L-shaped cross section.

[0104] Next, in Fig.33 In the embodiment of the present invention, a high-k dielectric material 145 is formed to fill the opening 149. The high-k dielectric material 145 may have an k value greater than about 7.0 (e.g., between about 7.0 and about 40), and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. In some embodiments, the high-k dielectric material 145 is ZrO 2 、Al 2 O 3 、HFO2 、 2 O 5 or TiO 2 The high-k dielectric material 145 may be formed using a suitable formation method such as CVD, PECVD, ALD, etc.

[0105] Next, in Fig.34A In the process, a planarization process, such as CMP, is performed to remove excess portions of the high-k dielectric material 145 from the upper surface of the fourth dielectric layer 138B and achieve a coplanar surface for the fourth dielectric layer 138B, the barrier layer 143, and the high-k dielectric material 145. After the planarization process, a plurality of MIM capacitors 147 are formed in the region 142 of the fourth dielectric layer 138B located between adjacent conductive lines 140A. Each of the MIM capacitors 147 includes a first barrier layer 143 (labeled as 143A) along a first sidewall of a first conductive line 140A, a second barrier layer 143 (labeled as 143B) along a second sidewall of a second conductive line 140A adjacent to the first conductive line 140A, and a high-k dielectric material 145 located between the first barrier layer 143A and the second barrier layer 143B. The high-k dielectric material 145 completely fills the space between the first barrier layer 143A and the second barrier layer 143B (eg, continuously extends from the first barrier layer 143A to the second barrier layer 143B). Fig.34A In an example of the present invention, the high-k dielectric material 145 includes a downward protrusion extending through the etch stop layer 141B to the fourth dielectric layer 138A. As an example, the aspect ratio of the conductive line 140A (calculated as the ratio between the height of the conductive line 140 and the width of the conductive line 140A) can be about 2 or about 4. As an example, the aspect ratio of the high-k dielectric material 145 can be greater than 10.

[0106] Fig.34B A top view of a conductive line 140A, a barrier layer 143 surrounding the conductive line 140A, and a high-k dielectric material 145 between adjacent conductive lines 140A is shown. It should be noted that not all components are shown for simplicity and clarity. Fig.34B In the example of FIG. 1 , the barrier layer 143 extends along (e.g., covers) all four sidewalls of each conductive line 140A. The barrier layer 143 along two opposite sidewalls of two adjacent conductive lines 140A and the high-k dielectric material 145 therebetween form a MIM capacitor 147. The barrier layer 143 (e.g., 143A and 134B) serves as an electrode of the capacitor, and the high-k dielectric material 145 serves as a dielectric medium between the electrodes of the capacitor. In the illustrated embodiment, the MIM capacitor 147 is coupled between two adjacent conductive lines 140A. In some embodiments, the adjacent conductive lines 140A are used to route the power supply voltage V in an alternating sequence. DD (e.g., positive supply voltage) and V SS(e.g., electrically grounded). MIM capacitor 147 may be used as a decoupling capacitor to stabilize the voltage on conductor 140A. As a result, less voltage disturbance (also referred to as supply voltage noise) is observed on conductor 140A, and the performance of the formed device is improved due to less supply voltage noise.

[0107] Next, in Fig.35A In the embodiment, additional layers of etch stop layer 141 (e.g., 141C, 141D, 141E, and 141F) and additional layers of fourth dielectric layer 138 (e.g., 138C, 138D, 138E, and 138F) are formed over fourth dielectric layer 138B. Additional layers of vias 139 (e.g., 139B and 139C) and additional layers of conductive lines 140 (e.g., 140B and 140C) are formed in alternating layers of fourth dielectric layer 138, as shown in FIG. Fig.35A The materials and formation methods for the etch stop layer 141, the fourth dielectric layer 138, the via 139, and the conductive line 140 are the same as or similar to those discussed above, and thus the details will not be repeated.

[0108] Next, an etch stop layer 141G, a passivation layer 144, an under-bump metallization (UBM) structure 146, and an external connector 148 are formed over the backside interconnect structure 136. The etch stop layer 141G may be formed using the same or similar material as the etch stop layer 141F. The passivation layer 144 may include a polymer such as PBO, polyimide, BCB, etc. Alternatively, the passivation layer 144 may include a non-organic dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc. The passivation layer 144 may be deposited by, for example, CVD, PVD, ALD, etc.

[0109] The UBM structure 146 is formed to pass through the passivation layer 144 and the etch stop layer 141G to the wire 140 in the backside interconnect structure 136, and the external connector 148 is formed on the UBM structure 146. The UBM structure 146 may include one or more layers of copper, nickel, gold, etc., which are formed by an electroplating process, etc. The external connector 148 (e.g., a solder ball, a copper pillar, a copper pillar with a solder material on the top) is formed on the UBM structure 146. The formation of the external connector 148 may include: placing a solder ball on the exposed portion of the UBM structure 146; and reflowing the solder ball. In some embodiments, the formation of the external connector 148 includes: performing a plating step to form a solder area above the topmost wire 140C; and then reflowing the solder area. The UBM structure 146 and the external connector 148 can be used to provide input / output connections to other electronic components (such as other device dies, redistribution structures, printed circuit boards (PCBs), motherboards, etc.). UBM structures 146 and external connections 148 may also be referred to as backside input / output pads, which may provide signal, supply voltage, and / or ground connections to the nanoFETs described above.

[0110] Fig.35A Three layers of conductive vias 139, three layers of conductive wires 140, and six layers of fourth dielectric layer 138 are shown in backside interconnect structure 136. However, it should be understood that backside interconnect structure 136 may include any number of conductive vias 139 and conductive wires 140 disposed in any number of fourth dielectric layers 138. Backside interconnect structure 136 may be electrically connected to conductive wires 134 (e.g., power rails) to provide circuitry (e.g., power circuitry) on the back side of the nanoFET. In addition, while MIM capacitor 147 is shown as being formed in one of fourth dielectric layers 138 (e.g., 138B), MIM capacitor 147 may be formed in any of fourth dielectric layers 138, as discussed above.

[0111] Recall that in the formation process for via 139 and each of conductive lines 140 and 134, an optional barrier layer may be formed before the conductive material (e.g., copper) fills the trench in the dielectric layer (e.g., 138 or 132). The optional barrier layer (if formed) is not formed in the Fig.35A Therefore, Fig.35A An embodiment may be shown in which the optional barrier layer is not formed in via 139 and conductive lines 140 and 134. However, for conductive lines 140A in the region (e.g., 142) where MIM capacitor 147 is formed, barrier layer 143 is formed along the sidewalls of those conductive lines 140 in the region, such as Fig.35A as shown in .

[0112] Fig.35AAnother embodiment of forming an optional barrier layer for all vias 139 and conductive lines 140 and 134 may also be shown. Fig.35A , but those skilled in the art will readily appreciate that the optional barrier layer may have Fig.35B In addition, for the conductive lines 140A in the regions (e.g., 142) where the MIM capacitor 147 is formed, the barrier layer 143 is also formed along the sidewalls of those conductive lines 140, such as Fig.35A In other words, for the wire 140A in the region (e.g., 142) where the MIM capacitor 147 is formed, a double-layer barrier layer (e.g., 151 and 143) is formed along the sidewalls thereof, and a single-layer barrier layer (e.g., 151) is formed along the bottom thereof. In contrast, the wire 140 outside the region (e.g., 142) has a single-layer barrier layer (e.g., 151) formed along the sidewalls and bottom thereof.

[0113] Fig.35B An embodiment is shown in which an optional barrier layer 151 (e.g., TiN, TaN, Ti, Ta) is formed for all vias 139 and conductive lines 140 and 134 in backside interconnect structure 136 (except conductive line 140A in region 142 where MIM capacitor 147 is formed). In some embodiments, Fig.29 During the processing step of , before forming the optional barrier layer 151 for the conductive line 140A in the fourth dielectric layer 138B, a patterned mask (e.g., a patterned photoresist) is formed to cover the trenches in the region 142 of the fourth dielectric layer 138B (e.g., at the location of the conductive line 140A to be formed later), so that only the optional barrier layer 151 for the conductive line 140 outside the region 142 is formed. The patterned mask layer is then removed, and a conductive material is formed in the trenches to form the conductive line 140A. Due to the formation process for the optional barrier layer 151 described above, the conductive line 140A outside the region 142 has the optional barrier layer 151 formed along its sidewalls and its bottom, while the conductive line 140 in the region 142 has the barrier layer 143 formed along its sidewalls. It should be noted that the bottom of the conductive line 140 in the region 142 is free of barrier layers 151 and 143. In some embodiments, the material (eg, TiN, TaN) of the barrier layer (eg, 151 , 143 ) has a higher resistance than the conductive material (eg, Cu) of the conductive line 140C. Fig.35B The example forms a single barrier layer 143 along the sidewalls of the conductive line 140A in the region 142 , thereby avoiding the formation of a double barrier layer along the sidewalls of the conductive line 140A in the region 142 , which can reduce the overall resistance of the PDN and the power consumption of the MIM capacitor 147 .

[0114] In the wiring supply voltage V SS and VDD The backside interconnect structure 136 includes a decoupling capacitor 147 between the wires 140 to stabilize the power supply voltage V SS and V DD , which results in improved device performance. The power supply voltage V is routed in the backside interconnect structure 136 SS and V DD And providing the decoupling capacitor 147 in the backside interconnect structure 136 allows the transistor structure 109 to be formed in a smaller area, which allows more devices to be formed in a given area. The use of a high-k dielectric material 145 having a high k value (e.g., a k value greater than about 7.0) in the decoupling capacitor 147 increases the amount of charge that the decoupling capacitor 147 can hold while allowing the size of the decoupling capacitor 147 to be minimized.

[0115] FIG. 36A to FIG. 36C 1 shows a cross-sectional view of a nanoFET device 180 after forming a backside interconnect structure 136, a passivation layer 144, a UBM structure 146, and an external connector 148. For simplicity, FIG. 36A to FIG. 36C The MIM capacitor 147 in FIG. 1 is shown in simplified form as including two barrier layers and a high-k dielectric material therebetween, it being understood that the details of the MIM capacitor are described in detail in, for example, Fig.35A , Fig.35B or Fig.43 In some embodiments, a plurality of (e.g., identical) nanoFET devices 180 are formed on a carrier substrate 150, and a cutting process is performed in the next step to separate the plurality of nanoFET devices into independent (e.g., separated) nanoFET devices. For ease of discussion, the portion of the nanoFET device 180 disposed between the front-side interconnect structure 120 and the back-side interconnect structure 136 is referred to as a device layer 160.

[0116] Figures 37 to 43 Another embodiment for forming the backside interconnect structure 136 is shown. To avoid clutter and to show the details of the backside interconnect structure 136, Figures 37 to 43 The backside interconnect structure 136 is shown, while other portions of the semiconductor device (eg, FIG. 27A to FIG. 27D The portion below the third dielectric layer 132 in FIG.

[0117] exist Fig.37 In the process, the etch stop layer 141A / 141B and the fourth dielectric layer 138A / 138B are formed on the third dielectric layer 132. The via 139A is formed in the fourth dielectric layer 138A, and the conductive line 140A is formed in the fourth dielectric layer 138B. Fig.29 The processing in is the same or similar, so it will not be repeated here. It should be noted that in Figures 37 to 43In the embodiment of FIG. 1 , an optional barrier layer 151 is formed for each of the via 139 and the conductive lines 140 and 134. The spacing D1 between adjacent conductive lines 140 has a value of, for example, 80 nm.

[0118] Next, in Fig.38 In the embodiment, a portion of the fourth dielectric layer 138B located in the region 142 of the fourth dielectric layer 138B is removed to form an opening 149. The sidewall of the conductive line 140A in the opening 149 is exposed. A suitable etching process, such as an anisotropic etching process, may be performed using a mask layer to remove a portion of the fourth dielectric layer 138B.

[0119] Next, in Fig.39 In the embodiment of the present invention, a high-k dielectric material 145 is formed (eg, conformally) in the opening 149 and over the upper surface of the fourth dielectric layer 138B. The high-k dielectric material 145 lines the exposed sidewalls and upper surface of the conductive line 140A.

[0120] Next, in Fig.40 In the embodiment of the present invention, an anisotropic etching process is performed to remove a portion of the high-k dielectric material 145 from the upper surface of the fourth dielectric layer 138B and from the bottom of the opening 149. In some embodiments, the anisotropic etching process also removes a portion of the etch stop layer 141B from the bottom of the opening 149. The remaining portion of the high-k dielectric material 145 lines (e.g., covers) the sidewalls of the conductive line 140 exposed by the opening 149. Due to the anisotropy of the anisotropic etching process, the portion of the etch stop layer 141B located below the remaining portion of the high-k dielectric material 145 also remains in the device.

[0121] Next, in Fig.41 In the embodiment of the present invention, a barrier material 151' lining the sidewalls and bottom of the opening 149 is formed on the upper surface of the fourth dielectric layer 138B (e.g., conformally). In some embodiments, the barrier material 151' is the same material used to form the optional barrier layer 151, such as titanium nitride, tantalum nitride, titanium, tantalum, etc. Next, a conductive material 153 is formed in the opening 149 on the barrier material 151'. The conductive material 153 can be the same material used to form the conductive line 140, such as copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, etc., and can be formed using, for example, CVD, ALD, PVD, plating, etc.

[0122] Next, in Fig.42In the process, a planarization process, such as CMP, is performed to remove excess portions of the barrier material 151' and excess portions of the conductive material 153 from the upper surface of the fourth dielectric layer 138B. The remaining portion of the conductive material 153 located in the opening 149 and the remaining portion of the barrier material 151' located in the opening 149 form a new conductive line 140A. The remaining portion of the barrier material 151' is referred to as a barrier layer 151 of the newly formed conductive line 140A. After the planarization process, a coplanar upper surface is achieved between the fourth dielectric layer 138B, the conductive line 140A, the barrier layer 151, and the high-k dielectric material 145.

[0123] like Fig.42 As shown in FIG. 1 , since the newly formed conductive line 140A is formed between the existing conductive lines 140A in the region 142, the spacing D2 between the conductive lines 140A in the region 142 is Fig.37 It should be noted that the spacing between adjacent conductive lines 140A outside the region 142 or between conductive lines 140 at the boundary of the region 142 and adjacent conductive lines 140 outside the region 142 still has the same value as the spacing D1.

[0124] exist Fig.42 In the embodiment of the present invention, a plurality of MIM capacitors 147 are formed in region 142. Each of MIM capacitors 147 includes a portion of barrier layer 151 along a first sidewall of first conductive line 140A (labeled 151A), a portion of barrier layer 151 along a second sidewall of second conductive line 140A adjacent to first conductive line 140A (labeled 151B), and a portion of high-k dielectric material 145 disposed therebetween. Due to the smaller spacing D2 between adjacent conductive lines 140A in region 142, the conductive lines 140A in region 142 are closer to each other than conductive lines 140A. Figures 28 to 35B As compared to the embodiments of the present invention, the capacitance density can be increased (eg, doubled). As an example, the aspect ratio of the conductive line 140A can be about 2 or about 4. As an example, the aspect ratio of the high-k dielectric material 145 can be greater than 10.

[0125] Next, in Fig.43 In the embodiment, additional layers of etch stop layer 141 (e.g., 141C, 141D, 141E, and 141F) and additional layers of fourth dielectric layer 138 (e.g., 138C, 138D, 138E, and 138F) are formed over fourth dielectric layer 138B. Additional layers of vias 139 (e.g., 139B and 139C) and additional layers of conductive lines 140 (e.g., 140B and 140C) are formed in alternating layers of fourth dielectric layer 138, as shown in FIG. Fig.43 Next, an etch stop layer 141G, a passivation layer 144 , an under bump metallization (UBM) structure 146 , and external connectors 148 are formed over the backside interconnect structure 136 .

[0126] Fig.44 and Fig.45 2 shows a cross-sectional view of a semiconductor package 200 in an embodiment at different manufacturing stages. Fig.44 and Fig.45 A simplified cross-sectional view of a nanoFET device 180 is used in which details of the frontside interconnect structure 120, device layer 160, and backside interconnect structure 136 are omitted. Therefore, the frontside interconnect structure 120, device layer 160, and backside interconnect structure 136 of the nanoFET device 180 are simply shown as rectangular shaped boxes.

[0127] exist Fig.44 In the nano FET device 180 (see for example FIG. 36A to FIG. 36C ) is attached to interposer 170. Interposer 170 includes substrate 171 (e.g., glass substrate, ceramic substrate, polymer substrate, etc.), redistribution structure (RDS) 173 on a first side of substrate 171, external connector 175 on a second side of substrate 171, and conductive path 172 (e.g., through substrate via (TSV)) located in substrate 171 and electrically coupling RDS 173 with external connector 175. RDS 173 includes multiple dielectric layers and conductive features (e.g., vias and wires) formed in the multiple dielectric layers. In an embodiment, external connector 148 of nanoFET device 180 is coupled to (e.g., bonded to) a conductive pad at an upper surface of RDS 173.

[0128] Next, in Fig.45 147, the external connectors 175 of the interposer 170 are bonded to conductive pads on the upper surface of the substrate 177. The substrate 177 can be, for example, a printed circuit board (PCB). The cover 183 is bonded to the carrier substrate 150 using a thermal interface material (TIM) 181. The heat sink 185 is attached to the upper surface of the cover 183 for dissipating the heat generated by the nanoFET device 180 during operation. In some embodiments, the high-k dielectric material used to form the MIM capacitor 147 advantageously increases the efficiency of heat transfer from the backside interconnect structure 136 to the heat sink 185.

[0129] Embodiments can achieve advantages. For example, including MIM capacitor 147 in backside interconnect structure 136 stabilizes power supply voltage V DD and the power supply voltage V SS , which improves device performance. The MIM capacitor 147 is closer to the formed nanoFET and has a better resistance to the electrode (e.g., barrier layer). In addition, the backside interconnect structure 136 includes the MIM capacitor 147, the power supply voltage V DD and / or supply voltage V SSAllowing more devices to be formed in a smaller area, thus increasing device integration density. Using high-k dielectric material 145 in MIM capacitor 147 allows for the formation of smaller MIM capacitors 147 while increasing the amount of charge that MIM capacitor 147 can hold. High-k dielectric material 145 also increases heat dissipation efficiency. Conventional methods for forming embedded MIM capacitors require additional processing steps, which increases production costs and may cause stress and device failure at the edge of the chip. The method disclosed herein can be easily integrated into existing BEOL processing without negatively affecting chip integrity.

[0130] Fig.46 1 is a flow chart of a method 1000 of forming a semiconductor device according to some embodiments. It should be understood that Fig.46 The embodiment methods shown in are merely examples of many possible embodiment methods. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, deletions, substitutions, rearrangements, or repetitions may be made. Fig.46 The steps shown in .

[0131] refer to Fig.46 In block 1010, a device layer including a nanostructure and a gate structure around the nanostructure is formed. In block 1020, a first interconnect structure is formed on a front side of the device layer. In block 1030, a second interconnect structure is formed on a back side of the device layer opposite to the front side of the device layer, including: forming a dielectric layer along the back side of the device layer using a first dielectric material; forming a first conductive component and a second conductive component in the dielectric layer; forming an opening in the dielectric layer by removing a portion of the dielectric layer disposed between the first conductive component and the second conductive component; forming a first barrier layer and a second barrier layer along a first sidewall of the first conductive component facing the second conductive component and along a second sidewall of the second conductive component facing the first conductive component, respectively; and forming a second dielectric material different from the first dielectric material in the opening between the first barrier layer and the second barrier layer.

[0132] According to an embodiment, a method for forming a semiconductor device includes: forming a device layer including a nanostructure and a gate structure around the nanostructure; forming a first interconnect structure on a front side of the device layer; and forming a second interconnect structure on a back side of the device layer opposite to the front side of the device layer, including: forming a dielectric layer along the back side of the device layer using a first dielectric material; forming a first conductive component and a second conductive component in the dielectric layer; forming an opening in the dielectric layer by removing a portion of the dielectric layer disposed between the first conductive component and the second conductive component; forming a first barrier layer and a second barrier layer along a first sidewall of the first conductive component facing the second conductive component and along a second sidewall of the second conductive component facing the first conductive component, respectively; and forming a second dielectric material different from the first dielectric material in the opening between the first barrier layer and the second barrier layer. In an embodiment, a first dielectric constant of the first dielectric material is lower than a second dielectric constant of the second dielectric material. In an embodiment, the first dielectric material is a low-K dielectric material, and the second dielectric material is a high-K dielectric material. In an embodiment, forming the opening is performed before forming the first barrier layer and the second barrier layer, wherein, after removing the portion of the dielectric layer to form the opening, the opening exposes the first sidewall of the first conductive component and exposes the second sidewall of the second conductive component. In an embodiment, forming the first barrier layer and the second barrier layer includes: lining the sidewalls and the bottom of the opening with a barrier material; and after the lining, removing the barrier material from the bottom of the opening, wherein a first remaining portion of the barrier material along the first sidewall of the first conductive component forms the first barrier layer, and a second remaining portion of the barrier material along the second sidewall of the second conductive component forms the second barrier layer. In an embodiment, removing the barrier material includes performing an anisotropic etching process to remove the barrier material from the bottom of the opening. In an embodiment, forming the second dielectric material includes: after forming the first barrier layer and the second barrier layer, filling the opening with the second dielectric material, wherein after the filling, the second dielectric material extends continuously from the first barrier layer to the second barrier layer. In an embodiment, forming the opening is performed after forming the first barrier layer and the second barrier layer, wherein, after removing a portion of the dielectric layer to form the opening, the opening exposes the first barrier layer disposed along a first sidewall of the first conductive component and exposes the second barrier layer disposed along a second sidewall of the second conductive component. In an embodiment, forming the second dielectric material comprises: lining the sidewalls and bottom of the opening with the second dielectric material, wherein a first portion of the second dielectric material extends along the first barrier layer, a second portion of the second dielectric material extends along the second barrier layer, and a third portion of the second dielectric material extends along the bottom of the opening; and after lining the sidewalls and bottom of the opening with the second dielectric material, removing the third portion of the second dielectric material from the bottom of the opening. In an embodiment, the method further comprises, after removing the third portion of the second dielectric material: lining the sidewalls and bottom of the opening with a barrier material; and after lining the sidewalls and bottom of the opening with the barrier material, filling the opening with a conductive material.In an embodiment, the method further includes, after filling the opening: removing the blocking material from a first surface of the dielectric layer away from the device layer, wherein after removing the blocking material, a remaining portion of the conductive material located in the opening forms a third conductive component, wherein the remaining portion of the blocking material extends along side walls of the third conductive component and a bottom of the third conductive component.

[0133] According to an embodiment, a method of forming a semiconductor device includes: forming a device layer including a nanostructure and a gate structure around the nanostructure; forming a first interconnect structure on a first side of the device layer; and forming a second interconnect structure on a second side of the device layer opposite to the first side of the device layer, including: forming a dielectric layer along the second side of the device layer using a first dielectric material; forming a first conductive component surrounded by a first barrier layer in the dielectric layer; forming a second conductive component surrounded by a second barrier layer in the dielectric layer; removing a portion of the dielectric layer disposed between the first conductive component and the second conductive component to form an opening in the dielectric layer, the opening exposing a first sidewall of the first barrier layer and a second sidewall of the second barrier layer; forming a second dielectric material different from the first dielectric material along the first sidewall of the first barrier layer and along the second sidewall of the second barrier layer; after forming the second dielectric material, lining the sidewalls and bottom of the opening with a third barrier layer; and after forming the third barrier layer, filling the opening with a conductive material. In an embodiment, the first dielectric material has a lower dielectric constant than the second dielectric material. In an embodiment, the first dielectric material is a low-K dielectric material, and the second dielectric material is a high-K dielectric material. In an embodiment, the first barrier layer, the second barrier layer and the third barrier layer are formed of the same material. In an embodiment, the first conductive component and the second conductive component are conductive lines. In an embodiment, the first conductive component and the second conductive component are vias.

[0134] According to an embodiment, a semiconductor device includes: a device layer including a nanostructure and a gate structure around the nanostructure; a first interconnect structure located on a first side of the device layer; and a second interconnect structure located on a second side of the device layer opposite to the first side of the device layer, including: a dielectric layer along the second side of the device layer, wherein the dielectric layer includes a first dielectric material; a first conductive component and a second conductive component embedded in the dielectric layer; and a metal-insulator-metal (MIM) capacitor located in the dielectric layer, including: a first barrier layer along a first sidewall of the first conductive component facing the second conductive component; a second barrier layer along a second sidewall of the second conductive component facing the first conductive component; and a second dielectric material located in the dielectric layer between the first barrier layer and the second barrier layer, wherein the second dielectric material is different from the first dielectric material. In an embodiment, the second dielectric material has a higher dielectric constant than the first dielectric material. In an embodiment, the second dielectric material extends continuously from the first barrier layer to the second barrier layer.

[0135] Some embodiments of the present application provide a method for forming a semiconductor device, the method comprising: forming a device layer comprising a nanostructure and a gate structure located around the nanostructure; forming a first interconnect structure on the front side of the device layer; and forming a second interconnect structure on the back side of the device layer opposite to the front side of the device layer, comprising: forming a dielectric layer along the back side of the device layer using a first dielectric material; forming a first conductive component and a second conductive component in the dielectric layer; forming an opening in the dielectric layer by removing a portion of the dielectric layer disposed between the first conductive component and the second conductive component; forming a first barrier layer and a second barrier layer respectively along a first side wall of the first conductive component facing the second conductive component and along a second side wall of the second conductive component facing the first conductive component; and forming a second dielectric material different from the first dielectric material in the opening between the first barrier layer and the second barrier layer.

[0136] In some embodiments, the first dielectric material has a first dielectric constant that is lower than a second dielectric constant of the second dielectric material. In some embodiments, the first dielectric material is a low-K dielectric material, and the second dielectric material is a high-K dielectric material. In some embodiments, forming the opening is performed before forming the first barrier layer and the second barrier layer, wherein, after removing the portion of the dielectric layer to form the opening, the opening exposes the first sidewall of the first conductive component and exposes the second sidewall of the second conductive component. In some embodiments, forming the first barrier layer and the second barrier layer includes: lining the sidewalls and bottom of the opening with a barrier material; and after the lining, removing the barrier material from the bottom of the opening, wherein a first remaining portion of the barrier material along the first sidewall of the first conductive component forms the first barrier layer, and a second remaining portion of the barrier material along the second sidewall of the second conductive component forms the second barrier layer. In some embodiments, removing the barrier material includes performing an anisotropic etching process to remove the barrier material from the bottom of the opening. In some embodiments, forming the second dielectric material comprises: filling the opening with the second dielectric material after forming the first barrier layer and the second barrier layer, wherein after the filling, the second dielectric material extends continuously from the first barrier layer to the second barrier layer. In some embodiments, forming the opening is performed after forming the first barrier layer and the second barrier layer, wherein after removing the portion of the dielectric layer to form the opening, the opening exposes the first barrier layer disposed along the first sidewall of the first conductive component and exposes the second barrier layer disposed along the second sidewall of the second conductive component. In some embodiments, forming the second dielectric material comprises: lining the sidewalls and bottom of the opening with the second dielectric material, wherein a first portion of the second dielectric material extends along the first barrier layer, a second portion of the second dielectric material extends along the second barrier layer, and a third portion of the second dielectric material extends along the bottom of the opening; and after lining the sidewalls and the bottom of the opening with the second dielectric material, removing the third portion of the second dielectric material from the bottom of the opening.

[0137] In some embodiments, the method further comprises, after removing the third portion of the second dielectric material: lining the sidewalls and the bottom of the opening with a barrier material; and after lining the sidewalls and the bottom of the opening with the barrier material, filling the opening with a conductive material. In some embodiments, the method further comprises, after filling the opening: removing the barrier material from a first surface of the dielectric layer remote from the device layer, wherein after removing the barrier material, a remaining portion of the conductive material located in the opening forms a third conductive component, wherein the remaining portion of the barrier material extends along the sidewalls of the third conductive component and the bottom of the third conductive component.

[0138] Some other embodiments of the present application provide a method for forming a semiconductor device, the method comprising: forming a device layer including a nanostructure and a gate structure located around the nanostructure; forming a first interconnect structure on a first side of the device layer; and forming a second interconnect structure on a second side of the device layer opposite to the first side of the device layer, comprising: forming a dielectric layer along the second side of the device layer using a first dielectric material; forming a first conductive component surrounded by a first barrier layer in the dielectric layer; forming a second conductive component surrounded by a second barrier layer in the dielectric layer; removing a portion of the dielectric layer disposed between the first conductive component and the second conductive component to form an opening in the dielectric layer, the opening exposing a first sidewall of the first barrier layer and a second sidewall of the second barrier layer; forming a second dielectric material different from the first dielectric material along the first sidewall of the first barrier layer and along the second sidewall of the second barrier layer; after forming the second dielectric material, lining the sidewalls and bottom of the opening with a third barrier layer; and after forming the third barrier layer, filling the opening with a conductive material.

[0139] In some embodiments, the first dielectric material has a lower dielectric constant than the second dielectric material. In some embodiments, the first dielectric material is a low-K dielectric material and the second dielectric material is a high-K dielectric material. In some embodiments, the first barrier layer, the second barrier layer, and the third barrier layer are formed of the same material. In some embodiments, the first conductive component and the second conductive component are wires. In some embodiments, the first conductive component and the second conductive component are vias.

[0140] Some other embodiments of the present application provide a semiconductor device, comprising: a device layer, comprising a nanostructure and a gate structure located around the nanostructure; a first interconnect structure, located on a first side of the device layer; and a second interconnect structure, located on a second side of the device layer opposite to the first side of the device layer, comprising: a dielectric layer, along the second side of the device layer, wherein the dielectric layer comprises a first dielectric material; a first conductive component and a second conductive component, embedded in the dielectric layer; and a metal-insulator-metal (MIM) capacitor, located in the dielectric layer, comprising: a first barrier layer, along a first sidewall of the first conductive component facing the second conductive component; a second barrier layer, along a second sidewall of the second conductive component facing the first conductive component; and a second dielectric material, located in the dielectric layer between the first barrier layer and the second barrier layer, wherein the second dielectric material is different from the first dielectric material.

[0141] In some embodiments, the second dielectric material has a higher dielectric constant than the first dielectric material. In some embodiments, the second dielectric material extends continuously from the first barrier layer to the second barrier layer.

[0142] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor device, the method comprising: forming a device layer including a nanostructure and a gate structure located around the nanostructure; forming a first interconnect structure on a front side of the device layer; as well as forming a second interconnect structure on a back side of the device layer opposite the front side of the device layer, comprising: forming a dielectric layer along the back side of the device layer using a first dielectric material; forming a first conductive feature and a second conductive feature in the dielectric layer; forming an opening in the dielectric layer by removing a portion of the dielectric layer disposed between the first conductive component and the second conductive component; forming a first barrier layer and a second barrier layer along a first side wall of the first conductive component facing the second conductive component and along a second side wall of the second conductive component facing the first conductive component, respectively; and A second dielectric material different from the first dielectric material is formed in the opening between the first barrier layer and the second barrier layer.

2. The method according to claim 1, wherein: The first dielectric material has a first dielectric constant lower than a second dielectric constant of the second dielectric material.

3. The method according to claim 2, wherein: The first dielectric material is a low-K dielectric material, and the second dielectric material is a high-K dielectric material.

4. The method according to claim 1, wherein: Forming the opening is performed before forming the first barrier layer and the second barrier layer, wherein after removing the portion of the dielectric layer to form the opening, the opening exposes the first sidewall of the first conductive component and exposes the second sidewall of the second conductive component.

5. The method according to claim 4, wherein: Forming the first barrier layer and the second barrier layer includes: lining the sidewalls and bottom of the opening with a barrier material; and After the lining, the barrier material is removed from the bottom of the opening, wherein a first remaining portion of the barrier material along the first sidewall of the first conductive component forms the first barrier layer, and a second remaining portion of the barrier material along the second sidewall of the second conductive component forms the second barrier layer.

6. The method according to claim 5, wherein: Removing the blocking material includes performing an anisotropic etching process to remove the blocking material from the bottom of the opening.

7. The method according to claim 5, wherein: Forming the second dielectric material includes filling the opening with the second dielectric material after forming the first barrier layer and the second barrier layer, wherein after the filling, the second dielectric material continuously extends from the first barrier layer to the second barrier layer.

8. The method according to claim 1, wherein: Forming the opening is performed after forming the first barrier layer and the second barrier layer, wherein, after removing the portion of the dielectric layer to form the opening, the opening exposes the first barrier layer disposed along the first side wall of the first conductive component and exposes the second barrier layer disposed along the second side wall of the second conductive component.

9. A method for forming a semiconductor device, the method comprising: forming a device layer including a nanostructure and a gate structure located around the nanostructure; forming a first interconnect structure on a first side of the device layer; as well as forming a second interconnect structure on a second side of the device layer opposite the first side of the device layer, comprising: forming a dielectric layer along the second side of the device layer using a first dielectric material; forming a first conductive feature surrounded by a first barrier layer in the dielectric layer; forming a second conductive feature in the dielectric layer surrounded by a second barrier layer; removing a portion of the dielectric layer disposed between the first conductive component and the second conductive component to form an opening in the dielectric layer, the opening exposing a first sidewall of the first barrier layer and a second sidewall of the second barrier layer; forming a second dielectric material different from the first dielectric material along the first sidewall of the first barrier layer and along the second sidewall of the second barrier layer; After forming the second dielectric material, lining the sidewalls and bottom of the opening with a third barrier layer; and After forming the third barrier layer, the opening is filled with a conductive material.

10. A semiconductor device comprising: A device layer, comprising a nanostructure and a gate structure located around the nanostructure; a first interconnect structure located on a first side of the device layer; as well as A second interconnect structure, located on a second side of the device layer opposite the first side of the device layer, comprises: a dielectric layer along the second side of the device layer, wherein the dielectric layer comprises a first dielectric material; a first conductive component and a second conductive component embedded in the dielectric layer; and A metal-insulator-metal (MIM) capacitor, located in the dielectric layer, comprising: a first barrier layer along a first side wall of the first conductive component facing the second conductive component; a second barrier layer along a second side wall of the second conductive component facing the first conductive component; and A second dielectric material is located in the dielectric layer between the first barrier layer and the second barrier layer, wherein the second dielectric material is different from the first dielectric material.

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