Field effect transistor structure integrated with synchronous current sampling function

Abstract

The invention provides a field effect transistor structure integrated with a synchronous current sampling function, which comprises a first plane structure, a second plane structure and a third plane structure, and is characterized in that the first plane structure comprises a first source electrode, a common grid electrode and a second source electrode; the second plane structure comprises a working field effect transistor and a sampling field effect transistor, the working field effect transistor comprises a first source region, a first gate region and a first drain region, the sampling field effect transistor comprises a second source region, a second gate region and a second drain region, the first source region is electrically connected with the first source electrode, and the second source region is electrically connected with the second source electrode; the first gate region and the second gate region are electrically connected with the common gate; the third planar structure comprises a common drain, and the first drain region and the second drain region are electrically connected with the common drain. The working field effect transistor and the sampling field effect transistor are compatible in process, and the working field effect transistor and the sampling field effect transistor share a grid electrode and a terminal, so that synchronous current sampling is realized, and the chip area is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a field effect transistor structure with integrated synchronous current sampling function. Background Art

[0002] In applications such as battery charge and discharge management, battery management protection, and battery fuel gauges, current sampling resistors are generally used to detect battery charge and discharge currents. A current sampling resistor is a resistor used to detect current in a circuit. It is usually placed in the load loop of the circuit and calculates the current by measuring the voltage difference between the two ends.

[0003] With the development of semiconductor technology, the use of metal-oxide-semiconductor field-effect transistors (MOSFET) as a means of current detection has been increasingly widely used. Figure 1 As shown, MOSFET includes a cell region 100 that can perform on-off functions and a terminal region 110 whose edge bears the voltage resistance. The cell region 100 is composed of a drain region 101 composed of an epitaxial layer, a polysilicon gate region 102 located in a groove and a source region 103 formed by ion implantation. The terminal region 110 is composed of a field limiting ring 111 and a floating electrode 112. When the on-state current flows through the MOSFET, due to the existence of the on-state resistance, there is a certain voltage drop on its conduction channel. Because the on-resistance of the device is basically stable, the voltage drop is proportional to the on-state current of the device. Detecting the on-state voltage drop of the MOSFET means detecting the current size of the device, thereby realizing the current sampling function.

[0004] There are two main types of field effect transistor structures with integrated current sampling resistor function in the prior art: the first is to package an additional sampling MOSFET with current sampling function when packaging the working MOSFET, but the additional packaging of the sampling MOSFET makes the packaging structure bulky and the cost high; the second is to integrate an independent sampling MOSFET with current sampling function in the working MOSFET, as shown below Figure 2 , showing a top schematic diagram of a MOSFET structure with an integrated independent current sampling function, including a working field effect transistor region 200 and a sampling field effect transistor region 210, wherein the working field effect transistor region 200 includes a first source pad 201 and a first gate pad 202, and the sampling field effect transistor region 210 includes a second source pad 211 and a second gate pad 212, and on the back side of the device, a common drain pad is electrically connected to the drain region of the working field effect transistor and the drain region of the sampling field effect transistor, respectively, as shown in FIG. Figure 3As shown, it is an equivalent circuit diagram of a MOSFET structure with an integrated independent current sampling function; a sampling MOSFET with an independent current sampling function is integrated in the working MOSFET, and the sampling MOSFET requires a separate terminal structure and gate area, occupying a large chip area.

[0005] Therefore, how to provide a field effect transistor structure with integrated synchronous current sampling function to realize current synchronous sampling and reduce chip area has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a field effect transistor structure with integrated synchronous current sampling function, which is used to solve the problem that the field effect transistor structure with integrated current sampling resistor function in the prior art cannot realize current synchronous sampling and has a large chip area.

[0007] To achieve the above objectives and other related objectives, the present invention provides a field effect transistor structure with integrated synchronous current sampling function, comprising:

[0008] A first planar structure includes a first source, a common gate, and a second source;

[0009] a second planar structure, located below the first planar structure in a vertical direction, the second planar structure comprising a working field effect transistor and a sampling field effect transistor, the working field effect transistor comprising a first source region, a first gate region and a first drain region, the first source region and the first source electrode are electrically connected, the first gate region and the common gate electrode are electrically connected, the sampling field effect transistor comprises a second source region, a second gate region and a second drain region, the second source region and the second source electrode are electrically connected, and the second gate region and the common gate electrode are electrically connected;

[0010] The third planar structure is located below the second planar structure in a vertical direction. The third planar structure includes a common drain. The first drain region is electrically connected to the common drain. The second drain region is electrically connected to the common drain.

[0011] Optionally, the working field effect transistor and the sampling field effect transistor are field effect transistors of the same conductivity type.

[0012] Optionally, the working field effect transistor includes an N-channel enhancement type field effect transistor, and the sampling field effect transistor includes an N-channel enhancement type field effect transistor.

[0013] Optionally, the working field effect transistor includes a P-channel enhancement type field effect transistor, and the sampling field effect transistor includes a P-channel enhancement type field effect transistor.

[0014] Optionally, it further includes a terminal region, which is arranged in a ring shape. In the horizontal direction, the first source, the common gate and the second source are all located in the area surrounded by the terminal region.

[0015] Optionally, an air-avoiding space is provided in the common gate, and the second source is located in the air-avoiding space.

[0016] Optionally, in the vertical direction, the working field effect transistor is located below the first source, and the sampling field effect transistor is located below the second source, wherein a first conductive trench and a second conductive trench are provided in the second planar structure, one end of the first conductive trench is electrically connected to the first gate region, and the other end of the first conductive trench is located below the common gate, one end of the second conductive trench is electrically connected to the second gate region, and the other end of the second conductive trench is located below the common gate.

[0017] Optionally, it also includes a first conductive via, a second conductive via, a third conductive via and a fourth conductive via, wherein the first conductive via is used to electrically connect the first conductive trench and the common gate, the second conductive via is used to electrically connect the second conductive trench and the common gate, the third conductive via is used to electrically connect the first source region and the first source electrode, and the fourth conductive via is used to electrically connect the second source region and the second source electrode.

[0018] Optionally, a passivation layer is provided above the first planar structure, and a first opening, a second opening and a third opening are provided in the passivation layer, wherein the first opening exposes the first source to form a first source pad, the second opening exposes the common gate to form a gate pad, and the third opening exposes the second source to form a second source pad.

[0019] Optionally, a cross-sectional area of ​​the working field effect transistor is larger than a cross-sectional area of ​​the sampling field effect transistor.

[0020] As described above, in the field effect transistor structure with integrated synchronous current sampling function of the present invention, the processes of the working field effect transistor and the sampling field effect transistor are compatible, and no additional plate making is required. In addition, the working field effect transistor and the sampling field effect transistor share a gate and a terminal. Compared with the prior art in which the sampling field effect transistor requires a separate terminal structure and a gate structure, the present invention can realize current synchronous sampling and reduce the chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Shown is a schematic diagram of the structure of a metal-oxide-semiconductor field-effect transistor.

[0022] Figure 2Shown is a top view schematic diagram of a MOSFET structure with an integrated independent current sensing function.

[0023] Figure 3 Shown is the equivalent circuit diagram of a MOSFET structure with an integrated independent current sensing function.

[0024] Figure 4 Shown is a schematic layout diagram of a field effect transistor with integrated synchronous current sampling function according to the present invention.

[0025] Figure 5 A top schematic diagram of a field effect transistor with integrated synchronous current sampling function according to the present invention is shown.

[0026] Figure 6 Shown is an equivalent circuit diagram of a field effect transistor with integrated synchronous current sampling function of the present invention.

[0027] Component number description

[0028] 100 cell area

[0029] 101 Leakage Area

[0030] 102 grid area

[0031] 103 Source Area

[0032] 110 Terminal Area

[0033] 111 Field Limiting Ring

[0034] 112 floating electrodes

[0035] 200 Working FET area

[0036] 201 first source pad

[0037] 202 first gate pad

[0038] 210 Sampling FET area

[0039] 211 second source pad

[0040] 212 second gate pad

[0041] 300 First Source

[0042] 301 Common Gate

[0043] 302 Second Source

[0044] 310 working field effect tube

[0045] 311 Sampling Field Effect Transistor

[0046] 312 First Source Area

[0047] 313 Second Source Area

[0048] 314 first conductive groove

[0049] 315 second conductive groove

[0050] 316 First conductive via

[0051] 317 Second conductive via

[0052] 318 third conductive via

[0053] 319 Fourth conductive via

[0054] 320 Terminal Area

[0055] 400 first source pad

[0056] 401 Gate pad

[0057] 402 second source pad DETAILED DESCRIPTION

[0058] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] See also Figures 1 to 6 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0060] This embodiment provides a field effect transistor structure with integrated synchronous current sampling function. Figure 4, which is a schematic diagram of the layout of the field effect transistor with integrated synchronous current sampling function, including a first plane structure, a second plane structure and a third plane structure, wherein the first plane structure includes a first source 300, a common gate 301 and a second source 302; the second plane structure is located below the first plane structure in the vertical direction, the second plane structure includes a working field effect transistor 310 and a sampling field effect transistor 311, the working field effect transistor includes a first source region 312, a first gate region and a first drain region, the first source region 312 is electrically connected to the first source 300, the first gate region is electrically connected to the common gate 301, the sampling field effect transistor 311 includes a second source region 313, a second gate region and a second drain region, the second source region 313 is electrically connected to the second source 302, and the second gate region is electrically connected to the common gate 301; the third plane structure is located below the second plane structure in the vertical direction, the third plane structure includes a common drain, the first drain region is electrically connected to the common drain, and the second drain region is electrically connected to the common drain.

[0061] As an example, in the present invention, the working field effect transistor and the sampling field effect transistor are turned on and off simultaneously during operation, and the sampling field effect transistor does not need to be driven separately. Therefore, the gate of the working field effect transistor and the gate of the sampling field effect transistor can be short-circuited to form a common gate 301.

[0062] As an example, in the vertical direction, the working field effect transistor 310 is located below the first source 300, the first source region 312 is electrically connected to the first source 300 through a third conductive through hole 318, a first conductive groove 314 is provided in the second planar structure, one end of the first conductive groove 314 is electrically connected to the first gate region, the other end of the first conductive groove 314 extends below the common gate 301, the first conductive groove 314 is electrically connected to the common gate 301 through a first conductive through hole 316, so as to realize the electrical connection between the common gate 301 and the first gate region; the sampling field effect transistor 311 is located Below the second source 302, the second source region 313 is electrically connected to the second source 302 through a fourth conductive through-hole 319, a second conductive groove 315 is provided in the second planar structure, one end of the second conductive groove 315 is electrically connected to the second gate region, the other end of the second conductive groove 315 extends under the common gate 301, and the second conductive groove 315 is electrically connected to the common gate 301 through a second conductive through-hole 317 to realize the electrical connection between the common gate 301 and the second gate region; preferably, in this embodiment, the cross-sectional area of ​​the working field effect transistor 310 is greater than the cross-sectional area of ​​the sampling field effect transistor 311.

[0063] As an example, an escape space is provided in the common gate 301 , and the second source 302 is located in the escape space, so that the second gate region can be electrically connected to the common gate 301 more evenly from all sides of the sampling field effect transistor 311 , thereby optimizing the potential distribution of the common gate 301 .

[0064] As an example, a terminal region 320 is further included. The terminal region 320 is arranged in a ring shape. In the horizontal direction, the first source 300 , the common gate 301 and the second source 302 are all located in the area surrounded by the terminal region 320 .

[0065] As an example, see Figure 5 , which is a top schematic diagram of a field effect transistor with integrated synchronous current sampling function of the present invention, wherein a passivation layer is arranged above the first planar structure, and a first opening, a second opening and a third opening are arranged in the passivation layer, wherein the first opening exposes the first source 300 to form a first source pad 400, the second opening exposes the common gate 301 to form a gate pad 401, and the third opening exposes the second source 302 to form a second source pad 402.

[0066] As an example, since the working field effect transistor and the sampling field effect transistor are turned on and off at the same time during the working process, the working field effect transistor and the sampling field effect transistor are field effect transistors of the same conductivity type, for example, the working field effect transistor and the sampling field effect transistor are both N-channel enhancement field effect transistors or both P-channel enhancement field effect transistors. Specifically, in this embodiment, the working field effect transistor and the sampling field effect transistor are both N-channel enhancement field effect transistors, see Figure 6 , which is an equivalent circuit diagram of a field effect transistor with integrated synchronous current sampling function of the present invention. Its working principle is: when the gate G is connected to a high potential, the gate-source voltage V (GS1) is greater than its turn-on voltage, sampling the gate-source voltage V of the field effect transistor (GS2) Greater than its turn-on voltage, both are turned on simultaneously; a drain-source voltage V is applied between the drain and source of the working field effect transistor (D1S1) , the source and drain are turned on; the source S2 of the sampling field effect transistor is grounded, and after the voltage is applied to the drain D, the source-drain voltage V of the sampling field effect transistor is obtained. (DS2) , V (DS2) The current obtained by dividing by the resistance of the sampling field effect transistor is the on-current of the working field effect transistor, realizing the current sampling function.

[0067] As an example, by controlling the implantation area of ​​the second source region 313 , the resistance of the sampling field effect transistor can be adjusted, which is equivalent to adjusting the resistance value of the current sampling resistor.

[0068] In summary, in the field effect transistor structure with integrated synchronous current sampling function of the present invention, the processes of the working field effect transistor and the sampling field effect transistor are compatible, no additional plate making is required, and the working field effect transistor and the sampling field effect transistor share a gate and a terminal. Compared with the sampling field effect transistor in the prior art, which requires a separate terminal structure and a gate structure, the present invention can realize current synchronous sampling and reduce the chip area. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0069] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A field effect transistor structure with integrated synchronous current sampling function, characterized in that: include: A first planar structure includes a first source, a common gate, and a second source; a second planar structure, located below the first planar structure in a vertical direction, the second planar structure comprising a working field effect transistor and a sampling field effect transistor, the working field effect transistor comprising a first source region, a first gate region and a first drain region, the first source region and the first source electrode are electrically connected, the first gate region and the common gate electrode are electrically connected, the sampling field effect transistor comprises a second source region, a second gate region and a second drain region, the second source region and the second source electrode are electrically connected, and the second gate region and the common gate electrode are electrically connected; The third planar structure is located below the second planar structure in a vertical direction. The third planar structure includes a common drain. The first drain region is electrically connected to the common drain. The second drain region is electrically connected to the common drain.

2. The field effect transistor structure with integrated synchronous current sampling function according to claim 1, characterized in that: The working field effect transistor and the sampling field effect transistor are field effect transistors of the same conductivity type.

3. The field effect transistor structure with integrated synchronous current sampling function according to claim 2, characterized in that: The working field effect transistor includes an N-channel enhancement type field effect transistor, and the sampling field effect transistor includes an N-channel enhancement type field effect transistor.

4. The field effect transistor structure with integrated synchronous current sampling function according to claim 2, characterized in that: The working field effect transistor includes a P-channel enhancement type field effect transistor, and the sampling field effect transistor includes a P-channel enhancement type field effect transistor.

5. The field effect transistor structure with integrated synchronous current sampling function according to claim 1, characterized in that: It also includes a terminal region, which is arranged in a ring shape. In the horizontal direction, the first source, the common gate and the second source are all located in the region surrounded by the terminal region.

6. The field effect transistor structure with integrated synchronous current sampling function according to claim 1, characterized in that: An escape space is provided in the common gate, and the second source is located in the escape space.

7. The field effect transistor structure with integrated synchronous current sampling function according to claim 6, characterized in that: In the vertical direction, the working field effect transistor is located below the first source, and the sampling field effect transistor is located below the second source, wherein a first conductive trench and a second conductive trench are provided in the second planar structure, one end of the first conductive trench is electrically connected to the first gate region, and the other end of the first conductive trench is located below the common gate, one end of the second conductive trench is electrically connected to the second gate region, and the other end of the second conductive trench is located below the common gate.

8. The field effect transistor structure with integrated synchronous current sampling function according to claim 7, characterized in that: It also includes a first conductive via, a second conductive via, a third conductive via and a fourth conductive via, wherein the first conductive via is used to electrically connect the first conductive trench and the common gate, the second conductive via is used to electrically connect the second conductive trench and the common gate, the third conductive via is used to electrically connect the first source region and the first source electrode, and the fourth conductive via is used to electrically connect the second source region and the second source electrode.

9. The field effect transistor structure with integrated synchronous current sampling function according to claim 1, characterized in that: A passivation layer is disposed above the first planar structure, and a first opening, a second opening and a third opening are disposed in the passivation layer, wherein the first opening exposes the first source to form a first source pad, the second opening exposes the common gate to form a gate pad, and the third opening exposes the second source to form a second source pad.

10. The field effect transistor structure with integrated synchronous current sampling function according to claim 1, characterized in that: The cross-sectional area of ​​the working field effect tube is greater than the cross-sectional area of ​​the sampling field effect tube.

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