ESD protection device

Abstract

The invention provides an ESD (Electro-Static Discharge) protection device, which comprises a substrate on which an epitaxial layer is formed; an annular deep trench isolation, wherein the deep trench isolation extends from the upper surface of the epitaxial layer to the substrate; the buried layer is located in an area defined by the deep trench isolation, and the buried layer is located in the substrate and is next to the upper surface of the substrate; the plurality of first well regions are positioned in a region enclosed by the deep trench isolation, are arranged in the epitaxial layer at intervals and are next to the upper surface of the epitaxial layer, and the first well regions are connected with the buried layer through the deep buried layer; the second well regions are located in an area defined by the deep trench isolations, the second well regions are located in the epitaxial layer, the second well regions are arranged between every two adjacent first well regions, transverse spacing is formed between every two adjacent first well regions and the second well regions in the X-axis direction, longitudinal spacing is formed between the first well regions and the buried layer, and transverse spacing is formed between every two adjacent second well regions in the X-axis direction. And the second well region is attached to the edge of the shallow trench isolation at the two ends of the Y axis. The ESD performance can be improved under the condition that the area of the device is not changed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an ESD protection device. Background Art

[0002] In the high-voltage BCD process platform, the DTI (deep trench isolation) process is introduced to achieve higher integration and better electrical isolation. Unlike traditional PN junction isolation, DTI is smaller in size and is physically isolated, which can greatly improve the integration of chip design. However, in the field of ESD (electrostatic discharge) high-voltage design, traditional design ideas have always been maintained. Even if DTI isolation is introduced, there are still some isolation rings inside the ESD device, such as Figure 1 As shown in the N-well 102, a certain distance a is required between the active area in the N-well 102 and the DTI. In addition, the ESD device requires that the breakdown voltage in the Y direction is much greater than the breakdown voltage in the X direction, that is, the distance b between the N-well 102 and the P-well 101 in the Y direction is greater than the distance c between the N-well 102 in the X direction. The width requirement of the active area and the N-well 102 results in a large waste of area in the Y direction of the PNP structure ESD device in the prior art.

[0003] In order to solve the above problems, a new type of ESD protection device needs to be proposed. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an ESD protection device for solving the problem that the width requirement of the active area and the N-well in the prior art leads to a large waste of area in the Y direction of the prior art PNP structure ESD device.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides an ESD protection device, comprising:

[0006] a substrate on which an epitaxial layer is formed;

[0007] A ring-shaped deep trench isolation extending from the upper surface of the epitaxial layer to the substrate;

[0008] A buried layer located in the area enclosed by the deep trench isolation, wherein the buried layer is located in the substrate and is close to the upper surface of the substrate;

[0009] A plurality of first well regions located in the area surrounded by the deep trench isolation, wherein the first well regions are arranged at intervals in the epitaxial layer and are close to the upper surface of the epitaxial layer, and the first well regions are connected to the buried layer through a deep buried layer;

[0010] A second well region located in the area surrounded by the deep trench isolation, the second well region being located in the epitaxial layer and each of the second well regions being respectively arranged between two adjacent first well regions, wherein two adjacent first well regions and second well regions have a lateral spacing in the direction of the X-axis, the first well region and the buried layer have a longitudinal spacing, and the second well region extends to the edge of the shallow trench isolation at both ends of the Y-axis;

[0011] A third well region in a ring shape located outside the area surrounded by the deep trench isolation, wherein the third well region is located in the epitaxial layer;

[0012] A plurality of first shallow trench isolations, wherein the first shallow trench isolations are located in the epitaxial layer between two adjacent first well regions and second well regions and are close to the upper surface of the epitaxial layer;

[0013] a second shallow trench isolation, wherein the second shallow trench isolation is located between the third well region and the first well region adjacent thereto;

[0014] A first heavily doped region and a second heavily doped region, wherein the first heavily doped region is located in the first well region outside, and the second heavily doped region is located in the first to triple well regions, the first well region is led out to the upper surface of the epitaxial layer through the first and double heavily doped regions or the second heavily doped regions thereon, and the second and triple well regions are led out through the second heavily doped region thereon.

[0015] Preferably, the substrate, the epitaxial layer, the second and triple well regions and the second heavily doped region are all of the first conductivity type; the buried layer, the deep buried layer, the first well region and the first heavily doped region are all of the second conductivity type.

[0016] Preferably, the first conductivity type is P type, and the second conductivity type is N type.

[0017] Preferably, the number of the first well regions is three, and the number of the second well regions is two.

[0018] Preferably, the method of using the device is configured as follows: in the first well region where the first and second heavily doped regions are formed, the first and second heavily doped regions are short-circuited to a high level; in the first well region where the second heavily doped region is formed, the second heavily doped region is connected to a high level and the second heavily doped region in the second and triple well regions is connected to a low level.

[0019] Preferably, a third shallow trench isolation is provided between the first and second heavily doped regions in the first well region.

[0020] As described above, the ESD protection device of the present invention has the following beneficial effects:

[0021] In the deep trench isolation process of the present invention, while maintaining the ESD device electrically isolated by the PN junction and physically isolated by the deep trench isolation, the isolation ring or other rings in the Y direction of the PNP structure ESD device can be omitted, thereby improving the ESD performance without changing the device area. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Shown is a schematic diagram of a top view of an ESD protection device in the prior art;

[0023] Figure 2 Shown is a schematic diagram of the top view of the ESD protection device of the present invention;

[0024] Figure 3 Shown is a schematic diagram of the cross-sectional structure of the ESD protection device of the present invention;

[0025] Figure 4 It is a schematic diagram comparing the ESD current discharge capabilities of the present invention and the prior art. DETAILED DESCRIPTION

[0026] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] See also Figure 2 and Figure 3 The present invention provides an ESD protection device, comprising:

[0028] A substrate 107, on which an epitaxial layer 109 is formed;

[0029] The substrate 107 may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer located below a thin semiconductor layer as an active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor generally include crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or their alloys (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.) or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.

[0030] In an embodiment of the present invention, the substrate 107, the epitaxial layer 109, the second and triple well regions and the second heavily doped region 105 are all of the first conductivity type; the buried layer 108, the deep buried layer 110, the first well region 101 and the first heavily doped region 104 are all of the second conductivity type.

[0031] A ring-shaped deep trench isolation extending from the upper surface of the epitaxial layer 109 to the substrate 107;

[0032] A buried layer 108 located in the area surrounded by the deep trench isolation, wherein the buried layer 108 is located in the substrate 107 and is close to the upper surface of the substrate 107;

[0033] A plurality of first well regions 101 located in the area surrounded by the deep trench isolation, the first well regions 101 are arranged at intervals in the epitaxial layer 109 and are close to the upper surface of the epitaxial layer 109, and the first well regions 101 are connected to the buried layer 108 through the deep buried layer 110;

[0034] A second well region 102 located in the area surrounded by the deep trench isolation, the second well region 102 is located in the epitaxial layer 109 and each second well region 102 is respectively arranged between two adjacent first well regions 101, wherein there is a lateral spacing between two adjacent first well regions 101 and second well regions 102 in the direction of the X-axis, there is a longitudinal spacing between the first well region 101 and the buried layer 108, and the second well region 102 is in contact with the edge of the shallow trench isolation at both ends of the Y-axis;

[0035] A third well region 103 in a ring shape located outside the area surrounded by the deep trench isolation, and the third well region 103 is located in the epitaxial layer 109;

[0036] A plurality of first shallow trench isolations 111 , wherein the first shallow trench isolations 111 are located in the epitaxial layer 109 between the first well regions 101 and the second well regions 102 adjacent to each other and are close to the upper surface of the epitaxial layer 109 ;

[0037] A second shallow trench isolation 112, wherein the second shallow trench isolation 112 is located between the third well region 103 and the adjacent first well region 101;

[0038] In the embodiment of the present invention, a third shallow trench isolation 113 is disposed between the first and second heavily doped regions in the first well region 101 .

[0039] The materials of shallow trench isolation and deep trench isolation 106 can be spin-on glass (SOG), dense oxide formed by high-density plasma chemical vapor deposition (HDP-CVDOX), silicon dioxide (SIO2) or double filling of silicon dioxide and silicon nitride (SIN), and the grinding method is chemical mechanical planarization grinding.

[0040] The first heavily doped region 104 and the second heavily doped region 105, the first heavily doped region 104 is located in the first well region 101 on the outside, the second heavily doped region 105 is located in the first to triple well regions, the first well region 101 is led out to the upper surface of the epitaxial layer 109 through the first, second heavily doped region or the second heavily doped region 105 thereon, and the second and triple well regions are led out through the second heavily doped region 105 thereon.

[0041] In an embodiment of the present invention, the first conductivity type is P type, and the second conductivity type is N type.

[0042] In the embodiment of the present invention, the number of the first well regions 101 is three, and the number of the second well regions 102 is two.

[0043] In an embodiment of the present invention, the method of using the device is configured as follows: in a first well region 101 in which a first and a second heavily doped region are formed, the first and the second heavily doped region are short-circuited to a high level; in a first well region 101 in which a second heavily doped region 105 is formed, the second heavily doped region 105 is connected to a high level and the second heavily doped region 105 in the second and triple well regions is connected to a low level.

[0044] That is, on the basis of the PNP structure of the prior art, the N-well rings (or other types of isolation rings) at the upper and lower ends are cancelled, and the P-well is extended to the deep trench isolation 106. The P-well of this structure is physically isolated from the outer device by the deep trench isolation 106, and is isolated from the substrate 107 by the PN junction formed by the N-type buried layer 108. It is still in a fully isolated state from the devices or circuits other than the ESD. However, compared with the PNP structure of the prior art, the PN junction area that can be used to discharge the ESD current is greatly improved while the area remains unchanged. Because the PN junction on the side and the PN junction on the bottom are improved synchronously, only the W (width) of the P-well is used here as a simple calculation. Compared with the structure of the prior art, the theoretical capacity of the structure of the present application is improved by about 2A / W.

[0045] See also Figure 4 The distance between the P-well and the deep trench isolation 106 is 15.5um, while the distance between the P-well and the deep trench isolation 106 of the structure of the present application is 0um. When the width of the device is 80um, the measured TLP (transmission line pulse generator, a research and testing method for electrostatic discharge protection technology of integrated circuits) data of the prior art structure and the structure of the present application are as follows. The failure current of the present application is 4.1A, and the failure current of the prior art structure is 3A. The actual improvement is 36% compared with the two, which is very close to the theoretical value of 15.5*2÷80~38.8%.

[0046] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0047] In summary, in the deep trench isolation process, the present invention can omit the isolation ring or other rings in the Y direction of the PNP structure ESD device while maintaining the ESD device being electrically isolated by the PN junction and physically isolated by the deep trench isolation, thereby improving the ESD performance without changing the device area. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0048] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An ESD protection device, characterized in that: At least: a substrate on which an epitaxial layer is formed; A ring-shaped deep trench isolation extending from the upper surface of the epitaxial layer to the substrate; A buried layer located in the area enclosed by the deep trench isolation, wherein the buried layer is located in the substrate and is close to the upper surface of the substrate; A plurality of first well regions located in the area surrounded by the deep trench isolation, wherein the first well regions are arranged at intervals in the epitaxial layer and are close to the upper surface of the epitaxial layer, and the first well regions are connected to the buried layer through a deep buried layer; A second well region located in the area surrounded by the deep trench isolation, the second well region being located in the epitaxial layer and each of the second well regions being respectively arranged between two adjacent first well regions, wherein two adjacent first well regions and second well regions have a lateral spacing in the direction of the X-axis, the first well region and the buried layer have a longitudinal spacing, and the second well region extends to the edge of the shallow trench isolation at both ends of the Y-axis; A third well region in a ring shape located outside the area surrounded by the deep trench isolation, wherein the third well region is located in the epitaxial layer; A plurality of first shallow trench isolations, wherein the first shallow trench isolations are located in the epitaxial layer between two adjacent first well regions and second well regions and are close to the upper surface of the epitaxial layer; a second shallow trench isolation, wherein the second shallow trench isolation is located between the third well region and the first well region adjacent thereto; A first heavily doped region and a second heavily doped region, wherein the first heavily doped region is located in the first well region outside, and the second heavily doped region is located in the first to triple well regions, the first well region is led out to the upper surface of the epitaxial layer through the first and double heavily doped regions or the second heavily doped regions thereon, and the second and triple well regions are led out through the second heavily doped region thereon.

2. The ESD protection device according to claim 1, characterized in that: The substrate, the epitaxial layer, the second and triple well regions and the second heavily doped region are all of the first conductivity type; the buried layer, the deep buried layer, the first well region and the first heavily doped region are all of the second conductivity type.

3. The ESD protection device according to claim 2, characterized in that: The first conductivity type is P type, and the second conductivity type is N type.

4. The ESD protection device according to claim 1, characterized in that: The number of the first well regions is three, and the number of the second well regions is two.

5. The ESD protection device according to claim 3, characterized in that: The method for using the device is configured as follows: in the first well region where the first and second heavily doped regions are formed, the first and second heavily doped regions are short-circuited to a high level; in the first well region where the second heavily doped region is formed, the second heavily doped region is connected to a high level and the second heavily doped region in the second and triple well regions is connected to a low level.

6. The ESD protection device according to claim 1, characterized in that: A third shallow trench isolation is provided between the first and second heavily doped regions in the first well region.

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