ESD protection devices

Abstract

This invention provides an ESD protection device, comprising: a substrate on which an epitaxial layer is formed; a ring-shaped deep trench isolation extending from the upper surface of the epitaxial layer to the substrate; a buried layer located within the area enclosed by the deep trench isolation, the buried layer being situated in the substrate and adjacent to the upper surface of the substrate; a plurality of first well regions located within the area enclosed by the deep trench isolation, the first well regions being spaced apart within the epitaxial layer and adjacent to the upper surface of the epitaxial layer, the first well regions being connected to the buried layer via the deep trench isolation; and second well regions located within the area enclosed by the deep trench isolation, the second well regions being situated in the epitaxial layer and each second well region being positioned between two adjacent first well regions, wherein the two adjacent first well regions and second well regions have a lateral spacing in the X-axis direction, a longitudinal spacing between the first well regions and the buried layer, and the second well regions are abutting the edges of the shallow trench isolation at both ends in the Y-axis direction. This invention can improve ESD performance without changing the device area.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an ESD protection device. Background Technology

[0002] In high-voltage BCD process platforms, DTI (deep trench isolation) technology is introduced to achieve higher integration and better electrical isolation. Unlike traditional PN junction isolation, DTI is smaller and provides physical isolation, which can greatly improve the integration of chip designs. However, in the field of ESD (electrostatic discharge) high-voltage design, traditional design approaches have been maintained. Even with the introduction of DTI isolation, some isolation rings still exist inside ESD devices, such as... Figure 1 As shown in the N-well 102, the active region in the N-well 102 has a certain distance 'a' requirement from the DTI. In addition, the ESD device requires that the breakdown voltage in the Y direction be much greater than the breakdown voltage in the X direction. That is, the distance 'b' between the N-well 102 and the P-well 101 in the Y direction is greater than the distance 'c' between the N-well 102 in the X direction. The width requirements of the active region and the N-well 102 lead to a large waste of area in the Y direction of the existing PNP structure ESD device.

[0003] To solve the above problems, a new type of ESD protection device is needed. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an ESD protection device to solve the problem that the width requirements of the active region and N-well in the prior art lead to a large waste of area in the Y direction of the prior art PNP structure ESD device.

[0005] To achieve the above and other related objectives, the present invention provides an ESD protection device, comprising:

[0006] A substrate on which an epitaxial layer is formed;

[0007] A ring-shaped deep trench isolation extends from the upper surface of the epitaxial layer to the substrate;

[0008] A buried layer located within the area enclosed by the deep trench isolation, the buried layer being located in the substrate and adjacent to the upper surface of the substrate;

[0009] Multiple first well regions are located within the area enclosed by the deep trench isolation. The first well regions are spaced apart in the epitaxial layer and are adjacent to the upper surface of the epitaxial layer. The first well regions are connected to the buried layer through a deep buried layer.

[0010] A second well region is located within the area enclosed by the deep trench isolation. The second well region is located in the epitaxial layer and each second well region is respectively disposed between two adjacent first well regions. The two adjacent first well regions and second well regions have a lateral spacing in the X-axis direction. The first well region has a longitudinal spacing with the buried layer. The second well region extends to the edge of the shallow trench isolation at both ends of the Y-axis.

[0011] A ring-shaped third well region is located outside the area enclosed by the deep trench isolation, and the third well region is located in the epitaxial layer;

[0012] Multiple first shallow trench isolations are provided, wherein the first shallow trench isolations are located in the epitaxial layer between two adjacent first well regions and second well regions and are adjacent to the upper surface of the epitaxial layer;

[0013] The second shallow trench isolation is located between the third well region and the adjacent first well region;

[0014] The first doped region and the second doped region are located in the first well region outside the first doped region, and the second doped region is located in the first to third well regions. The first well region is led out to the upper surface of the epitaxial layer through the first, second or second doped region thereon, and the second and third well regions are led out through the second doped region thereon.

[0015] Preferably, the substrate, the epitaxial layer, the second and third well regions, and the second heavily doped region are all of the first conductivity type; the buried layer, the deep buried layer, the first well region, and the first heavily doped region are all of the second conductivity type.

[0016] Preferably, the first conductivity type is P-type and the second conductivity type is N-type.

[0017] Preferably, the number of the first well regions is three, and the number of the second well regions is two.

[0018] Preferably, the method of using the device is configured such that: in the first well region where the first and second doped regions are formed, the first and second doped regions are short-circuited to a high level; in the first well region where the second doped region is formed, the second doped region is connected to a high level; and in the second and third well regions, the second doped region is connected to a low level.

[0019] Preferably, a third shallow trench is provided between the first and double-doped regions in the first well region for isolation.

[0020] As described above, the ESD protection device of the present invention has the following beneficial effects:

[0021] In the deep trench isolation process, this invention can omit the isolation ring or other rings in the Y direction of the PNP structure ESD device while maintaining the electrical isolation of the ESD device by the PN junction and the physical isolation by the deep trench. This improves the ESD performance without changing the device area. Attached Figure Description

[0022] Figure 1 The diagram shown is a top view of an existing ESD protection device.

[0023] Figure 2 The diagram shown is a top view of the ESD protection device of the present invention.

[0024] Figure 3 The diagram shown is a cross-sectional structural schematic of the ESD protection device of the present invention.

[0025] Figure 4 This diagram shows a comparison of the ESD current discharge capabilities of the present invention and existing technologies. Detailed Implementation

[0026] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] Please see Figure 2 and Figure 3 This invention provides an ESD protection device, comprising:

[0028] Substrate 107, on which an epitaxial layer 109 is formed;

[0029] Substrate 107 may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer serving as the active layer. The active layer and bulk semiconductor typically comprise the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0030] In an embodiment of the present invention, the substrate 107, the epitaxial layer 109, the second and third well regions and the second heavily doped region 105 are all of the first conductivity type; the buried layer 108, the deep buried layer 110, the first well region 101 and the first heavily doped region 104 are all of the second conductivity type.

[0031] The deep trench isolation is in the form of a ring, and the deep trench isolation extends from the upper surface of the epitaxial layer 109 to the substrate 107;

[0032] The buried layer 108 is located within the area enclosed by the deep trench isolation, and the buried layer 108 is located in the substrate 107 and is adjacent to the upper surface of the substrate 107.

[0033] Multiple first well regions 101 are located within the area enclosed by the deep trench isolation. The first well regions 101 are spaced apart in the epitaxial layer 109 and are adjacent to the upper surface of the epitaxial layer 109. The first well regions 101 are connected to the buried layer 108 through the deep buried layer 110.

[0034] The second well region 102 is located within the area enclosed by the deep trench isolation. The second well region 102 is located in the epitaxial layer 109 and each second well region 102 is respectively disposed between two adjacent first well regions 101. The two adjacent first well regions 101 and second well regions 102 have a lateral spacing in the X-axis direction. The first well region 101 has a longitudinal spacing with the buried layer 108. The two ends of the second well region 102 are attached to the edge of the shallow trench isolation at both ends of the Y-axis.

[0035] A ring-shaped third well region 103 is located outside the area enclosed by the deep trench isolation, and the third well region 103 is located in the epitaxial layer 109;

[0036] Multiple first shallow trench isolations 111 are located in the epitaxial layer 109 between two adjacent first well regions 101 and second well regions 102 and are adjacent to the upper surface of the epitaxial layer 109.

[0037] The second shallow trench isolation 112 is located between the third well region 103 and the adjacent first well region 101.

[0038] In an embodiment of the present invention, a third shallow trench isolation 113 is provided between the first and second doped regions in the first well region 101.

[0039] The materials for shallow trench isolation and deep trench isolation 106 can be spin-coated glass (SOG), dense oxide (HDP-CVDOX) formed by high-density plasma chemical vapor deposition, silicon dioxide (SiO2), or a combination of silicon dioxide and silicon nitride (Sin). The grinding method is chemical mechanical planarization grinding.

[0040] The first heavily doped region 104 and the second heavily doped region 105 are located in the first well region 101 outside the first heavily doped region 104, and the second heavily doped region 105 is located in the first to third well regions. The first well region 101 is led out to the upper surface of the epitaxial layer 109 through the first, second, or third heavily doped regions 105 thereon, and the second and third well regions are led out through the second heavily doped region 105 thereon.

[0041] In an embodiment of the present invention, the first conductivity type is P-type and the second conductivity type is N-type.

[0042] In an embodiment of the present invention, there are three first well regions 101 and two second well regions 102.

[0043] In an embodiment of the present invention, the device is used as follows: in a first well region 101 having first and second doped regions, the first and second doped regions are short-circuited to a high level; in a first well region 101 having a second doped region 105, the second doped region is connected to a high level; and in a second and third well region, the second doped region 105 is connected to a low level.

[0044] Based on the existing PNP structure, the N-well rings (or other types of isolation rings) at the top and bottom ends are eliminated, extending the P-well to a deep trench isolation 106. This structure provides physical isolation between the P-well and external devices via the deep trench isolation 106, and PN junction isolation with the substrate 107 formed by an N-type buried layer 108. It remains fully isolated from devices or circuits other than those affected by ESD. However, compared to the existing PNP structure, the PN junction area available for discharging ESD current is significantly increased without changing the total area. Because the PN junctions on the sides and bottom are increased simultaneously, only the W (width) of the P-well is used for simple calculations. Compared to the existing structure, the theoretical capability of this structure is approximately 2 A / W higher.

[0045] Please see Figure 4 The distance between the P-well and the deep trench isolation 106 is 15.5 μm, while the distance between the P-well and the deep trench isolation 106 in the structure of this application is 0 μm. When the width of the device is 80 μm, the measured TLP (transmission line pulse generator, a research and testing method for electrostatic discharge protection technology of integrated circuits) data of the prior art structure and the structure of this application are as follows: the failure current of this application is 4.1 A, while that of the prior art structure is 3 A. The actual improvement is 36%, which is very close to the theoretical value of 15.5*2÷80~38.8%.

[0046] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0047] In summary, this invention, in the deep trench isolation process, while maintaining the electrical isolation of the ESD device by the PN junction and the physical isolation by the deep trench, can omit the isolation ring or other rings in the Y direction of the PNP structure ESD device, thereby improving ESD performance without changing the device area. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0048] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An ESD protection device, characterized in that, At least including: A substrate on which an epitaxial layer is formed; A ring-shaped deep trench isolation extends from the upper surface of the epitaxial layer to the substrate; A buried layer located within the area enclosed by the deep trench isolation, the buried layer being located in the substrate and adjacent to the upper surface of the substrate; Multiple first well regions are located within the area enclosed by the deep trench isolation. The first well regions are spaced apart in the epitaxial layer and are adjacent to the upper surface of the epitaxial layer. The first well regions are connected to the buried layer through a deep buried layer. A second well region is located within the area enclosed by the deep trench isolation. The second well region is located in the epitaxial layer and each second well region is respectively disposed between two adjacent first well regions. The two adjacent first well regions and second well regions have a lateral spacing in the X-axis direction. The first well region has a longitudinal spacing with the buried layer. The two ends of the second well region are attached to the edge of the deep trench isolation. A ring-shaped third well region is located outside the area enclosed by the deep trench isolation, and the third well region is located in the epitaxial layer; Multiple first shallow trench isolations are provided, wherein the first shallow trench isolations are located in the epitaxial layer between two adjacent first well regions and second well regions and are adjacent to the upper surface of the epitaxial layer; The second shallow trench isolation is located between the third well region and the adjacent first well region; The first doped region and the second doped region are located in the first well region outside the first doped region, and the second doped region is located in the first to third well regions. The first well region is led out to the upper surface of the epitaxial layer through the first, second or second doped region thereon, and the second and third well regions are led out through the second doped region thereon.

2. The ESD protection device according to claim 1, characterized in that: The substrate, the epitaxial layer, the second and third well regions, and the second heavily doped region are all of the first conductivity type; the buried layer, the deep buried layer, the first well region, and the first heavily doped region are all of the second conductivity type.

3. The ESD protection device according to claim 2, characterized in that: The first conductivity type is P-type, and the second conductivity type is N-type.

4. The ESD protection device according to claim 1, characterized in that: The number of first well regions is three, and the number of second well regions is two.

5. The ESD protection device according to claim 3, characterized in that: The device is configured to be used as follows: in the first well region where the first and second doped regions are formed, the first and second doped regions are short-circuited to a high level; in the first well region where the second doped region is formed, the second doped region is connected to a high level; and in the second and third well regions, the second doped region is connected to a low level.

6. The ESD protection device according to claim 1, characterized in that: A third shallow trench is provided between the first and second doped regions in the first well region for isolation.

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