Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the steps that a substrate is provided, the substrate comprises isolation areas, connecting areas and a plurality of device areas, the device areas are arranged in a display mode, the isolation areas are arranged around the device areas, and the connecting areas are located between the adjacent device areas; forming a first photoresist layer on the substrate; the first photoresist layer is exposed and developed until the surface of the isolation area is exposed, the first photoresist layer with a device area pattern and a connection area pattern is formed, and the first photoresist layer on the connection area pattern is connected with the first photoresist layer on the adjacent device area. A connecting region is defined on a substrate, and the connecting region is located between adjacent device regions, so that when a first photoresist layer with a device region pattern and a connecting region pattern is subsequently formed on the substrate, the first photoresist layer on the connecting region pattern can be connected with the first photoresist layer on the adjacent device region; the connection of the first photoresist layers on the adjacent device regions is realized, and the stability of the first photoresist layers is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a method for forming a semiconductor structure. Background Art

[0002] An image sensor is an electronic device that converts optical images into electrical signals. The pixel size of an image sensor (CIS) is determined by the structure and size of a photodiode (PD), which is generally composed of an electron collection area and an isolation area.

[0003] However, as the size of image sensors continues to decrease, the challenges to photolithography conditions continue to increase. The smaller the pixel size, the more likely it is that high aspect ratio photoresists will peel off during the exposure process, affecting the performance of image sensors. Summary of the invention

[0004] The technical problem solved by the present invention is how to improve the performance of the image sensor.

[0005] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising an isolation region, a connection region and a plurality of device regions, wherein the plurality of device regions are arranged in a display, the isolation region is arranged around each of the device regions, and the connection region is located between adjacent device regions; forming a first photoresist layer on the substrate; exposing and developing the first photoresist layer until the surface of the isolation region is exposed to form a first photoresist layer having a device region pattern and a connection region pattern, wherein the first photoresist layer on the connection region pattern is connected to the first photoresist layer on the adjacent device region.

[0006] Optionally, the connection area includes a first sub-connection area, and the first sub-connection area is located between adjacent device areas in the diagonal direction of the device area. The method for forming the semiconductor structure also includes: forming a second photoresist layer on the substrate; exposing and developing the second photoresist layer until the surface of the isolation area is exposed to form a second photoresist layer having a device area pattern and a first sub-connection area pattern, wherein the second photoresist layer on the first sub-connection area pattern connects the second photoresist layer on the adjacent device area in the diagonal direction.

[0007] Optionally, the connection area includes a second sub-connection area, and the second sub-connection area is located between adjacent device areas in the adjacent edge direction of the device area. The method for forming the semiconductor structure also includes: forming a third photoresist layer on the substrate; exposing and developing the third photoresist layer until the surface of the isolation area is exposed to form a third photoresist layer having a device area pattern and a second sub-connection area pattern, wherein the third photoresist layer on the second sub-connection area pattern is connected to the third photoresist layer on the adjacent device area in the adjacent edge direction.

[0008] Optionally, the connection area includes a first sub-connection area and a second sub-connection area, the first sub-connection area is located between adjacent device areas in the diagonal direction of the device area, and the second sub-connection area is located between adjacent device areas in the adjacent side direction of the device area. The method for forming the semiconductor structure also includes: forming a fourth photoresist layer on the substrate; exposing and developing the fourth photoresist layer until the surface of the isolation area is exposed to form a fourth photoresist layer having a device area pattern, a first sub-connection area pattern, and a second sub-connection area pattern, wherein the fourth photoresist layer on the first sub-connection area pattern is connected to the fourth photoresist layer on the adjacent device area in the diagonal direction, and the fourth photoresist layer on the second sub-connection area pattern is connected to the fourth photoresist layer on the adjacent device area in the adjacent side direction.

[0009] Optionally, after the step of forming a first photoresist layer having a device area pattern and a connection area pattern, the step further includes: using the first photoresist layer having a device area pattern and a connection area pattern as a mask, performing ion implantation into the isolation area to form an initial isolation structure; and removing the first photoresist layer having a device area pattern and a connection area pattern until the surface of the device area and the surface of the connection area are exposed.

[0010] Optionally, the process parameters for ion implantation in the isolation region include implantation element of boron, implantation energy of 100KeV to 160MeV, and implantation dose of 1E12 ions / cm 2 To 5E12 ions / cm 2 .

[0011] Optionally, after the step of removing the first photoresist layer having the device area pattern and the connection area pattern, the method further includes: using a high temperature thermal process to heat treat the substrate so that the initial isolation structure diffuses into the connection area to form an isolation structure.

[0012] Optionally, a high temperature thermal process is used to heat treat the substrate so that the initial isolation structure diffuses into the connection area to form an isolation structure.

[0013] Optionally, the process parameters of the furnace tube process include: temperature of 600° C. to 950° C., time of 30 min to 90 min, and the process parameters of the rapid thermal annealing process include: annealing temperature of 900° C. to 1200° C., annealing time of 15 s to 45 s.

[0014] Optionally, the width of the isolation region ranges from 0.15 microns to 0.3 microns, the width of the connection region ranges from 0.12 microns to 0.2 microns, and the width of the device region ranges from 0.5 microns to 1.0 microns.

[0015] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0016] The technical solution of the present invention defines a connection area on a substrate, and the connection area is located between adjacent device areas, so that when a first photoresist layer having a device area pattern and a connection area pattern is subsequently formed on the substrate, the first photoresist layer on the connection area pattern can be connected to the first photoresist layer on the adjacent device area, thereby increasing the area of ​​the first photoresist layer, realizing the connection of the first photoresist layers on the adjacent device areas, improving the stability of the first photoresist layer, avoiding the problem of the first photoresist layer on the device area falling off, and thus improving the accuracy of subsequent isolation structure formation and device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figures 1 to 3 It is a schematic diagram of the structure of a semiconductor structure;

[0018] Figure 4 It is a schematic diagram of the structure of another semiconductor structure;

[0019] Figures 5 to 12 is a structural schematic diagram of a semiconductor structure forming process in an embodiment of the present invention;

[0020] Figures 13 to 19 is a structural schematic diagram of another semiconductor structure forming process in an embodiment of the present invention;

[0021] Figure 20 to Figure 26 is a structural schematic diagram of another semiconductor structure forming process in an embodiment of the present invention;

[0022] Fig. 27 It is a one-dimensional simulation diagram of the diffusion process of the connection region in the semiconductor structure described in the embodiment of the present invention. DETAILED DESCRIPTION

[0023] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0024] The current method for forming semiconductor structures can be referenced Figure 1 and Figure 2 , Figure 1 is a schematic diagram of a top view of the semiconductor structure, Figure 2 yes Figure 1 The cross-sectional schematic diagram along the AA1 direction in the figure, the method for forming the semiconductor structure comprises: providing a substrate 100, the substrate 100 comprising an isolation region 101 and a plurality of device regions I, wherein the plurality of device regions I are arranged in a row, and the isolation region 101 is arranged around each of the device regions I; forming a first photoresist layer 102 on the substrate 100; exposing and developing the first photoresist layer 102 until the surface of the isolation region 101 is exposed, so as to form a first photoresist layer 102 having a pattern of the device region I.

[0025] In the above scheme, since the first photoresist layer 102 is separately located on the device area I, and since the pixel size gradually decreases, the first photoresist layer 102 has a high aspect ratio and is prone to fall off during the exposure process. Figure 3 , Figure 3 It is a scanning schematic diagram of the semiconductor structure. Figure 3 The viewing direction and Figure 1 Consistent, Figure 3 The position of the first photoresist layer 102 in the middle red circle 103 changes, that is, it falls off, which affects the subsequent implantation of the isolation structure and the performance of the semiconductor device.

[0026] At present, in order to solve the above problems, another method for forming a semiconductor structure is provided. Figure 4 , Figure 4 It is a schematic diagram of the top view of the semiconductor structure, and the method for forming the semiconductor structure includes: providing a substrate, the substrate including an isolation area and a plurality of device areas 201, wherein the plurality of device areas 201 are arranged in a display, and the isolation area is arranged around each of the device areas 201; forming a first photoresist layer 202 on the substrate; performing exposure and development treatment on the first photoresist layer 202 until a portion of the surface of the isolation area is exposed, so as to form a first photoresist layer 202 having a partial isolation area pattern; performing ion implantation treatment on the isolation area to form an initial isolation structure; forming a second photoresist layer 203 on the substrate; performing exposure and development treatment on the second photoresist layer 203 until a portion of the surface of the isolation area is exposed, so as to form a second photoresist layer 203 having a partial isolation area pattern; performing ion implantation treatment on the isolation area to form an isolation structure.

[0027] In the above scheme, an isolation structure is formed by two exposure and development steps, which increases the area of ​​the photoresist layer for each exposure and development. This improves the stability of the photoresist layer during the exposure process and avoids the problem of the photoresist layer on the device area falling off. However, the above scheme requires two masks and the ion implantation process requires two times, which increases the process cost.

[0028] In order to solve the above technical problems, the present invention provides a method for forming a semiconductor structure, providing a substrate, wherein the substrate includes an isolation region, a connection region and a plurality of device regions, wherein the plurality of device regions are arranged in a display, the isolation region is arranged around each of the device regions, and the connection region is located between adjacent device regions; a first photoresist layer is formed on the substrate; the first photoresist layer is exposed and developed to expose the surface of the isolation region to form a first photoresist layer having a device region pattern and a connection region pattern, wherein the first photoresist layer on the connection region pattern is connected to the first photoresist layer on the adjacent device region.

[0029] In the above scheme, by setting the connection area between the adjacent device areas, when the first photoresist layer having the device area pattern and the connection area pattern is subsequently formed on the substrate, the first photoresist layer on the connection area pattern can be connected to the first photoresist layer on the adjacent device area, thereby realizing the connection of the first photoresist layers on the adjacent device areas, increasing the stability of the first photoresist layer, avoiding the problem of the first photoresist layer on the device area falling off, and thereby improving the accuracy of the subsequent isolation structure formation and the performance of the device.

[0030] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0031] Please refer to Figure 5 as well as Figure 6 , Figure 5 This is a top view of the structure. Figure 6 yes Figure 5 In the cross-sectional structure diagram along the BB1 ​​direction, a substrate 300 is provided, wherein the substrate 300 includes an isolation region 301, a connection region and a plurality of device regions I, wherein the plurality of device regions I are arranged in a row, the isolation region 301 is arranged around each of the device regions I, and the connection region is located between adjacent device regions I, wherein the connection region includes a first sub-connection region 302, and the first sub-connection region 302 is located between adjacent device regions I in a diagonal direction along the device region I.

[0032] In some embodiments of the present invention, the shape of the device region I is a rectangle, wherein the diagonal line of the rectangle is the diagonal direction of the device region I.

[0033] In some embodiments of the present invention, the width of the isolation region 301 ranges from 0.15 microns to 0.3 microns, the width of the first sub-connection region 302 ranges from 0.12 microns to 0.2 microns, and the width of the device region I ranges from 0.5 microns to 1.0 microns.

[0034] In some embodiments of the present invention, the substrate 300 is made of silicon.

[0035] In other embodiments, the material of the substrate 300 includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). The multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0036] In some embodiments of the present invention, the substrate 300 is an N-type semiconductor.

[0037] In other embodiments of the present invention, the substrate 300 is a P-type semiconductor.

[0038] Please refer to Figure 7 as well as Figure 8 , Figure 7 This is a top view of the structure. Figure 8 yes Figure 7 In the cross-sectional structure diagram along the BB1 ​​direction, a second photoresist layer 303 is formed on the substrate 300; the second photoresist layer 303 is exposed and developed until the surface of the isolation area 301 is exposed, forming a second photoresist layer 303 having a device area I pattern and a first sub-connection area 302 pattern.

[0039] The second photoresist layer 303 on the pattern of the first sub-connection region 302 is connected to the second photoresist layer 303 on the adjacent device region I in the diagonal direction.

[0040] In some embodiments of the present invention, please refer to Fig. 9 , Fig. 9 yes Figure 7 Scanning schematic diagram of the semiconductor structure, Fig. 9 It can be seen that after the second photoresist layer 303 is exposed and developed, the second photoresist layer 303 on the adjacent device area I in the diagonal direction is connected through the second photoresist layer 303 on the first sub-connection area 302 pattern, so that the second photoresist layer 303 on the wafer is connected as a whole, which improves the stability of the second photoresist layer 303 and avoids the problem of the second photoresist layer 303 on the device area I falling off, thereby improving the accuracy of the subsequent isolation structure 304 formation and the performance of the device.

[0041] Please refer to Fig.10 , Fig.10 The viewing direction and Figure 8 Consistently, using the second photoresist layer 303 having the pattern of the device area I and the pattern of the first sub-connection area 302 as a mask, ion implantation is performed on the isolation area 301 to form an initial isolation structure 3041; the second photoresist layer 303 having the pattern of the device area I and the pattern of the first sub-connection area 302 is removed until the surface of the device area I and the surface of the first sub-connection area 302 are exposed.

[0042] In some embodiments of the present invention, the process parameters for ion implantation in the isolation region 301 include: an ion implantation dose range of 1E12 ions / cm 2 To 5E12 ions / cm 2 The implanted ion type is P type and the implanted element is boron.

[0043] The semiconductor type of the device region I is opposite to the type of the implanted ions in the isolation region 301 .

[0044] In one embodiment, the semiconductor type of the device region I is N-type, and the type of the implanted ions in the isolation region 301 is P-type.

[0045] When the device region I is an N-type semiconductor, N-type ions may be provided by the substrate itself or injected separately.

[0046] Please refer to Fig.11 as well as Fig.12 , Fig.11 This is a top view of the structure. Fig.12 yes Fig.11 In the cross-sectional structural diagram along the BB1 ​​direction, the substrate 300 is heat-treated by a high-temperature thermal process, so that the initial isolation structure 3041 diffuses into the first sub-connection area 302 to form an isolation structure 304.

[0047] In some embodiments of the present invention, a high temperature thermal process is used to heat treat the substrate 300 so that the initial isolation structure 3041 diffuses into the first sub-connection region 302 to form an isolation structure 304 .

[0048] In some embodiments of the present invention, the high temperature thermal process includes a furnace tube process or a rapid thermal annealing process.

[0049] The process parameters of the furnace tube process include: temperature of 600°C to 950°C, time of 30 min to 90 min, and the process parameters of the rapid thermal annealing process include: annealing temperature of 900°C to 1200°C, annealing time of 15 seconds to 45 seconds.

[0050] In the above scheme, the technical solution of the present invention performs heat treatment on the substrate 300 so that the initial isolation structure 3041 diffuses into the first sub-connection area 302 to form an isolation structure 304, thereby reducing the process cost.

[0051] Combine the following Figures 13 to 19 Another embodiment of the semiconductor structure is described.

[0052] Please refer to Fig.13 as well as Fig.14 , Fig.13 This is a top view of the structure. Fig.14 yes Fig.13 In the cross-sectional structure diagram along the CC1 direction, a substrate 400 is provided, wherein the substrate 400 includes an isolation region 401, a connection region and a plurality of device regions I, wherein the plurality of device regions I are arranged in a row, the isolation region 401 is arranged around each of the device regions I, the connection region is located between adjacent device regions I, wherein the connection region includes a second sub-connection region 402, and the second sub-connection region 402 is located between adjacent device regions I along the adjacent side direction of the device region I.

[0053] In some embodiments of the present invention, the device region I is in the shape of a rectangle, wherein the rectangle includes sides that are perpendicular to each other in pairs, namely, the adjacent sides of the device region I.

[0054] In some embodiments of the present invention, the width of the isolation region 401 ranges from 0.15 microns to 3 microns, the width of the second sub-connection region 402 ranges from 0.12 microns to 0.2 microns, and the width of the device region I ranges from 0.5 microns to 1.0 microns.

[0055] In some embodiments of the present invention, the substrate 400 is made of silicon.

[0056] In other embodiments, the material of the substrate 400 includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0057] In some embodiments of the present invention, the substrate 400 is an N-type semiconductor.

[0058] In other embodiments of the present invention, the substrate 400 is a P-type semiconductor.

[0059] Please refer to Fig.15 as well as Fig.16 , Fig.15This is a top view of the structure. Fig.16 yes Fig.15 In the cross-sectional structure diagram along the CC1 direction, a third photoresist layer 403 is formed on the substrate 400; the third photoresist layer 403 is exposed and developed to expose the surface of the isolation area 401, so as to form a third photoresist layer 403 having a device area I pattern and a second sub-connection area 402 pattern, wherein the third photoresist layer 403 on the second sub-connection area 402 pattern is connected to the third photoresist layer 403 on the adjacent device area I in the adjacent edge direction.

[0060] In the above scheme, after the third photoresist layer 403 is exposed and developed, the third photoresist layer 403 on the adjacent device area I in the diagonal direction is connected through the third photoresist layer 403 on the second sub-connection area 402 pattern, so that the third photoresist layer 403 on the wafer is connected as a whole, thereby improving the stability of the third photoresist layer 403, avoiding the problem of the third photoresist layer 403 on the device area I falling off, and thereby improving the accuracy of the subsequent isolation structure 404 formation and the performance of the device.

[0061] Please refer to Fig.17 , Fig.17 The viewing direction and Fig.16 Consistently, using the third photoresist layer 403 having the device area I pattern and the connection area pattern as a mask, ion implantation is performed on the isolation area 401 to form an initial isolation structure 4041; the third photoresist layer 403 having the device area I pattern and the second sub-connection area 402 pattern is removed until the surface of the device area I and the surface of the second sub-connection area 402 are exposed.

[0062] In some embodiments of the present invention, the process parameters for ion implantation in the isolation region 401 include: an ion implantation dose range of 1E12 ions / cm 2 To 5E12 ions / cm 2 The implanted ion type is P type and the implanted element is boron.

[0063] The semiconductor type of the device region I is opposite to the type of the implanted ions in the isolation region 401 .

[0064] In one embodiment, the semiconductor type of the device region I is N-type, and the type of the implanted ions in the isolation region 401 is P-type.

[0065] When the device region I is an N-type semiconductor, N-type ions may be provided by the substrate itself or injected separately.

[0066] Please refer to Fig.18 as well as Fig.19 , Fig.18 This is a top view of the structure. Fig.19 yes Fig.18 In the cross-sectional structural diagram along the CC1 direction, the substrate 400 is heat-treated by a high-temperature thermal process, so that the initial isolation structure 4041 diffuses into the second sub-connection area 402 to form an isolation structure 404.

[0067] In some embodiments of the present invention, a high temperature thermal process is used to heat treat the substrate 400 so that the initial isolation structure 4041 diffuses into the second sub-connection region 402 to form an isolation structure 404 .

[0068] In some embodiments of the present invention, the high temperature thermal process includes a furnace tube process or a rapid thermal annealing process.

[0069] The process parameters of the furnace tube process include: temperature of 600°C to 950°C, time of 30 min to 90 min, and the process parameters of the rapid thermal annealing process include: annealing temperature of 900°C to 1200°C, annealing time of 15 seconds to 45 seconds.

[0070] In the above scheme, the technical solution of the present invention performs heat treatment on the substrate 400 so that the initial isolation structure 4041 diffuses into the second sub-connection area 402 to form an isolation structure 404, thereby reducing the process cost.

[0071] Combine the following Figure 20 to Figure 26 Another embodiment of the semiconductor structure is described.

[0072] Please refer to Fig. 20 as well as Fig.21 , Fig. 20 This is a top view of the structure. Fig.21 yes Fig. 20 In the cross-sectional structure diagram along the DD1 direction, a substrate 500 is provided, wherein the substrate 500 includes an isolation region 501, a connection region and a plurality of device regions I, wherein the plurality of device regions I are arranged in a display, the isolation region 501 is arranged around each of the device regions, and the connection region is located between adjacent device regions, wherein the connection region includes a first sub-connection region 5021 and a second sub-connection region 5022, wherein the first sub-connection region 5021 is located between adjacent device regions I in a diagonal direction of the device region, and the second sub-connection region 5022 is located between adjacent device regions I in a side direction of the device region.

[0073] In some embodiments of the present invention, the shape of the device area I is a rectangle, wherein the diagonal of the rectangle is the diagonal direction of the device area I, and the sides of the rectangle that are perpendicular to each other are the adjacent side directions of the device area I.

[0074] In some embodiments of the present invention, the width of the isolation region 501 ranges from 0.15 microns to 3 microns, the width of the first sub-connection region 5021 ranges from 0.12 microns to 0.2 microns, the width of the second sub-connection region 5022 ranges from 0.12 microns to 0.2 microns, and the width of the device region I ranges from 0.5 microns to 1.0 microns.

[0075] In some embodiments of the present invention, the substrate 500 is made of silicon.

[0076] In other embodiments, the material of the substrate 500 includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0077] In some embodiments of the present invention, the substrate 500 is an N-type semiconductor.

[0078] In other embodiments of the present invention, the substrate 500 is a P-type semiconductor.

[0079] Please refer to Fig. 22 as well as Fig.23 , Fig. 22 This is a top view of the structure. Fig.23 yes Fig. 22 In the cross-sectional structure diagram along the DD1 direction, a fourth photoresist layer 503 is formed on the substrate 500; the fourth photoresist layer 503 is exposed and developed until the surface of the isolation area 501 is exposed, so as to form a fourth photoresist layer 503 having a device area I pattern, a first sub-connection area 5021 pattern and a second sub-connection area 5022 pattern, wherein the fourth photoresist layer 503 on the first sub-connection area 5021 pattern is connected to the fourth photoresist layer 503 on the adjacent device area I in the diagonal direction, and the fourth photoresist layer 503 on the second sub-connection area 5022 pattern is connected to the fourth photoresist layer 503 on the adjacent device area I in the adjacent edge direction.

[0080] In the above scheme, after the fourth photoresist layer 503 is exposed and developed, the fourth photoresist layer 503 on the adjacent device area I in the diagonal direction is connected through the third photoresist layer on the first sub-connection area 5021 pattern, and the fourth photoresist layer 503 on the adjacent device area in the adjacent edge direction is connected through the fourth photoresist layer 503 on the second sub-connection area 5022 pattern, so that the fourth photoresist layer 503 on the wafer is connected as a whole, which improves the stability of the fourth photoresist layer 503 and avoids the problem of the fourth photoresist layer 503 on the device area I falling off, thereby improving the accuracy of the subsequent isolation structure 504 formation and the performance of the device.

[0081] In addition, the fourth photoresist layer 503 on each device region I is connected as a whole through the two connection regions of the first sub-connection region 5021 and the second sub-connection region 5022, so that the stability of the fourth photoresist layer 503 is further improved.

[0082] Please refer to Fig.24 , Fig.24 The viewing direction and Fig.23 Consistently, using the fourth photoresist layer 503 having the device area I pattern and the connection area pattern as a mask, ion implantation is performed on the isolation area 501 to form an initial isolation structure 5041; the fourth photoresist layer 503 having the device area I pattern, the first sub-connection area 5021 pattern and the second sub-connection area 5022 pattern is removed until the surface of the device area I and the surface of the first sub-connection area 5021 are exposed.

[0083] In some embodiments of the present invention, the process parameters for ion implantation in the isolation region 501 include: an ion implantation dose range of 1E12 ions / cm 2 To 5E12 ions / cm 2 The implanted ion type is P type and the implanted element is boron.

[0084] The semiconductor type of the device region I is opposite to the type of the implanted ions in the isolation region 501 .

[0085] In one embodiment, the semiconductor type of the device region I is N-type, and the type of the implanted ions in the isolation region 501 is P-type.

[0086] When the device region I is an N-type semiconductor, N-type ions may be provided by the substrate itself or injected separately.

[0087] Please refer to Fig.25 as well as Fig.26 , Fig.25 This is a top view of the structure. Fig.26 yes Fig.25In the cross-sectional structure diagram along the DD1 direction, the substrate 500 is heat-treated by a high-temperature thermal process, so that the initial isolation structure 5041 diffuses into the first sub-connection area 5021 and the second sub-connection area 5022 to form an isolation structure 504.

[0088] In some embodiments of the present invention, a high temperature thermal process is used to heat treat the substrate 500 so that the initial isolation structure 5041 diffuses into the first sub-connection region 5021 and the second sub-connection region 5022 to form an isolation structure 504 .

[0089] In some embodiments of the present invention, the high temperature thermal process includes a furnace tube process or a rapid thermal annealing process.

[0090] The process parameters of the furnace tube process include: temperature of 600°C to 950°C, time of 30 min to 90 min, and the process parameters of the rapid thermal annealing process include: annealing temperature of 900°C to 1200°C, annealing time of 15 seconds to 45 seconds.

[0091] In the above scheme, the technical solution of the present invention performs heat treatment on the substrate 500 so that the initial isolation structure 5041 diffuses into the first sub-connection area 5021 and the second sub-connection area 5022 to form an isolation structure 504, thereby reducing the process cost.

[0092] The following table 1 and Fig. 27 The diffusion process of the connection region in the semiconductor structure is described as follows:

[0093] It should be noted that Figures 5 to 12 The diffusion parameters of the connection region in the semiconductor structure of the embodiment, Figures 13 to 19 The diffusion parameters of the connection region in the semiconductor structure of the embodiment and Figure 20 to Figure 26 The diffusion parameters of the connection regions in the semiconductor structure in the embodiment are as shown in Table 1 and Fig. 27 The parameters of the diffusion process of the connection region in the semiconductor structure described in Figures 5 to 12 The semiconductor structure in the embodiment is described, and the diffusion process in other embodiments is not described here.

[0094]

[0095] Table 1

[0096] Among them, La represents the width of the device area I, Lb is the maximum width of the first sub-connection area 302, Lc is the minimum width of the first sub-connection area 302, Cmin is the minimum ion concentration in the first sub-connection area 302 after the diffusion process, and Cmax is the maximum ion concentration in the first sub-connection area 302 after the diffusion process.

[0097] Specifically, the ratio of the decrease in ion concentration in the isolation area is: (Cmax-Cmin) / Cmax, that is, the ratio of the difference between the maximum ion concentration Cmax in the first sub-connection area 302 after the diffusion process and the minimum ion concentration Cmin in the first sub-connection area 302 after the diffusion process to the maximum ion concentration Cmax in the first sub-connection area 302 after the diffusion process.

[0098] In one embodiment, the preset threshold is set to 1.78E16 ions / cm 3 When the maximum width Lb of the first sub-connection region 302 or the minimum width Lc of the first sub-connection region 302 is less than or equal to 0.2 micrometers, if the minimum ion concentration in the first sub-connection region 302 after the diffusion process is greater than or equal to 1.78E16 ions / cm 3 , that is, it can meet the concentration requirements within the isolation structure.

[0099] It can be seen from the above table that when the maximum width Lb of the first sub-connection region 302 or the minimum width Lc of the connection region is less than or equal to 0.2 microns, the minimum ion concentration in the first sub-connection region 302 after the diffusion process is greater than or equal to 1.78E16 ions / cm 3 , which can meet the concentration requirements within the final isolation structure, that is, during the diffusion process, the isolation structure is formed.

[0100] Please refer to Table 1 for reference Fig. 27 , Fig. 27 is a one-dimensional simulation diagram of the diffusion process of the first sub-connection region 302 in the semiconductor structure, Fig. 27 The curve when Lb or Lc is equal to 0.05 microns (i.e. Fig. 27 Taking the red curve in the middle as an example, when Lb or Lc is equal to 0.05 microns, the corresponding minimum ion concentration Cmin in the first sub-connection area 302 is equal to 1.78E16ions / cm 3 The maximum ion concentration Cmax in the first sub-connection region 302 is 7.36E16 ions / cm 3 At this time, the ion concentration in the first sub-connection area 302 can meet the concentration requirement of the isolation structure to be finally formed, that is, at this time, the diffusion process is in progress and the isolation structure is formed.

[0101] In summary, by defining a connection area on the substrate, the connection area is located between adjacent device areas, so that when a first photoresist layer having a device area pattern and a connection area pattern is subsequently formed on the substrate, the first photoresist layer on the connection area pattern can be connected to the first photoresist layer on the adjacent device area, thereby increasing the area of ​​the first photoresist layer, realizing the connection of the first photoresist layers on adjacent device areas, improving the stability of the first photoresist layer, avoiding the problem of the first photoresist layer on the device area falling off, and thereby improving the accuracy of subsequent isolation structure formation and device performance; in addition, the technical solution of the present invention performs heat treatment on the substrate so that the initial isolation structure diffuses into the connection area to form an isolation structure, thereby reducing the process cost.

[0102] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an isolation region, a connection region and a plurality of device regions, wherein the plurality of device regions are arranged in an array, the isolation region is arranged around each of the device regions, and the connection region is located between adjacent device regions; forming a first photoresist layer on the substrate; The first photoresist layer is exposed and developed until the surface of the isolation region is exposed, so as to form a first photoresist layer having a device region pattern and a connection region pattern, wherein the first photoresist layer on the connection region pattern is connected to the first photoresist layer on the adjacent device region.

2. The method for forming a semiconductor structure according to claim 1, wherein: The connection region includes a first sub-connection region, and the first sub-connection region is located between adjacent device regions in a diagonal direction of the device region. The method for forming the semiconductor structure further includes: forming a second photoresist layer on the substrate; The second photoresist layer is exposed and developed until the surface of the isolation area is exposed, so as to form a second photoresist layer having a device area pattern and a first sub-connection area pattern, wherein the second photoresist layer on the first sub-connection area pattern connects the second photoresist layer on the adjacent device area in the diagonal direction.

3. The method for forming a semiconductor structure according to claim 1, wherein: The connection region includes a second sub-connection region, and the second sub-connection region is located between adjacent device regions along the adjacent side of the device region. The method for forming the semiconductor structure further includes: forming a third photoresist layer on the substrate; The third photoresist layer is exposed and developed until the surface of the isolation area is exposed to form a third photoresist layer having a device area pattern and a second sub-connection area pattern, wherein the third photoresist layer on the second sub-connection area pattern is connected to the third photoresist layer on the adjacent device area in the adjacent edge direction.

4. The method for forming a semiconductor structure according to claim 1, wherein: The connection region includes a first sub-connection region and a second sub-connection region, the first sub-connection region is located between adjacent device regions in a diagonal direction of the device region, and the second sub-connection region is located between adjacent device regions in a side direction of the device region, and the method for forming the semiconductor structure further includes: forming a fourth photoresist layer on the substrate; The fourth photoresist layer is exposed and developed until the surface of the isolation area is exposed to form a fourth photoresist layer having a device area pattern, a first sub-connection area pattern and a second sub-connection area pattern, wherein the fourth photoresist layer on the first sub-connection area pattern is connected to the fourth photoresist layer on the adjacent device area in the diagonal direction, and the fourth photoresist layer on the second sub-connection area pattern is connected to the fourth photoresist layer on the adjacent device area in the adjacent edge direction.

5. The method for forming a semiconductor structure according to claim 1, wherein: After the step of forming a first photoresist layer having a device region pattern and a connection region pattern, the method further comprises: Using the first photoresist layer having the device region pattern and the connection region pattern as a mask, ion implantation is performed on the isolation region to form an initial isolation structure; The first photoresist layer having the device region pattern and the connection region pattern is removed until the surface of the device region and the surface of the connection region are exposed.

6. The method for forming a semiconductor structure according to claim 5, wherein: The process parameters for ion implantation in the isolation region include implantation element of boron, implantation energy of 100KeV to 160MeV, and implantation dose of 1E12 ions / cm 2 To 5E12 ions / cm 2 .

7. The method for forming a semiconductor structure according to claim 5, wherein: After the step of removing the first photoresist layer having the device area pattern and the connection area pattern, the method further comprises: The substrate is heat treated by adopting a high temperature thermal process, so that the initial isolation structure diffuses into the connection area to form an isolation structure.

8. The method for forming a semiconductor structure according to claim 7, wherein: The high temperature thermal process includes a furnace tube process or a rapid thermal annealing process.

9. The method for forming a semiconductor structure according to claim 8, wherein: The process parameters of the furnace tube process include: temperature of 600° C. to 950° C., time of 30 min to 90 min, and the process parameters of the rapid thermal annealing process include: annealing temperature of 900° C. to 1200° C., annealing time of 15 s to 45 s.

10. The method for forming a semiconductor structure according to claim 1, wherein: The width of the isolation region ranges from 0.15 micrometers to 0.3 micrometers, the width of the connection region ranges from 0.12 micrometers to 0.2 micrometers, and the width of the device region ranges from 0.5 micrometers to 1.0 micrometers.

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