Bottom cell of perovskite / TOPCon crystalline silicon laminated cell and preparation method thereof

Abstract

The invention discloses a bottom cell of a perovskite / TOPCon crystalline silicon laminated cell and a preparation method of the bottom cell, and belongs to the technical field of solar cells. An intrinsic amorphous silicon layer and a P-type amorphous silicon layer are deposited on the back surface of the bottom cell to replace a boron emitting electrode in a traditional laminated TOPCon cell; the problems of high process temperature and long process time in the preparation process of the crystalline silicon substrate are avoided, on the other hand, surface defects of crystalline silicon can be passivated, and surface defect states are reduced, so that the carrier recombination is reduced, and the open voltage is improved; and a mode of firstly depositing a polycrystalline silicon layer structure and then texturing is adopted to balance the problems of compounding and parasitic absorption, so that the surface structure of the perovskite cell can be more favorably superposed.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a bottom cell of a perovskite / TOPCon crystalline silicon stacked cell and a preparation method thereof. Background Art

[0002] A stacked solar cell is a type of solar cell that is characterized by stacking crystalline silicon cells and perovskite cells together, taking advantage of their respective advantages to form an overall cell structure to achieve higher photoelectric conversion efficiency. Crystalline silicon solar cells can absorb part of the visible light spectrum and have a high electron collection efficiency, while perovskite solar cells can absorb visible light and near-infrared spectra and have a high photoelectric conversion efficiency. The stacking of the two can achieve spectral complementarity and make full use of light absorption and electron transmission to achieve complementary effects, thereby improving overall performance.

[0003] Among them, N-type crystalline silicon cells have become the key development direction of the new generation of high-efficiency solar cells due to their advantages such as high minority carrier lifetime, low temperature coefficient and no photothermal induced attenuation caused by BO recombination, and have attracted more and more attention from the industry. The more mature N-type crystalline silicon cells mainly include N-PERT, N-PERL, N-TOPCon and N-IBC structural cells. However, when N-type crystalline silicon cells are stacked on perovskite cells, there are also some problems in the preparation process. First, the preparation of these structures of N-type high-efficiency cells requires the preparation of boron emitters (P+ layer). At present, the industry basically uses the method of tubular thermal diffusion to prepare boron emitters. However, due to the high process temperature and long process time of tubular deposition and advancement, it will lead to problems such as excessive energy consumption, low production capacity and equipment loss. Second, in order to enhance the light trapping ability of crystalline silicon cells, when preparing the velvet structure on the surface of crystalline silicon, on the one hand, the velvet structure has a large composite and requires a thicker polysilicon layer for passivation, but the increase in the thickness of the polysilicon layer will lead to an increase in parasitic absorption; on the other hand, the velvet pyramid is high in height, which increases the difficulty of superimposing perovskite cells on the surface. Third, the temperature used in the printing and sintering process of TOPCon batteries reaches 800-900°C. Such a high sintering temperature will affect the doping of phosphorus on the polysilicon layer. At the same time, the process also produces the problem of high energy consumption.

[0004] In view of this, the inventor conducted in-depth research on this demand, and thus the present case was produced. Summary of the invention

[0005] In order to overcome the above-mentioned deficiencies in the prior art, the present invention provides a bottom cell of a perovskite / TOPCon crystalline silicon tandem cell and a preparation method thereof, which avoids the problems of high process temperature and long process time during the preparation of the crystalline silicon substrate by depositing an intrinsic amorphous silicon layer and a P-type amorphous silicon layer on the back of the crystalline silicon substrate, and balances the problems of recombination and parasitic absorption by first preparing a polycrystalline silicon layer structure and then texturing, and cancels high-temperature sintering. Instead, a curing furnace is used to solidify the metal electrode to reduce energy consumption.

[0006] The present invention is achieved through the following technical solutions:

[0007] A method for preparing a bottom cell of a perovskite / TOPCon crystalline silicon stacked cell comprises the following steps:

[0008] (1) polishing and cleaning the crystalline silicon substrate;

[0009] (2) sequentially preparing a tunneling silicon oxide layer and a phosphorus-doped polysilicon layer on the front side of the crystalline silicon substrate in step (1);

[0010] (3) Prepare SiO on the front side of the crystalline silicon substrate in step (2) 2 mask layer;

[0011] (4) Remove the SiO2 on the back and sides of the crystalline silicon substrate in step (3) 2 Mask layer and wrap-around;

[0012] (5) depositing an intrinsic amorphous silicon layer and a P-type amorphous silicon layer in sequence on the back side of the crystalline silicon substrate in step (4);

[0013] (6) laser texturing is performed on the front surface of the crystalline silicon substrate in step (5);

[0014] (7) Remove the amorphous silicon layer and SiO2 remaining on the front side of the crystalline silicon substrate from the laser in step (6) 2 Mask layer and melted layer and damaged layer caused by laser;

[0015] (8) depositing a TCO conductive film layer on both sides of the crystalline silicon substrate in step (7);

[0016] (9) preparing a metal electrode on the back side of the crystalline silicon substrate in step (8) by passivation treatment and screen printing;

[0017] (10) The metal electrode prepared on the back side of the crystalline silicon substrate in step (9) is cured in a curing furnace to form an ohmic contact with the TCO conductive film layer on the back side of the crystalline silicon substrate.

[0018] In the step (3), SiO is prepared on the front side of the crystalline silicon substrate. 2 The mask layer plays the role of passivation and masking.

[0019] Preferably, in step (5), PECVD is used to introduce SiH 4 and H 2 , the temperature is 100-200°C, forming the intrinsic amorphous silicon layer; then SiH 4 and B 2 H 6 The boron source has a temperature of 150-250° C. to form the P-type amorphous silicon layer.

[0020] Preferably, the thickness of the intrinsic amorphous silicon layer is 5-10 nm, and the thickness of the P-type amorphous silicon layer is 10-50 nm.

[0021] In the step (5), the boron emitter in the traditional stacked TOPCon battery is replaced by depositing the intrinsic amorphous silicon layer and the P-type amorphous silicon layer on the back side of the crystalline silicon substrate. On the one hand, the problems of high process temperature and long process time during the preparation of the crystalline silicon substrate are avoided. On the other hand, the surface defects of the crystalline silicon substrate can be passivated, the surface defect states can be reduced, thereby reducing carrier recombination and improving the opening voltage.

[0022] Preferably, the single pulse energy of the laser texturing in step (6) is 50-100 uj, the pulse frequency is 1500-3500 kHz, the scanning speed is 30000-50000 mm / s, and the number of scans is 1-2 times.

[0023] In the step (6), by first depositing the poly layer structure on the front and back surfaces of the crystalline silicon substrate and then performing texturing, the problems of recombination and parasitic absorption can be balanced, and a lower reflectivity can be obtained by adjusting the laser parameters, which is more conducive to superimposing the surface structure of the perovskite cell.

[0024] Preferably, in step (8), the TCO conductive film layer is deposited on both sides of the crystalline silicon substrate by sputtering using a PVD method at a temperature of 100 to 300° C. and an Ar gas pressure of 0.1 to 2 Pa; the thickness of the TCO conductive film layer is 50 to 100 nm.

[0025] In the step (8), the TCO conductive film layer is deposited on both sides of the crystalline silicon substrate. The deposition process has a low temperature and will not affect the structure of the intrinsic amorphous silicon layer and the P-type amorphous silicon layer on the back side of the crystalline silicon substrate.

[0026] Preferably, in the step (10), the temperature for curing the metal electrode in the curing furnace is 100-150° C., and the time is 10-15 minutes.

[0027] In the step (10), the metal electrode on the back side of the crystalline silicon substrate is cured by using a curing furnace, so that a good ohmic contact is formed between the metal electrode and the TCO conductive film layer, thereby avoiding the damage to the performance of the polysilicon layer caused by the high temperature during the contact formation process using a sintering furnace.

[0028] The present invention also provides a bottom cell of a perovskite / TOPCon crystalline silicon stacked cell, which is prepared by the above-mentioned method for preparing the bottom cell of a perovskite / TOPCon crystalline silicon stacked cell.

[0029] The present invention also provides a perovskite / TOPCon crystalline silicon stacked cell, comprising a top cell and the above-mentioned bottom cell, wherein the structure of the bottom cell sequentially comprises a first TCO conductive film layer, a phosphorus-doped polycrystalline silicon layer, a tunneling oxide layer, a crystalline silicon substrate, an intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a second TCO conductive film layer and a metal electrode, wherein the metal electrode forms an ohmic contact with the second TCO conductive film layer; the first TCO conductive film layer of the bottom cell is connected to the top cell stack.

[0030] Preferably, the top cell is a perovskite cell.

[0031] Preferably, the structure of the perovskite battery includes a first transparent electrode layer, a first charge extraction layer, a perovskite layer, a second charge extraction layer and a second transparent electrode layer in sequence; the first transparent electrode layer is stacked and connected to the first TCO conductive film layer of the bottom battery.

[0032] The beneficial effects produced by the technical solution of the present invention are as follows:

[0033] (1) By depositing an intrinsic amorphous silicon layer and a P-type amorphous silicon layer on the back of the crystalline silicon substrate to replace the boron emitter in the traditional stacked TOPCon cell, on the one hand, the problems of high process temperature and long process time during the preparation of the crystalline silicon substrate are avoided; on the other hand, the surface defects of the crystalline silicon can be passivated and the surface defect states can be reduced, thereby reducing carrier recombination and increasing the opening voltage.

[0034] (2) By first depositing a poly layer structure on the front and back sides of the crystalline silicon substrate and then performing texturing, the problems of recombination and parasitic absorption can be balanced, and a lower reflectivity can be obtained by adjusting the laser parameters, which is more conducive to superimposing the surface structure of the perovskite cell.

[0035] (3) By depositing a TCO conductive film layer on both sides of a crystalline silicon substrate, the deposition process has a low temperature and will not affect the structure of the intrinsic amorphous silicon layer and the P-type amorphous silicon layer on the back side of the crystalline silicon substrate.

[0036] (4) The metal electrode on the back of the crystalline silicon substrate is solidified by using a curing furnace, so that a good ohmic contact is formed between the metal electrode and the TCO conductive film layer, thereby avoiding the damage to the performance of the polysilicon layer caused by the high temperature during the contact formation process using a sintering furnace. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 This is a flow chart for preparing the bottom cell of the TOPCon perovskite tandem battery for this application;

[0039] Figure 2 Schematic diagram of the layer structure of the TOPCon perovskite tandem cell of this application.

[0040] Among them, 1. the first TCO conductive film layer; 2. the phosphorus-doped polysilicon layer; 3. the tunneling oxide layer; 4. the crystalline silicon substrate; 5. the intrinsic amorphous silicon layer; 6. the P-type amorphous silicon layer; 7. the second TCO conductive film layer; 8. the metal electrode; 9. the first transparent electrode layer; 10. the first charge extraction layer; 11. the perovskite layer; 12. the second charge extraction layer; 13. the second transparent electrode layer. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the technical scheme in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Therefore, the following detailed description of the embodiments provided by the present invention is not intended to limit the scope of the claimed invention, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] This embodiment fully analyzes the existing technology for preparing TOPCon perovskite tandem cells using tubular deposition and diffusion, which will lead to problems such as excessive energy consumption, low production capacity and equipment loss, and the first texturing and then deposition of the polysilicon layer requires a thicker polysilicon layer for passivation, but the increase in the thickness of the polysilicon layer will lead to an increase in parasitic absorption; at the same time, the sintering temperature is too high to affect the distribution of phosphorus in the polysilicon layer. A bottom cell of a perovskite / TOPCon crystalline silicon tandem cell and a preparation method thereof are invented, and the specific implementation method is as follows:

[0043] A method for preparing a bottom cell of a perovskite / TOPCon crystalline silicon stacked cell comprises the following steps:

[0044] (1) polishing and cleaning the crystalline silicon substrate 4;

[0045] (2) sequentially preparing a tunneling silicon oxide layer 3 and a phosphorus-doped polysilicon layer 2 on the front surface of the crystalline silicon substrate 4 in step (1);

[0046] (3) Prepare SiO on the front side of the crystalline silicon substrate 4 in step (2) 2 mask layer;

[0047] (4) Remove the SiO2 on the back and sides of the crystalline silicon substrate in step (3) 2 Mask layer and wrap-around;

[0048] (5) depositing an intrinsic amorphous silicon layer 5 and a P-type amorphous silicon layer 6 in sequence on the back side of the crystalline silicon substrate 4 in step (4);

[0049] (6) laser texturing is performed on the front surface of the crystalline silicon substrate 4 in step (5);

[0050] (7) Remove the amorphous silicon layer and SiO2 remaining on the front surface of the crystalline silicon substrate 4 by laser in step (6) 2 Mask layer and melted layer and damaged layer caused by laser;

[0051] (8) depositing a TCO conductive film layer on both sides of the crystalline silicon substrate 4 in step (7);

[0052] (9) preparing a metal electrode 8 on the back side of the crystalline silicon substrate 4 in step (8) by passivation treatment and screen printing;

[0053] (10) The metal electrode 8 prepared on the back side of the crystalline silicon substrate 4 in step (9) is cured in a curing furnace to form an ohmic contact with the TCO conductive film layer on the back side of the crystalline silicon substrate 4.

[0054] In the step (3), SiO is prepared on the front side of the crystalline silicon substrate 4. 2 The mask layer plays the role of passivation and masking.

[0055] As a preferred embodiment, in step (5), the PECVD method is used to introduce SiH 4 and H 2 , the temperature is 100-200°C, forming an intrinsic amorphous silicon layer 5; then SiH 4 and B 2 H 6 Boron source, temperature is 150-250°C, forming a P-type amorphous silicon layer 6.

[0056] As a preferred implementation, the thickness of the intrinsic amorphous silicon layer 5 is 5-10 nm, and the thickness of the P-type amorphous silicon layer 6 is 10-50 nm.

[0057] In the step (5), the boron emitter in the traditional stacked TOPCon cell is replaced by depositing an intrinsic amorphous silicon layer 5 and a P-type amorphous silicon layer 6 on the back of the crystalline silicon substrate 4. On the one hand, the problems of high process temperature and long process time during the preparation of the crystalline silicon substrate 4 are avoided. On the other hand, the surface defects of the crystalline silicon substrate 4 can be passivated, the surface defect states can be reduced, thereby reducing carrier recombination and improving the opening voltage.

[0058] As a preferred implementation, the single pulse energy of the laser texturing in step (6) is 50-100uJ, the pulse frequency is 1500-3500kHz, the scanning speed is 30000-50000mm / s, and the number of scans is 1-2 times.

[0059] In the step (6), by first depositing the poly layer structure on the front and back surfaces of the crystalline silicon substrate 4 and then performing texturing, the problems of recombination and parasitic absorption can be balanced, and a lower reflectivity can be obtained by adjusting the laser parameters, which is more conducive to superimposing the surface structure of the perovskite cell 9.

[0060] As a preferred embodiment, in step (8), the TCO conductive film layer is deposited on both sides of the crystalline silicon substrate 4 by sputtering using a PVD method, the temperature is 100-300°C, and the Ar gas pressure is 0.1-2Pa; the thickness of the TCO conductive film layer is 50-100nm.

[0061] In the step (8), the TCO conductive film layer is deposited on both sides of the crystalline silicon substrate 4 . The deposition process has a low temperature and will not affect the structure of the intrinsic amorphous silicon layer 5 and the P-type amorphous silicon layer 6 on the back side of the crystalline silicon substrate 4 .

[0062] As a preferred embodiment, in the step (10), the temperature for curing the metal electrode 8 in the curing furnace is 100-150° C., and the time is 10-15 minutes.

[0063] In the step (10), the metal electrode 8 on the back side of the crystalline silicon substrate 4 is cured by using a curing furnace, so that a good ohmic contact is formed between the metal electrode 8 and the TCO conductive film layer, thereby avoiding the damage to the performance of the polysilicon layer caused by the high temperature during the contact formation process using a sintering furnace.

[0064] The present invention also provides a bottom cell of a perovskite / TOPCon crystalline silicon stacked cell, which is prepared by the above-mentioned method for preparing the bottom cell of a perovskite / TOPCon crystalline silicon stacked cell.

[0065] The present invention also provides a perovskite / TOPCon crystalline silicon stacked cell, comprising a top cell and the above-mentioned bottom cell, wherein the structure of the bottom cell sequentially comprises a first TCO conductive film layer 1, a phosphorus-doped polycrystalline silicon layer 2, a tunneling oxide layer 3, a crystalline silicon substrate 4, an intrinsic amorphous silicon layer 5, a P-type amorphous silicon layer 6, a second TCO conductive film layer 7 and a metal electrode 8, wherein the metal electrode 8 forms an ohmic contact with the second TCO conductive film layer 7; the first TCO conductive film layer 1 of the bottom cell is connected to the top cell stack.

[0066] As a preferred embodiment, the top cell is a perovskite cell.

[0067] As a preferred embodiment, the structure of the perovskite battery includes a first transparent electrode layer 9, a first charge extraction layer 10, a perovskite layer 11, a second charge extraction layer 12 and a second transparent electrode layer 13 in sequence; the first transparent electrode layer 9 is stacked and connected to the first TCO conductive film layer 1 of the bottom battery.

[0068] In order to more clearly illustrate the technical solutions and advantages of the present invention, the present invention is further described below in conjunction with embodiments.

[0069] Example 1

[0070] A perovskite / TOPCon crystalline silicon stacked cell, wherein the preparation method of the bottom cell comprises the following steps:

[0071] (1) Crystalline silicon substrate: N-type single crystal silicon wafers are selected, and after the damaged layer is removed and cleaned, double-sided alkaline polishing is performed using KOH;

[0072] (2) A 1 nm tunnel oxide layer and a 50 nm polysilicon layer were prepared on the front side of an N-type single crystal silicon wafer by LPCVD, and then loaded into a tubular phosphorus diffusion furnace to form a POCl 3 As a phosphorus source, a phosphorus-doped polysilicon layer is obtained, and the phosphorus doping concentration is 2.0×E21cm -3 ;

[0073] (3) Using LPCVD to deposit 100nm thick SiO on the front of N-type single crystal silicon wafer 2 mask layer;

[0074] (4) Removal of SiO2 from the back and sides of N-type single crystal silicon wafers 2 Mask layer and wrap-around;

[0075] (5) PECVD is used on the back of the N-type single crystal silicon wafer to introduce SiH 4 and H 2 , the temperature is 100℃, and a hydrogenated intrinsic amorphous silicon layer with a thickness of 5nm is formed; then SiH 4 and B 2H 6 Boron source, temperature is 150°C, forming a P-type amorphous silicon layer with a thickness of 10nm;

[0076] (6) Laser texturing is performed on the front side of the N-type single crystal silicon wafer, with a single pulse energy of 50uJ, a pulse frequency of 1500kHz, a scanning speed of 30000mm / s, and a scanning number of 1;

[0077] (7) Remove the amorphous silicon layer and SiO2 remaining on the front side of the N-type single crystal silicon wafer 2 Mask layer and melted layer and damaged layer caused by laser;

[0078] (8) sputtering a TCO conductive film layer on both sides of an N-type single crystal silicon wafer by a PVD method at a temperature of 100° C. and an Ar gas pressure of 0.1 Pa, wherein the thickness of the TCO conductive film layer is 50 nm;

[0079] (9) preparing a metal electrode on the back side of an N-type single crystal silicon wafer by passivation treatment and screen printing;

[0080] (10) The metal electrode prepared on the back side of the N-type single crystal silicon wafer is cured in a curing furnace at a temperature of 100 to 150° C. for 10 minutes to form an ohmic contact with the TCO conductive film layer on the back side of the N-type single crystal silicon wafer.

[0081] Example 2

[0082] A perovskite / TOPCon crystalline silicon stacked cell, wherein the preparation method of the bottom cell comprises the following steps:

[0083] (1) Crystalline silicon substrate: N-type single crystal silicon wafers are selected, and after the damaged layer is removed and cleaned, double-sided alkaline polishing is performed using NaOH;

[0084] (2) A 2nm tunnel oxide layer and a 100nm polysilicon layer were prepared on the front side of an N-type single crystal silicon wafer by LPCVD, and then loaded into a tubular phosphorus diffusion furnace with POCl 3 As a phosphorus source, a phosphorus-doped polysilicon layer is obtained, and the phosphorus doping concentration is 2.0×E21cm -3 ;

[0085] (3) Using PECVD to deposit 200nm thick SiO on the front of N-type single crystal silicon wafer 2 mask layer;

[0086] (4) Removal of SiO2 from the back and sides of N-type single crystal silicon wafers 2 Mask layer and wrap-around;

[0087] (5) PECVD is used on the back of the N-type single crystal silicon wafer to introduce SiH 4 and H 2, the temperature is 150℃, and a hydrogenated intrinsic amorphous silicon layer with a thickness of 8nm is formed; then SiH 4 and B 2 H 6 Boron source, temperature is 200°C, forming a P-type amorphous silicon layer with a thickness of 30nm;

[0088] (6) Laser texturing is used on the front side of the N-type single crystal silicon wafer, with a single pulse energy of 80uJ, a pulse frequency of 2500kHz, a scanning speed of 40000mm / s, and a scanning number of 2 times;

[0089] (7) Remove the amorphous silicon layer and SiO2 remaining on the front side of the N-type single crystal silicon wafer 2 Mask layer and melted layer and damaged layer caused by laser;

[0090] (8) sputtering a TCO conductive film layer on both sides of an N-type single crystal silicon wafer by a PVD method at a temperature of 200° C. and an Ar gas pressure of 1 Pa, wherein the thickness of the TCO conductive film layer is 80 nm;

[0091] (9) preparing a metal electrode on the back side of an N-type single crystal silicon wafer by passivation treatment and screen printing;

[0092] (10) The metal electrode prepared on the back side of the N-type single crystal silicon wafer is cured in a curing furnace at a temperature of 120° C. for 13 min to form an ohmic contact with the TCO conductive film layer on the back side of the N-type single crystal silicon wafer.

[0093] Example 3

[0094] A perovskite / TOPCon crystalline silicon stacked cell, wherein the preparation method of the bottom cell comprises the following steps:

[0095] (1) Crystalline silicon substrate: N-type single crystal silicon wafers are selected, and after the damaged layer is removed and cleaned, double-sided alkaline polishing is performed using TMAH;

[0096] (2) A 2nm tunnel oxide layer and an 80nm polysilicon layer were prepared on the front side of an N-type single crystal silicon wafer by LPCVD, and then loaded into a tubular phosphorus diffusion furnace with POCl 3 As a phosphorus source, a phosphorus-doped polysilicon layer is obtained, and the phosphorus doping concentration is 2.0×E21cm -3 ;

[0097] (3) Using PECVD to deposit 300nm thick SiO on the front of N-type single crystal silicon wafer 2 mask layer;

[0098] (4) Removal of SiO2 from the back and sides of N-type single crystal silicon wafers 2 Mask layer and wrap-around;

[0099] (5) PECVD is used on the back of the N-type single crystal silicon wafer to introduce SiH 4 and H 2 , the temperature is 200℃, and a hydrogenated intrinsic amorphous silicon layer with a thickness of 10nm is formed; then SiH 4 and B 2 H 6 Boron source, temperature is 250°C, forming a P-type amorphous silicon layer with a thickness of 50nm;

[0100] (6) Laser texturing is used on the front side of the N-type single crystal silicon wafer, with a single pulse energy of 100uJ, a pulse frequency of 3500kHz, a scanning speed of 50000mm / s, and a scanning number of 2 times;

[0101] (7) Remove the amorphous silicon layer and SiO2 remaining on the front side of the N-type single crystal silicon wafer 2 Mask layer and melted layer and damaged layer caused by laser;

[0102] (8) sputtering a TCO conductive film layer on both sides of an N-type single crystal silicon wafer by a PVD method at a temperature of 300° C. and an Ar gas pressure of 2 Pa, wherein the thickness of the TCO conductive film layer is 100 nm;

[0103] (9) preparing a metal electrode on the back side of an N-type single crystal silicon wafer by passivation treatment and screen printing;

[0104] (10) The metal electrode prepared on the back side of the N-type single crystal silicon wafer is cured in a curing furnace at a temperature of 150° C. for 15 min to form an ohmic contact with the TCO conductive film layer on the back side of the N-type single crystal silicon wafer.

[0105] Comparative Example 1

[0106] A perovskite / TOPCon crystalline silicon stacked cell, wherein the preparation method of the bottom cell comprises the following steps:

[0107] (1) Crystalline silicon substrate: select N-type single crystal silicon wafer, use 1wt% NaOH to texture the N-type single crystal silicon wafer, and use hydrogen peroxide and NaOH to clean the silicon wafer;

[0108] (2) Boron is diffused on the back of the N-type single crystal silicon wafer to form a boron-doped single crystal silicon layer. The temperature of the boron diffusion deposition is 1000°C and the time is 60 minutes. The square resistance of the boron-doped single crystal silicon layer is 400Ω / cm 2 ;

[0109] (3) Removing the BSG layer on the front side of the N-type single crystal silicon wafer;

[0110] (4) A 2nm tunnel oxide layer and a 100nm polysilicon layer were prepared on the front side of an N-type single crystal silicon wafer by LPCVD, and then loaded into a tubular phosphorus diffusion furnace to form a POCl3 As a phosphorus source, a phosphorus-doped polysilicon layer is obtained, and the phosphorus doping concentration is 2.0×E21cm -3 ;

[0111] (5) Remove the PSG layer on the front side of the N-type single crystal silicon wafer and the N-poly and residual BSG layer on the back side;

[0112] (6) Preparing a silicon nitride anti-reflection layer on both sides of an N-type single crystal silicon wafer;

[0113] (7) The bottom battery is obtained through passivation treatment, screen printing and high-temperature sintering.

[0114] Comparative Example 2

[0115] A perovskite / TOPCon crystalline silicon stacked cell, wherein the preparation method of the bottom cell comprises the following steps:

[0116] (1) Crystalline silicon substrate: select N-type single crystal silicon wafer, use 1wt% NaOH to texture the N-type single crystal silicon wafer, and use hydrogen peroxide and NaOH to clean the silicon wafer;

[0117] (2) A 2nm tunnel oxide layer and a 100nm polysilicon layer were prepared on the front side of an N-type single crystal silicon wafer by LPCVD, and then loaded into a tubular phosphorus diffusion furnace with POCl 3 As a phosphorus source, a phosphorus-doped polysilicon layer is obtained, and the phosphorus doping concentration is 2.0×E21cm -3 ;

[0118] (3) Using PECVD to deposit 200nm thick SiO on the front of N-type single crystal silicon wafer 2 mask layer;

[0119] (4) Removal of SiO2 from the back and sides of N-type single crystal silicon wafers 2 Mask layer and wrap-around;

[0120] (5) PECVD is used on the back of the N-type single crystal silicon wafer to introduce SiH 4 and H 2 , the temperature is 150℃, and a hydrogenated intrinsic amorphous silicon layer with a thickness of 8nm is formed; then SiH 4 and B 2 H 6 Boron source, temperature is 200°C, forming a P-type amorphous silicon layer with a thickness of 30nm;

[0121] (6) Remove the amorphous silicon layer and SiO2 remaining on the front side of the N-type single crystal silicon wafer 2 Mask layer and melted layer and damaged layer caused by laser;

[0122] (7) sputtering a TCO conductive film layer on both sides of an N-type single crystal silicon wafer by a PVD method at a temperature of 200° C. and an Ar gas pressure of 1 Pa, wherein the thickness of the TCO conductive film layer is 80 nm;

[0123] (8) preparing a metal electrode on the back side of an N-type single crystal silicon wafer by passivation treatment and screen printing;

[0124] (9) The metal electrode prepared on the back side of the crystalline silicon substrate in step (8) is cured in a curing furnace at a temperature of 120° C. for 13 min to form an ohmic contact with the TCO conductive film layer on the back side of the crystalline silicon substrate.

[0125] Comparative Example 3

[0126] A perovskite / TOPCon crystalline silicon stacked cell, wherein the preparation method of the bottom cell comprises the following steps:

[0127] (1) Crystalline silicon substrate: N-type single crystal silicon wafers are selected, and after the damaged layer is removed and cleaned, double-sided alkaline polishing is performed using NaOH;

[0128] (2) A 2nm tunnel oxide layer and a 100nm polysilicon layer were prepared on the front side of an N-type single crystal silicon wafer by LPCVD, and then loaded into a tubular phosphorus diffusion furnace with POCl 3 As a phosphorus source, a phosphorus-doped polysilicon layer is obtained, and the phosphorus doping concentration is 2.0×E21cm -3 ;

[0129] (3) Using PECVD to deposit 200nm thick SiO on the front of N-type single crystal silicon wafer 2 mask layer;

[0130] (4) Removal of SiO2 from the back and sides of N-type single crystal silicon wafers 2 Mask layer and wrap-around;

[0131] (5) Boron diffusion is performed on the back of the N-type single crystal silicon wafer to form a boron-doped single crystal silicon layer. The temperature of the boron diffusion deposition is 1000°C and the time is 60 minutes. The square resistance of the boron-doped single crystal silicon layer is 400Ω / cm 2 ;

[0132] (6) Laser texturing is used on the front side of the N-type single crystal silicon wafer, with a single pulse energy of 80uJ, a pulse frequency of 2500kHz, a scanning speed of 40000mm / s, and a scanning number of 2 times;

[0133] (7) Remove the amorphous silicon layer and SiO2 remaining on the front side of the N-type single crystal silicon wafer 2 Mask layer and melted layer and damaged layer caused by laser;

[0134] (8) sputtering a TCO conductive film layer on both sides of an N-type single crystal silicon wafer by a PVD method at a temperature of 200° C. and an Ar gas pressure of 1 Pa, wherein the thickness of the TCO conductive film layer is 80 nm;

[0135] (9) preparing a metal electrode on the back side of an N-type single crystal silicon wafer by passivation treatment and screen printing;

[0136] (10) The metal electrode prepared on the back side of the N-type single crystal silicon wafer is cured in a curing furnace at a temperature of 120° C. for 13 min to form an ohmic contact with the TCO conductive film layer on the back side of the crystalline silicon substrate.

[0137] Comparative Example 4

[0138] A perovskite / TOPCon crystalline silicon stacked cell, wherein the preparation method of the bottom cell comprises the following steps:

[0139] (1) Crystalline silicon substrate: N-type single crystal silicon wafers are selected, and after the damaged layer is removed and cleaned, double-sided alkaline polishing is performed using NaOH;

[0140] (2) A 2nm tunnel oxide layer and a 100nm polysilicon layer were prepared on the front side of an N-type single crystal silicon wafer by LPCVD, and then loaded into a tubular phosphorus diffusion furnace with POCl 3 As a phosphorus source, a phosphorus-doped polysilicon layer is obtained, and the phosphorus doping concentration is 2.0×E21cm -3 ;

[0141] (3) Using PECVD to deposit 200nm thick SiO on the front of N-type single crystal silicon wafer 2 mask layer;

[0142] (4) Removal of SiO2 from the back and sides of N-type single crystal silicon wafers 2 Mask layer and wrap-around;

[0143] (5) PECVD is used on the back of the N-type single crystal silicon wafer to introduce SiH 4, and H 2 , the temperature is 150℃, and a hydrogenated intrinsic amorphous silicon layer with a thickness of 8nm is formed; then SiH 4 and B 2 H 6 Boron source, temperature is 200°C, forming a P-type amorphous silicon layer with a thickness of 30nm;

[0144] (6) Laser texturing is used on the front side of the N-type single crystal silicon wafer, with a single pulse energy of 80uJ, a pulse frequency of 2500kHz, a scanning speed of 40000mm / s, and a scanning number of 2 times;

[0145] (7) Remove the amorphous silicon layer and SiO2 remaining on the front side of the N-type single crystal silicon wafer2 Mask layer and melted layer and damaged layer caused by laser;

[0146] (8) Preparing a silicon nitride anti-reflection layer on the back side of an N-type single crystal silicon wafer by PECVD;

[0147] (9) preparing a metal electrode on the back side of an N-type single crystal silicon wafer by passivation treatment and screen printing;

[0148] (10) The metal electrode prepared on the back side of the N-type single crystal silicon wafer is sintered at a high temperature of 900° C. in a sintering furnace to form an ohmic contact with the crystalline silicon substrate.

[0149] It should be noted that the method for testing the battery performance in the present invention refers to the following method.

[0150] Battery performance test: The TOPCon perovskite tandem cells obtained in the above embodiments and comparative examples were tested for photoelectric conversion efficiency (PCE), open circuit voltage (Voc), short circuit current (Jsc) and fill factor (FF) through a solar simulator and an IV tester. The test results of the perovskite crystalline silicon tandem cells are shown in Table 1.

[0151] Table 1 Comparison of battery performance of each group of embodiments and comparative examples

[0152]

[0153]

[0154] As shown in Table 1, in Examples 1 to 3, a tunneling oxide layer and an N-type polysilicon layer are first prepared on the front side, and then a laser texturing is performed. In addition, the defects on the surface of the crystalline silicon substrate are passivated, which increases the open circuit voltage and short circuit current and reduces the surface reflectivity. 2 The surface is passivated again by the layer, so the open circuit voltage and short circuit current of the perovskite crystalline silicon stack are relatively high; in addition, the P+ emitter is replaced by an intrinsic amorphous silicon layer and a P-type amorphous silicon layer on the back, and contact is formed in combination with low-temperature curing, which increases the open circuit voltage while improving the fill factor.

[0155] Comparative Example 1 is a conventional crystalline silicon cell stacked perovskite, and both Comparative Example 3 use a P+ emitter, which has relatively poor surface passivation, low open circuit voltage, relatively poor contact, and a low fill factor.

[0156] Compared with Examples 1 to 3, Comparative Example 2 adopts the method of first texturing and then preparing the tunnel oxide layer and N-type amorphous silicon layer on its surface. On the one hand, the surface defects increase, and on the other hand, the passivation effect achieved by the same polysilicon thickness is relatively poor. It is necessary to increase the polysilicon thickness to improve the passivation performance, but it will bring about the problem of parasitic absorption reducing the short-circuit current. Therefore, the open circuit voltage and short-circuit current of Comparative Example 2 are low. Comparative Example 4 adopts high-temperature sintering after depositing TCO on the surface, which destroys the PN junction and causes a decrease in overall efficiency.

[0157] The above shows that the present invention improves the overall efficiency of the stacked battery by replacing the P+ emitter with an intrinsic amorphous silicon layer and a P-type amorphous silicon layer on the back, first depositing a poly layer structure on the front and back sides of the crystalline silicon substrate and then performing texturing, and using a curing furnace to solidify the metal electrode on the back of the crystalline silicon substrate.

[0158] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for preparing a bottom cell of a perovskite / TOPCon crystalline silicon tandem cell, characterized in that: The following steps are involved: (1) polishing and cleaning the crystalline silicon substrate; (2) sequentially preparing a tunneling silicon oxide layer and a phosphorus-doped polysilicon layer on the front side of the crystalline silicon substrate in step (1); (3) preparing a SiO2 mask layer on the front side of the crystalline silicon substrate in step (2); (4) removing the SiO2 mask layer and the wrap-around layer on the back and side of the crystalline silicon substrate in step (3); (5) depositing an intrinsic amorphous silicon layer and a P-type amorphous silicon layer in sequence on the back side of the crystalline silicon substrate in step (4); (6) laser texturing is performed on the front surface of the crystalline silicon substrate in step (5); (7) removing the amorphous silicon layer, SiO2 mask layer, and the molten layer and damaged layer caused by the laser on the front side of the crystalline silicon substrate in step (6); (8) depositing a TCO conductive film layer on both sides of the crystalline silicon substrate in step (7); (9) preparing a metal electrode on the back side of the crystalline silicon substrate in step (8) by passivation treatment and screen printing; (10) The metal electrode prepared on the back side of the crystalline silicon substrate in step (9) is cured in a curing furnace to form an ohmic contact with the TCO conductive film layer on the back side of the crystalline silicon substrate.

2. The method for preparing the bottom cell of the perovskite / TOPCon crystalline silicon tandem cell according to claim 1, characterized in that: In the step (5), the PECVD method is adopted to introduce SiH4 and H2 at a temperature of 100-200°C to form the intrinsic amorphous silicon layer; then SiH4 and B2H6 boron source are introduced at a temperature of 150-250°C to form the P-type amorphous silicon layer.

3. The method for preparing the bottom cell of the perovskite / TOPCon crystalline silicon tandem cell according to claim 2, characterized in that: The thickness of the intrinsic amorphous silicon layer is 5-10 nm, and the thickness of the P-type amorphous silicon layer is 10-50 nm.

4. The method for preparing the bottom cell of the perovskite / TOPCon crystalline silicon tandem cell according to claim 1, characterized in that: The single pulse energy of the laser texturing in step (6) is 50-100uJ, the pulse frequency is 1500-3500kHz, the scanning speed is 30000-50000mm / s, and the number of scanning times is 1-2 times.

5. The method for preparing the bottom cell of the perovskite / TOPCon crystalline silicon tandem cell according to claim 1, characterized in that: In the step (8), the TCO conductive film layer is deposited on both sides of the crystalline silicon substrate by sputtering using a PVD method at a temperature of 100 to 300° C. and an Ar gas pressure of 0.1 to 2 Pa; the thickness of the TCO conductive film layer is 50 to 100 nm.

6. The method for preparing the bottom cell of the perovskite / TOPCon crystalline silicon tandem cell according to claim 1, characterized in that: In the step (10), the temperature for curing the metal electrode in the curing furnace is 100 to 150° C. and the time is 10 to 15 minutes.

7. A bottom cell of a perovskite / TOPCon crystalline silicon tandem cell, characterized in that: The bottom cell is prepared by the method for preparing the bottom cell of the perovskite / TOPCon crystalline silicon tandem cell as claimed in any one of claims 1 to 6.

8. A perovskite / TOPCon crystalline silicon tandem cell, characterized in that: It comprises a top cell and a bottom cell as claimed in claim 7, wherein the structure of the bottom cell sequentially comprises a first TCO conductive film layer, a phosphorus-doped polysilicon layer, a tunneling oxide layer, a crystalline silicon substrate, an intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a second TCO conductive film layer and a metal electrode, wherein the metal electrode forms an ohmic contact with the second TCO conductive film layer; and the first TCO conductive film layer of the bottom cell is connected to the top cell stack.

9. The perovskite / TOPCon crystalline silicon tandem cell according to claim 8, characterized in that: The top cell is a perovskite cell.

10. The perovskite / TOPCon crystalline silicon tandem cell according to claim 9, characterized in that: The structure of the perovskite cell includes a first transparent electrode layer, a first charge extraction layer, a perovskite layer, a second charge extraction layer and a second transparent electrode layer in sequence; the first transparent electrode layer is stacked and connected to the first TCO conductive film layer of the bottom cell.

Images